[linux-2.6-block.git] / drivers / fpga / dfl-pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for FPGA Device Feature List (DFL) PCIe device
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Zhang Yi <Yi.Z.Zhang@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 *   Joseph Grecco <joe.grecco@intel.com>
 *   Enno Luebbers <enno.luebbers@intel.com>
 *   Tim Whisonant <tim.whisonant@intel.com>
 *   Ananda Ravuri <ananda.ravuri@intel.com>
 *   Henry Mitchel <henry.mitchel@intel.com>
 */

#include <linux/pci.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/errno.h>
#include <linux/aer.h>

#include "dfl.h"

#define DRV_VERSION	"0.8"
#define DRV_NAME	"dfl-pci"

struct cci_drvdata {
	struct dfl_fpga_cdev *cdev;	/* container device */
};

static void __iomem *cci_pci_ioremap_bar(struct pci_dev *pcidev, int bar)
{
	if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME))
		return NULL;

	return pcim_iomap_table(pcidev)[bar];
}

static int cci_pci_alloc_irq(struct pci_dev *pcidev)
{
	int ret, nvec = pci_msix_vec_count(pcidev);

	if (nvec <= 0) {
		dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
		return 0;
	}

	ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
	if (ret < 0)
		return ret;

	return nvec;
}

static void cci_pci_free_irq(struct pci_dev *pcidev)
{
	pci_free_irq_vectors(pcidev);
}

/* PCI Device ID */
#define PCIE_DEVICE_ID_PF_INT_5_X	0xBCBD
#define PCIE_DEVICE_ID_PF_INT_6_X	0xBCC0
#define PCIE_DEVICE_ID_PF_DSC_1_X	0x09C4
/* VF Device */
#define PCIE_DEVICE_ID_VF_INT_5_X	0xBCBF
#define PCIE_DEVICE_ID_VF_INT_6_X	0xBCC1
#define PCIE_DEVICE_ID_VF_DSC_1_X	0x09C5

static struct pci_device_id cci_pcie_id_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
	{0,}
};
MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);

static int cci_init_drvdata(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata;

	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;

	pci_set_drvdata(pcidev, drvdata);

	return 0;
}

static void cci_remove_feature_devs(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);

	/* remove all children feature devices */
	dfl_fpga_feature_devs_remove(drvdata->cdev);
	cci_pci_free_irq(pcidev);
}

static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
{
	unsigned int i;
	int *table;

	table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
	if (!table)
		return table;

	for (i = 0; i < nvec; i++)
		table[i] = pci_irq_vector(pcidev, i);

	return table;
}

/* enumerate feature devices under pci device */
static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	int port_num, bar, i, nvec, ret = 0;
	struct dfl_fpga_enum_info *info;
	struct dfl_fpga_cdev *cdev;
	resource_size_t start, len;
	void __iomem *base;
	int *irq_table;
	u32 offset;
	u64 v;

	/* allocate enumeration info via pci_dev */
	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
	if (!info)
		return -ENOMEM;

	/* add irq info for enumeration if the device support irq */
	nvec = cci_pci_alloc_irq(pcidev);
	if (nvec < 0) {
		dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
		ret = nvec;
		goto enum_info_free_exit;
	} else if (nvec) {
		irq_table = cci_pci_create_irq_table(pcidev, nvec);
		if (!irq_table) {
			ret = -ENOMEM;
			goto irq_free_exit;
		}

		ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
		kfree(irq_table);
		if (ret)
			goto irq_free_exit;
	}

	/* start to find Device Feature List from Bar 0 */
	base = cci_pci_ioremap_bar(pcidev, 0);
	if (!base) {
		ret = -ENOMEM;
		goto irq_free_exit;
	}

	/*
	 * PF device has FME and Ports/AFUs, and VF device only has one
	 * Port/AFU. Check them and add related "Device Feature List" info
	 * for the next step enumeration.
	 */
	if (dfl_feature_is_fme(base)) {
		start = pci_resource_start(pcidev, 0);
		len = pci_resource_len(pcidev, 0);

		dfl_fpga_enum_info_add_dfl(info, start, len, base);

		/*
		 * find more Device Feature Lists (e.g. Ports) per information
		 * indicated by FME module.
		 */
		v = readq(base + FME_HDR_CAP);
		port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);

		WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);

		for (i = 0; i < port_num; i++) {
			v = readq(base + FME_HDR_PORT_OFST(i));

			/* skip ports which are not implemented. */
			if (!(v & FME_PORT_OFST_IMP))
				continue;

			/*
			 * add Port's Device Feature List information for next
			 * step enumeration.
			 */
			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
			base = cci_pci_ioremap_bar(pcidev, bar);
			if (!base)
				continue;

			start = pci_resource_start(pcidev, bar) + offset;
			len = pci_resource_len(pcidev, bar) - offset;

			dfl_fpga_enum_info_add_dfl(info, start, len,
						   base + offset);
		}
	} else if (dfl_feature_is_port(base)) {
		start = pci_resource_start(pcidev, 0);
		len = pci_resource_len(pcidev, 0);

		dfl_fpga_enum_info_add_dfl(info, start, len, base);
	} else {
		ret = -ENODEV;
		goto irq_free_exit;
	}

	/* start enumeration with prepared enumeration information */
	cdev = dfl_fpga_feature_devs_enumerate(info);
	if (IS_ERR(cdev)) {
		dev_err(&pcidev->dev, "Enumeration failure\n");
		ret = PTR_ERR(cdev);
		goto irq_free_exit;
	}

	drvdata->cdev = cdev;

irq_free_exit:
	if (ret)
		cci_pci_free_irq(pcidev);
enum_info_free_exit:
	dfl_fpga_enum_info_free(info);

	return ret;
}

static
int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
{
	int ret;

	ret = pcim_enable_device(pcidev);
	if (ret < 0) {
		dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
		return ret;
	}

	ret = pci_enable_pcie_error_reporting(pcidev);
	if (ret && ret != -EINVAL)
		dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);

	pci_set_master(pcidev);

	if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
		if (ret)
			goto disable_error_report_exit;
	} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
		if (ret)
			goto disable_error_report_exit;
	} else {
		ret = -EIO;
		dev_err(&pcidev->dev, "No suitable DMA support available.\n");
		goto disable_error_report_exit;
	}

	ret = cci_init_drvdata(pcidev);
	if (ret) {
		dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
		goto disable_error_report_exit;
	}

	ret = cci_enumerate_feature_devs(pcidev);
	if (!ret)
		return ret;

	dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);

disable_error_report_exit:
	pci_disable_pcie_error_reporting(pcidev);
	return ret;
}

static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	struct dfl_fpga_cdev *cdev = drvdata->cdev;
	int ret = 0;

	if (!num_vfs) {
		/*
		 * disable SRIOV and then put released ports back to default
		 * PF access mode.
		 */
		pci_disable_sriov(pcidev);

		dfl_fpga_cdev_config_ports_pf(cdev);

	} else {
		/*
		 * before enable SRIOV, put released ports into VF access mode
		 * first of all.
		 */
		ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
		if (ret)
			return ret;

		ret = pci_enable_sriov(pcidev, num_vfs);
		if (ret) {
			dfl_fpga_cdev_config_ports_pf(cdev);
			return ret;
		}
	}

	return num_vfs;
}

static void cci_pci_remove(struct pci_dev *pcidev)
{
	if (dev_is_pf(&pcidev->dev))
		cci_pci_sriov_configure(pcidev, 0);

	cci_remove_feature_devs(pcidev);
	pci_disable_pcie_error_reporting(pcidev);
}

static struct pci_driver cci_pci_driver = {
	.name = DRV_NAME,
	.id_table = cci_pcie_id_tbl,
	.probe = cci_pci_probe,
	.remove = cci_pci_remove,
	.sriov_configure = cci_pci_sriov_configure,
};

module_pci_driver(cci_pci_driver);

MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
72ddd9f3 ZY	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Driver for FPGA Device Feature List (DFL) PCIe device
	4	*
	5	* Copyright (C) 2017-2018 Intel Corporation, Inc.
	6	*
	7	* Authors:
	8	* Zhang Yi <Yi.Z.Zhang@intel.com>
	9	* Xiao Guangrong <guangrong.xiao@linux.intel.com>
	10	* Joseph Grecco <joe.grecco@intel.com>
	11	* Enno Luebbers <enno.luebbers@intel.com>
	12	* Tim Whisonant <tim.whisonant@intel.com>
	13	* Ananda Ravuri <ananda.ravuri@intel.com>
	14	* Henry Mitchel <henry.mitchel@intel.com>
	15	*/
	16
	17	#include <linux/pci.h>
	18	#include <linux/types.h>
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/stddef.h>
	22	#include <linux/errno.h>
	23	#include <linux/aer.h>
	24
968b8199 WH	25	#include "dfl.h"
968b8199 WH	26
72ddd9f3 ZY	27	#define DRV_VERSION "0.8"
	28	#define DRV_NAME "dfl-pci"
	29
968b8199 WH	30	struct cci_drvdata {
	31	struct dfl_fpga_cdev cdev; / container device */
	32	};
	33
	34	static void __iomem cci_pci_ioremap_bar(struct pci_dev pcidev, int bar)
	35	{
	36	if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME))
	37	return NULL;
	38
	39	return pcim_iomap_table(pcidev)[bar];
	40	}
	41
bfef946d XY	42	static int cci_pci_alloc_irq(struct pci_dev *pcidev)
	43	{
	44	int ret, nvec = pci_msix_vec_count(pcidev);
	45
	46	if (nvec <= 0) {
	47	dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
	48	return 0;
	49	}
	50
	51	ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
	52	if (ret < 0)
	53	return ret;
	54
	55	return nvec;
	56	}
	57
	58	static void cci_pci_free_irq(struct pci_dev *pcidev)
	59	{
	60	pci_free_irq_vectors(pcidev);
	61	}
	62
72ddd9f3 ZY	63	/* PCI Device ID */
	64	#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
	65	#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
	66	#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
	67	/* VF Device */
	68	#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
	69	#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
	70	#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
	71
	72	static struct pci_device_id cci_pcie_id_tbl[] = {
	73	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
	74	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
	75	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
	76	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
	77	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
	78	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
	79	{0,}
	80	};
	81	MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
	82
968b8199 WH	83	static int cci_init_drvdata(struct pci_dev *pcidev)
	84	{
	85	struct cci_drvdata *drvdata;
	86
	87	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
	88	if (!drvdata)
	89	return -ENOMEM;
	90
	91	pci_set_drvdata(pcidev, drvdata);
	92
	93	return 0;
	94	}
	95
	96	static void cci_remove_feature_devs(struct pci_dev *pcidev)
	97	{
	98	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	99
	100	/* remove all children feature devices */
	101	dfl_fpga_feature_devs_remove(drvdata->cdev);
bfef946d XY	102	cci_pci_free_irq(pcidev);
	103	}
	104
	105	static int cci_pci_create_irq_table(struct pci_dev pcidev, unsigned int nvec)
	106	{
	107	unsigned int i;
	108	int *table;
	109
	110	table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
	111	if (!table)
	112	return table;
	113
	114	for (i = 0; i < nvec; i++)
	115	table[i] = pci_irq_vector(pcidev, i);
	116
	117	return table;
968b8199 WH	118	}
	119
	120	/* enumerate feature devices under pci device */
	121	static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
	122	{
	123	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
bfef946d	124	int port_num, bar, i, nvec, ret = 0;
968b8199 WH	125	struct dfl_fpga_enum_info *info;
	126	struct dfl_fpga_cdev *cdev;
	127	resource_size_t start, len;
968b8199	128	void __iomem *base;
bfef946d	129	int *irq_table;
968b8199 WH	130	u32 offset;
	131	u64 v;
	132
	133	/* allocate enumeration info via pci_dev */
	134	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
	135	if (!info)
	136	return -ENOMEM;
	137
bfef946d XY	138	/* add irq info for enumeration if the device support irq */
	139	nvec = cci_pci_alloc_irq(pcidev);
	140	if (nvec < 0) {
	141	dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
	142	ret = nvec;
	143	goto enum_info_free_exit;
	144	} else if (nvec) {
	145	irq_table = cci_pci_create_irq_table(pcidev, nvec);
	146	if (!irq_table) {
	147	ret = -ENOMEM;
	148	goto irq_free_exit;
	149	}
	150
	151	ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
	152	kfree(irq_table);
	153	if (ret)
	154	goto irq_free_exit;
	155	}
	156
968b8199 WH	157	/* start to find Device Feature List from Bar 0 */
	158	base = cci_pci_ioremap_bar(pcidev, 0);
	159	if (!base) {
	160	ret = -ENOMEM;
bfef946d	161	goto irq_free_exit;
968b8199 WH	162	}
	163
	164	/*
	165	* PF device has FME and Ports/AFUs, and VF device only has one
	166	* Port/AFU. Check them and add related "Device Feature List" info
	167	* for the next step enumeration.
	168	*/
	169	if (dfl_feature_is_fme(base)) {
	170	start = pci_resource_start(pcidev, 0);
	171	len = pci_resource_len(pcidev, 0);
	172
	173	dfl_fpga_enum_info_add_dfl(info, start, len, base);
	174
	175	/*
	176	* find more Device Feature Lists (e.g. Ports) per information
	177	* indicated by FME module.
	178	*/
	179	v = readq(base + FME_HDR_CAP);
	180	port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
	181
	182	WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
	183
	184	for (i = 0; i < port_num; i++) {
	185	v = readq(base + FME_HDR_PORT_OFST(i));
	186
	187	/* skip ports which are not implemented. */
	188	if (!(v & FME_PORT_OFST_IMP))
	189	continue;
	190
	191	/*
	192	* add Port's Device Feature List information for next
	193	* step enumeration.
	194	*/
	195	bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
	196	offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
	197	base = cci_pci_ioremap_bar(pcidev, bar);
	198	if (!base)
	199	continue;
	200
	201	start = pci_resource_start(pcidev, bar) + offset;
	202	len = pci_resource_len(pcidev, bar) - offset;
	203
	204	dfl_fpga_enum_info_add_dfl(info, start, len,
	205	base + offset);
	206	}
	207	} else if (dfl_feature_is_port(base)) {
	208	start = pci_resource_start(pcidev, 0);
	209	len = pci_resource_len(pcidev, 0);
	210
	211	dfl_fpga_enum_info_add_dfl(info, start, len, base);
	212	} else {
	213	ret = -ENODEV;
bfef946d	214	goto irq_free_exit;
968b8199 WH	215	}
	216
	217	/* start enumeration with prepared enumeration information */
	218	cdev = dfl_fpga_feature_devs_enumerate(info);
	219	if (IS_ERR(cdev)) {
	220	dev_err(&pcidev->dev, "Enumeration failure\n");
	221	ret = PTR_ERR(cdev);
bfef946d	222	goto irq_free_exit;
968b8199 WH	223	}
	224
	225	drvdata->cdev = cdev;
	226
bfef946d XY	227	irq_free_exit:
	228	if (ret)
	229	cci_pci_free_irq(pcidev);
968b8199 WH	230	enum_info_free_exit:
	231	dfl_fpga_enum_info_free(info);
	232
	233	return ret;
	234	}
	235
72ddd9f3 ZY	236	static
	237	int cci_pci_probe(struct pci_dev pcidev, const struct pci_device_id pcidevid)
	238	{
	239	int ret;
	240
	241	ret = pcim_enable_device(pcidev);
	242	if (ret < 0) {
	243	dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
	244	return ret;
	245	}
	246
	247	ret = pci_enable_pcie_error_reporting(pcidev);
	248	if (ret && ret != -EINVAL)
	249	dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
	250
	251	pci_set_master(pcidev);
	252
	253	if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
	254	ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
	255	if (ret)
	256	goto disable_error_report_exit;
	257	} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
	258	ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
	259	if (ret)
	260	goto disable_error_report_exit;
	261	} else {
	262	ret = -EIO;
	263	dev_err(&pcidev->dev, "No suitable DMA support available.\n");
	264	goto disable_error_report_exit;
	265	}
	266
968b8199 WH	267	ret = cci_init_drvdata(pcidev);
	268	if (ret) {
	269	dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
	270	goto disable_error_report_exit;
	271	}
	272
	273	ret = cci_enumerate_feature_devs(pcidev);
bfef946d XY	274	if (!ret)
bfef946d XY	275	return ret;
968b8199	276
bfef946d	277	dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
72ddd9f3 ZY	278
	279	disable_error_report_exit:
	280	pci_disable_pcie_error_reporting(pcidev);
	281	return ret;
	282	}
	283
bdd4f307 WH	284	static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
	285	{
	286	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	287	struct dfl_fpga_cdev *cdev = drvdata->cdev;
	288	int ret = 0;
	289
	290	if (!num_vfs) {
	291	/*
	292	* disable SRIOV and then put released ports back to default
	293	* PF access mode.
	294	*/
	295	pci_disable_sriov(pcidev);
	296
	297	dfl_fpga_cdev_config_ports_pf(cdev);
	298
	299	} else {
	300	/*
	301	* before enable SRIOV, put released ports into VF access mode
	302	* first of all.
	303	*/
	304	ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
	305	if (ret)
	306	return ret;
	307
	308	ret = pci_enable_sriov(pcidev, num_vfs);
3c2760b7	309	if (ret) {
bdd4f307	310	dfl_fpga_cdev_config_ports_pf(cdev);
3c2760b7 XY	311	return ret;
3c2760b7 XY	312	}
bdd4f307 WH	313	}
bdd4f307 WH	314
3c2760b7	315	return num_vfs;
bdd4f307 WH	316	}
bdd4f307 WH	317
72ddd9f3 ZY	318	static void cci_pci_remove(struct pci_dev *pcidev)
72ddd9f3 ZY	319	{
bdd4f307 WH	320	if (dev_is_pf(&pcidev->dev))
	321	cci_pci_sriov_configure(pcidev, 0);
	322
968b8199	323	cci_remove_feature_devs(pcidev);
72ddd9f3 ZY	324	pci_disable_pcie_error_reporting(pcidev);
	325	}
	326
	327	static struct pci_driver cci_pci_driver = {
	328	.name = DRV_NAME,
	329	.id_table = cci_pcie_id_tbl,
	330	.probe = cci_pci_probe,
	331	.remove = cci_pci_remove,
bdd4f307	332	.sriov_configure = cci_pci_sriov_configure,
72ddd9f3 ZY	333	};
	334
	335	module_pci_driver(cci_pci_driver);
	336
	337	MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
	338	MODULE_AUTHOR("Intel Corporation");
	339	MODULE_LICENSE("GPL v2");