[linux-2.6-block.git] / drivers / fpga / dfl-pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for FPGA Device Feature List (DFL) PCIe device
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Zhang Yi <Yi.Z.Zhang@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 *   Joseph Grecco <joe.grecco@intel.com>
 *   Enno Luebbers <enno.luebbers@intel.com>
 *   Tim Whisonant <tim.whisonant@intel.com>
 *   Ananda Ravuri <ananda.ravuri@intel.com>
 *   Henry Mitchel <henry.mitchel@intel.com>
 */

#include <linux/pci.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/errno.h>
#include <linux/aer.h>

#include "dfl.h"

#define DRV_VERSION	"0.8"
#define DRV_NAME	"dfl-pci"

struct cci_drvdata {
	struct dfl_fpga_cdev *cdev;	/* container device */
};

static void __iomem *cci_pci_ioremap_bar(struct pci_dev *pcidev, int bar)
{
	if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME))
		return NULL;

	return pcim_iomap_table(pcidev)[bar];
}

/* PCI Device ID */
#define PCIE_DEVICE_ID_PF_INT_5_X	0xBCBD
#define PCIE_DEVICE_ID_PF_INT_6_X	0xBCC0
#define PCIE_DEVICE_ID_PF_DSC_1_X	0x09C4
/* VF Device */
#define PCIE_DEVICE_ID_VF_INT_5_X	0xBCBF
#define PCIE_DEVICE_ID_VF_INT_6_X	0xBCC1
#define PCIE_DEVICE_ID_VF_DSC_1_X	0x09C5

static struct pci_device_id cci_pcie_id_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
	{0,}
};
MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);

static int cci_init_drvdata(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata;

	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;

	pci_set_drvdata(pcidev, drvdata);

	return 0;
}

static void cci_remove_feature_devs(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);

	/* remove all children feature devices */
	dfl_fpga_feature_devs_remove(drvdata->cdev);
}

/* enumerate feature devices under pci device */
static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	struct dfl_fpga_enum_info *info;
	struct dfl_fpga_cdev *cdev;
	resource_size_t start, len;
	int port_num, bar, i, ret = 0;
	void __iomem *base;
	u32 offset;
	u64 v;

	/* allocate enumeration info via pci_dev */
	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
	if (!info)
		return -ENOMEM;

	/* start to find Device Feature List from Bar 0 */
	base = cci_pci_ioremap_bar(pcidev, 0);
	if (!base) {
		ret = -ENOMEM;
		goto enum_info_free_exit;
	}

	/*
	 * PF device has FME and Ports/AFUs, and VF device only has one
	 * Port/AFU. Check them and add related "Device Feature List" info
	 * for the next step enumeration.
	 */
	if (dfl_feature_is_fme(base)) {
		start = pci_resource_start(pcidev, 0);
		len = pci_resource_len(pcidev, 0);

		dfl_fpga_enum_info_add_dfl(info, start, len, base);

		/*
		 * find more Device Feature Lists (e.g. Ports) per information
		 * indicated by FME module.
		 */
		v = readq(base + FME_HDR_CAP);
		port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);

		WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);

		for (i = 0; i < port_num; i++) {
			v = readq(base + FME_HDR_PORT_OFST(i));

			/* skip ports which are not implemented. */
			if (!(v & FME_PORT_OFST_IMP))
				continue;

			/*
			 * add Port's Device Feature List information for next
			 * step enumeration.
			 */
			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
			base = cci_pci_ioremap_bar(pcidev, bar);
			if (!base)
				continue;

			start = pci_resource_start(pcidev, bar) + offset;
			len = pci_resource_len(pcidev, bar) - offset;

			dfl_fpga_enum_info_add_dfl(info, start, len,
						   base + offset);
		}
	} else if (dfl_feature_is_port(base)) {
		start = pci_resource_start(pcidev, 0);
		len = pci_resource_len(pcidev, 0);

		dfl_fpga_enum_info_add_dfl(info, start, len, base);
	} else {
		ret = -ENODEV;
		goto enum_info_free_exit;
	}

	/* start enumeration with prepared enumeration information */
	cdev = dfl_fpga_feature_devs_enumerate(info);
	if (IS_ERR(cdev)) {
		dev_err(&pcidev->dev, "Enumeration failure\n");
		ret = PTR_ERR(cdev);
		goto enum_info_free_exit;
	}

	drvdata->cdev = cdev;

enum_info_free_exit:
	dfl_fpga_enum_info_free(info);

	return ret;
}

static
int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
{
	int ret;

	ret = pcim_enable_device(pcidev);
	if (ret < 0) {
		dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
		return ret;
	}

	ret = pci_enable_pcie_error_reporting(pcidev);
	if (ret && ret != -EINVAL)
		dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);

	pci_set_master(pcidev);

	if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
		if (ret)
			goto disable_error_report_exit;
	} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
		if (ret)
			goto disable_error_report_exit;
	} else {
		ret = -EIO;
		dev_err(&pcidev->dev, "No suitable DMA support available.\n");
		goto disable_error_report_exit;
	}

	ret = cci_init_drvdata(pcidev);
	if (ret) {
		dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
		goto disable_error_report_exit;
	}

	ret = cci_enumerate_feature_devs(pcidev);
	if (ret) {
		dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
		goto disable_error_report_exit;
	}

	return ret;

disable_error_report_exit:
	pci_disable_pcie_error_reporting(pcidev);
	return ret;
}

static void cci_pci_remove(struct pci_dev *pcidev)
{
	cci_remove_feature_devs(pcidev);
	pci_disable_pcie_error_reporting(pcidev);
}

static struct pci_driver cci_pci_driver = {
	.name = DRV_NAME,
	.id_table = cci_pcie_id_tbl,
	.probe = cci_pci_probe,
	.remove = cci_pci_remove,
};

module_pci_driver(cci_pci_driver);

MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
72ddd9f3 ZY	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Driver for FPGA Device Feature List (DFL) PCIe device
	4	*
	5	* Copyright (C) 2017-2018 Intel Corporation, Inc.
	6	*
	7	* Authors:
	8	* Zhang Yi <Yi.Z.Zhang@intel.com>
	9	* Xiao Guangrong <guangrong.xiao@linux.intel.com>
	10	* Joseph Grecco <joe.grecco@intel.com>
	11	* Enno Luebbers <enno.luebbers@intel.com>
	12	* Tim Whisonant <tim.whisonant@intel.com>
	13	* Ananda Ravuri <ananda.ravuri@intel.com>
	14	* Henry Mitchel <henry.mitchel@intel.com>
	15	*/
	16
	17	#include <linux/pci.h>
	18	#include <linux/types.h>
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/stddef.h>
	22	#include <linux/errno.h>
	23	#include <linux/aer.h>
	24
968b8199 WH	25	#include "dfl.h"
968b8199 WH	26
72ddd9f3 ZY	27	#define DRV_VERSION "0.8"
	28	#define DRV_NAME "dfl-pci"
	29
968b8199 WH	30	struct cci_drvdata {
	31	struct dfl_fpga_cdev cdev; / container device */
	32	};
	33
	34	static void __iomem cci_pci_ioremap_bar(struct pci_dev pcidev, int bar)
	35	{
	36	if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME))
	37	return NULL;
	38
	39	return pcim_iomap_table(pcidev)[bar];
	40	}
	41
72ddd9f3 ZY	42	/* PCI Device ID */
	43	#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
	44	#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
	45	#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
	46	/* VF Device */
	47	#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
	48	#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
	49	#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
	50
	51	static struct pci_device_id cci_pcie_id_tbl[] = {
	52	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
	53	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
	54	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
	55	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
	56	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
	57	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
	58	{0,}
	59	};
	60	MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
	61
968b8199 WH	62	static int cci_init_drvdata(struct pci_dev *pcidev)
	63	{
	64	struct cci_drvdata *drvdata;
	65
	66	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
	67	if (!drvdata)
	68	return -ENOMEM;
	69
	70	pci_set_drvdata(pcidev, drvdata);
	71
	72	return 0;
	73	}
	74
	75	static void cci_remove_feature_devs(struct pci_dev *pcidev)
	76	{
	77	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	78
	79	/* remove all children feature devices */
	80	dfl_fpga_feature_devs_remove(drvdata->cdev);
	81	}
	82
	83	/* enumerate feature devices under pci device */
	84	static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
	85	{
	86	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	87	struct dfl_fpga_enum_info *info;
	88	struct dfl_fpga_cdev *cdev;
	89	resource_size_t start, len;
	90	int port_num, bar, i, ret = 0;
	91	void __iomem *base;
	92	u32 offset;
	93	u64 v;
	94
	95	/* allocate enumeration info via pci_dev */
	96	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
	97	if (!info)
	98	return -ENOMEM;
	99
	100	/* start to find Device Feature List from Bar 0 */
	101	base = cci_pci_ioremap_bar(pcidev, 0);
	102	if (!base) {
	103	ret = -ENOMEM;
	104	goto enum_info_free_exit;
	105	}
	106
	107	/*
	108	* PF device has FME and Ports/AFUs, and VF device only has one
	109	* Port/AFU. Check them and add related "Device Feature List" info
	110	* for the next step enumeration.
	111	*/
	112	if (dfl_feature_is_fme(base)) {
	113	start = pci_resource_start(pcidev, 0);
	114	len = pci_resource_len(pcidev, 0);
	115
	116	dfl_fpga_enum_info_add_dfl(info, start, len, base);
	117
	118	/*
	119	* find more Device Feature Lists (e.g. Ports) per information
	120	* indicated by FME module.
	121	*/
	122	v = readq(base + FME_HDR_CAP);
	123	port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
	124
	125	WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
126
127	for (i = 0; i < port_num; i++) {
128	v = readq(base + FME_HDR_PORT_OFST(i));
129
130	/* skip ports which are not implemented. */
131	if (!(v & FME_PORT_OFST_IMP))
132	continue;
133
134	/*
135	* add Port's Device Feature List information for next
136	* step enumeration.
137	*/
138	bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
139	offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
140	base = cci_pci_ioremap_bar(pcidev, bar);
141	if (!base)
142	continue;
143
144	start = pci_resource_start(pcidev, bar) + offset;
145	len = pci_resource_len(pcidev, bar) - offset;
146
147	dfl_fpga_enum_info_add_dfl(info, start, len,
148	base + offset);
149	}
150	} else if (dfl_feature_is_port(base)) {
151	start = pci_resource_start(pcidev, 0);
152	len = pci_resource_len(pcidev, 0);
153
154	dfl_fpga_enum_info_add_dfl(info, start, len, base);
155	} else {
156	ret = -ENODEV;
157	goto enum_info_free_exit;
158	}
159
160	/* start enumeration with prepared enumeration information */
161	cdev = dfl_fpga_feature_devs_enumerate(info);
162	if (IS_ERR(cdev)) {
163	dev_err(&pcidev->dev, "Enumeration failure\n");
164	ret = PTR_ERR(cdev);
165	goto enum_info_free_exit;
166	}
167
168	drvdata->cdev = cdev;
169
170	enum_info_free_exit:
171	dfl_fpga_enum_info_free(info);
172
173	return ret;
174	}
175
72ddd9f3 ZY	176	static
	177	int cci_pci_probe(struct pci_dev pcidev, const struct pci_device_id pcidevid)
	178	{
	179	int ret;
	180
	181	ret = pcim_enable_device(pcidev);
	182	if (ret < 0) {
	183	dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
	184	return ret;
	185	}
	186
	187	ret = pci_enable_pcie_error_reporting(pcidev);
	188	if (ret && ret != -EINVAL)
	189	dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
	190
	191	pci_set_master(pcidev);
	192
	193	if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
	194	ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
	195	if (ret)
	196	goto disable_error_report_exit;
	197	} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
	198	ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
	199	if (ret)
	200	goto disable_error_report_exit;
	201	} else {
	202	ret = -EIO;
	203	dev_err(&pcidev->dev, "No suitable DMA support available.\n");
	204	goto disable_error_report_exit;
	205	}
	206
968b8199 WH	207	ret = cci_init_drvdata(pcidev);
	208	if (ret) {
	209	dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
	210	goto disable_error_report_exit;
	211	}
	212
	213	ret = cci_enumerate_feature_devs(pcidev);
	214	if (ret) {
	215	dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
	216	goto disable_error_report_exit;
	217	}
	218
	219	return ret;
72ddd9f3 ZY	220
	221	disable_error_report_exit:
	222	pci_disable_pcie_error_reporting(pcidev);
	223	return ret;
	224	}
	225
	226	static void cci_pci_remove(struct pci_dev *pcidev)
	227	{
968b8199	228	cci_remove_feature_devs(pcidev);
72ddd9f3 ZY	229	pci_disable_pcie_error_reporting(pcidev);
	230	}
	231
	232	static struct pci_driver cci_pci_driver = {
	233	.name = DRV_NAME,
	234	.id_table = cci_pcie_id_tbl,
	235	.probe = cci_pci_probe,
	236	.remove = cci_pci_remove,
	237	};
	238
	239	module_pci_driver(cci_pci_driver);
	240
	241	MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
	242	MODULE_AUTHOR("Intel Corporation");
	243	MODULE_LICENSE("GPL v2");