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322ddebe KL |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Driver for FPGA Management Engine (FME) | |
4 | * | |
5 | * Copyright (C) 2017-2018 Intel Corporation, Inc. | |
6 | * | |
7 | * Authors: | |
8 | * Kang Luwei <luwei.kang@intel.com> | |
9 | * Xiao Guangrong <guangrong.xiao@linux.intel.com> | |
10 | * Joseph Grecco <joe.grecco@intel.com> | |
11 | * Enno Luebbers <enno.luebbers@intel.com> | |
12 | * Tim Whisonant <tim.whisonant@intel.com> | |
13 | * Ananda Ravuri <ananda.ravuri@intel.com> | |
14 | * Henry Mitchel <henry.mitchel@intel.com> | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
620e1902 | 19 | #include <linux/fpga-dfl.h> |
322ddebe KL |
20 | |
21 | #include "dfl.h" | |
29de7624 | 22 | #include "dfl-fme.h" |
322ddebe | 23 | |
0a27ff24 KL |
24 | static ssize_t ports_num_show(struct device *dev, |
25 | struct device_attribute *attr, char *buf) | |
26 | { | |
27 | void __iomem *base; | |
28 | u64 v; | |
29 | ||
30 | base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); | |
31 | ||
32 | v = readq(base + FME_HDR_CAP); | |
33 | ||
34 | return scnprintf(buf, PAGE_SIZE, "%u\n", | |
35 | (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v)); | |
36 | } | |
37 | static DEVICE_ATTR_RO(ports_num); | |
38 | ||
39 | /* | |
40 | * Bitstream (static FPGA region) identifier number. It contains the | |
41 | * detailed version and other information of this static FPGA region. | |
42 | */ | |
43 | static ssize_t bitstream_id_show(struct device *dev, | |
44 | struct device_attribute *attr, char *buf) | |
45 | { | |
46 | void __iomem *base; | |
47 | u64 v; | |
48 | ||
49 | base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); | |
50 | ||
51 | v = readq(base + FME_HDR_BITSTREAM_ID); | |
52 | ||
53 | return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); | |
54 | } | |
55 | static DEVICE_ATTR_RO(bitstream_id); | |
56 | ||
57 | /* | |
58 | * Bitstream (static FPGA region) meta data. It contains the synthesis | |
59 | * date, seed and other information of this static FPGA region. | |
60 | */ | |
61 | static ssize_t bitstream_metadata_show(struct device *dev, | |
62 | struct device_attribute *attr, char *buf) | |
63 | { | |
64 | void __iomem *base; | |
65 | u64 v; | |
66 | ||
67 | base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); | |
68 | ||
69 | v = readq(base + FME_HDR_BITSTREAM_MD); | |
70 | ||
71 | return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); | |
72 | } | |
73 | static DEVICE_ATTR_RO(bitstream_metadata); | |
74 | ||
dcfecd4d | 75 | static struct attribute *fme_hdr_attrs[] = { |
0a27ff24 KL |
76 | &dev_attr_ports_num.attr, |
77 | &dev_attr_bitstream_id.attr, | |
78 | &dev_attr_bitstream_metadata.attr, | |
79 | NULL, | |
80 | }; | |
dcfecd4d | 81 | ATTRIBUTE_GROUPS(fme_hdr); |
0a27ff24 | 82 | |
322ddebe KL |
83 | static int fme_hdr_init(struct platform_device *pdev, |
84 | struct dfl_feature *feature) | |
85 | { | |
0a27ff24 KL |
86 | void __iomem *base = feature->ioaddr; |
87 | int ret; | |
88 | ||
322ddebe | 89 | dev_dbg(&pdev->dev, "FME HDR Init.\n"); |
0a27ff24 KL |
90 | dev_dbg(&pdev->dev, "FME cap %llx.\n", |
91 | (unsigned long long)readq(base + FME_HDR_CAP)); | |
92 | ||
dcfecd4d | 93 | ret = device_add_groups(&pdev->dev, fme_hdr_groups); |
0a27ff24 KL |
94 | if (ret) |
95 | return ret; | |
322ddebe KL |
96 | |
97 | return 0; | |
98 | } | |
99 | ||
100 | static void fme_hdr_uinit(struct platform_device *pdev, | |
101 | struct dfl_feature *feature) | |
102 | { | |
103 | dev_dbg(&pdev->dev, "FME HDR UInit.\n"); | |
dcfecd4d | 104 | device_remove_groups(&pdev->dev, fme_hdr_groups); |
322ddebe KL |
105 | } |
106 | ||
107 | static const struct dfl_feature_ops fme_hdr_ops = { | |
108 | .init = fme_hdr_init, | |
109 | .uinit = fme_hdr_uinit, | |
110 | }; | |
111 | ||
112 | static struct dfl_feature_driver fme_feature_drvs[] = { | |
113 | { | |
114 | .id = FME_FEATURE_ID_HEADER, | |
115 | .ops = &fme_hdr_ops, | |
116 | }, | |
29de7624 KL |
117 | { |
118 | .id = FME_FEATURE_ID_PR_MGMT, | |
119 | .ops = &pr_mgmt_ops, | |
120 | }, | |
322ddebe KL |
121 | { |
122 | .ops = NULL, | |
123 | }, | |
124 | }; | |
125 | ||
620e1902 WH |
126 | static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata, |
127 | unsigned long arg) | |
128 | { | |
129 | /* No extension support for now */ | |
130 | return 0; | |
131 | } | |
132 | ||
322ddebe KL |
133 | static int fme_open(struct inode *inode, struct file *filp) |
134 | { | |
135 | struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode); | |
136 | struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev); | |
137 | int ret; | |
138 | ||
139 | if (WARN_ON(!pdata)) | |
140 | return -ENODEV; | |
141 | ||
142 | ret = dfl_feature_dev_use_begin(pdata); | |
143 | if (ret) | |
144 | return ret; | |
145 | ||
146 | dev_dbg(&fdev->dev, "Device File Open\n"); | |
147 | filp->private_data = pdata; | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | static int fme_release(struct inode *inode, struct file *filp) | |
153 | { | |
154 | struct dfl_feature_platform_data *pdata = filp->private_data; | |
155 | struct platform_device *pdev = pdata->dev; | |
156 | ||
157 | dev_dbg(&pdev->dev, "Device File Release\n"); | |
158 | dfl_feature_dev_use_end(pdata); | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | |
164 | { | |
165 | struct dfl_feature_platform_data *pdata = filp->private_data; | |
166 | struct platform_device *pdev = pdata->dev; | |
167 | struct dfl_feature *f; | |
168 | long ret; | |
169 | ||
170 | dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd); | |
171 | ||
172 | switch (cmd) { | |
620e1902 WH |
173 | case DFL_FPGA_GET_API_VERSION: |
174 | return DFL_FPGA_API_VERSION; | |
175 | case DFL_FPGA_CHECK_EXTENSION: | |
176 | return fme_ioctl_check_extension(pdata, arg); | |
322ddebe KL |
177 | default: |
178 | /* | |
179 | * Let sub-feature's ioctl function to handle the cmd. | |
180 | * Sub-feature's ioctl returns -ENODEV when cmd is not | |
181 | * handled in this sub feature, and returns 0 or other | |
182 | * error code if cmd is handled. | |
183 | */ | |
184 | dfl_fpga_dev_for_each_feature(pdata, f) { | |
185 | if (f->ops && f->ops->ioctl) { | |
186 | ret = f->ops->ioctl(pdev, f, cmd, arg); | |
187 | if (ret != -ENODEV) | |
188 | return ret; | |
189 | } | |
190 | } | |
191 | } | |
192 | ||
193 | return -EINVAL; | |
194 | } | |
195 | ||
29de7624 KL |
196 | static int fme_dev_init(struct platform_device *pdev) |
197 | { | |
198 | struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
199 | struct dfl_fme *fme; | |
200 | ||
201 | fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL); | |
202 | if (!fme) | |
203 | return -ENOMEM; | |
204 | ||
205 | fme->pdata = pdata; | |
206 | ||
207 | mutex_lock(&pdata->lock); | |
208 | dfl_fpga_pdata_set_private(pdata, fme); | |
209 | mutex_unlock(&pdata->lock); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | static void fme_dev_destroy(struct platform_device *pdev) | |
215 | { | |
216 | struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
217 | struct dfl_fme *fme; | |
218 | ||
219 | mutex_lock(&pdata->lock); | |
220 | fme = dfl_fpga_pdata_get_private(pdata); | |
221 | dfl_fpga_pdata_set_private(pdata, NULL); | |
222 | mutex_unlock(&pdata->lock); | |
223 | } | |
224 | ||
322ddebe KL |
225 | static const struct file_operations fme_fops = { |
226 | .owner = THIS_MODULE, | |
227 | .open = fme_open, | |
228 | .release = fme_release, | |
229 | .unlocked_ioctl = fme_ioctl, | |
230 | }; | |
231 | ||
232 | static int fme_probe(struct platform_device *pdev) | |
233 | { | |
234 | int ret; | |
235 | ||
29de7624 | 236 | ret = fme_dev_init(pdev); |
322ddebe KL |
237 | if (ret) |
238 | goto exit; | |
239 | ||
29de7624 KL |
240 | ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs); |
241 | if (ret) | |
242 | goto dev_destroy; | |
243 | ||
322ddebe KL |
244 | ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE); |
245 | if (ret) | |
246 | goto feature_uinit; | |
247 | ||
248 | return 0; | |
249 | ||
250 | feature_uinit: | |
251 | dfl_fpga_dev_feature_uinit(pdev); | |
29de7624 KL |
252 | dev_destroy: |
253 | fme_dev_destroy(pdev); | |
322ddebe KL |
254 | exit: |
255 | return ret; | |
256 | } | |
257 | ||
258 | static int fme_remove(struct platform_device *pdev) | |
259 | { | |
260 | dfl_fpga_dev_ops_unregister(pdev); | |
261 | dfl_fpga_dev_feature_uinit(pdev); | |
29de7624 | 262 | fme_dev_destroy(pdev); |
322ddebe KL |
263 | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static struct platform_driver fme_driver = { | |
268 | .driver = { | |
269 | .name = DFL_FPGA_FEATURE_DEV_FME, | |
270 | }, | |
271 | .probe = fme_probe, | |
272 | .remove = fme_remove, | |
273 | }; | |
274 | ||
275 | module_platform_driver(fme_driver); | |
276 | ||
277 | MODULE_DESCRIPTION("FPGA Management Engine driver"); | |
278 | MODULE_AUTHOR("Intel Corporation"); | |
279 | MODULE_LICENSE("GPL v2"); | |
280 | MODULE_ALIAS("platform:dfl-fme"); |