[linux-2.6-block.git] / drivers / fpga / altera-cvp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
 *
 * Copyright (C) 2017 DENX Software Engineering
 *
 * Anatolij Gustschin <agust@denx.de>
 *
 * Manage Altera FPGA firmware using PCIe CvP.
 * Firmware must be in binary "rbf" format.
 */

#include <linux/delay.h>
#include <linux/device.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/sizes.h>

#define CVP_BAR		0	/* BAR used for data transfer in memory mode */
#define CVP_DUMMY_WR	244	/* dummy writes to clear CvP state machine */
#define TIMEOUT_US	2000	/* CVP STATUS timeout for USERMODE polling */

/* Vendor Specific Extended Capability Registers */
#define VSE_PCIE_EXT_CAP_ID		0x0
#define VSE_PCIE_EXT_CAP_ID_VAL		0x000b	/* 16bit */

#define VSE_CVP_STATUS			0x1c	/* 32bit */
#define VSE_CVP_STATUS_CFG_RDY		BIT(18)	/* CVP_CONFIG_READY */
#define VSE_CVP_STATUS_CFG_ERR		BIT(19)	/* CVP_CONFIG_ERROR */
#define VSE_CVP_STATUS_CVP_EN		BIT(20)	/* ctrl block is enabling CVP */
#define VSE_CVP_STATUS_USERMODE		BIT(21)	/* USERMODE */
#define VSE_CVP_STATUS_CFG_DONE		BIT(23)	/* CVP_CONFIG_DONE */
#define VSE_CVP_STATUS_PLD_CLK_IN_USE	BIT(24)	/* PLD_CLK_IN_USE */

#define VSE_CVP_MODE_CTRL		0x20	/* 32bit */
#define VSE_CVP_MODE_CTRL_CVP_MODE	BIT(0)	/* CVP (1) or normal mode (0) */
#define VSE_CVP_MODE_CTRL_HIP_CLK_SEL	BIT(1) /* PMA (1) or fabric clock (0) */
#define VSE_CVP_MODE_CTRL_NUMCLKS_OFF	8	/* NUMCLKS bits offset */
#define VSE_CVP_MODE_CTRL_NUMCLKS_MASK	GENMASK(15, 8)

#define VSE_CVP_DATA			0x28	/* 32bit */
#define VSE_CVP_PROG_CTRL		0x2c	/* 32bit */
#define VSE_CVP_PROG_CTRL_CONFIG	BIT(0)
#define VSE_CVP_PROG_CTRL_START_XFER	BIT(1)

#define VSE_UNCOR_ERR_STATUS		0x34	/* 32bit */
#define VSE_UNCOR_ERR_CVP_CFG_ERR	BIT(5)	/* CVP_CONFIG_ERROR_LATCHED */

#define DRV_NAME		"altera-cvp"
#define ALTERA_CVP_MGR_NAME	"Altera CvP FPGA Manager"

/* Optional CvP config error status check for debugging */
static bool altera_cvp_chkcfg;

struct altera_cvp_conf {
	struct fpga_manager	*mgr;
	struct pci_dev		*pci_dev;
	void __iomem		*map;
	void			(*write_data)(struct altera_cvp_conf *conf,
					      u32 data);
	char			mgr_name[64];
	u8			numclks;
	u32			vsec_offset;
};

static int altera_read_config_dword(struct altera_cvp_conf *conf,
				    int where, u32 *val)
{
	return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
				     val);
}

static int altera_write_config_dword(struct altera_cvp_conf *conf,
				     int where, u32 val)
{
	return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
				      val);
}

static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
{
	struct altera_cvp_conf *conf = mgr->priv;
	u32 status;

	altera_read_config_dword(conf, VSE_CVP_STATUS, &status);

	if (status & VSE_CVP_STATUS_CFG_DONE)
		return FPGA_MGR_STATE_OPERATING;

	if (status & VSE_CVP_STATUS_CVP_EN)
		return FPGA_MGR_STATE_POWER_UP;

	return FPGA_MGR_STATE_UNKNOWN;
}

static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
{
	writel(val, conf->map);
}

static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
{
	pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
			       val);
}

/* switches between CvP clock and internal clock */
static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
{
	unsigned int i;
	u32 val;

	/* set 1 CVP clock cycle for every CVP Data Register Write */
	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
	val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
	val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);

	for (i = 0; i < CVP_DUMMY_WR; i++)
		conf->write_data(conf, 0); /* dummy data, could be any value */
}

static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
				  u32 status_val, int timeout_us)
{
	unsigned int retries;
	u32 val;

	retries = timeout_us / 10;
	if (timeout_us % 10)
		retries++;

	do {
		altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
		if ((val & status_mask) == status_val)
			return 0;

		/* use small usleep value to re-check and break early */
		usleep_range(10, 11);
	} while (--retries);

	return -ETIMEDOUT;
}

static int altera_cvp_teardown(struct fpga_manager *mgr,
			       struct fpga_image_info *info)
{
	struct altera_cvp_conf *conf = mgr->priv;
	int ret;
	u32 val;

	/* STEP 12 - reset START_XFER bit */
	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
	val &= ~VSE_CVP_PROG_CTRL_START_XFER;
	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);

	/* STEP 13 - reset CVP_CONFIG bit */
	val &= ~VSE_CVP_PROG_CTRL_CONFIG;
	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);

	/*
	 * STEP 14
	 * - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
	 *   writes to the HIP
	 */
	altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */

	/* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10);
	if (ret)
		dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");

	return ret;
}

static int altera_cvp_write_init(struct fpga_manager *mgr,
				 struct fpga_image_info *info,
				 const char *buf, size_t count)
{
	struct altera_cvp_conf *conf = mgr->priv;
	u32 iflags, val;
	int ret;

	iflags = info ? info->flags : 0;

	if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
		return -EINVAL;
	}

	/* Determine allowed clock to data ratio */
	if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
		conf->numclks = 8; /* ratio for all compressed images */
	else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
		conf->numclks = 4; /* for uncompressed and encrypted images */
	else
		conf->numclks = 1; /* for uncompressed and unencrypted images */

	/* STEP 1 - read CVP status and check CVP_EN flag */
	altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
	if (!(val & VSE_CVP_STATUS_CVP_EN)) {
		dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
		return -ENODEV;
	}

	if (val & VSE_CVP_STATUS_CFG_RDY) {
		dev_warn(&mgr->dev, "CvP already started, teardown first\n");
		ret = altera_cvp_teardown(mgr, info);
		if (ret)
			return ret;
	}

	/*
	 * STEP 2
	 * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
	 */
	/* switch from fabric to PMA clock */
	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
	val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);

	/* set CVP mode */
	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
	val |= VSE_CVP_MODE_CTRL_CVP_MODE;
	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);

	/*
	 * STEP 3
	 * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
	 */
	altera_cvp_dummy_write(conf);

	/* STEP 4 - set CVP_CONFIG bit */
	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
	/* request control block to begin transfer using CVP */
	val |= VSE_CVP_PROG_CTRL_CONFIG;
	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);

	/* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
				     VSE_CVP_STATUS_CFG_RDY, 10);
	if (ret) {
		dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
		return ret;
	}

	/*
	 * STEP 6
	 * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
	 */
	altera_cvp_dummy_write(conf);

	/* STEP 7 - set START_XFER */
	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
	val |= VSE_CVP_PROG_CTRL_START_XFER;
	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);

	/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
	val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
	val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);

	return 0;
}

static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
{
	struct altera_cvp_conf *conf = mgr->priv;
	u32 val;

	/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
	altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
	if (val & VSE_CVP_STATUS_CFG_ERR) {
		dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
			bytes);
		return -EPROTO;
	}
	return 0;
}

static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
			    size_t count)
{
	struct altera_cvp_conf *conf = mgr->priv;
	const u32 *data;
	size_t done, remaining;
	int status = 0;
	u32 mask;

	/* STEP 9 - write 32-bit data from RBF file to CVP data register */
	data = (u32 *)buf;
	remaining = count;
	done = 0;

	while (remaining >= 4) {
		conf->write_data(conf, *data++);
		done += 4;
		remaining -= 4;

		/*
		 * STEP 10 (optional) and STEP 11
		 * - check error flag
		 * - loop until data transfer completed
		 * Config images can be huge (more than 40 MiB), so
		 * only check after a new 4k data block has been written.
		 * This reduces the number of checks and speeds up the
		 * configuration process.
		 */
		if (altera_cvp_chkcfg && !(done % SZ_4K)) {
			status = altera_cvp_chk_error(mgr, done);
			if (status < 0)
				return status;
		}
	}

	/* write up to 3 trailing bytes, if any */
	mask = BIT(remaining * 8) - 1;
	if (mask)
		conf->write_data(conf, *data & mask);

	if (altera_cvp_chkcfg)
		status = altera_cvp_chk_error(mgr, count);

	return status;
}

static int altera_cvp_write_complete(struct fpga_manager *mgr,
				     struct fpga_image_info *info)
{
	struct altera_cvp_conf *conf = mgr->priv;
	u32 mask, val;
	int ret;

	ret = altera_cvp_teardown(mgr, info);
	if (ret)
		return ret;

	/* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
	altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
	if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
		dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
		return -EPROTO;
	}

	/* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
	val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
	val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);

	/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
	mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
	ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US);
	if (ret)
		dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");

	return ret;
}

static const struct fpga_manager_ops altera_cvp_ops = {
	.state		= altera_cvp_state,
	.write_init	= altera_cvp_write_init,
	.write		= altera_cvp_write,
	.write_complete	= altera_cvp_write_complete,
};

static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
{
	return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
}

static ssize_t chkcfg_store(struct device_driver *drv, const char *buf,
			    size_t count)
{
	int ret;

	ret = kstrtobool(buf, &altera_cvp_chkcfg);
	if (ret)
		return ret;

	return count;
}

static DRIVER_ATTR_RW(chkcfg);

static int altera_cvp_probe(struct pci_dev *pdev,
			    const struct pci_device_id *dev_id);
static void altera_cvp_remove(struct pci_dev *pdev);

static struct pci_device_id altera_cvp_id_tbl[] = {
	{ PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
	{ }
};
MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);

static struct pci_driver altera_cvp_driver = {
	.name   = DRV_NAME,
	.id_table = altera_cvp_id_tbl,
	.probe  = altera_cvp_probe,
	.remove = altera_cvp_remove,
};

static int altera_cvp_probe(struct pci_dev *pdev,
			    const struct pci_device_id *dev_id)
{
	struct altera_cvp_conf *conf;
	struct fpga_manager *mgr;
	int ret, offset;
	u16 cmd, val;
	u32 regval;

	/* Discover the Vendor Specific Offset for this device */
	offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
	if (!offset) {
		dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
		return -ENODEV;
	}

	/*
	 * First check if this is the expected FPGA device. PCI config
	 * space access works without enabling the PCI device, memory
	 * space access is enabled further down.
	 */
	pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
	if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
		dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
		return -ENODEV;
	}

	pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, &regval);
	if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
		dev_err(&pdev->dev,
			"CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
			regval);
		return -ENODEV;
	}

	conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
	if (!conf)
		return -ENOMEM;

	conf->vsec_offset = offset;

	/*
	 * Enable memory BAR access. We cannot use pci_enable_device() here
	 * because it will make the driver unusable with FPGA devices that
	 * have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
	 * platform. Such BARs will not have an assigned address range and
	 * pci_enable_device() will fail, complaining about not claimed BAR,
	 * even if the concerned BAR is not needed for FPGA configuration
	 * at all. Thus, enable the device via PCI config space command.
	 */
	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
	if (!(cmd & PCI_COMMAND_MEMORY)) {
		cmd |= PCI_COMMAND_MEMORY;
		pci_write_config_word(pdev, PCI_COMMAND, cmd);
	}

	ret = pci_request_region(pdev, CVP_BAR, "CVP");
	if (ret) {
		dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
		goto err_disable;
	}

	conf->pci_dev = pdev;
	conf->write_data = altera_cvp_write_data_iomem;

	conf->map = pci_iomap(pdev, CVP_BAR, 0);
	if (!conf->map) {
		dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
		conf->write_data = altera_cvp_write_data_config;
	}

	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
		 ALTERA_CVP_MGR_NAME, pci_name(pdev));

	mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
				   &altera_cvp_ops, conf);
	if (!mgr) {
		ret = -ENOMEM;
		goto err_unmap;
	}

	pci_set_drvdata(pdev, mgr);

	ret = fpga_mgr_register(mgr);
	if (ret)
		goto err_unmap;

	return 0;

err_unmap:
	if (conf->map)
		pci_iounmap(pdev, conf->map);
	pci_release_region(pdev, CVP_BAR);
err_disable:
	cmd &= ~PCI_COMMAND_MEMORY;
	pci_write_config_word(pdev, PCI_COMMAND, cmd);
	return ret;
}

static void altera_cvp_remove(struct pci_dev *pdev)
{
	struct fpga_manager *mgr = pci_get_drvdata(pdev);
	struct altera_cvp_conf *conf = mgr->priv;
	u16 cmd;

	fpga_mgr_unregister(mgr);
	if (conf->map)
		pci_iounmap(pdev, conf->map);
	pci_release_region(pdev, CVP_BAR);
	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
	cmd &= ~PCI_COMMAND_MEMORY;
	pci_write_config_word(pdev, PCI_COMMAND, cmd);
}

static int __init altera_cvp_init(void)
{
	int ret;

	ret = pci_register_driver(&altera_cvp_driver);
	if (ret)
		return ret;

	ret = driver_create_file(&altera_cvp_driver.driver,
				 &driver_attr_chkcfg);
	if (ret)
		pr_warn("Can't create sysfs chkcfg file\n");

	return 0;
}

static void __exit altera_cvp_exit(void)
{
	driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
	pci_unregister_driver(&altera_cvp_driver);
}

module_init(altera_cvp_init);
module_exit(altera_cvp_exit);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");
Commit	Line	Data
8e8e69d6	1	// SPDX-License-Identifier: GPL-2.0-only
34d1dc17 AG	2	/*
	3	* FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
	4	*
	5	* Copyright (C) 2017 DENX Software Engineering
	6	*
	7	* Anatolij Gustschin <agust@denx.de>
	8	*
34d1dc17 AG	9	* Manage Altera FPGA firmware using PCIe CvP.
	10	* Firmware must be in binary "rbf" format.
	11	*/
	12
	13	#include <linux/delay.h>
	14	#include <linux/device.h>
	15	#include <linux/fpga/fpga-mgr.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/sizes.h>
	19
	20	#define CVP_BAR 0 /* BAR used for data transfer in memory mode */
	21	#define CVP_DUMMY_WR 244 /* dummy writes to clear CvP state machine */
	22	#define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */
	23
	24	/* Vendor Specific Extended Capability Registers */
eb12511f	25	#define VSE_PCIE_EXT_CAP_ID 0x0
34d1dc17 AG	26	#define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */
34d1dc17 AG	27
eb12511f	28	#define VSE_CVP_STATUS 0x1c /* 32bit */
34d1dc17 AG	29	#define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */
	30	#define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */
	31	#define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */
	32	#define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */
	33	#define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */
	34	#define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */
	35
eb12511f	36	#define VSE_CVP_MODE_CTRL 0x20 /* 32bit */
34d1dc17 AG	37	#define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */
	38	#define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */
	39	#define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */
	40	#define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)
	41
eb12511f TT	42	#define VSE_CVP_DATA 0x28 /* 32bit */
eb12511f TT	43	#define VSE_CVP_PROG_CTRL 0x2c /* 32bit */
34d1dc17 AG	44	#define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
	45	#define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
	46
eb12511f	47	#define VSE_UNCOR_ERR_STATUS 0x34 /* 32bit */
34d1dc17 AG	48	#define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
	49
	50	#define DRV_NAME "altera-cvp"
	51	#define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
	52
	53	/* Optional CvP config error status check for debugging */
	54	static bool altera_cvp_chkcfg;
	55
	56	struct altera_cvp_conf {
	57	struct fpga_manager *mgr;
	58	struct pci_dev *pci_dev;
	59	void __iomem *map;
998c1de5 CP	60	void (write_data)(struct altera_cvp_conf conf,
998c1de5 CP	61	u32 data);
34d1dc17 AG	62	char mgr_name[64];
34d1dc17 AG	63	u8 numclks;
eb12511f	64	u32 vsec_offset;
34d1dc17 AG	65	};
34d1dc17 AG	66
eb12511f TT	67	static int altera_read_config_dword(struct altera_cvp_conf *conf,
	68	int where, u32 *val)
	69	{
	70	return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
	71	val);
	72	}
	73
	74	static int altera_write_config_dword(struct altera_cvp_conf *conf,
	75	int where, u32 val)
	76	{
	77	return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
	78	val);
	79	}
	80
34d1dc17 AG	81	static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
	82	{
	83	struct altera_cvp_conf *conf = mgr->priv;
	84	u32 status;
	85
eb12511f	86	altera_read_config_dword(conf, VSE_CVP_STATUS, &status);
34d1dc17 AG	87
	88	if (status & VSE_CVP_STATUS_CFG_DONE)
	89	return FPGA_MGR_STATE_OPERATING;
	90
	91	if (status & VSE_CVP_STATUS_CVP_EN)
	92	return FPGA_MGR_STATE_POWER_UP;
	93
	94	return FPGA_MGR_STATE_UNKNOWN;
	95	}
	96
	97	static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
	98	{
	99	writel(val, conf->map);
	100	}
	101
	102	static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
	103	{
eb12511f TT	104	pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
eb12511f TT	105	val);
34d1dc17 AG	106	}
	107
	108	/* switches between CvP clock and internal clock */
	109	static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
	110	{
	111	unsigned int i;
	112	u32 val;
	113
	114	/* set 1 CVP clock cycle for every CVP Data Register Write */
eb12511f	115	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
34d1dc17 AG	116	val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
34d1dc17 AG	117	val \|= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
eb12511f	118	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
34d1dc17 AG	119
	120	for (i = 0; i < CVP_DUMMY_WR; i++)
	121	conf->write_data(conf, 0); /* dummy data, could be any value */
	122	}
	123
	124	static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
	125	u32 status_val, int timeout_us)
	126	{
	127	unsigned int retries;
	128	u32 val;
	129
	130	retries = timeout_us / 10;
	131	if (timeout_us % 10)
	132	retries++;
	133
	134	do {
eb12511f	135	altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
34d1dc17 AG	136	if ((val & status_mask) == status_val)
	137	return 0;
	138
	139	/* use small usleep value to re-check and break early */
	140	usleep_range(10, 11);
	141	} while (--retries);
	142
	143	return -ETIMEDOUT;
	144	}
	145
	146	static int altera_cvp_teardown(struct fpga_manager *mgr,
	147	struct fpga_image_info *info)
	148	{
	149	struct altera_cvp_conf *conf = mgr->priv;
34d1dc17 AG	150	int ret;
	151	u32 val;
	152
	153	/* STEP 12 - reset START_XFER bit */
eb12511f	154	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
34d1dc17	155	val &= ~VSE_CVP_PROG_CTRL_START_XFER;
eb12511f	156	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
34d1dc17 AG	157
	158	/* STEP 13 - reset CVP_CONFIG bit */
	159	val &= ~VSE_CVP_PROG_CTRL_CONFIG;
eb12511f	160	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
34d1dc17 AG	161
	162	/*
	163	* STEP 14
	164	* - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
	165	* writes to the HIP
	166	*/
	167	altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */
	168
	169	/* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
	170	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10);
	171	if (ret)
	172	dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
	173
	174	return ret;
	175	}
	176
	177	static int altera_cvp_write_init(struct fpga_manager *mgr,
	178	struct fpga_image_info *info,
	179	const char *buf, size_t count)
	180	{
	181	struct altera_cvp_conf *conf = mgr->priv;
34d1dc17 AG	182	u32 iflags, val;
	183	int ret;
	184
	185	iflags = info ? info->flags : 0;
	186
	187	if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
	188	dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
	189	return -EINVAL;
	190	}
	191
	192	/* Determine allowed clock to data ratio */
	193	if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
	194	conf->numclks = 8; /* ratio for all compressed images */
	195	else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
	196	conf->numclks = 4; /* for uncompressed and encrypted images */
	197	else
	198	conf->numclks = 1; /* for uncompressed and unencrypted images */
	199
	200	/* STEP 1 - read CVP status and check CVP_EN flag */
eb12511f	201	altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
34d1dc17 AG	202	if (!(val & VSE_CVP_STATUS_CVP_EN)) {
	203	dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
	204	return -ENODEV;
	205	}
	206
	207	if (val & VSE_CVP_STATUS_CFG_RDY) {
	208	dev_warn(&mgr->dev, "CvP already started, teardown first\n");
	209	ret = altera_cvp_teardown(mgr, info);
	210	if (ret)
	211	return ret;
	212	}
	213
	214	/*
	215	* STEP 2
	216	* - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
	217	*/
	218	/* switch from fabric to PMA clock */
eb12511f	219	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
34d1dc17	220	val \|= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
eb12511f	221	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
34d1dc17 AG	222
34d1dc17 AG	223	/* set CVP mode */
eb12511f	224	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
34d1dc17	225	val \|= VSE_CVP_MODE_CTRL_CVP_MODE;
eb12511f	226	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
34d1dc17 AG	227
	228	/*
	229	* STEP 3
	230	* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
	231	*/
	232	altera_cvp_dummy_write(conf);
	233
	234	/* STEP 4 - set CVP_CONFIG bit */
eb12511f	235	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
34d1dc17 AG	236	/* request control block to begin transfer using CVP */
34d1dc17 AG	237	val \|= VSE_CVP_PROG_CTRL_CONFIG;
eb12511f	238	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
34d1dc17 AG	239
	240	/* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
	241	ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
	242	VSE_CVP_STATUS_CFG_RDY, 10);
	243	if (ret) {
	244	dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
	245	return ret;
	246	}
	247
	248	/*
	249	* STEP 6
	250	* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
	251	*/
	252	altera_cvp_dummy_write(conf);
	253
	254	/* STEP 7 - set START_XFER */
eb12511f	255	altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
34d1dc17	256	val \|= VSE_CVP_PROG_CTRL_START_XFER;
eb12511f	257	altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
34d1dc17 AG	258
34d1dc17 AG	259	/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
eb12511f	260	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
34d1dc17 AG	261	val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
34d1dc17 AG	262	val \|= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
eb12511f	263	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
34d1dc17 AG	264
	265	return 0;
	266	}
	267
	268	static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
	269	{
	270	struct altera_cvp_conf *conf = mgr->priv;
	271	u32 val;
	272
	273	/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
eb12511f	274	altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
34d1dc17 AG	275	if (val & VSE_CVP_STATUS_CFG_ERR) {
	276	dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
	277	bytes);
	278	return -EPROTO;
	279	}
	280	return 0;
	281	}
	282
	283	static int altera_cvp_write(struct fpga_manager mgr, const char buf,
	284	size_t count)
	285	{
	286	struct altera_cvp_conf *conf = mgr->priv;
	287	const u32 *data;
	288	size_t done, remaining;
	289	int status = 0;
	290	u32 mask;
	291
	292	/* STEP 9 - write 32-bit data from RBF file to CVP data register */
	293	data = (u32 *)buf;
	294	remaining = count;
	295	done = 0;
	296
	297	while (remaining >= 4) {
	298	conf->write_data(conf, *data++);
	299	done += 4;
	300	remaining -= 4;
	301
	302	/*
	303	* STEP 10 (optional) and STEP 11
	304	* - check error flag
	305	* - loop until data transfer completed
	306	* Config images can be huge (more than 40 MiB), so
	307	* only check after a new 4k data block has been written.
	308	* This reduces the number of checks and speeds up the
	309	* configuration process.
	310	*/
	311	if (altera_cvp_chkcfg && !(done % SZ_4K)) {
	312	status = altera_cvp_chk_error(mgr, done);
	313	if (status < 0)
	314	return status;
	315	}
	316	}
	317
	318	/* write up to 3 trailing bytes, if any */
	319	mask = BIT(remaining * 8) - 1;
	320	if (mask)
	321	conf->write_data(conf, *data & mask);
	322
	323	if (altera_cvp_chkcfg)
	324	status = altera_cvp_chk_error(mgr, count);
	325
	326	return status;
	327	}
	328
	329	static int altera_cvp_write_complete(struct fpga_manager *mgr,
	330	struct fpga_image_info *info)
	331	{
	332	struct altera_cvp_conf *conf = mgr->priv;
eb12511f	333	u32 mask, val;
34d1dc17	334	int ret;
34d1dc17 AG	335
	336	ret = altera_cvp_teardown(mgr, info);
	337	if (ret)
	338	return ret;
	339
	340	/* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
eb12511f	341	altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
34d1dc17 AG	342	if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
	343	dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
	344	return -EPROTO;
	345	}
	346
	347	/* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
eb12511f	348	altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
34d1dc17 AG	349	val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
34d1dc17 AG	350	val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
eb12511f	351	altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
34d1dc17 AG	352
	353	/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
	354	mask = VSE_CVP_STATUS_PLD_CLK_IN_USE \| VSE_CVP_STATUS_USERMODE;
	355	ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US);
	356	if (ret)
	357	dev_err(&mgr->dev, "PLD_CLK_IN_USE\|USERMODE timeout\n");
	358
	359	return ret;
	360	}
	361
	362	static const struct fpga_manager_ops altera_cvp_ops = {
	363	.state = altera_cvp_state,
	364	.write_init = altera_cvp_write_init,
	365	.write = altera_cvp_write,
	366	.write_complete = altera_cvp_write_complete,
	367	};
	368
55e001aa	369	static ssize_t chkcfg_show(struct device_driver dev, char buf)
34d1dc17 AG	370	{
	371	return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
	372	}
	373
55e001aa	374	static ssize_t chkcfg_store(struct device_driver drv, const char buf,
34d1dc17 AG	375	size_t count)
	376	{
	377	int ret;
	378
	379	ret = kstrtobool(buf, &altera_cvp_chkcfg);
	380	if (ret)
	381	return ret;
	382
	383	return count;
	384	}
	385
55e001aa	386	static DRIVER_ATTR_RW(chkcfg);
34d1dc17 AG	387
	388	static int altera_cvp_probe(struct pci_dev *pdev,
	389	const struct pci_device_id *dev_id);
	390	static void altera_cvp_remove(struct pci_dev *pdev);
	391
34d1dc17 AG	392	static struct pci_device_id altera_cvp_id_tbl[] = {
	393	{ PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
	394	{ }
	395	};
	396	MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);
	397
	398	static struct pci_driver altera_cvp_driver = {
	399	.name = DRV_NAME,
	400	.id_table = altera_cvp_id_tbl,
	401	.probe = altera_cvp_probe,
	402	.remove = altera_cvp_remove,
	403	};
	404
	405	static int altera_cvp_probe(struct pci_dev *pdev,
	406	const struct pci_device_id *dev_id)
	407	{
	408	struct altera_cvp_conf *conf;
7085e2a9	409	struct fpga_manager *mgr;
eb12511f	410	int ret, offset;
34d1dc17	411	u16 cmd, val;
68f60538	412	u32 regval;
eb12511f TT	413
	414	/* Discover the Vendor Specific Offset for this device */
	415	offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
	416	if (!offset) {
	417	dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
	418	return -ENODEV;
	419	}
34d1dc17 AG	420
	421	/*
	422	* First check if this is the expected FPGA device. PCI config
	423	* space access works without enabling the PCI device, memory
	424	* space access is enabled further down.
	425	*/
eb12511f	426	pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
34d1dc17 AG	427	if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
	428	dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
	429	return -ENODEV;
	430	}
	431
eb12511f	432	pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, &regval);
68f60538 AP	433	if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
	434	dev_err(&pdev->dev,
	435	"CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
	436	regval);
	437	return -ENODEV;
	438	}
	439
34d1dc17 AG	440	conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
	441	if (!conf)
	442	return -ENOMEM;
	443
eb12511f TT	444	conf->vsec_offset = offset;
eb12511f TT	445
34d1dc17 AG	446	/*
	447	* Enable memory BAR access. We cannot use pci_enable_device() here
	448	* because it will make the driver unusable with FPGA devices that
	449	* have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
	450	* platform. Such BARs will not have an assigned address range and
	451	* pci_enable_device() will fail, complaining about not claimed BAR,
	452	* even if the concerned BAR is not needed for FPGA configuration
	453	* at all. Thus, enable the device via PCI config space command.
	454	*/
	455	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
	456	if (!(cmd & PCI_COMMAND_MEMORY)) {
	457	cmd \|= PCI_COMMAND_MEMORY;
	458	pci_write_config_word(pdev, PCI_COMMAND, cmd);
	459	}
	460
	461	ret = pci_request_region(pdev, CVP_BAR, "CVP");
	462	if (ret) {
	463	dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
	464	goto err_disable;
	465	}
	466
	467	conf->pci_dev = pdev;
	468	conf->write_data = altera_cvp_write_data_iomem;
	469
	470	conf->map = pci_iomap(pdev, CVP_BAR, 0);
	471	if (!conf->map) {
	472	dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
	473	conf->write_data = altera_cvp_write_data_config;
	474	}
	475
	476	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
	477	ALTERA_CVP_MGR_NAME, pci_name(pdev));
	478
084181fe AT	479	mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
084181fe AT	480	&altera_cvp_ops, conf);
122c5770 CJ	481	if (!mgr) {
	482	ret = -ENOMEM;
	483	goto err_unmap;
	484	}
7085e2a9 AT	485
	486	pci_set_drvdata(pdev, mgr);
	487
	488	ret = fpga_mgr_register(mgr);
084181fe	489	if (ret)
34d1dc17 AG	490	goto err_unmap;
34d1dc17 AG	491
34d1dc17 AG	492	return 0;
	493
	494	err_unmap:
187fade8 AG	495	if (conf->map)
187fade8 AG	496	pci_iounmap(pdev, conf->map);
34d1dc17 AG	497	pci_release_region(pdev, CVP_BAR);
	498	err_disable:
	499	cmd &= ~PCI_COMMAND_MEMORY;
	500	pci_write_config_word(pdev, PCI_COMMAND, cmd);
	501	return ret;
	502	}
	503
	504	static void altera_cvp_remove(struct pci_dev *pdev)
	505	{
	506	struct fpga_manager *mgr = pci_get_drvdata(pdev);
	507	struct altera_cvp_conf *conf = mgr->priv;
	508	u16 cmd;
	509
7085e2a9	510	fpga_mgr_unregister(mgr);
187fade8 AG	511	if (conf->map)
187fade8 AG	512	pci_iounmap(pdev, conf->map);
34d1dc17 AG	513	pci_release_region(pdev, CVP_BAR);
	514	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
	515	cmd &= ~PCI_COMMAND_MEMORY;
	516	pci_write_config_word(pdev, PCI_COMMAND, cmd);
	517	}
	518
30522a95 AG	519	static int __init altera_cvp_init(void)
	520	{
	521	int ret;
	522
	523	ret = pci_register_driver(&altera_cvp_driver);
	524	if (ret)
	525	return ret;
	526
	527	ret = driver_create_file(&altera_cvp_driver.driver,
	528	&driver_attr_chkcfg);
	529	if (ret)
	530	pr_warn("Can't create sysfs chkcfg file\n");
	531
	532	return 0;
	533	}
	534
	535	static void __exit altera_cvp_exit(void)
	536	{
	537	driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
	538	pci_unregister_driver(&altera_cvp_driver);
	539	}
	540
	541	module_init(altera_cvp_init);
	542	module_exit(altera_cvp_exit);
34d1dc17 AG	543
	544	MODULE_LICENSE("GPL v2");
	545	MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
	546	MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");