[linux-2.6-block.git] / drivers / fpga / Makefile

# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the fpga framework and fpga manager drivers.
#

# Core FPGA Manager Framework
obj-$(CONFIG_FPGA)			+= fpga-mgr.o

# FPGA Manager Drivers
obj-$(CONFIG_FPGA_MGR_ALTERA_CVP)	+= altera-cvp.o
obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI)	+= machxo2-spi.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC)	+= stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o

# FPGA Bridge Drivers
obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)	+= altera-freeze-bridge.o
obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o

# High Level Interfaces
obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o

# FPGA Device Feature List Support
obj-$(CONFIG_FPGA_DFL)			+= dfl.o
obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
obj-$(CONFIG_FPGA_DFL_FME_MGR)		+= dfl-fme-mgr.o
obj-$(CONFIG_FPGA_DFL_FME_BRIDGE)	+= dfl-fme-br.o
obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
obj-$(CONFIG_FPGA_DFL_AFU)		+= dfl-afu.o

dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o

# Drivers for FPGAs which implement DFL
obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
Commit	Line	Data
b2441318	1	# SPDX-License-Identifier: GPL-2.0
6a8c3be7 AT	2	#
	3	# Makefile for the fpga framework and fpga manager drivers.
	4	#
	5
	6	# Core FPGA Manager Framework
	7	obj-$(CONFIG_FPGA) += fpga-mgr.o
	8
	9	# FPGA Manager Drivers
34d1dc17	10	obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
5692fae0	11	obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
21f8ba2e	12	obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
88fb3a00	13	obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
fab6266e	14	obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
acbb910a	15	obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
e7eef1d7	16	obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
4348f7e2	17	obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
061c97d1	18	obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
37784706	19	obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
d201cc17	20	obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
5b73cb5b	21	obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
21aeda95 AT	22
	23	# FPGA Bridge Drivers
	24	obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
e5f8efa5	25	obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
ca24a648	26	obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
7e961c12	27	obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
0fa20cdf AT	28
	29	# High Level Interfaces
	30	obj-$(CONFIG_FPGA_REGION) += fpga-region.o
ef3acdd8	31	obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
543be3d8 WH	32
	33	# FPGA Device Feature List Support
	34	obj-$(CONFIG_FPGA_DFL) += dfl.o
322ddebe	35	obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
af275ec6	36	obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
de892dff	37	obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
bb61b9be	38	obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
1a1527cf	39	obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
322ddebe	40
29de7624	41	dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
fa8dda1e	42	dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
72ddd9f3 ZY	43
	44	# Drivers for FPGAs which implement DFL
	45	obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o