Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
6a8c3be7 AT |
2 | # |
3 | # Makefile for the fpga framework and fpga manager drivers. | |
4 | # | |
5 | ||
6 | # Core FPGA Manager Framework | |
7 | obj-$(CONFIG_FPGA) += fpga-mgr.o | |
8 | ||
9 | # FPGA Manager Drivers | |
34d1dc17 | 10 | obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o |
5692fae0 | 11 | obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o |
21f8ba2e | 12 | obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o |
88fb3a00 | 13 | obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o |
fab6266e | 14 | obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o |
acbb910a | 15 | obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o |
e7eef1d7 | 16 | obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o |
4348f7e2 | 17 | obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o |
061c97d1 | 18 | obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o |
37784706 | 19 | obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o |
c09f7471 | 20 | obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o |
baf7d27d | 21 | obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o |
5f8d4a90 | 22 | obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o |
463dd43b IB |
23 | obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) += lattice-sysconfig.o |
24 | obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) += lattice-sysconfig-spi.o | |
baf7d27d NM |
25 | obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o |
26 | obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o | |
21aeda95 | 27 | |
bdf86d0e RW |
28 | # FPGA Secure Update Drivers |
29 | obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) += intel-m10-bmc-sec-update.o | |
30 | ||
21aeda95 AT |
31 | # FPGA Bridge Drivers |
32 | obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o | |
e5f8efa5 | 33 | obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o |
ca24a648 | 34 | obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o |
7e961c12 | 35 | obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o |
0fa20cdf AT |
36 | |
37 | # High Level Interfaces | |
38 | obj-$(CONFIG_FPGA_REGION) += fpga-region.o | |
ef3acdd8 | 39 | obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o |
543be3d8 WH |
40 | |
41 | # FPGA Device Feature List Support | |
42 | obj-$(CONFIG_FPGA_DFL) += dfl.o | |
322ddebe | 43 | obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o |
af275ec6 | 44 | obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o |
de892dff | 45 | obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o |
bb61b9be | 46 | obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o |
1a1527cf | 47 | obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o |
322ddebe | 48 | |
cb3c2c47 | 49 | dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o |
724142f8 | 50 | dfl-fme-objs += dfl-fme-perf.o |
fa8dda1e | 51 | dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o |
44d24753 | 52 | dfl-afu-objs += dfl-afu-error.o |
72ddd9f3 | 53 | |
56172ab3 XY |
54 | obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o |
55 | ||
72ddd9f3 ZY |
56 | # Drivers for FPGAs which implement DFL |
57 | obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o |