Commit | Line | Data |
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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
6a8c3be7 AT |
2 | # |
3 | # Makefile for the fpga framework and fpga manager drivers. | |
4 | # | |
5 | ||
6 | # Core FPGA Manager Framework | |
7 | obj-$(CONFIG_FPGA) += fpga-mgr.o | |
8 | ||
9 | # FPGA Manager Drivers | |
34d1dc17 | 10 | obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o |
5692fae0 | 11 | obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o |
21f8ba2e | 12 | obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o |
fab6266e | 13 | obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o |
acbb910a | 14 | obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o |
4348f7e2 | 15 | obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o |
061c97d1 | 16 | obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o |
37784706 | 17 | obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o |
d201cc17 | 18 | obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o |
5b73cb5b | 19 | obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o |
21aeda95 AT |
20 | |
21 | # FPGA Bridge Drivers | |
22 | obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o | |
e5f8efa5 | 23 | obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o |
ca24a648 | 24 | obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o |
7e961c12 | 25 | obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o |
0fa20cdf AT |
26 | |
27 | # High Level Interfaces | |
28 | obj-$(CONFIG_FPGA_REGION) += fpga-region.o | |
ef3acdd8 | 29 | obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o |