Commit | Line | Data |
---|---|---|
6a8c3be7 AT |
1 | # |
2 | # FPGA framework configuration | |
3 | # | |
4 | ||
50fa0285 | 5 | menuconfig FPGA |
6a8c3be7 AT |
6 | tristate "FPGA Configuration Framework" |
7 | help | |
8 | Say Y here if you want support for configuring FPGAs from the | |
9 | kernel. The FPGA framework adds a FPGA manager class and FPGA | |
10 | manager drivers. | |
11 | ||
fab6266e AT |
12 | if FPGA |
13 | ||
84e93f1d AT |
14 | config FPGA_MGR_SOCFPGA |
15 | tristate "Altera SOCFPGA FPGA Manager" | |
16 | depends on ARCH_SOCFPGA || COMPILE_TEST | |
0fa20cdf | 17 | help |
84e93f1d | 18 | FPGA manager driver support for Altera SOCFPGA. |
ef3acdd8 | 19 | |
84e93f1d AT |
20 | config FPGA_MGR_SOCFPGA_A10 |
21 | tristate "Altera SoCFPGA Arria10" | |
22 | depends on ARCH_SOCFPGA || COMPILE_TEST | |
23 | select REGMAP_MMIO | |
ef3acdd8 | 24 | help |
84e93f1d | 25 | FPGA manager driver support for Altera Arria10 SoCFPGA. |
0fa20cdf | 26 | |
84e93f1d AT |
27 | config ALTERA_PR_IP_CORE |
28 | tristate "Altera Partial Reconfiguration IP Core" | |
29 | help | |
30 | Core driver support for Altera Partial Reconfiguration IP component | |
21f8ba2e | 31 | |
84e93f1d AT |
32 | config ALTERA_PR_IP_CORE_PLAT |
33 | tristate "Platform support of Altera Partial Reconfiguration IP Core" | |
34 | depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM | |
34d1dc17 | 35 | help |
84e93f1d AT |
36 | Platform driver support for Altera Partial Reconfiguration IP |
37 | component | |
34d1dc17 | 38 | |
5692fae0 JC |
39 | config FPGA_MGR_ALTERA_PS_SPI |
40 | tristate "Altera FPGA Passive Serial over SPI" | |
41 | depends on SPI | |
42 | help | |
43 | FPGA manager driver support for Altera Arria/Cyclone/Stratix | |
44 | using the passive serial interface over SPI. | |
45 | ||
84e93f1d AT |
46 | config FPGA_MGR_ALTERA_CVP |
47 | tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" | |
48 | depends on PCI | |
acbb910a | 49 | help |
84e93f1d AT |
50 | FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V |
51 | and Arria 10 Altera FPGAs using the CvP interface over PCIe. | |
acbb910a | 52 | |
84e93f1d AT |
53 | config FPGA_MGR_ZYNQ_FPGA |
54 | tristate "Xilinx Zynq FPGA" | |
55 | depends on ARCH_ZYNQ || COMPILE_TEST | |
4348f7e2 | 56 | help |
84e93f1d | 57 | FPGA manager driver support for Xilinx Zynq FPGAs. |
4348f7e2 | 58 | |
061c97d1 AG |
59 | config FPGA_MGR_XILINX_SPI |
60 | tristate "Xilinx Configuration over Slave Serial (SPI)" | |
61 | depends on SPI | |
62 | help | |
63 | FPGA manager driver support for Xilinx FPGA configuration | |
64 | over slave serial interface. | |
65 | ||
84e93f1d AT |
66 | config FPGA_MGR_ICE40_SPI |
67 | tristate "Lattice iCE40 SPI" | |
68 | depends on OF && SPI | |
37784706 | 69 | help |
84e93f1d AT |
70 | FPGA manager driver support for Lattice iCE40 FPGAs over SPI. |
71 | ||
88fb3a00 PP |
72 | config FPGA_MGR_MACHXO2_SPI |
73 | tristate "Lattice MachXO2 SPI" | |
74 | depends on SPI | |
75 | help | |
76 | FPGA manager driver support for Lattice MachXO2 configuration | |
77 | over slave SPI interface. | |
78 | ||
84e93f1d AT |
79 | config FPGA_MGR_TS73XX |
80 | tristate "Technologic Systems TS-73xx SBC FPGA Manager" | |
81 | depends on ARCH_EP93XX && MACH_TS72XX | |
82 | help | |
83 | FPGA manager driver support for the Altera Cyclone II FPGA | |
84 | present on the TS-73xx SBC boards. | |
37784706 | 85 | |
21aeda95 AT |
86 | config FPGA_BRIDGE |
87 | tristate "FPGA Bridge Framework" | |
21aeda95 AT |
88 | help |
89 | Say Y here if you want to support bridges connected between host | |
90 | processors and FPGAs or between FPGAs. | |
91 | ||
e5f8efa5 AT |
92 | config SOCFPGA_FPGA_BRIDGE |
93 | tristate "Altera SoCFPGA FPGA Bridges" | |
94 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
95 | help | |
96 | Say Y to enable drivers for FPGA bridges for Altera SOCFPGA | |
97 | devices. | |
98 | ||
ca24a648 AT |
99 | config ALTERA_FREEZE_BRIDGE |
100 | tristate "Altera FPGA Freeze Bridge" | |
101 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
102 | help | |
103 | Say Y to enable drivers for Altera FPGA Freeze bridges. A | |
104 | freeze bridge is a bridge that exists in the FPGA fabric to | |
105 | isolate one region of the FPGA from the busses while that | |
106 | region is being reprogrammed. | |
107 | ||
7e961c12 MF |
108 | config XILINX_PR_DECOUPLER |
109 | tristate "Xilinx LogiCORE PR Decoupler" | |
110 | depends on FPGA_BRIDGE | |
111 | depends on HAS_IOMEM | |
112 | help | |
113 | Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. | |
114 | The PR Decoupler exists in the FPGA fabric to isolate one | |
115 | region of the FPGA from the busses while that region is | |
116 | being reprogrammed during partial reconfig. | |
117 | ||
84e93f1d AT |
118 | config FPGA_REGION |
119 | tristate "FPGA Region" | |
120 | depends on FPGA_BRIDGE | |
121 | help | |
122 | FPGA Region common code. A FPGA Region controls a FPGA Manager | |
123 | and the FPGA Bridges associated with either a reconfigurable | |
124 | region of an FPGA or a whole FPGA. | |
125 | ||
126 | config OF_FPGA_REGION | |
127 | tristate "FPGA Region Device Tree Overlay Support" | |
128 | depends on OF && FPGA_REGION | |
129 | help | |
130 | Support for loading FPGA images by applying a Device Tree | |
131 | overlay. | |
132 | ||
fab6266e | 133 | endif # FPGA |