[linux-2.6-block.git] / drivers / fpga / Kconfig

#
# FPGA framework configuration
#

menuconfig FPGA
	tristate "FPGA Configuration Framework"
	help
	  Say Y here if you want support for configuring FPGAs from the
	  kernel.  The FPGA framework adds a FPGA manager class and FPGA
	  manager drivers.

if FPGA

config FPGA_MGR_SOCFPGA
	tristate "Altera SOCFPGA FPGA Manager"
	depends on ARCH_SOCFPGA || COMPILE_TEST
	help
	  FPGA manager driver support for Altera SOCFPGA.

config FPGA_MGR_SOCFPGA_A10
	tristate "Altera SoCFPGA Arria10"
	depends on ARCH_SOCFPGA || COMPILE_TEST
	select REGMAP_MMIO
	help
	  FPGA manager driver support for Altera Arria10 SoCFPGA.

config ALTERA_PR_IP_CORE
        tristate "Altera Partial Reconfiguration IP Core"
        help
          Core driver support for Altera Partial Reconfiguration IP component

config ALTERA_PR_IP_CORE_PLAT
	tristate "Platform support of Altera Partial Reconfiguration IP Core"
	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
	help
	  Platform driver support for Altera Partial Reconfiguration IP
	  component

config FPGA_MGR_ALTERA_PS_SPI
	tristate "Altera FPGA Passive Serial over SPI"
	depends on SPI
	help
	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
	  using the passive serial interface over SPI.

config FPGA_MGR_ALTERA_CVP
	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
	depends on PCI
	help
	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
	  and Arria 10 Altera FPGAs using the CvP interface over PCIe.

config FPGA_MGR_ZYNQ_FPGA
	tristate "Xilinx Zynq FPGA"
	depends on ARCH_ZYNQ || COMPILE_TEST
	help
	  FPGA manager driver support for Xilinx Zynq FPGAs.

config FPGA_MGR_STRATIX10_SOC
	tristate "Intel Stratix10 SoC FPGA Manager"
	depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
	help
	  FPGA manager driver support for the Intel Stratix10 SoC.

config FPGA_MGR_XILINX_SPI
	tristate "Xilinx Configuration over Slave Serial (SPI)"
	depends on SPI
	help
	  FPGA manager driver support for Xilinx FPGA configuration
	  over slave serial interface.

config FPGA_MGR_ICE40_SPI
	tristate "Lattice iCE40 SPI"
	depends on OF && SPI
	help
	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.

config FPGA_MGR_MACHXO2_SPI
	tristate "Lattice MachXO2 SPI"
	depends on SPI
	help
	  FPGA manager driver support for Lattice MachXO2 configuration
	  over slave SPI interface.

config FPGA_MGR_TS73XX
	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
	depends on ARCH_EP93XX && MACH_TS72XX
	help
	  FPGA manager driver support for the Altera Cyclone II FPGA
	  present on the TS-73xx SBC boards.

config FPGA_BRIDGE
	tristate "FPGA Bridge Framework"
	help
	  Say Y here if you want to support bridges connected between host
	  processors and FPGAs or between FPGAs.

config SOCFPGA_FPGA_BRIDGE
	tristate "Altera SoCFPGA FPGA Bridges"
	depends on ARCH_SOCFPGA && FPGA_BRIDGE
	help
	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
	  devices.

config ALTERA_FREEZE_BRIDGE
	tristate "Altera FPGA Freeze Bridge"
	depends on ARCH_SOCFPGA && FPGA_BRIDGE
	help
	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
	  freeze bridge is a bridge that exists in the FPGA fabric to
	  isolate one region of the FPGA from the busses while that
	  region is being reprogrammed.

config XILINX_PR_DECOUPLER
	tristate "Xilinx LogiCORE PR Decoupler"
	depends on FPGA_BRIDGE
	depends on HAS_IOMEM
	help
	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
	  The PR Decoupler exists in the FPGA fabric to isolate one
	  region of the FPGA from the busses while that region is
	  being reprogrammed during partial reconfig.

config FPGA_REGION
	tristate "FPGA Region"
	depends on FPGA_BRIDGE
	help
	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
	  and the FPGA Bridges associated with either a reconfigurable
	  region of an FPGA or a whole FPGA.

config OF_FPGA_REGION
	tristate "FPGA Region Device Tree Overlay Support"
	depends on OF && FPGA_REGION
	help
	  Support for loading FPGA images by applying a Device Tree
	  overlay.

config FPGA_DFL
	tristate "FPGA Device Feature List (DFL) support"
	select FPGA_BRIDGE
	select FPGA_REGION
	help
	  Device Feature List (DFL) defines a feature list structure that
	  creates a linked list of feature headers within the MMIO space
	  to provide an extensible way of adding features for FPGA.
	  Driver can walk through the feature headers to enumerate feature
	  devices (e.g. FPGA Management Engine, Port and Accelerator
	  Function Unit) and their private features for target FPGA devices.

	  Select this option to enable common support for Field-Programmable
	  Gate Array (FPGA) solutions which implement Device Feature List.
	  It provides enumeration APIs and feature device infrastructure.

config FPGA_DFL_FME
	tristate "FPGA DFL FME Driver"
	depends on FPGA_DFL
	help
	  The FPGA Management Engine (FME) is a feature device implemented
	  under Device Feature List (DFL) framework. Select this option to
	  enable the platform device driver for FME which implements all
	  FPGA platform level management features. There shall be one FME
	  per DFL based FPGA device.

config FPGA_DFL_FME_MGR
	tristate "FPGA DFL FME Manager Driver"
	depends on FPGA_DFL_FME && HAS_IOMEM
	help
	  Say Y to enable FPGA Manager driver for FPGA Management Engine.

config FPGA_DFL_FME_BRIDGE
	tristate "FPGA DFL FME Bridge Driver"
	depends on FPGA_DFL_FME && HAS_IOMEM
	help
	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.

config FPGA_DFL_FME_REGION
	tristate "FPGA DFL FME Region Driver"
	depends on FPGA_DFL_FME && HAS_IOMEM
	help
	  Say Y to enable FPGA Region driver for FPGA Management Engine.

config FPGA_DFL_AFU
	tristate "FPGA DFL AFU Driver"
	depends on FPGA_DFL
	help
	  This is the driver for FPGA Accelerated Function Unit (AFU) which
	  implements AFU and Port management features. A User AFU connects
	  to the FPGA infrastructure via a Port. There may be more than one
	  Port/AFU per DFL based FPGA device.

config FPGA_DFL_PCI
	tristate "FPGA DFL PCIe Device Driver"
	depends on PCI && FPGA_DFL
	help
	  Select this option to enable PCIe driver for PCIe-based
	  Field-Programmable Gate Array (FPGA) solutions which implement
	  the Device Feature List (DFL). This driver provides interfaces
	  for userspace applications to configure, enumerate, open and access
	  FPGA accelerators on the FPGA DFL devices, enables system level
	  management functions such as FPGA partial reconfiguration, power
	  management and virtualization with DFL framework and DFL feature
	  device drivers.

	  To compile this as a module, choose M here.

endif # FPGA
Commit	Line	Data
6a8c3be7 AT	1	#
	2	# FPGA framework configuration
	3	#
	4
50fa0285	5	menuconfig FPGA
6a8c3be7 AT	6	tristate "FPGA Configuration Framework"
	7	help
	8	Say Y here if you want support for configuring FPGAs from the
	9	kernel. The FPGA framework adds a FPGA manager class and FPGA
	10	manager drivers.
	11
fab6266e AT	12	if FPGA
fab6266e AT	13
84e93f1d AT	14	config FPGA_MGR_SOCFPGA
	15	tristate "Altera SOCFPGA FPGA Manager"
	16	depends on ARCH_SOCFPGA \|\| COMPILE_TEST
0fa20cdf	17	help
84e93f1d	18	FPGA manager driver support for Altera SOCFPGA.
ef3acdd8	19
84e93f1d AT	20	config FPGA_MGR_SOCFPGA_A10
	21	tristate "Altera SoCFPGA Arria10"
	22	depends on ARCH_SOCFPGA \|\| COMPILE_TEST
	23	select REGMAP_MMIO
ef3acdd8	24	help
84e93f1d	25	FPGA manager driver support for Altera Arria10 SoCFPGA.
0fa20cdf	26
84e93f1d AT	27	config ALTERA_PR_IP_CORE
	28	tristate "Altera Partial Reconfiguration IP Core"
	29	help
	30	Core driver support for Altera Partial Reconfiguration IP component
21f8ba2e	31
84e93f1d AT	32	config ALTERA_PR_IP_CORE_PLAT
	33	tristate "Platform support of Altera Partial Reconfiguration IP Core"
	34	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
34d1dc17	35	help
84e93f1d AT	36	Platform driver support for Altera Partial Reconfiguration IP
84e93f1d AT	37	component
34d1dc17	38
5692fae0 JC	39	config FPGA_MGR_ALTERA_PS_SPI
	40	tristate "Altera FPGA Passive Serial over SPI"
	41	depends on SPI
	42	help
	43	FPGA manager driver support for Altera Arria/Cyclone/Stratix
	44	using the passive serial interface over SPI.
	45
84e93f1d AT	46	config FPGA_MGR_ALTERA_CVP
	47	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
	48	depends on PCI
acbb910a	49	help
84e93f1d AT	50	FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
84e93f1d AT	51	and Arria 10 Altera FPGAs using the CvP interface over PCIe.
acbb910a	52
84e93f1d AT	53	config FPGA_MGR_ZYNQ_FPGA
	54	tristate "Xilinx Zynq FPGA"
	55	depends on ARCH_ZYNQ \|\| COMPILE_TEST
4348f7e2	56	help
84e93f1d	57	FPGA manager driver support for Xilinx Zynq FPGAs.
4348f7e2	58
e7eef1d7 AT	59	config FPGA_MGR_STRATIX10_SOC
	60	tristate "Intel Stratix10 SoC FPGA Manager"
	61	depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
	62	help
	63	FPGA manager driver support for the Intel Stratix10 SoC.
	64
061c97d1 AG	65	config FPGA_MGR_XILINX_SPI
	66	tristate "Xilinx Configuration over Slave Serial (SPI)"
	67	depends on SPI
	68	help
	69	FPGA manager driver support for Xilinx FPGA configuration
	70	over slave serial interface.
	71
84e93f1d AT	72	config FPGA_MGR_ICE40_SPI
	73	tristate "Lattice iCE40 SPI"
	74	depends on OF && SPI
37784706	75	help
84e93f1d AT	76	FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
84e93f1d AT	77
88fb3a00 PP	78	config FPGA_MGR_MACHXO2_SPI
	79	tristate "Lattice MachXO2 SPI"
	80	depends on SPI
	81	help
	82	FPGA manager driver support for Lattice MachXO2 configuration
	83	over slave SPI interface.
	84
84e93f1d AT	85	config FPGA_MGR_TS73XX
	86	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
	87	depends on ARCH_EP93XX && MACH_TS72XX
	88	help
	89	FPGA manager driver support for the Altera Cyclone II FPGA
	90	present on the TS-73xx SBC boards.
37784706	91
21aeda95 AT	92	config FPGA_BRIDGE
21aeda95 AT	93	tristate "FPGA Bridge Framework"
21aeda95 AT	94	help
	95	Say Y here if you want to support bridges connected between host
	96	processors and FPGAs or between FPGAs.
	97
e5f8efa5 AT	98	config SOCFPGA_FPGA_BRIDGE
	99	tristate "Altera SoCFPGA FPGA Bridges"
	100	depends on ARCH_SOCFPGA && FPGA_BRIDGE
	101	help
	102	Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
	103	devices.
	104
ca24a648 AT	105	config ALTERA_FREEZE_BRIDGE
	106	tristate "Altera FPGA Freeze Bridge"
	107	depends on ARCH_SOCFPGA && FPGA_BRIDGE
	108	help
	109	Say Y to enable drivers for Altera FPGA Freeze bridges. A
	110	freeze bridge is a bridge that exists in the FPGA fabric to
	111	isolate one region of the FPGA from the busses while that
	112	region is being reprogrammed.
	113
7e961c12 MF	114	config XILINX_PR_DECOUPLER
	115	tristate "Xilinx LogiCORE PR Decoupler"
	116	depends on FPGA_BRIDGE
	117	depends on HAS_IOMEM
	118	help
	119	Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
	120	The PR Decoupler exists in the FPGA fabric to isolate one
	121	region of the FPGA from the busses while that region is
	122	being reprogrammed during partial reconfig.
	123
84e93f1d AT	124	config FPGA_REGION
	125	tristate "FPGA Region"
	126	depends on FPGA_BRIDGE
	127	help
	128	FPGA Region common code. A FPGA Region controls a FPGA Manager
	129	and the FPGA Bridges associated with either a reconfigurable
	130	region of an FPGA or a whole FPGA.
	131
	132	config OF_FPGA_REGION
	133	tristate "FPGA Region Device Tree Overlay Support"
	134	depends on OF && FPGA_REGION
	135	help
	136	Support for loading FPGA images by applying a Device Tree
	137	overlay.
	138
543be3d8 WH	139	config FPGA_DFL
	140	tristate "FPGA Device Feature List (DFL) support"
	141	select FPGA_BRIDGE
	142	select FPGA_REGION
	143	help
	144	Device Feature List (DFL) defines a feature list structure that
	145	creates a linked list of feature headers within the MMIO space
	146	to provide an extensible way of adding features for FPGA.
	147	Driver can walk through the feature headers to enumerate feature
	148	devices (e.g. FPGA Management Engine, Port and Accelerator
	149	Function Unit) and their private features for target FPGA devices.
	150
	151	Select this option to enable common support for Field-Programmable
	152	Gate Array (FPGA) solutions which implement Device Feature List.
	153	It provides enumeration APIs and feature device infrastructure.
	154
322ddebe KL	155	config FPGA_DFL_FME
	156	tristate "FPGA DFL FME Driver"
	157	depends on FPGA_DFL
	158	help
	159	The FPGA Management Engine (FME) is a feature device implemented
	160	under Device Feature List (DFL) framework. Select this option to
	161	enable the platform device driver for FME which implements all
	162	FPGA platform level management features. There shall be one FME
	163	per DFL based FPGA device.
	164
af275ec6 WH	165	config FPGA_DFL_FME_MGR
	166	tristate "FPGA DFL FME Manager Driver"
	167	depends on FPGA_DFL_FME && HAS_IOMEM
	168	help
	169	Say Y to enable FPGA Manager driver for FPGA Management Engine.
	170
de892dff WH	171	config FPGA_DFL_FME_BRIDGE
	172	tristate "FPGA DFL FME Bridge Driver"
	173	depends on FPGA_DFL_FME && HAS_IOMEM
	174	help
	175	Say Y to enable FPGA Bridge driver for FPGA Management Engine.
	176
bb61b9be WH	177	config FPGA_DFL_FME_REGION
	178	tristate "FPGA DFL FME Region Driver"
	179	depends on FPGA_DFL_FME && HAS_IOMEM
	180	help
	181	Say Y to enable FPGA Region driver for FPGA Management Engine.
	182
1a1527cf WH	183	config FPGA_DFL_AFU
	184	tristate "FPGA DFL AFU Driver"
	185	depends on FPGA_DFL
	186	help
	187	This is the driver for FPGA Accelerated Function Unit (AFU) which
	188	implements AFU and Port management features. A User AFU connects
	189	to the FPGA infrastructure via a Port. There may be more than one
	190	Port/AFU per DFL based FPGA device.
	191
72ddd9f3 ZY	192	config FPGA_DFL_PCI
	193	tristate "FPGA DFL PCIe Device Driver"
	194	depends on PCI && FPGA_DFL
	195	help
	196	Select this option to enable PCIe driver for PCIe-based
	197	Field-Programmable Gate Array (FPGA) solutions which implement
	198	the Device Feature List (DFL). This driver provides interfaces
	199	for userspace applications to configure, enumerate, open and access
	200	FPGA accelerators on the FPGA DFL devices, enables system level
	201	management functions such as FPGA partial reconfiguration, power
	202	management and virtualization with DFL framework and DFL feature
	203	device drivers.
	204
	205	To compile this as a module, choose M here.
	206
fab6266e	207	endif # FPGA