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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5443cc5f | 2 | /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. |
2ce76a6a | 3 | * Copyright (C) 2015 Linaro Ltd. |
2a1eb58a | 4 | */ |
d0f6fa7b | 5 | #include <linux/platform_device.h> |
dea85242 | 6 | #include <linux/init.h> |
b6a1dfbc KG |
7 | #include <linux/cpumask.h> |
8 | #include <linux/export.h> | |
f01e90fe | 9 | #include <linux/dma-mapping.h> |
8c1b7dc9 | 10 | #include <linux/module.h> |
b6a1dfbc | 11 | #include <linux/types.h> |
916f743d | 12 | #include <linux/qcom_scm.h> |
d0f6fa7b | 13 | #include <linux/of.h> |
8c1b7dc9 | 14 | #include <linux/of_address.h> |
d0f6fa7b AG |
15 | #include <linux/of_platform.h> |
16 | #include <linux/clk.h> | |
dd4fe5b2 | 17 | #include <linux/reset-controller.h> |
57d3b816 | 18 | #include <linux/arm-smccc.h> |
2a1eb58a | 19 | |
b6a1dfbc | 20 | #include "qcom_scm.h" |
a353e4a0 | 21 | |
8c1b7dc9 BA |
22 | static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); |
23 | module_param(download_mode, bool, 0); | |
24 | ||
ab0822d5 | 25 | #define SCM_HAS_CORE_CLK BIT(0) |
26 | #define SCM_HAS_IFACE_CLK BIT(1) | |
27 | #define SCM_HAS_BUS_CLK BIT(2) | |
28 | ||
d0f6fa7b AG |
29 | struct qcom_scm { |
30 | struct device *dev; | |
31 | struct clk *core_clk; | |
32 | struct clk *iface_clk; | |
33 | struct clk *bus_clk; | |
dd4fe5b2 | 34 | struct reset_controller_dev reset; |
8c1b7dc9 BA |
35 | |
36 | u64 dload_mode_addr; | |
d0f6fa7b AG |
37 | }; |
38 | ||
d82bd359 AKD |
39 | struct qcom_scm_current_perm_info { |
40 | __le32 vmid; | |
41 | __le32 perm; | |
42 | __le64 ctx; | |
43 | __le32 ctx_size; | |
44 | __le32 unused; | |
45 | }; | |
46 | ||
47 | struct qcom_scm_mem_map_info { | |
48 | __le64 mem_addr; | |
49 | __le64 mem_size; | |
50 | }; | |
51 | ||
57d3b816 EB |
52 | #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 |
53 | #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 | |
54 | #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 | |
55 | #define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20 | |
56 | ||
57 | #define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04 | |
58 | #define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02 | |
59 | #define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10 | |
60 | #define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40 | |
61 | ||
62 | struct qcom_scm_wb_entry { | |
63 | int flag; | |
64 | void *entry; | |
65 | }; | |
66 | ||
67 | static struct qcom_scm_wb_entry qcom_scm_wb[] = { | |
68 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 }, | |
69 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 }, | |
70 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 }, | |
71 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 }, | |
72 | }; | |
73 | ||
9a434cee EB |
74 | static const char *qcom_scm_convention_names[] = { |
75 | [SMC_CONVENTION_UNKNOWN] = "unknown", | |
76 | [SMC_CONVENTION_ARM_32] = "smc arm 32", | |
77 | [SMC_CONVENTION_ARM_64] = "smc arm 64", | |
78 | [SMC_CONVENTION_LEGACY] = "smc legacy", | |
79 | }; | |
80 | ||
d0f6fa7b AG |
81 | static struct qcom_scm *__scm; |
82 | ||
83 | static int qcom_scm_clk_enable(void) | |
84 | { | |
85 | int ret; | |
86 | ||
87 | ret = clk_prepare_enable(__scm->core_clk); | |
88 | if (ret) | |
89 | goto bail; | |
90 | ||
91 | ret = clk_prepare_enable(__scm->iface_clk); | |
92 | if (ret) | |
93 | goto disable_core; | |
94 | ||
95 | ret = clk_prepare_enable(__scm->bus_clk); | |
96 | if (ret) | |
97 | goto disable_iface; | |
98 | ||
99 | return 0; | |
100 | ||
101 | disable_iface: | |
102 | clk_disable_unprepare(__scm->iface_clk); | |
103 | disable_core: | |
104 | clk_disable_unprepare(__scm->core_clk); | |
105 | bail: | |
106 | return ret; | |
107 | } | |
108 | ||
109 | static void qcom_scm_clk_disable(void) | |
110 | { | |
111 | clk_disable_unprepare(__scm->core_clk); | |
112 | clk_disable_unprepare(__scm->iface_clk); | |
113 | clk_disable_unprepare(__scm->bus_clk); | |
114 | } | |
115 | ||
9a434cee EB |
116 | static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, |
117 | u32 cmd_id); | |
118 | ||
119 | enum qcom_scm_convention qcom_scm_convention; | |
120 | static bool has_queried __read_mostly; | |
121 | static DEFINE_SPINLOCK(query_lock); | |
122 | ||
123 | static void __query_convention(void) | |
124 | { | |
125 | unsigned long flags; | |
126 | struct qcom_scm_desc desc = { | |
127 | .svc = QCOM_SCM_SVC_INFO, | |
128 | .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, | |
129 | .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, | |
130 | QCOM_SCM_INFO_IS_CALL_AVAIL) | | |
131 | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT), | |
132 | .arginfo = QCOM_SCM_ARGS(1), | |
133 | .owner = ARM_SMCCC_OWNER_SIP, | |
134 | }; | |
135 | struct qcom_scm_res res; | |
136 | int ret; | |
137 | ||
138 | spin_lock_irqsave(&query_lock, flags); | |
139 | if (has_queried) | |
140 | goto out; | |
141 | ||
142 | qcom_scm_convention = SMC_CONVENTION_ARM_64; | |
143 | // Device isn't required as there is only one argument - no device | |
144 | // needed to dma_map_single to secure world | |
145 | ret = scm_smc_call(NULL, &desc, &res, true); | |
146 | if (!ret && res.result[0] == 1) | |
147 | goto out; | |
148 | ||
149 | qcom_scm_convention = SMC_CONVENTION_ARM_32; | |
150 | ret = scm_smc_call(NULL, &desc, &res, true); | |
151 | if (!ret && res.result[0] == 1) | |
152 | goto out; | |
153 | ||
154 | qcom_scm_convention = SMC_CONVENTION_LEGACY; | |
155 | out: | |
156 | has_queried = true; | |
157 | spin_unlock_irqrestore(&query_lock, flags); | |
158 | pr_info("qcom_scm: convention: %s\n", | |
159 | qcom_scm_convention_names[qcom_scm_convention]); | |
160 | } | |
161 | ||
162 | static inline enum qcom_scm_convention __get_convention(void) | |
163 | { | |
164 | if (unlikely(!has_queried)) | |
165 | __query_convention(); | |
166 | return qcom_scm_convention; | |
167 | } | |
168 | ||
169 | /** | |
170 | * qcom_scm_call() - Invoke a syscall in the secure world | |
171 | * @dev: device | |
172 | * @svc_id: service identifier | |
173 | * @cmd_id: command identifier | |
174 | * @desc: Descriptor structure containing arguments and return values | |
175 | * | |
176 | * Sends a command to the SCM and waits for the command to finish processing. | |
177 | * This should *only* be called in pre-emptible context. | |
178 | */ | |
179 | static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, | |
180 | struct qcom_scm_res *res) | |
181 | { | |
182 | might_sleep(); | |
183 | switch (__get_convention()) { | |
184 | case SMC_CONVENTION_ARM_32: | |
185 | case SMC_CONVENTION_ARM_64: | |
186 | return scm_smc_call(dev, desc, res, false); | |
187 | case SMC_CONVENTION_LEGACY: | |
188 | return scm_legacy_call(dev, desc, res); | |
189 | default: | |
190 | pr_err("Unknown current SCM calling convention.\n"); | |
191 | return -EINVAL; | |
192 | } | |
193 | } | |
194 | ||
195 | /** | |
196 | * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() | |
197 | * @dev: device | |
198 | * @svc_id: service identifier | |
199 | * @cmd_id: command identifier | |
200 | * @desc: Descriptor structure containing arguments and return values | |
201 | * @res: Structure containing results from SMC/HVC call | |
202 | * | |
203 | * Sends a command to the SCM and waits for the command to finish processing. | |
204 | * This can be called in atomic context. | |
205 | */ | |
206 | static int qcom_scm_call_atomic(struct device *dev, | |
207 | const struct qcom_scm_desc *desc, | |
208 | struct qcom_scm_res *res) | |
209 | { | |
210 | switch (__get_convention()) { | |
211 | case SMC_CONVENTION_ARM_32: | |
212 | case SMC_CONVENTION_ARM_64: | |
213 | return scm_smc_call(dev, desc, res, true); | |
214 | case SMC_CONVENTION_LEGACY: | |
215 | return scm_legacy_call_atomic(dev, desc, res); | |
216 | default: | |
217 | pr_err("Unknown current SCM calling convention.\n"); | |
218 | return -EINVAL; | |
219 | } | |
220 | } | |
221 | ||
222 | static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, | |
223 | u32 cmd_id) | |
224 | { | |
225 | int ret; | |
226 | struct qcom_scm_desc desc = { | |
227 | .svc = QCOM_SCM_SVC_INFO, | |
228 | .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, | |
229 | .owner = ARM_SMCCC_OWNER_SIP, | |
230 | }; | |
231 | struct qcom_scm_res res; | |
232 | ||
233 | desc.arginfo = QCOM_SCM_ARGS(1); | |
234 | switch (__get_convention()) { | |
235 | case SMC_CONVENTION_ARM_32: | |
236 | case SMC_CONVENTION_ARM_64: | |
237 | desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) | | |
238 | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); | |
239 | break; | |
240 | case SMC_CONVENTION_LEGACY: | |
241 | desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id); | |
242 | break; | |
243 | default: | |
244 | pr_err("Unknown SMC convention being used\n"); | |
245 | return -EINVAL; | |
246 | } | |
247 | ||
248 | ret = qcom_scm_call(dev, &desc, &res); | |
249 | ||
250 | return ret ? : res.result[0]; | |
251 | } | |
252 | ||
a353e4a0 | 253 | /** |
65f0c90b | 254 | * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus |
a353e4a0 LI |
255 | * @entry: Entry point function for the cpus |
256 | * @cpus: The cpumask of cpus that will use the entry point | |
257 | * | |
65f0c90b EB |
258 | * Set the Linux entry point for the SCM to transfer control to when coming |
259 | * out of a power down. CPU power down may be executed on cpuidle or hotplug. | |
a353e4a0 | 260 | */ |
65f0c90b | 261 | int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) |
a353e4a0 | 262 | { |
57d3b816 EB |
263 | int ret; |
264 | int flags = 0; | |
265 | int cpu; | |
266 | struct qcom_scm_desc desc = { | |
267 | .svc = QCOM_SCM_SVC_BOOT, | |
268 | .cmd = QCOM_SCM_BOOT_SET_ADDR, | |
269 | .arginfo = QCOM_SCM_ARGS(2), | |
270 | }; | |
271 | ||
272 | /* | |
273 | * Reassign only if we are switching from hotplug entry point | |
274 | * to cpuidle entry point or vice versa. | |
275 | */ | |
276 | for_each_cpu(cpu, cpus) { | |
277 | if (entry == qcom_scm_wb[cpu].entry) | |
278 | continue; | |
279 | flags |= qcom_scm_wb[cpu].flag; | |
280 | } | |
281 | ||
282 | /* No change in entry function */ | |
283 | if (!flags) | |
284 | return 0; | |
285 | ||
286 | desc.args[0] = flags; | |
287 | desc.args[1] = virt_to_phys(entry); | |
288 | ||
289 | ret = qcom_scm_call(__scm->dev, &desc, NULL); | |
290 | if (!ret) { | |
291 | for_each_cpu(cpu, cpus) | |
292 | qcom_scm_wb[cpu].entry = entry; | |
293 | } | |
294 | ||
295 | return ret; | |
a353e4a0 | 296 | } |
65f0c90b | 297 | EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); |
2ce76a6a LI |
298 | |
299 | /** | |
65f0c90b | 300 | * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus |
2ce76a6a LI |
301 | * @entry: Entry point function for the cpus |
302 | * @cpus: The cpumask of cpus that will use the entry point | |
303 | * | |
65f0c90b EB |
304 | * Set the cold boot address of the cpus. Any cpu outside the supported |
305 | * range would be removed from the cpu present mask. | |
2ce76a6a | 306 | */ |
65f0c90b | 307 | int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) |
2ce76a6a | 308 | { |
57d3b816 EB |
309 | int flags = 0; |
310 | int cpu; | |
311 | int scm_cb_flags[] = { | |
312 | QCOM_SCM_FLAG_COLDBOOT_CPU0, | |
313 | QCOM_SCM_FLAG_COLDBOOT_CPU1, | |
314 | QCOM_SCM_FLAG_COLDBOOT_CPU2, | |
315 | QCOM_SCM_FLAG_COLDBOOT_CPU3, | |
316 | }; | |
317 | struct qcom_scm_desc desc = { | |
318 | .svc = QCOM_SCM_SVC_BOOT, | |
319 | .cmd = QCOM_SCM_BOOT_SET_ADDR, | |
320 | .arginfo = QCOM_SCM_ARGS(2), | |
321 | .owner = ARM_SMCCC_OWNER_SIP, | |
322 | }; | |
323 | ||
324 | if (!cpus || (cpus && cpumask_empty(cpus))) | |
325 | return -EINVAL; | |
326 | ||
327 | for_each_cpu(cpu, cpus) { | |
328 | if (cpu < ARRAY_SIZE(scm_cb_flags)) | |
329 | flags |= scm_cb_flags[cpu]; | |
330 | else | |
331 | set_cpu_present(cpu, false); | |
332 | } | |
333 | ||
334 | desc.args[0] = flags; | |
335 | desc.args[1] = virt_to_phys(entry); | |
336 | ||
337 | return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); | |
2ce76a6a | 338 | } |
65f0c90b | 339 | EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); |
767b0235 | 340 | |
767b0235 LI |
341 | /** |
342 | * qcom_scm_cpu_power_down() - Power down the cpu | |
343 | * @flags - Flags to flush cache | |
344 | * | |
345 | * This is an end point to power down cpu. If there was a pending interrupt, | |
346 | * the control would return from this function, otherwise, the cpu jumps to the | |
347 | * warm boot entry point set for this cpu upon reset. | |
348 | */ | |
349 | void qcom_scm_cpu_power_down(u32 flags) | |
350 | { | |
57d3b816 EB |
351 | struct qcom_scm_desc desc = { |
352 | .svc = QCOM_SCM_SVC_BOOT, | |
353 | .cmd = QCOM_SCM_BOOT_TERMINATE_PC, | |
354 | .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, | |
355 | .arginfo = QCOM_SCM_ARGS(1), | |
356 | .owner = ARM_SMCCC_OWNER_SIP, | |
357 | }; | |
358 | ||
359 | qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); | |
767b0235 LI |
360 | } |
361 | EXPORT_SYMBOL(qcom_scm_cpu_power_down); | |
9626b699 | 362 | |
65f0c90b | 363 | int qcom_scm_set_remote_state(u32 state, u32 id) |
f01e90fe | 364 | { |
57d3b816 EB |
365 | struct qcom_scm_desc desc = { |
366 | .svc = QCOM_SCM_SVC_BOOT, | |
367 | .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, | |
368 | .arginfo = QCOM_SCM_ARGS(2), | |
369 | .args[0] = state, | |
370 | .args[1] = id, | |
371 | .owner = ARM_SMCCC_OWNER_SIP, | |
372 | }; | |
373 | struct qcom_scm_res res; | |
374 | int ret; | |
375 | ||
376 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
377 | ||
378 | return ret ? : res.result[0]; | |
f01e90fe | 379 | } |
65f0c90b | 380 | EXPORT_SYMBOL(qcom_scm_set_remote_state); |
f01e90fe | 381 | |
57d3b816 EB |
382 | static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) |
383 | { | |
384 | struct qcom_scm_desc desc = { | |
385 | .svc = QCOM_SCM_SVC_BOOT, | |
386 | .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, | |
387 | .arginfo = QCOM_SCM_ARGS(2), | |
388 | .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE, | |
389 | .owner = ARM_SMCCC_OWNER_SIP, | |
390 | }; | |
391 | ||
392 | desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; | |
393 | ||
394 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
395 | } | |
396 | ||
65f0c90b | 397 | static void qcom_scm_set_download_mode(bool enable) |
b0a1614f | 398 | { |
65f0c90b EB |
399 | bool avail; |
400 | int ret = 0; | |
b0a1614f | 401 | |
65f0c90b EB |
402 | avail = __qcom_scm_is_call_available(__scm->dev, |
403 | QCOM_SCM_SVC_BOOT, | |
404 | QCOM_SCM_BOOT_SET_DLOAD_MODE); | |
405 | if (avail) { | |
406 | ret = __qcom_scm_set_dload_mode(__scm->dev, enable); | |
407 | } else if (__scm->dload_mode_addr) { | |
57d3b816 EB |
408 | ret = qcom_scm_io_writel(__scm->dload_mode_addr, |
409 | enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); | |
65f0c90b EB |
410 | } else { |
411 | dev_err(__scm->dev, | |
412 | "No available mechanism for setting download mode\n"); | |
413 | } | |
b0a1614f | 414 | |
65f0c90b EB |
415 | if (ret) |
416 | dev_err(__scm->dev, "failed to set download mode: %d\n", ret); | |
b0a1614f | 417 | } |
b0a1614f | 418 | |
f01e90fe BA |
419 | /** |
420 | * qcom_scm_pas_init_image() - Initialize peripheral authentication service | |
421 | * state machine for a given peripheral, using the | |
422 | * metadata | |
423 | * @peripheral: peripheral id | |
424 | * @metadata: pointer to memory containing ELF header, program header table | |
425 | * and optional blob of data used for authenticating the metadata | |
426 | * and the rest of the firmware | |
427 | * @size: size of the metadata | |
428 | * | |
429 | * Returns 0 on success. | |
430 | */ | |
431 | int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) | |
432 | { | |
433 | dma_addr_t mdata_phys; | |
434 | void *mdata_buf; | |
435 | int ret; | |
57d3b816 EB |
436 | struct qcom_scm_desc desc = { |
437 | .svc = QCOM_SCM_SVC_PIL, | |
438 | .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, | |
439 | .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), | |
440 | .args[0] = peripheral, | |
441 | .owner = ARM_SMCCC_OWNER_SIP, | |
442 | }; | |
443 | struct qcom_scm_res res; | |
f01e90fe BA |
444 | |
445 | /* | |
446 | * During the scm call memory protection will be enabled for the meta | |
447 | * data blob, so make sure it's physically contiguous, 4K aligned and | |
448 | * non-cachable to avoid XPU violations. | |
449 | */ | |
450 | mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, | |
451 | GFP_KERNEL); | |
452 | if (!mdata_buf) { | |
453 | dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); | |
454 | return -ENOMEM; | |
455 | } | |
456 | memcpy(mdata_buf, metadata, size); | |
457 | ||
458 | ret = qcom_scm_clk_enable(); | |
459 | if (ret) | |
460 | goto free_metadata; | |
461 | ||
57d3b816 EB |
462 | desc.args[1] = mdata_phys; |
463 | ||
464 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
f01e90fe BA |
465 | |
466 | qcom_scm_clk_disable(); | |
467 | ||
468 | free_metadata: | |
469 | dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); | |
470 | ||
57d3b816 | 471 | return ret ? : res.result[0]; |
f01e90fe BA |
472 | } |
473 | EXPORT_SYMBOL(qcom_scm_pas_init_image); | |
474 | ||
475 | /** | |
476 | * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral | |
477 | * for firmware loading | |
478 | * @peripheral: peripheral id | |
479 | * @addr: start address of memory area to prepare | |
480 | * @size: size of the memory area to prepare | |
481 | * | |
482 | * Returns 0 on success. | |
483 | */ | |
484 | int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) | |
485 | { | |
486 | int ret; | |
57d3b816 EB |
487 | struct qcom_scm_desc desc = { |
488 | .svc = QCOM_SCM_SVC_PIL, | |
489 | .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, | |
490 | .arginfo = QCOM_SCM_ARGS(3), | |
491 | .args[0] = peripheral, | |
492 | .args[1] = addr, | |
493 | .args[2] = size, | |
494 | .owner = ARM_SMCCC_OWNER_SIP, | |
495 | }; | |
496 | struct qcom_scm_res res; | |
f01e90fe BA |
497 | |
498 | ret = qcom_scm_clk_enable(); | |
499 | if (ret) | |
500 | return ret; | |
501 | ||
57d3b816 | 502 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
f01e90fe BA |
503 | qcom_scm_clk_disable(); |
504 | ||
57d3b816 | 505 | return ret ? : res.result[0]; |
f01e90fe BA |
506 | } |
507 | EXPORT_SYMBOL(qcom_scm_pas_mem_setup); | |
508 | ||
509 | /** | |
510 | * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware | |
511 | * and reset the remote processor | |
512 | * @peripheral: peripheral id | |
513 | * | |
514 | * Return 0 on success. | |
515 | */ | |
516 | int qcom_scm_pas_auth_and_reset(u32 peripheral) | |
517 | { | |
518 | int ret; | |
57d3b816 EB |
519 | struct qcom_scm_desc desc = { |
520 | .svc = QCOM_SCM_SVC_PIL, | |
521 | .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, | |
522 | .arginfo = QCOM_SCM_ARGS(1), | |
523 | .args[0] = peripheral, | |
524 | .owner = ARM_SMCCC_OWNER_SIP, | |
525 | }; | |
526 | struct qcom_scm_res res; | |
f01e90fe BA |
527 | |
528 | ret = qcom_scm_clk_enable(); | |
529 | if (ret) | |
530 | return ret; | |
531 | ||
57d3b816 | 532 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
f01e90fe BA |
533 | qcom_scm_clk_disable(); |
534 | ||
57d3b816 | 535 | return ret ? : res.result[0]; |
f01e90fe BA |
536 | } |
537 | EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset); | |
538 | ||
539 | /** | |
540 | * qcom_scm_pas_shutdown() - Shut down the remote processor | |
541 | * @peripheral: peripheral id | |
542 | * | |
543 | * Returns 0 on success. | |
544 | */ | |
545 | int qcom_scm_pas_shutdown(u32 peripheral) | |
546 | { | |
547 | int ret; | |
57d3b816 EB |
548 | struct qcom_scm_desc desc = { |
549 | .svc = QCOM_SCM_SVC_PIL, | |
550 | .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, | |
551 | .arginfo = QCOM_SCM_ARGS(1), | |
552 | .args[0] = peripheral, | |
553 | .owner = ARM_SMCCC_OWNER_SIP, | |
554 | }; | |
555 | struct qcom_scm_res res; | |
f01e90fe BA |
556 | |
557 | ret = qcom_scm_clk_enable(); | |
558 | if (ret) | |
559 | return ret; | |
560 | ||
57d3b816 EB |
561 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
562 | ||
f01e90fe BA |
563 | qcom_scm_clk_disable(); |
564 | ||
57d3b816 | 565 | return ret ? : res.result[0]; |
f01e90fe BA |
566 | } |
567 | EXPORT_SYMBOL(qcom_scm_pas_shutdown); | |
568 | ||
65f0c90b EB |
569 | /** |
570 | * qcom_scm_pas_supported() - Check if the peripheral authentication service is | |
571 | * available for the given peripherial | |
572 | * @peripheral: peripheral id | |
573 | * | |
574 | * Returns true if PAS is supported for this peripheral, otherwise false. | |
575 | */ | |
576 | bool qcom_scm_pas_supported(u32 peripheral) | |
577 | { | |
578 | int ret; | |
57d3b816 EB |
579 | struct qcom_scm_desc desc = { |
580 | .svc = QCOM_SCM_SVC_PIL, | |
581 | .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, | |
582 | .arginfo = QCOM_SCM_ARGS(1), | |
583 | .args[0] = peripheral, | |
584 | .owner = ARM_SMCCC_OWNER_SIP, | |
585 | }; | |
586 | struct qcom_scm_res res; | |
65f0c90b EB |
587 | |
588 | ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, | |
589 | QCOM_SCM_PIL_PAS_IS_SUPPORTED); | |
590 | if (ret <= 0) | |
591 | return false; | |
592 | ||
57d3b816 EB |
593 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
594 | ||
595 | return ret ? false : !!res.result[0]; | |
65f0c90b EB |
596 | } |
597 | EXPORT_SYMBOL(qcom_scm_pas_supported); | |
598 | ||
57d3b816 EB |
599 | static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) |
600 | { | |
601 | struct qcom_scm_desc desc = { | |
602 | .svc = QCOM_SCM_SVC_PIL, | |
603 | .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, | |
604 | .arginfo = QCOM_SCM_ARGS(2), | |
605 | .args[0] = reset, | |
606 | .args[1] = 0, | |
607 | .owner = ARM_SMCCC_OWNER_SIP, | |
608 | }; | |
609 | struct qcom_scm_res res; | |
610 | int ret; | |
611 | ||
612 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
613 | ||
614 | return ret ? : res.result[0]; | |
615 | } | |
616 | ||
dd4fe5b2 BA |
617 | static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev, |
618 | unsigned long idx) | |
619 | { | |
620 | if (idx != 0) | |
621 | return -EINVAL; | |
622 | ||
623 | return __qcom_scm_pas_mss_reset(__scm->dev, 1); | |
624 | } | |
625 | ||
626 | static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev, | |
627 | unsigned long idx) | |
628 | { | |
629 | if (idx != 0) | |
630 | return -EINVAL; | |
631 | ||
632 | return __qcom_scm_pas_mss_reset(__scm->dev, 0); | |
633 | } | |
634 | ||
635 | static const struct reset_control_ops qcom_scm_pas_reset_ops = { | |
636 | .assert = qcom_scm_pas_reset_assert, | |
637 | .deassert = qcom_scm_pas_reset_deassert, | |
638 | }; | |
639 | ||
65f0c90b EB |
640 | int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) |
641 | { | |
57d3b816 EB |
642 | struct qcom_scm_desc desc = { |
643 | .svc = QCOM_SCM_SVC_IO, | |
644 | .cmd = QCOM_SCM_IO_READ, | |
645 | .arginfo = QCOM_SCM_ARGS(1), | |
646 | .args[0] = addr, | |
647 | .owner = ARM_SMCCC_OWNER_SIP, | |
648 | }; | |
649 | struct qcom_scm_res res; | |
650 | int ret; | |
651 | ||
652 | ||
653 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
654 | if (ret >= 0) | |
655 | *val = res.result[0]; | |
656 | ||
657 | return ret < 0 ? ret : 0; | |
65f0c90b EB |
658 | } |
659 | EXPORT_SYMBOL(qcom_scm_io_readl); | |
660 | ||
661 | int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) | |
662 | { | |
57d3b816 EB |
663 | struct qcom_scm_desc desc = { |
664 | .svc = QCOM_SCM_SVC_IO, | |
665 | .cmd = QCOM_SCM_IO_WRITE, | |
666 | .arginfo = QCOM_SCM_ARGS(2), | |
667 | .args[0] = addr, | |
668 | .args[1] = val, | |
669 | .owner = ARM_SMCCC_OWNER_SIP, | |
670 | }; | |
671 | ||
672 | ||
673 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
65f0c90b EB |
674 | } |
675 | EXPORT_SYMBOL(qcom_scm_io_writel); | |
676 | ||
0434a406 RC |
677 | /** |
678 | * qcom_scm_restore_sec_cfg_available() - Check if secure environment | |
679 | * supports restore security config interface. | |
680 | * | |
681 | * Return true if restore-cfg interface is supported, false if not. | |
682 | */ | |
683 | bool qcom_scm_restore_sec_cfg_available(void) | |
684 | { | |
685 | return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, | |
5443cc5f | 686 | QCOM_SCM_MP_RESTORE_SEC_CFG); |
0434a406 RC |
687 | } |
688 | EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available); | |
689 | ||
a2c680c6 RC |
690 | int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) |
691 | { | |
57d3b816 EB |
692 | struct qcom_scm_desc desc = { |
693 | .svc = QCOM_SCM_SVC_MP, | |
694 | .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, | |
695 | .arginfo = QCOM_SCM_ARGS(2), | |
696 | .args[0] = device_id, | |
697 | .args[1] = spare, | |
698 | .owner = ARM_SMCCC_OWNER_SIP, | |
699 | }; | |
700 | struct qcom_scm_res res; | |
701 | int ret; | |
702 | ||
703 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
704 | ||
705 | return ret ? : res.result[0]; | |
a2c680c6 RC |
706 | } |
707 | EXPORT_SYMBOL(qcom_scm_restore_sec_cfg); | |
708 | ||
b182cc4d SV |
709 | int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) |
710 | { | |
57d3b816 EB |
711 | struct qcom_scm_desc desc = { |
712 | .svc = QCOM_SCM_SVC_MP, | |
713 | .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, | |
714 | .arginfo = QCOM_SCM_ARGS(1), | |
715 | .args[0] = spare, | |
716 | .owner = ARM_SMCCC_OWNER_SIP, | |
717 | }; | |
718 | struct qcom_scm_res res; | |
719 | int ret; | |
720 | ||
721 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
722 | ||
723 | if (size) | |
724 | *size = res.result[0]; | |
725 | ||
726 | return ret ? : res.result[1]; | |
b182cc4d SV |
727 | } |
728 | EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size); | |
729 | ||
730 | int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) | |
731 | { | |
57d3b816 EB |
732 | struct qcom_scm_desc desc = { |
733 | .svc = QCOM_SCM_SVC_MP, | |
734 | .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, | |
735 | .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, | |
736 | QCOM_SCM_VAL), | |
737 | .args[0] = addr, | |
738 | .args[1] = size, | |
739 | .args[2] = spare, | |
740 | .owner = ARM_SMCCC_OWNER_SIP, | |
741 | }; | |
742 | int ret; | |
743 | ||
744 | desc.args[0] = addr; | |
745 | desc.args[1] = size; | |
746 | desc.args[2] = spare; | |
747 | desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, | |
748 | QCOM_SCM_VAL); | |
749 | ||
750 | ret = qcom_scm_call(__scm->dev, &desc, NULL); | |
751 | ||
752 | /* the pg table has been initialized already, ignore the error */ | |
753 | if (ret == -EPERM) | |
754 | ret = 0; | |
755 | ||
756 | return ret; | |
b182cc4d SV |
757 | } |
758 | EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); | |
759 | ||
57d3b816 EB |
760 | static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, |
761 | size_t mem_sz, phys_addr_t src, size_t src_sz, | |
762 | phys_addr_t dest, size_t dest_sz) | |
763 | { | |
764 | int ret; | |
765 | struct qcom_scm_desc desc = { | |
766 | .svc = QCOM_SCM_SVC_MP, | |
767 | .cmd = QCOM_SCM_MP_ASSIGN, | |
768 | .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL, | |
769 | QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, | |
770 | QCOM_SCM_VAL, QCOM_SCM_VAL), | |
771 | .args[0] = mem_region, | |
772 | .args[1] = mem_sz, | |
773 | .args[2] = src, | |
774 | .args[3] = src_sz, | |
775 | .args[4] = dest, | |
776 | .args[5] = dest_sz, | |
777 | .args[6] = 0, | |
778 | .owner = ARM_SMCCC_OWNER_SIP, | |
779 | }; | |
780 | struct qcom_scm_res res; | |
781 | ||
782 | ret = qcom_scm_call(dev, &desc, &res); | |
783 | ||
784 | return ret ? : res.result[0]; | |
785 | } | |
786 | ||
d82bd359 AKD |
787 | /** |
788 | * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership | |
789 | * @mem_addr: mem region whose ownership need to be reassigned | |
790 | * @mem_sz: size of the region. | |
791 | * @srcvm: vmid for current set of owners, each set bit in | |
792 | * flag indicate a unique owner | |
c8b08fc0 | 793 | * @newvm: array having new owners and corresponding permission |
d82bd359 AKD |
794 | * flags |
795 | * @dest_cnt: number of owners in next set. | |
796 | * | |
c8b08fc0 | 797 | * Return negative errno on failure or 0 on success with @srcvm updated. |
d82bd359 AKD |
798 | */ |
799 | int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, | |
800 | unsigned int *srcvm, | |
af311ff9 SB |
801 | const struct qcom_scm_vmperm *newvm, |
802 | unsigned int dest_cnt) | |
d82bd359 AKD |
803 | { |
804 | struct qcom_scm_current_perm_info *destvm; | |
805 | struct qcom_scm_mem_map_info *mem_to_map; | |
806 | phys_addr_t mem_to_map_phys; | |
807 | phys_addr_t dest_phys; | |
459b1f86 | 808 | dma_addr_t ptr_phys; |
d82bd359 AKD |
809 | size_t mem_to_map_sz; |
810 | size_t dest_sz; | |
811 | size_t src_sz; | |
812 | size_t ptr_sz; | |
813 | int next_vm; | |
814 | __le32 *src; | |
815 | void *ptr; | |
af311ff9 SB |
816 | int ret, i, b; |
817 | unsigned long srcvm_bits = *srcvm; | |
d82bd359 | 818 | |
af311ff9 | 819 | src_sz = hweight_long(srcvm_bits) * sizeof(*src); |
d82bd359 AKD |
820 | mem_to_map_sz = sizeof(*mem_to_map); |
821 | dest_sz = dest_cnt * sizeof(*destvm); | |
822 | ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + | |
823 | ALIGN(dest_sz, SZ_64); | |
824 | ||
459b1f86 | 825 | ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL); |
d82bd359 AKD |
826 | if (!ptr) |
827 | return -ENOMEM; | |
828 | ||
829 | /* Fill source vmid detail */ | |
830 | src = ptr; | |
af311ff9 SB |
831 | i = 0; |
832 | for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG) | |
833 | src[i++] = cpu_to_le32(b); | |
d82bd359 AKD |
834 | |
835 | /* Fill details of mem buff to map */ | |
836 | mem_to_map = ptr + ALIGN(src_sz, SZ_64); | |
837 | mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64); | |
af311ff9 SB |
838 | mem_to_map->mem_addr = cpu_to_le64(mem_addr); |
839 | mem_to_map->mem_size = cpu_to_le64(mem_sz); | |
d82bd359 AKD |
840 | |
841 | next_vm = 0; | |
842 | /* Fill details of next vmid detail */ | |
843 | destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); | |
844 | dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); | |
af311ff9 SB |
845 | for (i = 0; i < dest_cnt; i++, destvm++, newvm++) { |
846 | destvm->vmid = cpu_to_le32(newvm->vmid); | |
847 | destvm->perm = cpu_to_le32(newvm->perm); | |
848 | destvm->ctx = 0; | |
849 | destvm->ctx_size = 0; | |
850 | next_vm |= BIT(newvm->vmid); | |
d82bd359 AKD |
851 | } |
852 | ||
853 | ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz, | |
854 | ptr_phys, src_sz, dest_phys, dest_sz); | |
459b1f86 | 855 | dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys); |
d82bd359 AKD |
856 | if (ret) { |
857 | dev_err(__scm->dev, | |
c8b08fc0 | 858 | "Assign memory protection call failed %d\n", ret); |
d82bd359 AKD |
859 | return -EINVAL; |
860 | } | |
861 | ||
862 | *srcvm = next_vm; | |
863 | return 0; | |
864 | } | |
865 | EXPORT_SYMBOL(qcom_scm_assign_mem); | |
866 | ||
65f0c90b EB |
867 | /** |
868 | * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available | |
869 | */ | |
870 | bool qcom_scm_ocmem_lock_available(void) | |
871 | { | |
872 | return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM, | |
873 | QCOM_SCM_OCMEM_LOCK_CMD); | |
874 | } | |
875 | EXPORT_SYMBOL(qcom_scm_ocmem_lock_available); | |
876 | ||
877 | /** | |
878 | * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM | |
879 | * region to the specified initiator | |
880 | * | |
881 | * @id: tz initiator id | |
882 | * @offset: OCMEM offset | |
883 | * @size: OCMEM size | |
884 | * @mode: access mode (WIDE/NARROW) | |
885 | */ | |
886 | int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, | |
887 | u32 mode) | |
888 | { | |
57d3b816 EB |
889 | struct qcom_scm_desc desc = { |
890 | .svc = QCOM_SCM_SVC_OCMEM, | |
891 | .cmd = QCOM_SCM_OCMEM_LOCK_CMD, | |
892 | .args[0] = id, | |
893 | .args[1] = offset, | |
894 | .args[2] = size, | |
895 | .args[3] = mode, | |
896 | .arginfo = QCOM_SCM_ARGS(4), | |
897 | }; | |
898 | ||
899 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
65f0c90b EB |
900 | } |
901 | EXPORT_SYMBOL(qcom_scm_ocmem_lock); | |
902 | ||
903 | /** | |
904 | * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM | |
905 | * region from the specified initiator | |
906 | * | |
907 | * @id: tz initiator id | |
908 | * @offset: OCMEM offset | |
909 | * @size: OCMEM size | |
910 | */ | |
911 | int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) | |
912 | { | |
57d3b816 EB |
913 | struct qcom_scm_desc desc = { |
914 | .svc = QCOM_SCM_SVC_OCMEM, | |
915 | .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD, | |
916 | .args[0] = id, | |
917 | .args[1] = offset, | |
918 | .args[2] = size, | |
919 | .arginfo = QCOM_SCM_ARGS(3), | |
920 | }; | |
921 | ||
922 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
65f0c90b EB |
923 | } |
924 | EXPORT_SYMBOL(qcom_scm_ocmem_unlock); | |
925 | ||
926 | /** | |
927 | * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. | |
928 | * | |
929 | * Return true if HDCP is supported, false if not. | |
930 | */ | |
931 | bool qcom_scm_hdcp_available(void) | |
932 | { | |
933 | int ret = qcom_scm_clk_enable(); | |
934 | ||
935 | if (ret) | |
936 | return ret; | |
937 | ||
938 | ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, | |
939 | QCOM_SCM_HDCP_INVOKE); | |
940 | ||
941 | qcom_scm_clk_disable(); | |
942 | ||
820f6365 | 943 | return ret > 0; |
65f0c90b EB |
944 | } |
945 | EXPORT_SYMBOL(qcom_scm_hdcp_available); | |
946 | ||
947 | /** | |
948 | * qcom_scm_hdcp_req() - Send HDCP request. | |
949 | * @req: HDCP request array | |
950 | * @req_cnt: HDCP request array count | |
951 | * @resp: response buffer passed to SCM | |
952 | * | |
953 | * Write HDCP register(s) through SCM. | |
954 | */ | |
955 | int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) | |
956 | { | |
57d3b816 EB |
957 | int ret; |
958 | struct qcom_scm_desc desc = { | |
959 | .svc = QCOM_SCM_SVC_HDCP, | |
960 | .cmd = QCOM_SCM_HDCP_INVOKE, | |
961 | .arginfo = QCOM_SCM_ARGS(10), | |
962 | .args = { | |
963 | req[0].addr, | |
964 | req[0].val, | |
965 | req[1].addr, | |
966 | req[1].val, | |
967 | req[2].addr, | |
968 | req[2].val, | |
969 | req[3].addr, | |
970 | req[3].val, | |
971 | req[4].addr, | |
972 | req[4].val | |
973 | }, | |
974 | .owner = ARM_SMCCC_OWNER_SIP, | |
975 | }; | |
976 | struct qcom_scm_res res; | |
977 | ||
978 | if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) | |
979 | return -ERANGE; | |
65f0c90b | 980 | |
57d3b816 | 981 | ret = qcom_scm_clk_enable(); |
65f0c90b EB |
982 | if (ret) |
983 | return ret; | |
984 | ||
57d3b816 EB |
985 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
986 | *resp = res.result[0]; | |
987 | ||
65f0c90b | 988 | qcom_scm_clk_disable(); |
57d3b816 | 989 | |
65f0c90b EB |
990 | return ret; |
991 | } | |
992 | EXPORT_SYMBOL(qcom_scm_hdcp_req); | |
993 | ||
994 | int qcom_scm_qsmmu500_wait_safe_toggle(bool en) | |
995 | { | |
57d3b816 EB |
996 | struct qcom_scm_desc desc = { |
997 | .svc = QCOM_SCM_SVC_SMMU_PROGRAM, | |
998 | .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, | |
999 | .arginfo = QCOM_SCM_ARGS(2), | |
1000 | .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL, | |
1001 | .args[1] = en, | |
1002 | .owner = ARM_SMCCC_OWNER_SIP, | |
1003 | }; | |
1004 | ||
1005 | ||
1006 | return qcom_scm_call_atomic(__scm->dev, &desc, NULL); | |
65f0c90b EB |
1007 | } |
1008 | EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); | |
1009 | ||
1010 | static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) | |
1011 | { | |
1012 | struct device_node *tcsr; | |
1013 | struct device_node *np = dev->of_node; | |
1014 | struct resource res; | |
1015 | u32 offset; | |
1016 | int ret; | |
1017 | ||
1018 | tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); | |
1019 | if (!tcsr) | |
1020 | return 0; | |
1021 | ||
1022 | ret = of_address_to_resource(tcsr, 0, &res); | |
1023 | of_node_put(tcsr); | |
1024 | if (ret) | |
1025 | return ret; | |
1026 | ||
1027 | ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); | |
1028 | if (ret < 0) | |
1029 | return ret; | |
1030 | ||
1031 | *addr = res.start + offset; | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | /** | |
1037 | * qcom_scm_is_available() - Checks if SCM is available | |
1038 | */ | |
1039 | bool qcom_scm_is_available(void) | |
1040 | { | |
1041 | return !!__scm; | |
1042 | } | |
1043 | EXPORT_SYMBOL(qcom_scm_is_available); | |
1044 | ||
d0f6fa7b AG |
1045 | static int qcom_scm_probe(struct platform_device *pdev) |
1046 | { | |
1047 | struct qcom_scm *scm; | |
ab0822d5 | 1048 | unsigned long clks; |
d0f6fa7b AG |
1049 | int ret; |
1050 | ||
1051 | scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); | |
1052 | if (!scm) | |
1053 | return -ENOMEM; | |
1054 | ||
8c1b7dc9 BA |
1055 | ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); |
1056 | if (ret < 0) | |
1057 | return ret; | |
1058 | ||
ab0822d5 | 1059 | clks = (unsigned long)of_device_get_match_data(&pdev->dev); |
60cd420c BA |
1060 | |
1061 | scm->core_clk = devm_clk_get(&pdev->dev, "core"); | |
1062 | if (IS_ERR(scm->core_clk)) { | |
1063 | if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER) | |
1064 | return PTR_ERR(scm->core_clk); | |
1065 | ||
1066 | if (clks & SCM_HAS_CORE_CLK) { | |
1067 | dev_err(&pdev->dev, "failed to acquire core clk\n"); | |
ed19b86e | 1068 | return PTR_ERR(scm->core_clk); |
ab0822d5 | 1069 | } |
60cd420c BA |
1070 | |
1071 | scm->core_clk = NULL; | |
d0f6fa7b AG |
1072 | } |
1073 | ||
60cd420c BA |
1074 | scm->iface_clk = devm_clk_get(&pdev->dev, "iface"); |
1075 | if (IS_ERR(scm->iface_clk)) { | |
1076 | if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER) | |
1077 | return PTR_ERR(scm->iface_clk); | |
1078 | ||
1079 | if (clks & SCM_HAS_IFACE_CLK) { | |
1080 | dev_err(&pdev->dev, "failed to acquire iface clk\n"); | |
d0f6fa7b AG |
1081 | return PTR_ERR(scm->iface_clk); |
1082 | } | |
60cd420c BA |
1083 | |
1084 | scm->iface_clk = NULL; | |
ab0822d5 | 1085 | } |
d0f6fa7b | 1086 | |
60cd420c BA |
1087 | scm->bus_clk = devm_clk_get(&pdev->dev, "bus"); |
1088 | if (IS_ERR(scm->bus_clk)) { | |
1089 | if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER) | |
1090 | return PTR_ERR(scm->bus_clk); | |
1091 | ||
1092 | if (clks & SCM_HAS_BUS_CLK) { | |
1093 | dev_err(&pdev->dev, "failed to acquire bus clk\n"); | |
d0f6fa7b AG |
1094 | return PTR_ERR(scm->bus_clk); |
1095 | } | |
60cd420c BA |
1096 | |
1097 | scm->bus_clk = NULL; | |
d0f6fa7b AG |
1098 | } |
1099 | ||
dd4fe5b2 BA |
1100 | scm->reset.ops = &qcom_scm_pas_reset_ops; |
1101 | scm->reset.nr_resets = 1; | |
1102 | scm->reset.of_node = pdev->dev.of_node; | |
bd4760ca WY |
1103 | ret = devm_reset_controller_register(&pdev->dev, &scm->reset); |
1104 | if (ret) | |
1105 | return ret; | |
dd4fe5b2 | 1106 | |
d0f6fa7b AG |
1107 | /* vote for max clk rate for highest performance */ |
1108 | ret = clk_set_rate(scm->core_clk, INT_MAX); | |
1109 | if (ret) | |
1110 | return ret; | |
1111 | ||
1112 | __scm = scm; | |
1113 | __scm->dev = &pdev->dev; | |
1114 | ||
9a434cee | 1115 | __query_convention(); |
6b1751a8 | 1116 | |
8c1b7dc9 BA |
1117 | /* |
1118 | * If requested enable "download mode", from this point on warmboot | |
1119 | * will cause the the boot stages to enter download mode, unless | |
1120 | * disabled below by a clean shutdown/reboot. | |
1121 | */ | |
1122 | if (download_mode) | |
1123 | qcom_scm_set_download_mode(true); | |
1124 | ||
d0f6fa7b AG |
1125 | return 0; |
1126 | } | |
1127 | ||
8c1b7dc9 BA |
1128 | static void qcom_scm_shutdown(struct platform_device *pdev) |
1129 | { | |
1130 | /* Clean shutdown, disable download mode to allow normal restart */ | |
1131 | if (download_mode) | |
1132 | qcom_scm_set_download_mode(false); | |
1133 | } | |
1134 | ||
d0f6fa7b | 1135 | static const struct of_device_id qcom_scm_dt_match[] = { |
ab0822d5 | 1136 | { .compatible = "qcom,scm-apq8064", |
b58a2d31 | 1137 | /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ |
ab0822d5 | 1138 | }, |
60cd420c BA |
1139 | { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK | |
1140 | SCM_HAS_IFACE_CLK | | |
1141 | SCM_HAS_BUS_CLK) | |
ab0822d5 | 1142 | }, |
60cd420c BA |
1143 | { .compatible = "qcom,scm-ipq4019" }, |
1144 | { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK }, | |
1145 | { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK }, | |
1146 | { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK | | |
1147 | SCM_HAS_IFACE_CLK | | |
1148 | SCM_HAS_BUS_CLK) | |
53e51b4a | 1149 | }, |
60cd420c BA |
1150 | { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK | |
1151 | SCM_HAS_IFACE_CLK | | |
1152 | SCM_HAS_BUS_CLK) | |
ab0822d5 | 1153 | }, |
60cd420c BA |
1154 | { .compatible = "qcom,scm-msm8996" }, |
1155 | { .compatible = "qcom,scm" }, | |
d0f6fa7b AG |
1156 | {} |
1157 | }; | |
1158 | ||
d0f6fa7b AG |
1159 | static struct platform_driver qcom_scm_driver = { |
1160 | .driver = { | |
1161 | .name = "qcom_scm", | |
1162 | .of_match_table = qcom_scm_dt_match, | |
1163 | }, | |
1164 | .probe = qcom_scm_probe, | |
8c1b7dc9 | 1165 | .shutdown = qcom_scm_shutdown, |
d0f6fa7b AG |
1166 | }; |
1167 | ||
1168 | static int __init qcom_scm_init(void) | |
1169 | { | |
d0f6fa7b AG |
1170 | return platform_driver_register(&qcom_scm_driver); |
1171 | } | |
6c8e99d8 | 1172 | subsys_initcall(qcom_scm_init); |