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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5443cc5f | 2 | /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. |
2ce76a6a | 3 | * Copyright (C) 2015 Linaro Ltd. |
2a1eb58a | 4 | */ |
d0f6fa7b | 5 | #include <linux/platform_device.h> |
dea85242 | 6 | #include <linux/init.h> |
b6a1dfbc KG |
7 | #include <linux/cpumask.h> |
8 | #include <linux/export.h> | |
f01e90fe | 9 | #include <linux/dma-mapping.h> |
8c1b7dc9 | 10 | #include <linux/module.h> |
b6a1dfbc | 11 | #include <linux/types.h> |
916f743d | 12 | #include <linux/qcom_scm.h> |
d0f6fa7b | 13 | #include <linux/of.h> |
8c1b7dc9 | 14 | #include <linux/of_address.h> |
d0f6fa7b AG |
15 | #include <linux/of_platform.h> |
16 | #include <linux/clk.h> | |
dd4fe5b2 | 17 | #include <linux/reset-controller.h> |
57d3b816 | 18 | #include <linux/arm-smccc.h> |
2a1eb58a | 19 | |
c50031f0 | 20 | #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) |
55845f46 | 21 | #include <asm/smp_plat.h> |
c50031f0 | 22 | #endif |
55845f46 | 23 | |
b6a1dfbc | 24 | #include "qcom_scm.h" |
a353e4a0 | 25 | |
8c1b7dc9 BA |
26 | static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); |
27 | module_param(download_mode, bool, 0); | |
28 | ||
ab0822d5 | 29 | #define SCM_HAS_CORE_CLK BIT(0) |
30 | #define SCM_HAS_IFACE_CLK BIT(1) | |
31 | #define SCM_HAS_BUS_CLK BIT(2) | |
32 | ||
d0f6fa7b AG |
33 | struct qcom_scm { |
34 | struct device *dev; | |
35 | struct clk *core_clk; | |
36 | struct clk *iface_clk; | |
37 | struct clk *bus_clk; | |
dd4fe5b2 | 38 | struct reset_controller_dev reset; |
8c1b7dc9 BA |
39 | |
40 | u64 dload_mode_addr; | |
d0f6fa7b AG |
41 | }; |
42 | ||
d82bd359 AKD |
43 | struct qcom_scm_current_perm_info { |
44 | __le32 vmid; | |
45 | __le32 perm; | |
46 | __le64 ctx; | |
47 | __le32 ctx_size; | |
48 | __le32 unused; | |
49 | }; | |
50 | ||
51 | struct qcom_scm_mem_map_info { | |
52 | __le64 mem_addr; | |
53 | __le64 mem_size; | |
54 | }; | |
55 | ||
57d3b816 EB |
56 | #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 |
57 | #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 | |
58 | #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 | |
59 | #define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20 | |
60 | ||
61 | #define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04 | |
62 | #define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02 | |
63 | #define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10 | |
64 | #define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40 | |
65 | ||
66 | struct qcom_scm_wb_entry { | |
67 | int flag; | |
68 | void *entry; | |
69 | }; | |
70 | ||
71 | static struct qcom_scm_wb_entry qcom_scm_wb[] = { | |
72 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 }, | |
73 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 }, | |
74 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 }, | |
75 | { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 }, | |
76 | }; | |
77 | ||
6bc45428 | 78 | static const char * const qcom_scm_convention_names[] = { |
9a434cee EB |
79 | [SMC_CONVENTION_UNKNOWN] = "unknown", |
80 | [SMC_CONVENTION_ARM_32] = "smc arm 32", | |
81 | [SMC_CONVENTION_ARM_64] = "smc arm 64", | |
82 | [SMC_CONVENTION_LEGACY] = "smc legacy", | |
83 | }; | |
84 | ||
d0f6fa7b AG |
85 | static struct qcom_scm *__scm; |
86 | ||
87 | static int qcom_scm_clk_enable(void) | |
88 | { | |
89 | int ret; | |
90 | ||
91 | ret = clk_prepare_enable(__scm->core_clk); | |
92 | if (ret) | |
93 | goto bail; | |
94 | ||
95 | ret = clk_prepare_enable(__scm->iface_clk); | |
96 | if (ret) | |
97 | goto disable_core; | |
98 | ||
99 | ret = clk_prepare_enable(__scm->bus_clk); | |
100 | if (ret) | |
101 | goto disable_iface; | |
102 | ||
103 | return 0; | |
104 | ||
105 | disable_iface: | |
106 | clk_disable_unprepare(__scm->iface_clk); | |
107 | disable_core: | |
108 | clk_disable_unprepare(__scm->core_clk); | |
109 | bail: | |
110 | return ret; | |
111 | } | |
112 | ||
113 | static void qcom_scm_clk_disable(void) | |
114 | { | |
115 | clk_disable_unprepare(__scm->core_clk); | |
116 | clk_disable_unprepare(__scm->iface_clk); | |
117 | clk_disable_unprepare(__scm->bus_clk); | |
118 | } | |
119 | ||
f6ea568f SB |
120 | enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN; |
121 | static DEFINE_SPINLOCK(scm_query_lock); | |
9a434cee | 122 | |
f6ea568f | 123 | static enum qcom_scm_convention __get_convention(void) |
9a434cee EB |
124 | { |
125 | unsigned long flags; | |
126 | struct qcom_scm_desc desc = { | |
127 | .svc = QCOM_SCM_SVC_INFO, | |
128 | .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, | |
129 | .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, | |
130 | QCOM_SCM_INFO_IS_CALL_AVAIL) | | |
131 | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT), | |
132 | .arginfo = QCOM_SCM_ARGS(1), | |
133 | .owner = ARM_SMCCC_OWNER_SIP, | |
134 | }; | |
135 | struct qcom_scm_res res; | |
f6ea568f | 136 | enum qcom_scm_convention probed_convention; |
9a434cee | 137 | int ret; |
257f2935 | 138 | bool forced = false; |
9a434cee | 139 | |
f6ea568f SB |
140 | if (likely(qcom_scm_convention != SMC_CONVENTION_UNKNOWN)) |
141 | return qcom_scm_convention; | |
9a434cee | 142 | |
f6ea568f SB |
143 | /* |
144 | * Device isn't required as there is only one argument - no device | |
145 | * needed to dma_map_single to secure world | |
146 | */ | |
147 | probed_convention = SMC_CONVENTION_ARM_64; | |
148 | ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true); | |
9a434cee | 149 | if (!ret && res.result[0] == 1) |
f6ea568f | 150 | goto found; |
9a434cee | 151 | |
257f2935 SB |
152 | /* |
153 | * Some SC7180 firmwares didn't implement the | |
154 | * QCOM_SCM_INFO_IS_CALL_AVAIL call, so we fallback to forcing ARM_64 | |
155 | * calling conventions on these firmwares. Luckily we don't make any | |
156 | * early calls into the firmware on these SoCs so the device pointer | |
157 | * will be valid here to check if the compatible matches. | |
158 | */ | |
159 | if (of_device_is_compatible(__scm ? __scm->dev->of_node : NULL, "qcom,scm-sc7180")) { | |
160 | forced = true; | |
161 | goto found; | |
162 | } | |
163 | ||
f6ea568f SB |
164 | probed_convention = SMC_CONVENTION_ARM_32; |
165 | ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true); | |
9a434cee | 166 | if (!ret && res.result[0] == 1) |
f6ea568f SB |
167 | goto found; |
168 | ||
169 | probed_convention = SMC_CONVENTION_LEGACY; | |
170 | found: | |
171 | spin_lock_irqsave(&scm_query_lock, flags); | |
172 | if (probed_convention != qcom_scm_convention) { | |
173 | qcom_scm_convention = probed_convention; | |
257f2935 SB |
174 | pr_info("qcom_scm: convention: %s%s\n", |
175 | qcom_scm_convention_names[qcom_scm_convention], | |
176 | forced ? " (forced)" : ""); | |
f6ea568f SB |
177 | } |
178 | spin_unlock_irqrestore(&scm_query_lock, flags); | |
9a434cee | 179 | |
9a434cee EB |
180 | return qcom_scm_convention; |
181 | } | |
182 | ||
183 | /** | |
184 | * qcom_scm_call() - Invoke a syscall in the secure world | |
185 | * @dev: device | |
186 | * @svc_id: service identifier | |
187 | * @cmd_id: command identifier | |
188 | * @desc: Descriptor structure containing arguments and return values | |
189 | * | |
190 | * Sends a command to the SCM and waits for the command to finish processing. | |
191 | * This should *only* be called in pre-emptible context. | |
192 | */ | |
193 | static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, | |
194 | struct qcom_scm_res *res) | |
195 | { | |
196 | might_sleep(); | |
197 | switch (__get_convention()) { | |
198 | case SMC_CONVENTION_ARM_32: | |
199 | case SMC_CONVENTION_ARM_64: | |
200 | return scm_smc_call(dev, desc, res, false); | |
201 | case SMC_CONVENTION_LEGACY: | |
202 | return scm_legacy_call(dev, desc, res); | |
203 | default: | |
204 | pr_err("Unknown current SCM calling convention.\n"); | |
205 | return -EINVAL; | |
206 | } | |
207 | } | |
208 | ||
209 | /** | |
210 | * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() | |
211 | * @dev: device | |
212 | * @svc_id: service identifier | |
213 | * @cmd_id: command identifier | |
214 | * @desc: Descriptor structure containing arguments and return values | |
215 | * @res: Structure containing results from SMC/HVC call | |
216 | * | |
217 | * Sends a command to the SCM and waits for the command to finish processing. | |
218 | * This can be called in atomic context. | |
219 | */ | |
220 | static int qcom_scm_call_atomic(struct device *dev, | |
221 | const struct qcom_scm_desc *desc, | |
222 | struct qcom_scm_res *res) | |
223 | { | |
224 | switch (__get_convention()) { | |
225 | case SMC_CONVENTION_ARM_32: | |
226 | case SMC_CONVENTION_ARM_64: | |
227 | return scm_smc_call(dev, desc, res, true); | |
228 | case SMC_CONVENTION_LEGACY: | |
229 | return scm_legacy_call_atomic(dev, desc, res); | |
230 | default: | |
231 | pr_err("Unknown current SCM calling convention.\n"); | |
232 | return -EINVAL; | |
233 | } | |
234 | } | |
235 | ||
9d11af8b SB |
236 | static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, |
237 | u32 cmd_id) | |
9a434cee EB |
238 | { |
239 | int ret; | |
240 | struct qcom_scm_desc desc = { | |
241 | .svc = QCOM_SCM_SVC_INFO, | |
242 | .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, | |
243 | .owner = ARM_SMCCC_OWNER_SIP, | |
244 | }; | |
245 | struct qcom_scm_res res; | |
246 | ||
247 | desc.arginfo = QCOM_SCM_ARGS(1); | |
248 | switch (__get_convention()) { | |
249 | case SMC_CONVENTION_ARM_32: | |
250 | case SMC_CONVENTION_ARM_64: | |
251 | desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) | | |
252 | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); | |
253 | break; | |
254 | case SMC_CONVENTION_LEGACY: | |
255 | desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id); | |
256 | break; | |
257 | default: | |
258 | pr_err("Unknown SMC convention being used\n"); | |
38212b2a | 259 | return false; |
9a434cee EB |
260 | } |
261 | ||
262 | ret = qcom_scm_call(dev, &desc, &res); | |
263 | ||
9d11af8b | 264 | return ret ? false : !!res.result[0]; |
9a434cee EB |
265 | } |
266 | ||
c50031f0 | 267 | #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) |
55845f46 SG |
268 | static int __qcom_scm_set_boot_addr_mc(void *entry, const cpumask_t *cpus, |
269 | unsigned int flags) | |
270 | { | |
271 | struct qcom_scm_desc desc = { | |
272 | .svc = QCOM_SCM_SVC_BOOT, | |
273 | .cmd = QCOM_SCM_BOOT_SET_ADDR_MC, | |
274 | .owner = ARM_SMCCC_OWNER_SIP, | |
275 | .arginfo = QCOM_SCM_ARGS(6), | |
276 | }; | |
277 | unsigned int cpu; | |
278 | u64 map; | |
279 | ||
280 | /* Need a device for DMA of the additional arguments */ | |
281 | if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY) | |
282 | return -EOPNOTSUPP; | |
283 | ||
284 | desc.args[0] = virt_to_phys(entry); | |
285 | for_each_cpu(cpu, cpus) { | |
286 | map = cpu_logical_map(cpu); | |
287 | desc.args[1] |= BIT(MPIDR_AFFINITY_LEVEL(map, 0)); | |
288 | desc.args[2] |= BIT(MPIDR_AFFINITY_LEVEL(map, 1)); | |
289 | desc.args[3] |= BIT(MPIDR_AFFINITY_LEVEL(map, 2)); | |
290 | } | |
291 | desc.args[4] = ~0ULL; /* Reserved for affinity level 3 */ | |
292 | desc.args[5] = flags; | |
293 | ||
294 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
295 | } | |
c50031f0 BA |
296 | #else |
297 | static inline int __qcom_scm_set_boot_addr_mc(void *entry, const cpumask_t *cpus, | |
298 | unsigned int flags) | |
299 | { | |
300 | return -EINVAL; | |
301 | } | |
302 | #endif | |
55845f46 SG |
303 | |
304 | static int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) | |
a353e4a0 | 305 | { |
57d3b816 EB |
306 | int ret; |
307 | int flags = 0; | |
308 | int cpu; | |
309 | struct qcom_scm_desc desc = { | |
310 | .svc = QCOM_SCM_SVC_BOOT, | |
311 | .cmd = QCOM_SCM_BOOT_SET_ADDR, | |
312 | .arginfo = QCOM_SCM_ARGS(2), | |
313 | }; | |
314 | ||
315 | /* | |
316 | * Reassign only if we are switching from hotplug entry point | |
317 | * to cpuidle entry point or vice versa. | |
318 | */ | |
319 | for_each_cpu(cpu, cpus) { | |
320 | if (entry == qcom_scm_wb[cpu].entry) | |
321 | continue; | |
322 | flags |= qcom_scm_wb[cpu].flag; | |
323 | } | |
324 | ||
325 | /* No change in entry function */ | |
326 | if (!flags) | |
327 | return 0; | |
328 | ||
329 | desc.args[0] = flags; | |
330 | desc.args[1] = virt_to_phys(entry); | |
331 | ||
332 | ret = qcom_scm_call(__scm->dev, &desc, NULL); | |
333 | if (!ret) { | |
334 | for_each_cpu(cpu, cpus) | |
335 | qcom_scm_wb[cpu].entry = entry; | |
336 | } | |
337 | ||
338 | return ret; | |
a353e4a0 | 339 | } |
2ce76a6a LI |
340 | |
341 | /** | |
55845f46 | 342 | * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus |
2ce76a6a LI |
343 | * @entry: Entry point function for the cpus |
344 | * @cpus: The cpumask of cpus that will use the entry point | |
345 | * | |
55845f46 SG |
346 | * Set the Linux entry point for the SCM to transfer control to when coming |
347 | * out of a power down. CPU power down may be executed on cpuidle or hotplug. | |
2ce76a6a | 348 | */ |
55845f46 SG |
349 | int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) |
350 | { | |
351 | if (!cpus || cpumask_empty(cpus)) | |
352 | return -EINVAL; | |
353 | ||
354 | if (__qcom_scm_set_boot_addr_mc(entry, cpus, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT)) | |
355 | /* Fallback to old SCM call */ | |
356 | return __qcom_scm_set_warm_boot_addr(entry, cpus); | |
357 | return 0; | |
358 | } | |
359 | EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); | |
360 | ||
361 | static int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) | |
2ce76a6a | 362 | { |
57d3b816 EB |
363 | int flags = 0; |
364 | int cpu; | |
365 | int scm_cb_flags[] = { | |
366 | QCOM_SCM_FLAG_COLDBOOT_CPU0, | |
367 | QCOM_SCM_FLAG_COLDBOOT_CPU1, | |
368 | QCOM_SCM_FLAG_COLDBOOT_CPU2, | |
369 | QCOM_SCM_FLAG_COLDBOOT_CPU3, | |
370 | }; | |
371 | struct qcom_scm_desc desc = { | |
372 | .svc = QCOM_SCM_SVC_BOOT, | |
373 | .cmd = QCOM_SCM_BOOT_SET_ADDR, | |
374 | .arginfo = QCOM_SCM_ARGS(2), | |
375 | .owner = ARM_SMCCC_OWNER_SIP, | |
376 | }; | |
377 | ||
57d3b816 EB |
378 | for_each_cpu(cpu, cpus) { |
379 | if (cpu < ARRAY_SIZE(scm_cb_flags)) | |
380 | flags |= scm_cb_flags[cpu]; | |
381 | else | |
382 | set_cpu_present(cpu, false); | |
383 | } | |
384 | ||
385 | desc.args[0] = flags; | |
386 | desc.args[1] = virt_to_phys(entry); | |
387 | ||
388 | return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); | |
2ce76a6a | 389 | } |
55845f46 SG |
390 | |
391 | /** | |
392 | * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus | |
393 | * @entry: Entry point function for the cpus | |
394 | * @cpus: The cpumask of cpus that will use the entry point | |
395 | * | |
396 | * Set the cold boot address of the cpus. Any cpu outside the supported | |
397 | * range would be removed from the cpu present mask. | |
398 | */ | |
399 | int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) | |
400 | { | |
401 | if (!cpus || cpumask_empty(cpus)) | |
402 | return -EINVAL; | |
403 | ||
404 | if (__qcom_scm_set_boot_addr_mc(entry, cpus, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT)) | |
405 | /* Fallback to old SCM call */ | |
406 | return __qcom_scm_set_cold_boot_addr(entry, cpus); | |
407 | return 0; | |
408 | } | |
65f0c90b | 409 | EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); |
767b0235 | 410 | |
767b0235 LI |
411 | /** |
412 | * qcom_scm_cpu_power_down() - Power down the cpu | |
413 | * @flags - Flags to flush cache | |
414 | * | |
415 | * This is an end point to power down cpu. If there was a pending interrupt, | |
416 | * the control would return from this function, otherwise, the cpu jumps to the | |
417 | * warm boot entry point set for this cpu upon reset. | |
418 | */ | |
419 | void qcom_scm_cpu_power_down(u32 flags) | |
420 | { | |
57d3b816 EB |
421 | struct qcom_scm_desc desc = { |
422 | .svc = QCOM_SCM_SVC_BOOT, | |
423 | .cmd = QCOM_SCM_BOOT_TERMINATE_PC, | |
424 | .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, | |
425 | .arginfo = QCOM_SCM_ARGS(1), | |
426 | .owner = ARM_SMCCC_OWNER_SIP, | |
427 | }; | |
428 | ||
429 | qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); | |
767b0235 LI |
430 | } |
431 | EXPORT_SYMBOL(qcom_scm_cpu_power_down); | |
9626b699 | 432 | |
65f0c90b | 433 | int qcom_scm_set_remote_state(u32 state, u32 id) |
f01e90fe | 434 | { |
57d3b816 EB |
435 | struct qcom_scm_desc desc = { |
436 | .svc = QCOM_SCM_SVC_BOOT, | |
437 | .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, | |
438 | .arginfo = QCOM_SCM_ARGS(2), | |
439 | .args[0] = state, | |
440 | .args[1] = id, | |
441 | .owner = ARM_SMCCC_OWNER_SIP, | |
442 | }; | |
443 | struct qcom_scm_res res; | |
444 | int ret; | |
445 | ||
446 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
447 | ||
448 | return ret ? : res.result[0]; | |
f01e90fe | 449 | } |
65f0c90b | 450 | EXPORT_SYMBOL(qcom_scm_set_remote_state); |
f01e90fe | 451 | |
57d3b816 EB |
452 | static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) |
453 | { | |
454 | struct qcom_scm_desc desc = { | |
455 | .svc = QCOM_SCM_SVC_BOOT, | |
456 | .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, | |
457 | .arginfo = QCOM_SCM_ARGS(2), | |
458 | .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE, | |
459 | .owner = ARM_SMCCC_OWNER_SIP, | |
460 | }; | |
461 | ||
462 | desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; | |
463 | ||
b88c2828 | 464 | return qcom_scm_call_atomic(__scm->dev, &desc, NULL); |
57d3b816 EB |
465 | } |
466 | ||
65f0c90b | 467 | static void qcom_scm_set_download_mode(bool enable) |
b0a1614f | 468 | { |
65f0c90b EB |
469 | bool avail; |
470 | int ret = 0; | |
b0a1614f | 471 | |
65f0c90b EB |
472 | avail = __qcom_scm_is_call_available(__scm->dev, |
473 | QCOM_SCM_SVC_BOOT, | |
474 | QCOM_SCM_BOOT_SET_DLOAD_MODE); | |
475 | if (avail) { | |
476 | ret = __qcom_scm_set_dload_mode(__scm->dev, enable); | |
477 | } else if (__scm->dload_mode_addr) { | |
57d3b816 EB |
478 | ret = qcom_scm_io_writel(__scm->dload_mode_addr, |
479 | enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); | |
65f0c90b EB |
480 | } else { |
481 | dev_err(__scm->dev, | |
482 | "No available mechanism for setting download mode\n"); | |
483 | } | |
b0a1614f | 484 | |
65f0c90b EB |
485 | if (ret) |
486 | dev_err(__scm->dev, "failed to set download mode: %d\n", ret); | |
b0a1614f | 487 | } |
b0a1614f | 488 | |
f01e90fe BA |
489 | /** |
490 | * qcom_scm_pas_init_image() - Initialize peripheral authentication service | |
491 | * state machine for a given peripheral, using the | |
492 | * metadata | |
493 | * @peripheral: peripheral id | |
494 | * @metadata: pointer to memory containing ELF header, program header table | |
495 | * and optional blob of data used for authenticating the metadata | |
496 | * and the rest of the firmware | |
497 | * @size: size of the metadata | |
498 | * | |
499 | * Returns 0 on success. | |
500 | */ | |
501 | int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) | |
502 | { | |
503 | dma_addr_t mdata_phys; | |
504 | void *mdata_buf; | |
505 | int ret; | |
57d3b816 EB |
506 | struct qcom_scm_desc desc = { |
507 | .svc = QCOM_SCM_SVC_PIL, | |
508 | .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, | |
509 | .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), | |
510 | .args[0] = peripheral, | |
511 | .owner = ARM_SMCCC_OWNER_SIP, | |
512 | }; | |
513 | struct qcom_scm_res res; | |
f01e90fe BA |
514 | |
515 | /* | |
516 | * During the scm call memory protection will be enabled for the meta | |
517 | * data blob, so make sure it's physically contiguous, 4K aligned and | |
518 | * non-cachable to avoid XPU violations. | |
519 | */ | |
520 | mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, | |
521 | GFP_KERNEL); | |
522 | if (!mdata_buf) { | |
523 | dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); | |
524 | return -ENOMEM; | |
525 | } | |
526 | memcpy(mdata_buf, metadata, size); | |
527 | ||
528 | ret = qcom_scm_clk_enable(); | |
529 | if (ret) | |
530 | goto free_metadata; | |
531 | ||
57d3b816 EB |
532 | desc.args[1] = mdata_phys; |
533 | ||
534 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
f01e90fe BA |
535 | |
536 | qcom_scm_clk_disable(); | |
537 | ||
538 | free_metadata: | |
539 | dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); | |
540 | ||
57d3b816 | 541 | return ret ? : res.result[0]; |
f01e90fe BA |
542 | } |
543 | EXPORT_SYMBOL(qcom_scm_pas_init_image); | |
544 | ||
545 | /** | |
546 | * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral | |
547 | * for firmware loading | |
548 | * @peripheral: peripheral id | |
549 | * @addr: start address of memory area to prepare | |
550 | * @size: size of the memory area to prepare | |
551 | * | |
552 | * Returns 0 on success. | |
553 | */ | |
554 | int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) | |
555 | { | |
556 | int ret; | |
57d3b816 EB |
557 | struct qcom_scm_desc desc = { |
558 | .svc = QCOM_SCM_SVC_PIL, | |
559 | .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, | |
560 | .arginfo = QCOM_SCM_ARGS(3), | |
561 | .args[0] = peripheral, | |
562 | .args[1] = addr, | |
563 | .args[2] = size, | |
564 | .owner = ARM_SMCCC_OWNER_SIP, | |
565 | }; | |
566 | struct qcom_scm_res res; | |
f01e90fe BA |
567 | |
568 | ret = qcom_scm_clk_enable(); | |
569 | if (ret) | |
570 | return ret; | |
571 | ||
57d3b816 | 572 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
f01e90fe BA |
573 | qcom_scm_clk_disable(); |
574 | ||
57d3b816 | 575 | return ret ? : res.result[0]; |
f01e90fe BA |
576 | } |
577 | EXPORT_SYMBOL(qcom_scm_pas_mem_setup); | |
578 | ||
579 | /** | |
580 | * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware | |
581 | * and reset the remote processor | |
582 | * @peripheral: peripheral id | |
583 | * | |
584 | * Return 0 on success. | |
585 | */ | |
586 | int qcom_scm_pas_auth_and_reset(u32 peripheral) | |
587 | { | |
588 | int ret; | |
57d3b816 EB |
589 | struct qcom_scm_desc desc = { |
590 | .svc = QCOM_SCM_SVC_PIL, | |
591 | .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, | |
592 | .arginfo = QCOM_SCM_ARGS(1), | |
593 | .args[0] = peripheral, | |
594 | .owner = ARM_SMCCC_OWNER_SIP, | |
595 | }; | |
596 | struct qcom_scm_res res; | |
f01e90fe BA |
597 | |
598 | ret = qcom_scm_clk_enable(); | |
599 | if (ret) | |
600 | return ret; | |
601 | ||
57d3b816 | 602 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
f01e90fe BA |
603 | qcom_scm_clk_disable(); |
604 | ||
57d3b816 | 605 | return ret ? : res.result[0]; |
f01e90fe BA |
606 | } |
607 | EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset); | |
608 | ||
609 | /** | |
610 | * qcom_scm_pas_shutdown() - Shut down the remote processor | |
611 | * @peripheral: peripheral id | |
612 | * | |
613 | * Returns 0 on success. | |
614 | */ | |
615 | int qcom_scm_pas_shutdown(u32 peripheral) | |
616 | { | |
617 | int ret; | |
57d3b816 EB |
618 | struct qcom_scm_desc desc = { |
619 | .svc = QCOM_SCM_SVC_PIL, | |
620 | .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, | |
621 | .arginfo = QCOM_SCM_ARGS(1), | |
622 | .args[0] = peripheral, | |
623 | .owner = ARM_SMCCC_OWNER_SIP, | |
624 | }; | |
625 | struct qcom_scm_res res; | |
f01e90fe BA |
626 | |
627 | ret = qcom_scm_clk_enable(); | |
628 | if (ret) | |
629 | return ret; | |
630 | ||
57d3b816 EB |
631 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
632 | ||
f01e90fe BA |
633 | qcom_scm_clk_disable(); |
634 | ||
57d3b816 | 635 | return ret ? : res.result[0]; |
f01e90fe BA |
636 | } |
637 | EXPORT_SYMBOL(qcom_scm_pas_shutdown); | |
638 | ||
65f0c90b EB |
639 | /** |
640 | * qcom_scm_pas_supported() - Check if the peripheral authentication service is | |
641 | * available for the given peripherial | |
642 | * @peripheral: peripheral id | |
643 | * | |
644 | * Returns true if PAS is supported for this peripheral, otherwise false. | |
645 | */ | |
646 | bool qcom_scm_pas_supported(u32 peripheral) | |
647 | { | |
648 | int ret; | |
57d3b816 EB |
649 | struct qcom_scm_desc desc = { |
650 | .svc = QCOM_SCM_SVC_PIL, | |
651 | .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, | |
652 | .arginfo = QCOM_SCM_ARGS(1), | |
653 | .args[0] = peripheral, | |
654 | .owner = ARM_SMCCC_OWNER_SIP, | |
655 | }; | |
656 | struct qcom_scm_res res; | |
65f0c90b | 657 | |
9d11af8b SB |
658 | if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, |
659 | QCOM_SCM_PIL_PAS_IS_SUPPORTED)) | |
65f0c90b EB |
660 | return false; |
661 | ||
57d3b816 EB |
662 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
663 | ||
664 | return ret ? false : !!res.result[0]; | |
65f0c90b EB |
665 | } |
666 | EXPORT_SYMBOL(qcom_scm_pas_supported); | |
667 | ||
57d3b816 EB |
668 | static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) |
669 | { | |
670 | struct qcom_scm_desc desc = { | |
671 | .svc = QCOM_SCM_SVC_PIL, | |
672 | .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, | |
673 | .arginfo = QCOM_SCM_ARGS(2), | |
674 | .args[0] = reset, | |
675 | .args[1] = 0, | |
676 | .owner = ARM_SMCCC_OWNER_SIP, | |
677 | }; | |
678 | struct qcom_scm_res res; | |
679 | int ret; | |
680 | ||
681 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
682 | ||
683 | return ret ? : res.result[0]; | |
684 | } | |
685 | ||
dd4fe5b2 BA |
686 | static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev, |
687 | unsigned long idx) | |
688 | { | |
689 | if (idx != 0) | |
690 | return -EINVAL; | |
691 | ||
692 | return __qcom_scm_pas_mss_reset(__scm->dev, 1); | |
693 | } | |
694 | ||
695 | static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev, | |
696 | unsigned long idx) | |
697 | { | |
698 | if (idx != 0) | |
699 | return -EINVAL; | |
700 | ||
701 | return __qcom_scm_pas_mss_reset(__scm->dev, 0); | |
702 | } | |
703 | ||
704 | static const struct reset_control_ops qcom_scm_pas_reset_ops = { | |
705 | .assert = qcom_scm_pas_reset_assert, | |
706 | .deassert = qcom_scm_pas_reset_deassert, | |
707 | }; | |
708 | ||
65f0c90b EB |
709 | int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) |
710 | { | |
57d3b816 EB |
711 | struct qcom_scm_desc desc = { |
712 | .svc = QCOM_SCM_SVC_IO, | |
713 | .cmd = QCOM_SCM_IO_READ, | |
714 | .arginfo = QCOM_SCM_ARGS(1), | |
715 | .args[0] = addr, | |
716 | .owner = ARM_SMCCC_OWNER_SIP, | |
717 | }; | |
718 | struct qcom_scm_res res; | |
719 | int ret; | |
720 | ||
721 | ||
b88c2828 | 722 | ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); |
57d3b816 EB |
723 | if (ret >= 0) |
724 | *val = res.result[0]; | |
725 | ||
726 | return ret < 0 ? ret : 0; | |
65f0c90b EB |
727 | } |
728 | EXPORT_SYMBOL(qcom_scm_io_readl); | |
729 | ||
730 | int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) | |
731 | { | |
57d3b816 EB |
732 | struct qcom_scm_desc desc = { |
733 | .svc = QCOM_SCM_SVC_IO, | |
734 | .cmd = QCOM_SCM_IO_WRITE, | |
735 | .arginfo = QCOM_SCM_ARGS(2), | |
736 | .args[0] = addr, | |
737 | .args[1] = val, | |
738 | .owner = ARM_SMCCC_OWNER_SIP, | |
739 | }; | |
740 | ||
b88c2828 | 741 | return qcom_scm_call_atomic(__scm->dev, &desc, NULL); |
65f0c90b EB |
742 | } |
743 | EXPORT_SYMBOL(qcom_scm_io_writel); | |
744 | ||
0434a406 RC |
745 | /** |
746 | * qcom_scm_restore_sec_cfg_available() - Check if secure environment | |
747 | * supports restore security config interface. | |
748 | * | |
749 | * Return true if restore-cfg interface is supported, false if not. | |
750 | */ | |
751 | bool qcom_scm_restore_sec_cfg_available(void) | |
752 | { | |
753 | return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, | |
5443cc5f | 754 | QCOM_SCM_MP_RESTORE_SEC_CFG); |
0434a406 RC |
755 | } |
756 | EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available); | |
757 | ||
a2c680c6 RC |
758 | int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) |
759 | { | |
57d3b816 EB |
760 | struct qcom_scm_desc desc = { |
761 | .svc = QCOM_SCM_SVC_MP, | |
762 | .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, | |
763 | .arginfo = QCOM_SCM_ARGS(2), | |
764 | .args[0] = device_id, | |
765 | .args[1] = spare, | |
766 | .owner = ARM_SMCCC_OWNER_SIP, | |
767 | }; | |
768 | struct qcom_scm_res res; | |
769 | int ret; | |
770 | ||
771 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
772 | ||
773 | return ret ? : res.result[0]; | |
a2c680c6 RC |
774 | } |
775 | EXPORT_SYMBOL(qcom_scm_restore_sec_cfg); | |
776 | ||
b182cc4d SV |
777 | int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) |
778 | { | |
57d3b816 EB |
779 | struct qcom_scm_desc desc = { |
780 | .svc = QCOM_SCM_SVC_MP, | |
781 | .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, | |
782 | .arginfo = QCOM_SCM_ARGS(1), | |
783 | .args[0] = spare, | |
784 | .owner = ARM_SMCCC_OWNER_SIP, | |
785 | }; | |
786 | struct qcom_scm_res res; | |
787 | int ret; | |
788 | ||
789 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
790 | ||
791 | if (size) | |
792 | *size = res.result[0]; | |
793 | ||
794 | return ret ? : res.result[1]; | |
b182cc4d SV |
795 | } |
796 | EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size); | |
797 | ||
798 | int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) | |
799 | { | |
57d3b816 EB |
800 | struct qcom_scm_desc desc = { |
801 | .svc = QCOM_SCM_SVC_MP, | |
802 | .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, | |
803 | .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, | |
804 | QCOM_SCM_VAL), | |
805 | .args[0] = addr, | |
806 | .args[1] = size, | |
807 | .args[2] = spare, | |
808 | .owner = ARM_SMCCC_OWNER_SIP, | |
809 | }; | |
810 | int ret; | |
811 | ||
812 | desc.args[0] = addr; | |
813 | desc.args[1] = size; | |
814 | desc.args[2] = spare; | |
815 | desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, | |
816 | QCOM_SCM_VAL); | |
817 | ||
818 | ret = qcom_scm_call(__scm->dev, &desc, NULL); | |
819 | ||
820 | /* the pg table has been initialized already, ignore the error */ | |
821 | if (ret == -EPERM) | |
822 | ret = 0; | |
823 | ||
824 | return ret; | |
b182cc4d SV |
825 | } |
826 | EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); | |
827 | ||
6d885330 SV |
828 | int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, |
829 | u32 cp_nonpixel_start, | |
830 | u32 cp_nonpixel_size) | |
831 | { | |
832 | int ret; | |
833 | struct qcom_scm_desc desc = { | |
834 | .svc = QCOM_SCM_SVC_MP, | |
835 | .cmd = QCOM_SCM_MP_VIDEO_VAR, | |
836 | .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, | |
837 | QCOM_SCM_VAL, QCOM_SCM_VAL), | |
838 | .args[0] = cp_start, | |
839 | .args[1] = cp_size, | |
840 | .args[2] = cp_nonpixel_start, | |
841 | .args[3] = cp_nonpixel_size, | |
842 | .owner = ARM_SMCCC_OWNER_SIP, | |
843 | }; | |
844 | struct qcom_scm_res res; | |
845 | ||
846 | ret = qcom_scm_call(__scm->dev, &desc, &res); | |
847 | ||
848 | return ret ? : res.result[0]; | |
849 | } | |
850 | EXPORT_SYMBOL(qcom_scm_mem_protect_video_var); | |
851 | ||
57d3b816 EB |
852 | static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, |
853 | size_t mem_sz, phys_addr_t src, size_t src_sz, | |
854 | phys_addr_t dest, size_t dest_sz) | |
855 | { | |
856 | int ret; | |
857 | struct qcom_scm_desc desc = { | |
858 | .svc = QCOM_SCM_SVC_MP, | |
859 | .cmd = QCOM_SCM_MP_ASSIGN, | |
860 | .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL, | |
861 | QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, | |
862 | QCOM_SCM_VAL, QCOM_SCM_VAL), | |
863 | .args[0] = mem_region, | |
864 | .args[1] = mem_sz, | |
865 | .args[2] = src, | |
866 | .args[3] = src_sz, | |
867 | .args[4] = dest, | |
868 | .args[5] = dest_sz, | |
869 | .args[6] = 0, | |
870 | .owner = ARM_SMCCC_OWNER_SIP, | |
871 | }; | |
872 | struct qcom_scm_res res; | |
873 | ||
874 | ret = qcom_scm_call(dev, &desc, &res); | |
875 | ||
876 | return ret ? : res.result[0]; | |
877 | } | |
878 | ||
d82bd359 AKD |
879 | /** |
880 | * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership | |
881 | * @mem_addr: mem region whose ownership need to be reassigned | |
882 | * @mem_sz: size of the region. | |
883 | * @srcvm: vmid for current set of owners, each set bit in | |
884 | * flag indicate a unique owner | |
c8b08fc0 | 885 | * @newvm: array having new owners and corresponding permission |
d82bd359 AKD |
886 | * flags |
887 | * @dest_cnt: number of owners in next set. | |
888 | * | |
c8b08fc0 | 889 | * Return negative errno on failure or 0 on success with @srcvm updated. |
d82bd359 AKD |
890 | */ |
891 | int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, | |
892 | unsigned int *srcvm, | |
af311ff9 SB |
893 | const struct qcom_scm_vmperm *newvm, |
894 | unsigned int dest_cnt) | |
d82bd359 AKD |
895 | { |
896 | struct qcom_scm_current_perm_info *destvm; | |
897 | struct qcom_scm_mem_map_info *mem_to_map; | |
898 | phys_addr_t mem_to_map_phys; | |
899 | phys_addr_t dest_phys; | |
459b1f86 | 900 | dma_addr_t ptr_phys; |
d82bd359 AKD |
901 | size_t mem_to_map_sz; |
902 | size_t dest_sz; | |
903 | size_t src_sz; | |
904 | size_t ptr_sz; | |
905 | int next_vm; | |
906 | __le32 *src; | |
907 | void *ptr; | |
af311ff9 SB |
908 | int ret, i, b; |
909 | unsigned long srcvm_bits = *srcvm; | |
d82bd359 | 910 | |
af311ff9 | 911 | src_sz = hweight_long(srcvm_bits) * sizeof(*src); |
d82bd359 AKD |
912 | mem_to_map_sz = sizeof(*mem_to_map); |
913 | dest_sz = dest_cnt * sizeof(*destvm); | |
914 | ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + | |
915 | ALIGN(dest_sz, SZ_64); | |
916 | ||
459b1f86 | 917 | ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL); |
d82bd359 AKD |
918 | if (!ptr) |
919 | return -ENOMEM; | |
920 | ||
921 | /* Fill source vmid detail */ | |
922 | src = ptr; | |
af311ff9 SB |
923 | i = 0; |
924 | for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG) | |
925 | src[i++] = cpu_to_le32(b); | |
d82bd359 AKD |
926 | |
927 | /* Fill details of mem buff to map */ | |
928 | mem_to_map = ptr + ALIGN(src_sz, SZ_64); | |
929 | mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64); | |
af311ff9 SB |
930 | mem_to_map->mem_addr = cpu_to_le64(mem_addr); |
931 | mem_to_map->mem_size = cpu_to_le64(mem_sz); | |
d82bd359 AKD |
932 | |
933 | next_vm = 0; | |
934 | /* Fill details of next vmid detail */ | |
935 | destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); | |
936 | dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); | |
af311ff9 SB |
937 | for (i = 0; i < dest_cnt; i++, destvm++, newvm++) { |
938 | destvm->vmid = cpu_to_le32(newvm->vmid); | |
939 | destvm->perm = cpu_to_le32(newvm->perm); | |
940 | destvm->ctx = 0; | |
941 | destvm->ctx_size = 0; | |
942 | next_vm |= BIT(newvm->vmid); | |
d82bd359 AKD |
943 | } |
944 | ||
945 | ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz, | |
946 | ptr_phys, src_sz, dest_phys, dest_sz); | |
459b1f86 | 947 | dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys); |
d82bd359 AKD |
948 | if (ret) { |
949 | dev_err(__scm->dev, | |
c8b08fc0 | 950 | "Assign memory protection call failed %d\n", ret); |
d82bd359 AKD |
951 | return -EINVAL; |
952 | } | |
953 | ||
954 | *srcvm = next_vm; | |
955 | return 0; | |
956 | } | |
957 | EXPORT_SYMBOL(qcom_scm_assign_mem); | |
958 | ||
65f0c90b EB |
959 | /** |
960 | * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available | |
961 | */ | |
962 | bool qcom_scm_ocmem_lock_available(void) | |
963 | { | |
964 | return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM, | |
965 | QCOM_SCM_OCMEM_LOCK_CMD); | |
966 | } | |
967 | EXPORT_SYMBOL(qcom_scm_ocmem_lock_available); | |
968 | ||
969 | /** | |
970 | * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM | |
971 | * region to the specified initiator | |
972 | * | |
973 | * @id: tz initiator id | |
974 | * @offset: OCMEM offset | |
975 | * @size: OCMEM size | |
976 | * @mode: access mode (WIDE/NARROW) | |
977 | */ | |
978 | int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, | |
979 | u32 mode) | |
980 | { | |
57d3b816 EB |
981 | struct qcom_scm_desc desc = { |
982 | .svc = QCOM_SCM_SVC_OCMEM, | |
983 | .cmd = QCOM_SCM_OCMEM_LOCK_CMD, | |
984 | .args[0] = id, | |
985 | .args[1] = offset, | |
986 | .args[2] = size, | |
987 | .args[3] = mode, | |
988 | .arginfo = QCOM_SCM_ARGS(4), | |
989 | }; | |
990 | ||
991 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
65f0c90b EB |
992 | } |
993 | EXPORT_SYMBOL(qcom_scm_ocmem_lock); | |
994 | ||
995 | /** | |
996 | * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM | |
997 | * region from the specified initiator | |
998 | * | |
999 | * @id: tz initiator id | |
1000 | * @offset: OCMEM offset | |
1001 | * @size: OCMEM size | |
1002 | */ | |
1003 | int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) | |
1004 | { | |
57d3b816 EB |
1005 | struct qcom_scm_desc desc = { |
1006 | .svc = QCOM_SCM_SVC_OCMEM, | |
1007 | .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD, | |
1008 | .args[0] = id, | |
1009 | .args[1] = offset, | |
1010 | .args[2] = size, | |
1011 | .arginfo = QCOM_SCM_ARGS(3), | |
1012 | }; | |
1013 | ||
1014 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
65f0c90b EB |
1015 | } |
1016 | EXPORT_SYMBOL(qcom_scm_ocmem_unlock); | |
1017 | ||
0f206514 EB |
1018 | /** |
1019 | * qcom_scm_ice_available() - Is the ICE key programming interface available? | |
1020 | * | |
1021 | * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and | |
1022 | * qcom_scm_ice_set_key() are available. | |
1023 | */ | |
1024 | bool qcom_scm_ice_available(void) | |
1025 | { | |
1026 | return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, | |
1027 | QCOM_SCM_ES_INVALIDATE_ICE_KEY) && | |
1028 | __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, | |
1029 | QCOM_SCM_ES_CONFIG_SET_ICE_KEY); | |
1030 | } | |
1031 | EXPORT_SYMBOL(qcom_scm_ice_available); | |
1032 | ||
1033 | /** | |
1034 | * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key | |
1035 | * @index: the keyslot to invalidate | |
1036 | * | |
433611ea EB |
1037 | * The UFSHCI and eMMC standards define a standard way to do this, but it |
1038 | * doesn't work on these SoCs; only this SCM call does. | |
1039 | * | |
1040 | * It is assumed that the SoC has only one ICE instance being used, as this SCM | |
1041 | * call doesn't specify which ICE instance the keyslot belongs to. | |
0f206514 EB |
1042 | * |
1043 | * Return: 0 on success; -errno on failure. | |
1044 | */ | |
1045 | int qcom_scm_ice_invalidate_key(u32 index) | |
1046 | { | |
1047 | struct qcom_scm_desc desc = { | |
1048 | .svc = QCOM_SCM_SVC_ES, | |
1049 | .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY, | |
1050 | .arginfo = QCOM_SCM_ARGS(1), | |
1051 | .args[0] = index, | |
1052 | .owner = ARM_SMCCC_OWNER_SIP, | |
1053 | }; | |
1054 | ||
1055 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
1056 | } | |
1057 | EXPORT_SYMBOL(qcom_scm_ice_invalidate_key); | |
1058 | ||
1059 | /** | |
1060 | * qcom_scm_ice_set_key() - Set an inline encryption key | |
1061 | * @index: the keyslot into which to set the key | |
1062 | * @key: the key to program | |
1063 | * @key_size: the size of the key in bytes | |
1064 | * @cipher: the encryption algorithm the key is for | |
1065 | * @data_unit_size: the encryption data unit size, i.e. the size of each | |
1066 | * individual plaintext and ciphertext. Given in 512-byte | |
1067 | * units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc. | |
1068 | * | |
1069 | * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it | |
433611ea EB |
1070 | * can then be used to encrypt/decrypt UFS or eMMC I/O requests inline. |
1071 | * | |
1072 | * The UFSHCI and eMMC standards define a standard way to do this, but it | |
1073 | * doesn't work on these SoCs; only this SCM call does. | |
0f206514 | 1074 | * |
433611ea EB |
1075 | * It is assumed that the SoC has only one ICE instance being used, as this SCM |
1076 | * call doesn't specify which ICE instance the keyslot belongs to. | |
0f206514 EB |
1077 | * |
1078 | * Return: 0 on success; -errno on failure. | |
1079 | */ | |
1080 | int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, | |
1081 | enum qcom_scm_ice_cipher cipher, u32 data_unit_size) | |
1082 | { | |
1083 | struct qcom_scm_desc desc = { | |
1084 | .svc = QCOM_SCM_SVC_ES, | |
1085 | .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY, | |
1086 | .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW, | |
1087 | QCOM_SCM_VAL, QCOM_SCM_VAL, | |
1088 | QCOM_SCM_VAL), | |
1089 | .args[0] = index, | |
1090 | .args[2] = key_size, | |
1091 | .args[3] = cipher, | |
1092 | .args[4] = data_unit_size, | |
1093 | .owner = ARM_SMCCC_OWNER_SIP, | |
1094 | }; | |
1095 | void *keybuf; | |
1096 | dma_addr_t key_phys; | |
1097 | int ret; | |
1098 | ||
1099 | /* | |
1100 | * 'key' may point to vmalloc()'ed memory, but we need to pass a | |
1101 | * physical address that's been properly flushed. The sanctioned way to | |
1102 | * do this is by using the DMA API. But as is best practice for crypto | |
1103 | * keys, we also must wipe the key after use. This makes kmemdup() + | |
1104 | * dma_map_single() not clearly correct, since the DMA API can use | |
1105 | * bounce buffers. Instead, just use dma_alloc_coherent(). Programming | |
1106 | * keys is normally rare and thus not performance-critical. | |
1107 | */ | |
1108 | ||
1109 | keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys, | |
1110 | GFP_KERNEL); | |
1111 | if (!keybuf) | |
1112 | return -ENOMEM; | |
1113 | memcpy(keybuf, key, key_size); | |
1114 | desc.args[1] = key_phys; | |
1115 | ||
1116 | ret = qcom_scm_call(__scm->dev, &desc, NULL); | |
1117 | ||
1118 | memzero_explicit(keybuf, key_size); | |
1119 | ||
1120 | dma_free_coherent(__scm->dev, key_size, keybuf, key_phys); | |
1121 | return ret; | |
1122 | } | |
1123 | EXPORT_SYMBOL(qcom_scm_ice_set_key); | |
1124 | ||
65f0c90b EB |
1125 | /** |
1126 | * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. | |
1127 | * | |
1128 | * Return true if HDCP is supported, false if not. | |
1129 | */ | |
1130 | bool qcom_scm_hdcp_available(void) | |
1131 | { | |
9d11af8b | 1132 | bool avail; |
65f0c90b EB |
1133 | int ret = qcom_scm_clk_enable(); |
1134 | ||
1135 | if (ret) | |
1136 | return ret; | |
1137 | ||
9d11af8b | 1138 | avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, |
65f0c90b EB |
1139 | QCOM_SCM_HDCP_INVOKE); |
1140 | ||
1141 | qcom_scm_clk_disable(); | |
1142 | ||
9d11af8b | 1143 | return avail; |
65f0c90b EB |
1144 | } |
1145 | EXPORT_SYMBOL(qcom_scm_hdcp_available); | |
1146 | ||
1147 | /** | |
1148 | * qcom_scm_hdcp_req() - Send HDCP request. | |
1149 | * @req: HDCP request array | |
1150 | * @req_cnt: HDCP request array count | |
1151 | * @resp: response buffer passed to SCM | |
1152 | * | |
1153 | * Write HDCP register(s) through SCM. | |
1154 | */ | |
1155 | int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) | |
1156 | { | |
57d3b816 EB |
1157 | int ret; |
1158 | struct qcom_scm_desc desc = { | |
1159 | .svc = QCOM_SCM_SVC_HDCP, | |
1160 | .cmd = QCOM_SCM_HDCP_INVOKE, | |
1161 | .arginfo = QCOM_SCM_ARGS(10), | |
1162 | .args = { | |
1163 | req[0].addr, | |
1164 | req[0].val, | |
1165 | req[1].addr, | |
1166 | req[1].val, | |
1167 | req[2].addr, | |
1168 | req[2].val, | |
1169 | req[3].addr, | |
1170 | req[3].val, | |
1171 | req[4].addr, | |
1172 | req[4].val | |
1173 | }, | |
1174 | .owner = ARM_SMCCC_OWNER_SIP, | |
1175 | }; | |
1176 | struct qcom_scm_res res; | |
1177 | ||
1178 | if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) | |
1179 | return -ERANGE; | |
65f0c90b | 1180 | |
57d3b816 | 1181 | ret = qcom_scm_clk_enable(); |
65f0c90b EB |
1182 | if (ret) |
1183 | return ret; | |
1184 | ||
57d3b816 EB |
1185 | ret = qcom_scm_call(__scm->dev, &desc, &res); |
1186 | *resp = res.result[0]; | |
1187 | ||
65f0c90b | 1188 | qcom_scm_clk_disable(); |
57d3b816 | 1189 | |
65f0c90b EB |
1190 | return ret; |
1191 | } | |
1192 | EXPORT_SYMBOL(qcom_scm_hdcp_req); | |
1193 | ||
1194 | int qcom_scm_qsmmu500_wait_safe_toggle(bool en) | |
1195 | { | |
57d3b816 EB |
1196 | struct qcom_scm_desc desc = { |
1197 | .svc = QCOM_SCM_SVC_SMMU_PROGRAM, | |
1198 | .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, | |
1199 | .arginfo = QCOM_SCM_ARGS(2), | |
1200 | .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL, | |
1201 | .args[1] = en, | |
1202 | .owner = ARM_SMCCC_OWNER_SIP, | |
1203 | }; | |
1204 | ||
1205 | ||
1206 | return qcom_scm_call_atomic(__scm->dev, &desc, NULL); | |
65f0c90b EB |
1207 | } |
1208 | EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); | |
1209 | ||
de3438c4 TG |
1210 | bool qcom_scm_lmh_dcvsh_available(void) |
1211 | { | |
1212 | return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); | |
1213 | } | |
1214 | EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); | |
1215 | ||
1216 | int qcom_scm_lmh_profile_change(u32 profile_id) | |
1217 | { | |
1218 | struct qcom_scm_desc desc = { | |
1219 | .svc = QCOM_SCM_SVC_LMH, | |
1220 | .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, | |
1221 | .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), | |
1222 | .args[0] = profile_id, | |
1223 | .owner = ARM_SMCCC_OWNER_SIP, | |
1224 | }; | |
1225 | ||
1226 | return qcom_scm_call(__scm->dev, &desc, NULL); | |
1227 | } | |
1228 | EXPORT_SYMBOL(qcom_scm_lmh_profile_change); | |
1229 | ||
1230 | int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, | |
1231 | u64 limit_node, u32 node_id, u64 version) | |
1232 | { | |
1233 | dma_addr_t payload_phys; | |
1234 | u32 *payload_buf; | |
1235 | int ret, payload_size = 5 * sizeof(u32); | |
1236 | ||
1237 | struct qcom_scm_desc desc = { | |
1238 | .svc = QCOM_SCM_SVC_LMH, | |
1239 | .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, | |
1240 | .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, | |
1241 | QCOM_SCM_VAL, QCOM_SCM_VAL), | |
1242 | .args[1] = payload_size, | |
1243 | .args[2] = limit_node, | |
1244 | .args[3] = node_id, | |
1245 | .args[4] = version, | |
1246 | .owner = ARM_SMCCC_OWNER_SIP, | |
1247 | }; | |
1248 | ||
1249 | payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); | |
1250 | if (!payload_buf) | |
1251 | return -ENOMEM; | |
1252 | ||
1253 | payload_buf[0] = payload_fn; | |
1254 | payload_buf[1] = 0; | |
1255 | payload_buf[2] = payload_reg; | |
1256 | payload_buf[3] = 1; | |
1257 | payload_buf[4] = payload_val; | |
1258 | ||
1259 | desc.args[0] = payload_phys; | |
1260 | ||
1261 | ret = qcom_scm_call(__scm->dev, &desc, NULL); | |
1262 | ||
1263 | dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys); | |
1264 | return ret; | |
1265 | } | |
1266 | EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); | |
1267 | ||
65f0c90b EB |
1268 | static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) |
1269 | { | |
1270 | struct device_node *tcsr; | |
1271 | struct device_node *np = dev->of_node; | |
1272 | struct resource res; | |
1273 | u32 offset; | |
1274 | int ret; | |
1275 | ||
1276 | tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); | |
1277 | if (!tcsr) | |
1278 | return 0; | |
1279 | ||
1280 | ret = of_address_to_resource(tcsr, 0, &res); | |
1281 | of_node_put(tcsr); | |
1282 | if (ret) | |
1283 | return ret; | |
1284 | ||
1285 | ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); | |
1286 | if (ret < 0) | |
1287 | return ret; | |
1288 | ||
1289 | *addr = res.start + offset; | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | /** | |
1295 | * qcom_scm_is_available() - Checks if SCM is available | |
1296 | */ | |
1297 | bool qcom_scm_is_available(void) | |
1298 | { | |
1299 | return !!__scm; | |
1300 | } | |
1301 | EXPORT_SYMBOL(qcom_scm_is_available); | |
1302 | ||
d0f6fa7b AG |
1303 | static int qcom_scm_probe(struct platform_device *pdev) |
1304 | { | |
1305 | struct qcom_scm *scm; | |
ab0822d5 | 1306 | unsigned long clks; |
d0f6fa7b AG |
1307 | int ret; |
1308 | ||
1309 | scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); | |
1310 | if (!scm) | |
1311 | return -ENOMEM; | |
1312 | ||
8c1b7dc9 BA |
1313 | ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); |
1314 | if (ret < 0) | |
1315 | return ret; | |
1316 | ||
ab0822d5 | 1317 | clks = (unsigned long)of_device_get_match_data(&pdev->dev); |
60cd420c BA |
1318 | |
1319 | scm->core_clk = devm_clk_get(&pdev->dev, "core"); | |
1320 | if (IS_ERR(scm->core_clk)) { | |
1321 | if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER) | |
1322 | return PTR_ERR(scm->core_clk); | |
1323 | ||
1324 | if (clks & SCM_HAS_CORE_CLK) { | |
1325 | dev_err(&pdev->dev, "failed to acquire core clk\n"); | |
ed19b86e | 1326 | return PTR_ERR(scm->core_clk); |
ab0822d5 | 1327 | } |
60cd420c BA |
1328 | |
1329 | scm->core_clk = NULL; | |
d0f6fa7b AG |
1330 | } |
1331 | ||
60cd420c BA |
1332 | scm->iface_clk = devm_clk_get(&pdev->dev, "iface"); |
1333 | if (IS_ERR(scm->iface_clk)) { | |
1334 | if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER) | |
1335 | return PTR_ERR(scm->iface_clk); | |
1336 | ||
1337 | if (clks & SCM_HAS_IFACE_CLK) { | |
1338 | dev_err(&pdev->dev, "failed to acquire iface clk\n"); | |
d0f6fa7b AG |
1339 | return PTR_ERR(scm->iface_clk); |
1340 | } | |
60cd420c BA |
1341 | |
1342 | scm->iface_clk = NULL; | |
ab0822d5 | 1343 | } |
d0f6fa7b | 1344 | |
60cd420c BA |
1345 | scm->bus_clk = devm_clk_get(&pdev->dev, "bus"); |
1346 | if (IS_ERR(scm->bus_clk)) { | |
1347 | if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER) | |
1348 | return PTR_ERR(scm->bus_clk); | |
1349 | ||
1350 | if (clks & SCM_HAS_BUS_CLK) { | |
1351 | dev_err(&pdev->dev, "failed to acquire bus clk\n"); | |
d0f6fa7b AG |
1352 | return PTR_ERR(scm->bus_clk); |
1353 | } | |
60cd420c BA |
1354 | |
1355 | scm->bus_clk = NULL; | |
d0f6fa7b AG |
1356 | } |
1357 | ||
dd4fe5b2 BA |
1358 | scm->reset.ops = &qcom_scm_pas_reset_ops; |
1359 | scm->reset.nr_resets = 1; | |
1360 | scm->reset.of_node = pdev->dev.of_node; | |
bd4760ca WY |
1361 | ret = devm_reset_controller_register(&pdev->dev, &scm->reset); |
1362 | if (ret) | |
1363 | return ret; | |
dd4fe5b2 | 1364 | |
d0f6fa7b AG |
1365 | /* vote for max clk rate for highest performance */ |
1366 | ret = clk_set_rate(scm->core_clk, INT_MAX); | |
1367 | if (ret) | |
1368 | return ret; | |
1369 | ||
1370 | __scm = scm; | |
1371 | __scm->dev = &pdev->dev; | |
1372 | ||
f6ea568f | 1373 | __get_convention(); |
6b1751a8 | 1374 | |
8c1b7dc9 BA |
1375 | /* |
1376 | * If requested enable "download mode", from this point on warmboot | |
1377 | * will cause the the boot stages to enter download mode, unless | |
1378 | * disabled below by a clean shutdown/reboot. | |
1379 | */ | |
1380 | if (download_mode) | |
1381 | qcom_scm_set_download_mode(true); | |
1382 | ||
d0f6fa7b AG |
1383 | return 0; |
1384 | } | |
1385 | ||
8c1b7dc9 BA |
1386 | static void qcom_scm_shutdown(struct platform_device *pdev) |
1387 | { | |
1388 | /* Clean shutdown, disable download mode to allow normal restart */ | |
1389 | if (download_mode) | |
1390 | qcom_scm_set_download_mode(false); | |
1391 | } | |
1392 | ||
d0f6fa7b | 1393 | static const struct of_device_id qcom_scm_dt_match[] = { |
ab0822d5 | 1394 | { .compatible = "qcom,scm-apq8064", |
b58a2d31 | 1395 | /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ |
ab0822d5 | 1396 | }, |
60cd420c BA |
1397 | { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK | |
1398 | SCM_HAS_IFACE_CLK | | |
1399 | SCM_HAS_BUS_CLK) | |
ab0822d5 | 1400 | }, |
60cd420c | 1401 | { .compatible = "qcom,scm-ipq4019" }, |
82a6cbf0 KD |
1402 | { .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK | |
1403 | SCM_HAS_IFACE_CLK | | |
1404 | SCM_HAS_BUS_CLK) }, | |
60cd420c BA |
1405 | { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK }, |
1406 | { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK }, | |
1407 | { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK | | |
1408 | SCM_HAS_IFACE_CLK | | |
1409 | SCM_HAS_BUS_CLK) | |
53e51b4a | 1410 | }, |
bca4392a VL |
1411 | { .compatible = "qcom,scm-msm8953", .data = (void *)(SCM_HAS_CORE_CLK | |
1412 | SCM_HAS_IFACE_CLK | | |
1413 | SCM_HAS_BUS_CLK) | |
1414 | }, | |
60cd420c BA |
1415 | { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK | |
1416 | SCM_HAS_IFACE_CLK | | |
1417 | SCM_HAS_BUS_CLK) | |
ab0822d5 | 1418 | }, |
4bdc8c8d | 1419 | { .compatible = "qcom,scm-msm8994" }, |
60cd420c BA |
1420 | { .compatible = "qcom,scm-msm8996" }, |
1421 | { .compatible = "qcom,scm" }, | |
d0f6fa7b AG |
1422 | {} |
1423 | }; | |
b42000e4 | 1424 | MODULE_DEVICE_TABLE(of, qcom_scm_dt_match); |
d0f6fa7b | 1425 | |
d0f6fa7b AG |
1426 | static struct platform_driver qcom_scm_driver = { |
1427 | .driver = { | |
1428 | .name = "qcom_scm", | |
1429 | .of_match_table = qcom_scm_dt_match, | |
87abf2ba | 1430 | .suppress_bind_attrs = true, |
d0f6fa7b AG |
1431 | }, |
1432 | .probe = qcom_scm_probe, | |
8c1b7dc9 | 1433 | .shutdown = qcom_scm_shutdown, |
d0f6fa7b AG |
1434 | }; |
1435 | ||
1436 | static int __init qcom_scm_init(void) | |
1437 | { | |
d0f6fa7b AG |
1438 | return platform_driver_register(&qcom_scm_driver); |
1439 | } | |
6c8e99d8 | 1440 | subsys_initcall(qcom_scm_init); |
b42000e4 JS |
1441 | |
1442 | MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver"); | |
1443 | MODULE_LICENSE("GPL v2"); |