[linux-2.6-block.git] / drivers / firewire / ohci.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _FIREWIRE_OHCI_H
#define _FIREWIRE_OHCI_H

/* OHCI register map */

#define OHCI1394_Version                      0x000
#define OHCI1394_GUID_ROM                     0x004
#define OHCI1394_ATRetries                    0x008
#define OHCI1394_CSRData                      0x00C
#define OHCI1394_CSRCompareData               0x010
#define OHCI1394_CSRControl                   0x014
#define OHCI1394_ConfigROMhdr                 0x018
#define OHCI1394_BusID                        0x01C
#define OHCI1394_BusOptions                   0x020
#define OHCI1394_GUIDHi                       0x024
#define OHCI1394_GUIDLo                       0x028
#define OHCI1394_ConfigROMmap                 0x034
#define OHCI1394_PostedWriteAddressLo         0x038
#define OHCI1394_PostedWriteAddressHi         0x03C
#define OHCI1394_VendorID                     0x040
#define OHCI1394_HCControlSet                 0x050
#define OHCI1394_HCControlClear               0x054
#define  OHCI1394_HCControl_BIBimageValid	0x80000000
#define  OHCI1394_HCControl_noByteSwapData	0x40000000
#define  OHCI1394_HCControl_programPhyEnable	0x00800000
#define  OHCI1394_HCControl_aPhyEnhanceEnable	0x00400000
#define  OHCI1394_HCControl_LPS			0x00080000
#define  OHCI1394_HCControl_postedWriteEnable	0x00040000
#define  OHCI1394_HCControl_linkEnable		0x00020000
#define  OHCI1394_HCControl_softReset		0x00010000
#define OHCI1394_SelfIDBuffer                 0x064
#define OHCI1394_SelfIDCount                  0x068
#define OHCI1394_IRMultiChanMaskHiSet         0x070
#define OHCI1394_IRMultiChanMaskHiClear       0x074
#define OHCI1394_IRMultiChanMaskLoSet         0x078
#define OHCI1394_IRMultiChanMaskLoClear       0x07C
#define OHCI1394_IntEventSet                  0x080
#define OHCI1394_IntEventClear                0x084
#define OHCI1394_IntMaskSet                   0x088
#define OHCI1394_IntMaskClear                 0x08C
#define OHCI1394_IsoXmitIntEventSet           0x090
#define OHCI1394_IsoXmitIntEventClear         0x094
#define OHCI1394_IsoXmitIntMaskSet            0x098
#define OHCI1394_IsoXmitIntMaskClear          0x09C
#define OHCI1394_IsoRecvIntEventSet           0x0A0
#define OHCI1394_IsoRecvIntEventClear         0x0A4
#define OHCI1394_IsoRecvIntMaskSet            0x0A8
#define OHCI1394_IsoRecvIntMaskClear          0x0AC
#define OHCI1394_InitialBandwidthAvailable    0x0B0
#define OHCI1394_InitialChannelsAvailableHi   0x0B4
#define OHCI1394_InitialChannelsAvailableLo   0x0B8
#define OHCI1394_FairnessControl              0x0DC
#define OHCI1394_LinkControlSet               0x0E0
#define OHCI1394_LinkControlClear             0x0E4
#define   OHCI1394_LinkControl_rcvSelfID	(1 << 9)
#define   OHCI1394_LinkControl_rcvPhyPkt	(1 << 10)
#define   OHCI1394_LinkControl_cycleTimerEnable	(1 << 20)
#define   OHCI1394_LinkControl_cycleMaster	(1 << 21)
#define   OHCI1394_LinkControl_cycleSource	(1 << 22)
#define OHCI1394_NodeID                       0x0E8
#define   OHCI1394_NodeID_idValid             0x80000000
#define   OHCI1394_NodeID_root                0x40000000
#define   OHCI1394_NodeID_nodeNumber          0x0000003f
#define   OHCI1394_NodeID_busNumber           0x0000ffc0
#define OHCI1394_PhyControl                   0x0EC
#define   OHCI1394_PhyControl_Read(addr)	(((addr) << 8) | 0x00008000)
#define   OHCI1394_PhyControl_ReadDone		0x80000000
#define   OHCI1394_PhyControl_ReadData(r)	(((r) & 0x00ff0000) >> 16)
#define   OHCI1394_PhyControl_Write(addr, data)	(((addr) << 8) | (data) | 0x00004000)
#define   OHCI1394_PhyControl_WritePending	0x00004000
#define OHCI1394_IsochronousCycleTimer        0x0F0
#define OHCI1394_AsReqFilterHiSet             0x100
#define OHCI1394_AsReqFilterHiClear           0x104
#define OHCI1394_AsReqFilterLoSet             0x108
#define OHCI1394_AsReqFilterLoClear           0x10C
#define OHCI1394_PhyReqFilterHiSet            0x110
#define OHCI1394_PhyReqFilterHiClear          0x114
#define OHCI1394_PhyReqFilterLoSet            0x118
#define OHCI1394_PhyReqFilterLoClear          0x11C
#define OHCI1394_PhyUpperBound                0x120

#define OHCI1394_AsReqTrContextBase           0x180
#define OHCI1394_AsReqTrContextControlSet     0x180
#define OHCI1394_AsReqTrContextControlClear   0x184
#define OHCI1394_AsReqTrCommandPtr            0x18C

#define OHCI1394_AsRspTrContextBase           0x1A0
#define OHCI1394_AsRspTrContextControlSet     0x1A0
#define OHCI1394_AsRspTrContextControlClear   0x1A4
#define OHCI1394_AsRspTrCommandPtr            0x1AC

#define OHCI1394_AsReqRcvContextBase          0x1C0
#define OHCI1394_AsReqRcvContextControlSet    0x1C0
#define OHCI1394_AsReqRcvContextControlClear  0x1C4
#define OHCI1394_AsReqRcvCommandPtr           0x1CC

#define OHCI1394_AsRspRcvContextBase          0x1E0
#define OHCI1394_AsRspRcvContextControlSet    0x1E0
#define OHCI1394_AsRspRcvContextControlClear  0x1E4
#define OHCI1394_AsRspRcvCommandPtr           0x1EC

/* Isochronous transmit registers */
#define OHCI1394_IsoXmitContextBase(n)           (0x200 + 16 * (n))
#define OHCI1394_IsoXmitContextControlSet(n)     (0x200 + 16 * (n))
#define OHCI1394_IsoXmitContextControlClear(n)   (0x204 + 16 * (n))
#define OHCI1394_IsoXmitCommandPtr(n)            (0x20C + 16 * (n))

/* Isochronous receive registers */
#define OHCI1394_IsoRcvContextBase(n)         (0x400 + 32 * (n))
#define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n))
#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
#define OHCI1394_IsoRcvCommandPtr(n)          (0x40C + 32 * (n))
#define OHCI1394_IsoRcvContextMatch(n)        (0x410 + 32 * (n))

/* Interrupts Mask/Events */
#define OHCI1394_reqTxComplete		0x00000001
#define OHCI1394_respTxComplete		0x00000002
#define OHCI1394_ARRQ			0x00000004
#define OHCI1394_ARRS			0x00000008
#define OHCI1394_RQPkt			0x00000010
#define OHCI1394_RSPkt			0x00000020
#define OHCI1394_isochTx		0x00000040
#define OHCI1394_isochRx		0x00000080
#define OHCI1394_postedWriteErr		0x00000100
#define OHCI1394_lockRespErr		0x00000200
#define OHCI1394_selfIDComplete		0x00010000
#define OHCI1394_busReset		0x00020000
#define OHCI1394_regAccessFail		0x00040000
#define OHCI1394_phy			0x00080000
#define OHCI1394_cycleSynch		0x00100000
#define OHCI1394_cycle64Seconds		0x00200000
#define OHCI1394_cycleLost		0x00400000
#define OHCI1394_cycleInconsistent	0x00800000
#define OHCI1394_unrecoverableError	0x01000000
#define OHCI1394_cycleTooLong		0x02000000
#define OHCI1394_phyRegRcvd		0x04000000
#define OHCI1394_masterIntEnable	0x80000000

#define OHCI1394_evt_no_status		0x0
#define OHCI1394_evt_long_packet	0x2
#define OHCI1394_evt_missing_ack	0x3
#define OHCI1394_evt_underrun		0x4
#define OHCI1394_evt_overrun		0x5
#define OHCI1394_evt_descriptor_read	0x6
#define OHCI1394_evt_data_read		0x7
#define OHCI1394_evt_data_write		0x8
#define OHCI1394_evt_bus_reset		0x9
#define OHCI1394_evt_timeout		0xa
#define OHCI1394_evt_tcode_err		0xb
#define OHCI1394_evt_reserved_b		0xc
#define OHCI1394_evt_reserved_c		0xd
#define OHCI1394_evt_unknown		0xe
#define OHCI1394_evt_flushed		0xf

#define OHCI1394_phy_tcode		0xe

// Self-ID DMA.

#define OHCI1394_SelfIDCount_selfIDError_MASK		0x80000000
#define OHCI1394_SelfIDCount_selfIDError_SHIFT		31
#define OHCI1394_SelfIDCount_selfIDGeneration_MASK	0x00ff0000
#define OHCI1394_SelfIDCount_selfIDGeneration_SHIFT	16
#define OHCI1394_SelfIDCount_selfIDSize_MASK		0x000007fc
#define OHCI1394_SelfIDCount_selfIDSize_SHIFT		2

static inline bool ohci1394_self_id_count_is_error(u32 value)
{
	return !!((value & OHCI1394_SelfIDCount_selfIDError_MASK) >> OHCI1394_SelfIDCount_selfIDError_SHIFT);
}

static inline u8 ohci1394_self_id_count_get_generation(u32 value)
{
	return (value & OHCI1394_SelfIDCount_selfIDGeneration_MASK) >> OHCI1394_SelfIDCount_selfIDGeneration_SHIFT;
}

// In 1394 OHCI specification, the maximum size of self ID stream is 504 quadlets
// (= 63 devices * 4 self ID packets * 2 quadlets). The selfIDSize field accommodates it and its
// additional first quadlet, since the field is 9 bits (0x1ff = 511).
static inline u32 ohci1394_self_id_count_get_size(u32 value)
{
	return (value & OHCI1394_SelfIDCount_selfIDSize_MASK) >> OHCI1394_SelfIDCount_selfIDSize_SHIFT;
}

#define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK	0x00ff0000
#define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT	16
#define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK	0x0000ffff
#define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT	0

static inline u8 ohci1394_self_id_receive_q0_get_generation(u32 quadlet0)
{
	return (quadlet0 & OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK) >> OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT;
}

static inline u16 ohci1394_self_id_receive_q0_get_timestamp(u32 quadlet0)
{
	return (quadlet0 & OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK) >> OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT;
}

#endif /* _FIREWIRE_OHCI_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
77c9a5da SR	2	#ifndef _FIREWIRE_OHCI_H
77c9a5da SR	3	#define _FIREWIRE_OHCI_H
ed568912 KH	4
	5	/* OHCI register map */
	6
	7	#define OHCI1394_Version 0x000
	8	#define OHCI1394_GUID_ROM 0x004
	9	#define OHCI1394_ATRetries 0x008
	10	#define OHCI1394_CSRData 0x00C
	11	#define OHCI1394_CSRCompareData 0x010
	12	#define OHCI1394_CSRControl 0x014
	13	#define OHCI1394_ConfigROMhdr 0x018
	14	#define OHCI1394_BusID 0x01C
	15	#define OHCI1394_BusOptions 0x020
	16	#define OHCI1394_GUIDHi 0x024
	17	#define OHCI1394_GUIDLo 0x028
	18	#define OHCI1394_ConfigROMmap 0x034
	19	#define OHCI1394_PostedWriteAddressLo 0x038
	20	#define OHCI1394_PostedWriteAddressHi 0x03C
	21	#define OHCI1394_VendorID 0x040
	22	#define OHCI1394_HCControlSet 0x050
	23	#define OHCI1394_HCControlClear 0x054
	24	#define OHCI1394_HCControl_BIBimageValid 0x80000000
	25	#define OHCI1394_HCControl_noByteSwapData 0x40000000
	26	#define OHCI1394_HCControl_programPhyEnable 0x00800000
	27	#define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
	28	#define OHCI1394_HCControl_LPS 0x00080000
	29	#define OHCI1394_HCControl_postedWriteEnable 0x00040000
	30	#define OHCI1394_HCControl_linkEnable 0x00020000
	31	#define OHCI1394_HCControl_softReset 0x00010000
	32	#define OHCI1394_SelfIDBuffer 0x064
	33	#define OHCI1394_SelfIDCount 0x068
	34	#define OHCI1394_IRMultiChanMaskHiSet 0x070
	35	#define OHCI1394_IRMultiChanMaskHiClear 0x074
	36	#define OHCI1394_IRMultiChanMaskLoSet 0x078
	37	#define OHCI1394_IRMultiChanMaskLoClear 0x07C
	38	#define OHCI1394_IntEventSet 0x080
	39	#define OHCI1394_IntEventClear 0x084
	40	#define OHCI1394_IntMaskSet 0x088
	41	#define OHCI1394_IntMaskClear 0x08C
	42	#define OHCI1394_IsoXmitIntEventSet 0x090
	43	#define OHCI1394_IsoXmitIntEventClear 0x094
	44	#define OHCI1394_IsoXmitIntMaskSet 0x098
	45	#define OHCI1394_IsoXmitIntMaskClear 0x09C
	46	#define OHCI1394_IsoRecvIntEventSet 0x0A0
	47	#define OHCI1394_IsoRecvIntEventClear 0x0A4
	48	#define OHCI1394_IsoRecvIntMaskSet 0x0A8
	49	#define OHCI1394_IsoRecvIntMaskClear 0x0AC
	50	#define OHCI1394_InitialBandwidthAvailable 0x0B0
	51	#define OHCI1394_InitialChannelsAvailableHi 0x0B4
	52	#define OHCI1394_InitialChannelsAvailableLo 0x0B8
	53	#define OHCI1394_FairnessControl 0x0DC
	54	#define OHCI1394_LinkControlSet 0x0E0
	55	#define OHCI1394_LinkControlClear 0x0E4
	56	#define OHCI1394_LinkControl_rcvSelfID (1 << 9)
	57	#define OHCI1394_LinkControl_rcvPhyPkt (1 << 10)
	58	#define OHCI1394_LinkControl_cycleTimerEnable (1 << 20)
	59	#define OHCI1394_LinkControl_cycleMaster (1 << 21)
	60	#define OHCI1394_LinkControl_cycleSource (1 << 22)
	61	#define OHCI1394_NodeID 0x0E8
	62	#define OHCI1394_NodeID_idValid 0x80000000
4ffb7a6a	63	#define OHCI1394_NodeID_root 0x40000000
02ff8f8e SR	64	#define OHCI1394_NodeID_nodeNumber 0x0000003f
02ff8f8e SR	65	#define OHCI1394_NodeID_busNumber 0x0000ffc0
ed568912 KH	66	#define OHCI1394_PhyControl 0x0EC
	67	#define OHCI1394_PhyControl_Read(addr) (((addr) << 8) \| 0x00008000)
	68	#define OHCI1394_PhyControl_ReadDone 0x80000000
	69	#define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
5e20c282	70	#define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) \| (data) \| 0x00004000)
925e7a65	71	#define OHCI1394_PhyControl_WritePending 0x00004000
ed568912 KH	72	#define OHCI1394_IsochronousCycleTimer 0x0F0
	73	#define OHCI1394_AsReqFilterHiSet 0x100
	74	#define OHCI1394_AsReqFilterHiClear 0x104
	75	#define OHCI1394_AsReqFilterLoSet 0x108
	76	#define OHCI1394_AsReqFilterLoClear 0x10C
	77	#define OHCI1394_PhyReqFilterHiSet 0x110
	78	#define OHCI1394_PhyReqFilterHiClear 0x114
	79	#define OHCI1394_PhyReqFilterLoSet 0x118
	80	#define OHCI1394_PhyReqFilterLoClear 0x11C
	81	#define OHCI1394_PhyUpperBound 0x120
	82
	83	#define OHCI1394_AsReqTrContextBase 0x180
	84	#define OHCI1394_AsReqTrContextControlSet 0x180
	85	#define OHCI1394_AsReqTrContextControlClear 0x184
	86	#define OHCI1394_AsReqTrCommandPtr 0x18C
	87
	88	#define OHCI1394_AsRspTrContextBase 0x1A0
	89	#define OHCI1394_AsRspTrContextControlSet 0x1A0
	90	#define OHCI1394_AsRspTrContextControlClear 0x1A4
	91	#define OHCI1394_AsRspTrCommandPtr 0x1AC
	92
	93	#define OHCI1394_AsReqRcvContextBase 0x1C0
	94	#define OHCI1394_AsReqRcvContextControlSet 0x1C0
	95	#define OHCI1394_AsReqRcvContextControlClear 0x1C4
	96	#define OHCI1394_AsReqRcvCommandPtr 0x1CC
	97
	98	#define OHCI1394_AsRspRcvContextBase 0x1E0
	99	#define OHCI1394_AsRspRcvContextControlSet 0x1E0
	100	#define OHCI1394_AsRspRcvContextControlClear 0x1E4
	101	#define OHCI1394_AsRspRcvCommandPtr 0x1EC
	102
	103	/* Isochronous transmit registers */
	104	#define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
	105	#define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
	106	#define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n))
	107	#define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n))
	108
	109	/* Isochronous receive registers */
295e3feb	110	#define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n))
ed568912 KH	111	#define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n))
	112	#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
	113	#define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n))
	114	#define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
	115
	116	/* Interrupts Mask/Events */
5e20c282 SR	117	#define OHCI1394_reqTxComplete 0x00000001
	118	#define OHCI1394_respTxComplete 0x00000002
	119	#define OHCI1394_ARRQ 0x00000004
	120	#define OHCI1394_ARRS 0x00000008
	121	#define OHCI1394_RQPkt 0x00000010
	122	#define OHCI1394_RSPkt 0x00000020
	123	#define OHCI1394_isochTx 0x00000040
	124	#define OHCI1394_isochRx 0x00000080
	125	#define OHCI1394_postedWriteErr 0x00000100
	126	#define OHCI1394_lockRespErr 0x00000200
	127	#define OHCI1394_selfIDComplete 0x00010000
	128	#define OHCI1394_busReset 0x00020000
75f7832e	129	#define OHCI1394_regAccessFail 0x00040000
5e20c282 SR	130	#define OHCI1394_phy 0x00080000
	131	#define OHCI1394_cycleSynch 0x00100000
	132	#define OHCI1394_cycle64Seconds 0x00200000
	133	#define OHCI1394_cycleLost 0x00400000
	134	#define OHCI1394_cycleInconsistent 0x00800000
	135	#define OHCI1394_unrecoverableError 0x01000000
	136	#define OHCI1394_cycleTooLong 0x02000000
	137	#define OHCI1394_phyRegRcvd 0x04000000
	138	#define OHCI1394_masterIntEnable 0x80000000
ed568912 KH	139
	140	#define OHCI1394_evt_no_status 0x0
	141	#define OHCI1394_evt_long_packet 0x2
	142	#define OHCI1394_evt_missing_ack 0x3
	143	#define OHCI1394_evt_underrun 0x4
	144	#define OHCI1394_evt_overrun 0x5
	145	#define OHCI1394_evt_descriptor_read 0x6
	146	#define OHCI1394_evt_data_read 0x7
	147	#define OHCI1394_evt_data_write 0x8
	148	#define OHCI1394_evt_bus_reset 0x9
	149	#define OHCI1394_evt_timeout 0xa
	150	#define OHCI1394_evt_tcode_err 0xb
	151	#define OHCI1394_evt_reserved_b 0xc
	152	#define OHCI1394_evt_reserved_c 0xd
	153	#define OHCI1394_evt_unknown 0xe
	154	#define OHCI1394_evt_flushed 0xf
	155
	156	#define OHCI1394_phy_tcode 0xe
	157
7a14f78d TS	158	// Self-ID DMA.
	159
	160	#define OHCI1394_SelfIDCount_selfIDError_MASK 0x80000000
	161	#define OHCI1394_SelfIDCount_selfIDError_SHIFT 31
	162	#define OHCI1394_SelfIDCount_selfIDGeneration_MASK 0x00ff0000
	163	#define OHCI1394_SelfIDCount_selfIDGeneration_SHIFT 16
	164	#define OHCI1394_SelfIDCount_selfIDSize_MASK 0x000007fc
	165	#define OHCI1394_SelfIDCount_selfIDSize_SHIFT 2
	166
	167	static inline bool ohci1394_self_id_count_is_error(u32 value)
	168	{
	169	return !!((value & OHCI1394_SelfIDCount_selfIDError_MASK) >> OHCI1394_SelfIDCount_selfIDError_SHIFT);
	170	}
	171
	172	static inline u8 ohci1394_self_id_count_get_generation(u32 value)
	173	{
	174	return (value & OHCI1394_SelfIDCount_selfIDGeneration_MASK) >> OHCI1394_SelfIDCount_selfIDGeneration_SHIFT;
	175	}
	176
	177	// In 1394 OHCI specification, the maximum size of self ID stream is 504 quadlets
	178	// (= 63 devices * 4 self ID packets * 2 quadlets). The selfIDSize field accommodates it and its
	179	// additional first quadlet, since the field is 9 bits (0x1ff = 511).
	180	static inline u32 ohci1394_self_id_count_get_size(u32 value)
	181	{
	182	return (value & OHCI1394_SelfIDCount_selfIDSize_MASK) >> OHCI1394_SelfIDCount_selfIDSize_SHIFT;
	183	}
	184
	185	#define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK 0x00ff0000
	186	#define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT 16
	187	#define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK 0x0000ffff
	188	#define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT 0
	189
	190	static inline u8 ohci1394_self_id_receive_q0_get_generation(u32 quadlet0)
	191	{
	192	return (quadlet0 & OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK) >> OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT;
	193	}
	194
	195	static inline u16 ohci1394_self_id_receive_q0_get_timestamp(u32 quadlet0)
	196	{
	197	return (quadlet0 & OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK) >> OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT;
	198	}
	199
77c9a5da	200	#endif /* _FIREWIRE_OHCI_H */