Commit | Line | Data |
---|---|---|
c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
e524f616 | 21 | #include <linux/compiler.h> |
ed568912 | 22 | #include <linux/delay.h> |
cf3e72fd | 23 | #include <linux/dma-mapping.h> |
c26f0234 | 24 | #include <linux/gfp.h> |
a7fb60db SR |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/kernel.h> | |
faa2fb4e | 28 | #include <linux/mm.h> |
a7fb60db SR |
29 | #include <linux/module.h> |
30 | #include <linux/pci.h> | |
c26f0234 | 31 | #include <linux/spinlock.h> |
cf3e72fd | 32 | |
c26f0234 | 33 | #include <asm/page.h> |
ee71c2f9 | 34 | #include <asm/system.h> |
ed568912 | 35 | |
ed568912 | 36 | #include "fw-ohci.h" |
a7fb60db | 37 | #include "fw-transaction.h" |
ed568912 | 38 | |
a77754a7 KH |
39 | #define DESCRIPTOR_OUTPUT_MORE 0 |
40 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
41 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
42 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
43 | #define DESCRIPTOR_STATUS (1 << 11) | |
44 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
45 | #define DESCRIPTOR_PING (1 << 7) | |
46 | #define DESCRIPTOR_YY (1 << 6) | |
47 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
48 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
49 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
50 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
51 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
52 | |
53 | struct descriptor { | |
54 | __le16 req_count; | |
55 | __le16 control; | |
56 | __le32 data_address; | |
57 | __le32 branch_address; | |
58 | __le16 res_count; | |
59 | __le16 transfer_status; | |
60 | } __attribute__((aligned(16))); | |
61 | ||
295e3feb KH |
62 | struct db_descriptor { |
63 | __le16 first_size; | |
64 | __le16 control; | |
65 | __le16 second_req_count; | |
66 | __le16 first_req_count; | |
67 | __le32 branch_address; | |
68 | __le16 second_res_count; | |
69 | __le16 first_res_count; | |
70 | __le32 reserved0; | |
71 | __le32 first_buffer; | |
72 | __le32 second_buffer; | |
73 | __le32 reserved1; | |
74 | } __attribute__((aligned(16))); | |
75 | ||
a77754a7 KH |
76 | #define CONTROL_SET(regs) (regs) |
77 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
78 | #define COMMAND_PTR(regs) ((regs) + 12) | |
79 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 80 | |
32b46093 | 81 | struct ar_buffer { |
ed568912 | 82 | struct descriptor descriptor; |
32b46093 KH |
83 | struct ar_buffer *next; |
84 | __le32 data[0]; | |
85 | }; | |
ed568912 | 86 | |
32b46093 KH |
87 | struct ar_context { |
88 | struct fw_ohci *ohci; | |
89 | struct ar_buffer *current_buffer; | |
90 | struct ar_buffer *last_buffer; | |
91 | void *pointer; | |
72e318e0 | 92 | u32 regs; |
ed568912 KH |
93 | struct tasklet_struct tasklet; |
94 | }; | |
95 | ||
30200739 KH |
96 | struct context; |
97 | ||
98 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
99 | struct descriptor *d, | |
100 | struct descriptor *last); | |
101 | struct context { | |
373b2edd | 102 | struct fw_ohci *ohci; |
30200739 | 103 | u32 regs; |
373b2edd | 104 | |
30200739 KH |
105 | struct descriptor *buffer; |
106 | dma_addr_t buffer_bus; | |
107 | size_t buffer_size; | |
108 | struct descriptor *head_descriptor; | |
109 | struct descriptor *tail_descriptor; | |
110 | struct descriptor *tail_descriptor_last; | |
111 | struct descriptor *prev_descriptor; | |
112 | ||
113 | descriptor_callback_t callback; | |
114 | ||
373b2edd | 115 | struct tasklet_struct tasklet; |
30200739 | 116 | }; |
30200739 | 117 | |
a77754a7 KH |
118 | #define IT_HEADER_SY(v) ((v) << 0) |
119 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
120 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
121 | #define IT_HEADER_TAG(v) ((v) << 14) | |
122 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
123 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
124 | |
125 | struct iso_context { | |
126 | struct fw_iso_context base; | |
30200739 | 127 | struct context context; |
9b32d5f3 KH |
128 | void *header; |
129 | size_t header_length; | |
ed568912 KH |
130 | }; |
131 | ||
132 | #define CONFIG_ROM_SIZE 1024 | |
133 | ||
134 | struct fw_ohci { | |
135 | struct fw_card card; | |
136 | ||
e364cf4e | 137 | u32 version; |
ed568912 KH |
138 | __iomem char *registers; |
139 | dma_addr_t self_id_bus; | |
140 | __le32 *self_id_cpu; | |
141 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 142 | int node_id; |
ed568912 KH |
143 | int generation; |
144 | int request_generation; | |
d60d7f1d | 145 | u32 bus_seconds; |
ed568912 | 146 | |
c781c06d KH |
147 | /* |
148 | * Spinlock for accessing fw_ohci data. Never call out of | |
149 | * this driver with this lock held. | |
150 | */ | |
ed568912 KH |
151 | spinlock_t lock; |
152 | u32 self_id_buffer[512]; | |
153 | ||
154 | /* Config rom buffers */ | |
155 | __be32 *config_rom; | |
156 | dma_addr_t config_rom_bus; | |
157 | __be32 *next_config_rom; | |
158 | dma_addr_t next_config_rom_bus; | |
159 | u32 next_header; | |
160 | ||
161 | struct ar_context ar_request_ctx; | |
162 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
163 | struct context at_request_ctx; |
164 | struct context at_response_ctx; | |
ed568912 KH |
165 | |
166 | u32 it_context_mask; | |
167 | struct iso_context *it_context_list; | |
168 | u32 ir_context_mask; | |
169 | struct iso_context *ir_context_list; | |
170 | }; | |
171 | ||
95688e97 | 172 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
173 | { |
174 | return container_of(card, struct fw_ohci, card); | |
175 | } | |
176 | ||
295e3feb KH |
177 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
178 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
179 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
180 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
181 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
182 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
183 | |
184 | #define CONTEXT_RUN 0x8000 | |
185 | #define CONTEXT_WAKE 0x1000 | |
186 | #define CONTEXT_DEAD 0x0800 | |
187 | #define CONTEXT_ACTIVE 0x0400 | |
188 | ||
189 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
190 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
191 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
192 | ||
193 | #define FW_OHCI_MAJOR 240 | |
194 | #define OHCI1394_REGISTER_SIZE 0x800 | |
195 | #define OHCI_LOOP_COUNT 500 | |
196 | #define OHCI1394_PCI_HCI_Control 0x40 | |
197 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 198 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 199 | #define OHCI_VERSION_1_1 0x010010 |
f319b6a0 KH |
200 | #define ISO_BUFFER_SIZE (64 * 1024) |
201 | #define AT_BUFFER_SIZE 4096 | |
0edeefd9 | 202 | |
ed568912 KH |
203 | static char ohci_driver_name[] = KBUILD_MODNAME; |
204 | ||
95688e97 | 205 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
206 | { |
207 | writel(data, ohci->registers + offset); | |
208 | } | |
209 | ||
95688e97 | 210 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
211 | { |
212 | return readl(ohci->registers + offset); | |
213 | } | |
214 | ||
95688e97 | 215 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
216 | { |
217 | /* Do a dummy read to flush writes. */ | |
218 | reg_read(ohci, OHCI1394_Version); | |
219 | } | |
220 | ||
221 | static int | |
222 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
223 | int clear_bits, int set_bits) | |
224 | { | |
225 | struct fw_ohci *ohci = fw_ohci(card); | |
226 | u32 val, old; | |
227 | ||
228 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
362e901c | 229 | flush_writes(ohci); |
ed568912 KH |
230 | msleep(2); |
231 | val = reg_read(ohci, OHCI1394_PhyControl); | |
232 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
233 | fw_error("failed to set phy reg bits.\n"); | |
234 | return -EBUSY; | |
235 | } | |
236 | ||
237 | old = OHCI1394_PhyControl_ReadData(val); | |
238 | old = (old & ~clear_bits) | set_bits; | |
239 | reg_write(ohci, OHCI1394_PhyControl, | |
240 | OHCI1394_PhyControl_Write(addr, old)); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
32b46093 | 245 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 246 | { |
32b46093 KH |
247 | struct device *dev = ctx->ohci->card.device; |
248 | struct ar_buffer *ab; | |
249 | dma_addr_t ab_bus; | |
250 | size_t offset; | |
251 | ||
252 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
253 | if (ab == NULL) | |
254 | return -ENOMEM; | |
255 | ||
256 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
257 | if (dma_mapping_error(ab_bus)) { | |
258 | free_page((unsigned long) ab); | |
259 | return -ENOMEM; | |
260 | } | |
261 | ||
2d826cc5 | 262 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
263 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
264 | DESCRIPTOR_STATUS | | |
265 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
266 | offset = offsetof(struct ar_buffer, data); |
267 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
268 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
269 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
270 | ab->descriptor.branch_address = 0; | |
271 | ||
272 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
273 | ||
ec839e43 | 274 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
275 | ctx->last_buffer->next = ab; |
276 | ctx->last_buffer = ab; | |
277 | ||
a77754a7 | 278 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 279 | flush_writes(ctx->ohci); |
32b46093 KH |
280 | |
281 | return 0; | |
ed568912 KH |
282 | } |
283 | ||
32b46093 | 284 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 285 | { |
ed568912 | 286 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
287 | struct fw_packet p; |
288 | u32 status, length, tcode; | |
2639a6fb | 289 | |
32b46093 KH |
290 | p.header[0] = le32_to_cpu(buffer[0]); |
291 | p.header[1] = le32_to_cpu(buffer[1]); | |
292 | p.header[2] = le32_to_cpu(buffer[2]); | |
2639a6fb KH |
293 | |
294 | tcode = (p.header[0] >> 4) & 0x0f; | |
295 | switch (tcode) { | |
296 | case TCODE_WRITE_QUADLET_REQUEST: | |
297 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 298 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 299 | p.header_length = 16; |
32b46093 | 300 | p.payload_length = 0; |
2639a6fb KH |
301 | break; |
302 | ||
2639a6fb | 303 | case TCODE_READ_BLOCK_REQUEST : |
32b46093 KH |
304 | p.header[3] = le32_to_cpu(buffer[3]); |
305 | p.header_length = 16; | |
306 | p.payload_length = 0; | |
307 | break; | |
308 | ||
309 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
310 | case TCODE_READ_BLOCK_RESPONSE: |
311 | case TCODE_LOCK_REQUEST: | |
312 | case TCODE_LOCK_RESPONSE: | |
32b46093 | 313 | p.header[3] = le32_to_cpu(buffer[3]); |
2639a6fb | 314 | p.header_length = 16; |
32b46093 | 315 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
316 | break; |
317 | ||
318 | case TCODE_WRITE_RESPONSE: | |
319 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 320 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 321 | p.header_length = 12; |
32b46093 | 322 | p.payload_length = 0; |
2639a6fb KH |
323 | break; |
324 | } | |
ed568912 | 325 | |
32b46093 KH |
326 | p.payload = (void *) buffer + p.header_length; |
327 | ||
328 | /* FIXME: What to do about evt_* errors? */ | |
329 | length = (p.header_length + p.payload_length + 3) / 4; | |
330 | status = le32_to_cpu(buffer[length]); | |
331 | ||
332 | p.ack = ((status >> 16) & 0x1f) - 16; | |
333 | p.speed = (status >> 21) & 0x7; | |
334 | p.timestamp = status & 0xffff; | |
335 | p.generation = ohci->request_generation; | |
ed568912 | 336 | |
c781c06d KH |
337 | /* |
338 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
339 | * the new generation number when a bus reset happens (see |
340 | * section 8.4.2.3). This helps us determine when a request | |
341 | * was received and make sure we send the response in the same | |
342 | * generation. We only need this for requests; for responses | |
343 | * we use the unique tlabel for finding the matching | |
c781c06d KH |
344 | * request. |
345 | */ | |
ed568912 | 346 | |
2639a6fb | 347 | if (p.ack + 16 == 0x09) |
32b46093 | 348 | ohci->request_generation = (buffer[2] >> 16) & 0xff; |
ed568912 | 349 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 350 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 351 | else |
2639a6fb | 352 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 353 | |
32b46093 KH |
354 | return buffer + length + 1; |
355 | } | |
ed568912 | 356 | |
32b46093 KH |
357 | static void ar_context_tasklet(unsigned long data) |
358 | { | |
359 | struct ar_context *ctx = (struct ar_context *)data; | |
360 | struct fw_ohci *ohci = ctx->ohci; | |
361 | struct ar_buffer *ab; | |
362 | struct descriptor *d; | |
363 | void *buffer, *end; | |
364 | ||
365 | ab = ctx->current_buffer; | |
366 | d = &ab->descriptor; | |
367 | ||
368 | if (d->res_count == 0) { | |
369 | size_t size, rest, offset; | |
370 | ||
c781c06d KH |
371 | /* |
372 | * This descriptor is finished and we may have a | |
32b46093 | 373 | * packet split across this and the next buffer. We |
c781c06d KH |
374 | * reuse the page for reassembling the split packet. |
375 | */ | |
32b46093 KH |
376 | |
377 | offset = offsetof(struct ar_buffer, data); | |
378 | dma_unmap_single(ohci->card.device, | |
0a9972ba SR |
379 | le32_to_cpu(ab->descriptor.data_address) - offset, |
380 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
32b46093 KH |
381 | |
382 | buffer = ab; | |
383 | ab = ab->next; | |
384 | d = &ab->descriptor; | |
385 | size = buffer + PAGE_SIZE - ctx->pointer; | |
386 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
387 | memmove(buffer, ctx->pointer, size); | |
388 | memcpy(buffer + size, ab->data, rest); | |
389 | ctx->current_buffer = ab; | |
390 | ctx->pointer = (void *) ab->data + rest; | |
391 | end = buffer + size + rest; | |
392 | ||
393 | while (buffer < end) | |
394 | buffer = handle_ar_packet(ctx, buffer); | |
395 | ||
396 | free_page((unsigned long)buffer); | |
397 | ar_context_add_page(ctx); | |
398 | } else { | |
399 | buffer = ctx->pointer; | |
400 | ctx->pointer = end = | |
401 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
402 | ||
403 | while (buffer < end) | |
404 | buffer = handle_ar_packet(ctx, buffer); | |
405 | } | |
ed568912 KH |
406 | } |
407 | ||
408 | static int | |
72e318e0 | 409 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 410 | { |
32b46093 | 411 | struct ar_buffer ab; |
ed568912 | 412 | |
72e318e0 KH |
413 | ctx->regs = regs; |
414 | ctx->ohci = ohci; | |
415 | ctx->last_buffer = &ab; | |
ed568912 KH |
416 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
417 | ||
32b46093 KH |
418 | ar_context_add_page(ctx); |
419 | ar_context_add_page(ctx); | |
420 | ctx->current_buffer = ab.next; | |
421 | ctx->pointer = ctx->current_buffer->data; | |
422 | ||
2aef469a KH |
423 | return 0; |
424 | } | |
425 | ||
426 | static void ar_context_run(struct ar_context *ctx) | |
427 | { | |
428 | struct ar_buffer *ab = ctx->current_buffer; | |
429 | dma_addr_t ab_bus; | |
430 | size_t offset; | |
431 | ||
432 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 433 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
434 | |
435 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 436 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 437 | flush_writes(ctx->ohci); |
ed568912 | 438 | } |
373b2edd | 439 | |
a186b4a6 JW |
440 | static struct descriptor * |
441 | find_branch_descriptor(struct descriptor *d, int z) | |
442 | { | |
443 | int b, key; | |
444 | ||
445 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
446 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
447 | ||
448 | /* figure out which descriptor the branch address goes in */ | |
449 | if (z == 2 && (b == 3 || key == 2)) | |
450 | return d; | |
451 | else | |
452 | return d + z - 1; | |
453 | } | |
454 | ||
30200739 KH |
455 | static void context_tasklet(unsigned long data) |
456 | { | |
457 | struct context *ctx = (struct context *) data; | |
458 | struct fw_ohci *ohci = ctx->ohci; | |
459 | struct descriptor *d, *last; | |
460 | u32 address; | |
461 | int z; | |
462 | ||
463 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
464 | ctx->buffer_size, DMA_TO_DEVICE); | |
465 | ||
466 | d = ctx->tail_descriptor; | |
467 | last = ctx->tail_descriptor_last; | |
468 | ||
469 | while (last->branch_address != 0) { | |
470 | address = le32_to_cpu(last->branch_address); | |
471 | z = address & 0xf; | |
2d826cc5 | 472 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d); |
a186b4a6 | 473 | last = find_branch_descriptor(d, z); |
30200739 KH |
474 | |
475 | if (!ctx->callback(ctx, d, last)) | |
476 | break; | |
477 | ||
478 | ctx->tail_descriptor = d; | |
479 | ctx->tail_descriptor_last = last; | |
480 | } | |
481 | } | |
482 | ||
483 | static int | |
484 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
485 | size_t buffer_size, u32 regs, | |
486 | descriptor_callback_t callback) | |
487 | { | |
488 | ctx->ohci = ohci; | |
489 | ctx->regs = regs; | |
490 | ctx->buffer_size = buffer_size; | |
491 | ctx->buffer = kmalloc(buffer_size, GFP_KERNEL); | |
492 | if (ctx->buffer == NULL) | |
493 | return -ENOMEM; | |
494 | ||
495 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); | |
496 | ctx->callback = callback; | |
497 | ||
498 | ctx->buffer_bus = | |
499 | dma_map_single(ohci->card.device, ctx->buffer, | |
500 | buffer_size, DMA_TO_DEVICE); | |
501 | if (dma_mapping_error(ctx->buffer_bus)) { | |
502 | kfree(ctx->buffer); | |
503 | return -ENOMEM; | |
504 | } | |
505 | ||
506 | ctx->head_descriptor = ctx->buffer; | |
507 | ctx->prev_descriptor = ctx->buffer; | |
508 | ctx->tail_descriptor = ctx->buffer; | |
509 | ctx->tail_descriptor_last = ctx->buffer; | |
510 | ||
c781c06d KH |
511 | /* |
512 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 KH |
513 | * branch address and looks like it's been sent. That way we |
514 | * have a descriptor to append DMA programs to. Also, the | |
515 | * ring buffer invariant is that it always has at least one | |
c781c06d KH |
516 | * element so that head == tail means buffer full. |
517 | */ | |
30200739 | 518 | |
2d826cc5 | 519 | memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor)); |
a77754a7 | 520 | ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); |
30200739 KH |
521 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); |
522 | ctx->head_descriptor++; | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
9b32d5f3 | 527 | static void |
30200739 KH |
528 | context_release(struct context *ctx) |
529 | { | |
530 | struct fw_card *card = &ctx->ohci->card; | |
531 | ||
532 | dma_unmap_single(card->device, ctx->buffer_bus, | |
533 | ctx->buffer_size, DMA_TO_DEVICE); | |
534 | kfree(ctx->buffer); | |
535 | } | |
536 | ||
537 | static struct descriptor * | |
538 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
539 | { | |
540 | struct descriptor *d, *tail, *end; | |
541 | ||
542 | d = ctx->head_descriptor; | |
543 | tail = ctx->tail_descriptor; | |
2d826cc5 | 544 | end = ctx->buffer + ctx->buffer_size / sizeof(*d); |
30200739 KH |
545 | |
546 | if (d + z <= tail) { | |
547 | goto has_space; | |
548 | } else if (d > tail && d + z <= end) { | |
549 | goto has_space; | |
550 | } else if (d > tail && ctx->buffer + z <= tail) { | |
551 | d = ctx->buffer; | |
552 | goto has_space; | |
553 | } | |
554 | ||
555 | return NULL; | |
556 | ||
557 | has_space: | |
2d826cc5 KH |
558 | memset(d, 0, z * sizeof(*d)); |
559 | *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d); | |
30200739 KH |
560 | |
561 | return d; | |
562 | } | |
563 | ||
295e3feb | 564 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
565 | { |
566 | struct fw_ohci *ohci = ctx->ohci; | |
567 | ||
a77754a7 | 568 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
30200739 | 569 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); |
a77754a7 KH |
570 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
571 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
572 | flush_writes(ohci); |
573 | } | |
574 | ||
575 | static void context_append(struct context *ctx, | |
576 | struct descriptor *d, int z, int extra) | |
577 | { | |
578 | dma_addr_t d_bus; | |
579 | ||
2d826cc5 | 580 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d); |
30200739 KH |
581 | |
582 | ctx->head_descriptor = d + z + extra; | |
583 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
a186b4a6 | 584 | ctx->prev_descriptor = find_branch_descriptor(d, z); |
30200739 KH |
585 | |
586 | dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus, | |
587 | ctx->buffer_size, DMA_TO_DEVICE); | |
588 | ||
a77754a7 | 589 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
590 | flush_writes(ctx->ohci); |
591 | } | |
592 | ||
593 | static void context_stop(struct context *ctx) | |
594 | { | |
595 | u32 reg; | |
b8295668 | 596 | int i; |
30200739 | 597 | |
a77754a7 | 598 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 599 | flush_writes(ctx->ohci); |
30200739 | 600 | |
b8295668 | 601 | for (i = 0; i < 10; i++) { |
a77754a7 | 602 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 KH |
603 | if ((reg & CONTEXT_ACTIVE) == 0) |
604 | break; | |
605 | ||
606 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
b980f5a2 | 607 | mdelay(1); |
b8295668 | 608 | } |
30200739 | 609 | } |
ed568912 | 610 | |
f319b6a0 KH |
611 | struct driver_data { |
612 | struct fw_packet *packet; | |
613 | }; | |
ed568912 | 614 | |
c781c06d KH |
615 | /* |
616 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 617 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
618 | * generation handling and locking around packet queue manipulation. |
619 | */ | |
f319b6a0 KH |
620 | static int |
621 | at_context_queue_packet(struct context *ctx, struct fw_packet *packet) | |
ed568912 | 622 | { |
ed568912 | 623 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 624 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
625 | struct driver_data *driver_data; |
626 | struct descriptor *d, *last; | |
627 | __le32 *header; | |
ed568912 | 628 | int z, tcode; |
f319b6a0 | 629 | u32 reg; |
ed568912 | 630 | |
f319b6a0 KH |
631 | d = context_get_descriptors(ctx, 4, &d_bus); |
632 | if (d == NULL) { | |
633 | packet->ack = RCODE_SEND_ERROR; | |
634 | return -1; | |
ed568912 KH |
635 | } |
636 | ||
a77754a7 | 637 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
638 | d[0].res_count = cpu_to_le16(packet->timestamp); |
639 | ||
c781c06d KH |
640 | /* |
641 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
642 | * from the IEEE1394 layout, so shift the fields around |
643 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
644 | * which we need to prepend an extra quadlet. |
645 | */ | |
f319b6a0 KH |
646 | |
647 | header = (__le32 *) &d[1]; | |
ed568912 | 648 | if (packet->header_length > 8) { |
f319b6a0 KH |
649 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
650 | (packet->speed << 16)); | |
651 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
652 | (packet->header[0] & 0xffff0000)); | |
653 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
654 | |
655 | tcode = (packet->header[0] >> 4) & 0x0f; | |
656 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 657 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 658 | else |
f319b6a0 KH |
659 | header[3] = (__force __le32) packet->header[3]; |
660 | ||
661 | d[0].req_count = cpu_to_le16(packet->header_length); | |
ed568912 | 662 | } else { |
f319b6a0 KH |
663 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
664 | (packet->speed << 16)); | |
665 | header[1] = cpu_to_le32(packet->header[0]); | |
666 | header[2] = cpu_to_le32(packet->header[1]); | |
667 | d[0].req_count = cpu_to_le16(12); | |
ed568912 KH |
668 | } |
669 | ||
f319b6a0 KH |
670 | driver_data = (struct driver_data *) &d[3]; |
671 | driver_data->packet = packet; | |
20d11673 | 672 | packet->driver_data = driver_data; |
a186b4a6 | 673 | |
f319b6a0 KH |
674 | if (packet->payload_length > 0) { |
675 | payload_bus = | |
676 | dma_map_single(ohci->card.device, packet->payload, | |
677 | packet->payload_length, DMA_TO_DEVICE); | |
678 | if (dma_mapping_error(payload_bus)) { | |
679 | packet->ack = RCODE_SEND_ERROR; | |
680 | return -1; | |
681 | } | |
682 | ||
683 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
684 | d[2].data_address = cpu_to_le32(payload_bus); | |
685 | last = &d[2]; | |
686 | z = 3; | |
ed568912 | 687 | } else { |
f319b6a0 KH |
688 | last = &d[0]; |
689 | z = 2; | |
ed568912 | 690 | } |
ed568912 | 691 | |
a77754a7 KH |
692 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
693 | DESCRIPTOR_IRQ_ALWAYS | | |
694 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 695 | |
f319b6a0 KH |
696 | /* FIXME: Document how the locking works. */ |
697 | if (ohci->generation != packet->generation) { | |
ab88ca48 SR |
698 | if (packet->payload_length > 0) |
699 | dma_unmap_single(ohci->card.device, payload_bus, | |
700 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
701 | packet->ack = RCODE_GENERATION; |
702 | return -1; | |
703 | } | |
704 | ||
705 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 706 | |
f319b6a0 | 707 | /* If the context isn't already running, start it up. */ |
a77754a7 | 708 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 709 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
710 | context_run(ctx, 0); |
711 | ||
712 | return 0; | |
ed568912 KH |
713 | } |
714 | ||
f319b6a0 KH |
715 | static int handle_at_packet(struct context *context, |
716 | struct descriptor *d, | |
717 | struct descriptor *last) | |
ed568912 | 718 | { |
f319b6a0 | 719 | struct driver_data *driver_data; |
ed568912 | 720 | struct fw_packet *packet; |
f319b6a0 KH |
721 | struct fw_ohci *ohci = context->ohci; |
722 | dma_addr_t payload_bus; | |
ed568912 KH |
723 | int evt; |
724 | ||
f319b6a0 KH |
725 | if (last->transfer_status == 0) |
726 | /* This descriptor isn't done yet, stop iteration. */ | |
727 | return 0; | |
ed568912 | 728 | |
f319b6a0 KH |
729 | driver_data = (struct driver_data *) &d[3]; |
730 | packet = driver_data->packet; | |
731 | if (packet == NULL) | |
732 | /* This packet was cancelled, just continue. */ | |
733 | return 1; | |
730c32f5 | 734 | |
f319b6a0 KH |
735 | payload_bus = le32_to_cpu(last->data_address); |
736 | if (payload_bus != 0) | |
737 | dma_unmap_single(ohci->card.device, payload_bus, | |
ed568912 | 738 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 739 | |
f319b6a0 KH |
740 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
741 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 742 | |
f319b6a0 KH |
743 | switch (evt) { |
744 | case OHCI1394_evt_timeout: | |
745 | /* Async response transmit timed out. */ | |
746 | packet->ack = RCODE_CANCELLED; | |
747 | break; | |
ed568912 | 748 | |
f319b6a0 | 749 | case OHCI1394_evt_flushed: |
c781c06d KH |
750 | /* |
751 | * The packet was flushed should give same error as | |
752 | * when we try to use a stale generation count. | |
753 | */ | |
f319b6a0 KH |
754 | packet->ack = RCODE_GENERATION; |
755 | break; | |
ed568912 | 756 | |
f319b6a0 | 757 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
758 | /* |
759 | * Using a valid (current) generation count, but the | |
760 | * node is not on the bus or not sending acks. | |
761 | */ | |
f319b6a0 KH |
762 | packet->ack = RCODE_NO_ACK; |
763 | break; | |
ed568912 | 764 | |
f319b6a0 KH |
765 | case ACK_COMPLETE + 0x10: |
766 | case ACK_PENDING + 0x10: | |
767 | case ACK_BUSY_X + 0x10: | |
768 | case ACK_BUSY_A + 0x10: | |
769 | case ACK_BUSY_B + 0x10: | |
770 | case ACK_DATA_ERROR + 0x10: | |
771 | case ACK_TYPE_ERROR + 0x10: | |
772 | packet->ack = evt - 0x10; | |
773 | break; | |
ed568912 | 774 | |
f319b6a0 KH |
775 | default: |
776 | packet->ack = RCODE_SEND_ERROR; | |
777 | break; | |
778 | } | |
ed568912 | 779 | |
f319b6a0 | 780 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 781 | |
f319b6a0 | 782 | return 1; |
ed568912 KH |
783 | } |
784 | ||
a77754a7 KH |
785 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
786 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
787 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
788 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
789 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb KH |
790 | |
791 | static void | |
792 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
793 | { | |
794 | struct fw_packet response; | |
795 | int tcode, length, i; | |
796 | ||
a77754a7 | 797 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 798 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 799 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
800 | else |
801 | length = 4; | |
802 | ||
803 | i = csr - CSR_CONFIG_ROM; | |
804 | if (i + length > CONFIG_ROM_SIZE) { | |
805 | fw_fill_response(&response, packet->header, | |
806 | RCODE_ADDRESS_ERROR, NULL, 0); | |
807 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
808 | fw_fill_response(&response, packet->header, | |
809 | RCODE_TYPE_ERROR, NULL, 0); | |
810 | } else { | |
811 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
812 | (void *) ohci->config_rom + i, length); | |
813 | } | |
814 | ||
815 | fw_core_handle_response(&ohci->card, &response); | |
816 | } | |
817 | ||
818 | static void | |
819 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
820 | { | |
821 | struct fw_packet response; | |
822 | int tcode, length, ext_tcode, sel; | |
823 | __be32 *payload, lock_old; | |
824 | u32 lock_arg, lock_data; | |
825 | ||
a77754a7 KH |
826 | tcode = HEADER_GET_TCODE(packet->header[0]); |
827 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 828 | payload = packet->payload; |
a77754a7 | 829 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
830 | |
831 | if (tcode == TCODE_LOCK_REQUEST && | |
832 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
833 | lock_arg = be32_to_cpu(payload[0]); | |
834 | lock_data = be32_to_cpu(payload[1]); | |
835 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
836 | lock_arg = 0; | |
837 | lock_data = 0; | |
838 | } else { | |
839 | fw_fill_response(&response, packet->header, | |
840 | RCODE_TYPE_ERROR, NULL, 0); | |
841 | goto out; | |
842 | } | |
843 | ||
844 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
845 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
846 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
847 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
848 | ||
849 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
850 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
851 | else | |
852 | fw_notify("swap not done yet\n"); | |
853 | ||
854 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 855 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
856 | out: |
857 | fw_core_handle_response(&ohci->card, &response); | |
858 | } | |
859 | ||
860 | static void | |
f319b6a0 | 861 | handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
862 | { |
863 | u64 offset; | |
864 | u32 csr; | |
865 | ||
473d28c7 KH |
866 | if (ctx == &ctx->ohci->at_request_ctx) { |
867 | packet->ack = ACK_PENDING; | |
868 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
869 | } | |
93c4cceb KH |
870 | |
871 | offset = | |
872 | ((unsigned long long) | |
a77754a7 | 873 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
874 | packet->header[2]; |
875 | csr = offset - CSR_REGISTER_BASE; | |
876 | ||
877 | /* Handle config rom reads. */ | |
878 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
879 | handle_local_rom(ctx->ohci, packet, csr); | |
880 | else switch (csr) { | |
881 | case CSR_BUS_MANAGER_ID: | |
882 | case CSR_BANDWIDTH_AVAILABLE: | |
883 | case CSR_CHANNELS_AVAILABLE_HI: | |
884 | case CSR_CHANNELS_AVAILABLE_LO: | |
885 | handle_local_lock(ctx->ohci, packet, csr); | |
886 | break; | |
887 | default: | |
888 | if (ctx == &ctx->ohci->at_request_ctx) | |
889 | fw_core_handle_request(&ctx->ohci->card, packet); | |
890 | else | |
891 | fw_core_handle_response(&ctx->ohci->card, packet); | |
892 | break; | |
893 | } | |
473d28c7 KH |
894 | |
895 | if (ctx == &ctx->ohci->at_response_ctx) { | |
896 | packet->ack = ACK_COMPLETE; | |
897 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
898 | } | |
93c4cceb | 899 | } |
e636fe25 | 900 | |
ed568912 | 901 | static void |
f319b6a0 | 902 | at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 903 | { |
ed568912 | 904 | unsigned long flags; |
f319b6a0 | 905 | int retval; |
ed568912 KH |
906 | |
907 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
908 | ||
a77754a7 | 909 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 910 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
911 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
912 | handle_local_request(ctx, packet); | |
913 | return; | |
e636fe25 | 914 | } |
ed568912 | 915 | |
f319b6a0 | 916 | retval = at_context_queue_packet(ctx, packet); |
ed568912 KH |
917 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
918 | ||
f319b6a0 KH |
919 | if (retval < 0) |
920 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
a186b4a6 | 921 | |
ed568912 KH |
922 | } |
923 | ||
924 | static void bus_reset_tasklet(unsigned long data) | |
925 | { | |
926 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 927 | int self_id_count, i, j, reg; |
ed568912 KH |
928 | int generation, new_generation; |
929 | unsigned long flags; | |
4eaff7d6 SR |
930 | void *free_rom = NULL; |
931 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
932 | |
933 | reg = reg_read(ohci, OHCI1394_NodeID); | |
934 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 935 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
936 | return; |
937 | } | |
02ff8f8e SR |
938 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
939 | fw_notify("malconfigured bus\n"); | |
940 | return; | |
941 | } | |
942 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
943 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 944 | |
c781c06d KH |
945 | /* |
946 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
947 | * bytes in the self ID receive buffer. Since we also receive |
948 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
949 | * bit extra to get the actual number of self IDs. |
950 | */ | |
ed568912 KH |
951 | |
952 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
953 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
ee71c2f9 | 954 | rmb(); |
ed568912 KH |
955 | |
956 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
957 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
958 | fw_error("inconsistent self IDs\n"); | |
959 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
960 | } | |
ee71c2f9 | 961 | rmb(); |
ed568912 | 962 | |
c781c06d KH |
963 | /* |
964 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
965 | * problem we face is that a new bus reset can start while we |
966 | * read out the self IDs from the DMA buffer. If this happens, | |
967 | * the DMA buffer will be overwritten with new self IDs and we | |
968 | * will read out inconsistent data. The OHCI specification | |
969 | * (section 11.2) recommends a technique similar to | |
970 | * linux/seqlock.h, where we remember the generation of the | |
971 | * self IDs in the buffer before reading them out and compare | |
972 | * it to the current generation after reading them out. If | |
973 | * the two generations match we know we have a consistent set | |
c781c06d KH |
974 | * of self IDs. |
975 | */ | |
ed568912 KH |
976 | |
977 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
978 | if (new_generation != generation) { | |
979 | fw_notify("recursive bus reset detected, " | |
980 | "discarding self ids\n"); | |
981 | return; | |
982 | } | |
983 | ||
984 | /* FIXME: Document how the locking works. */ | |
985 | spin_lock_irqsave(&ohci->lock, flags); | |
986 | ||
987 | ohci->generation = generation; | |
f319b6a0 KH |
988 | context_stop(&ohci->at_request_ctx); |
989 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
990 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
991 | ||
c781c06d KH |
992 | /* |
993 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
994 | * have to do it under the spinlock also. If a new config rom |
995 | * was set up before this reset, the old one is now no longer | |
996 | * in use and we can free it. Update the config rom pointers | |
997 | * to point to the current config rom and clear the | |
c781c06d KH |
998 | * next_config_rom pointer so a new udpate can take place. |
999 | */ | |
ed568912 KH |
1000 | |
1001 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1002 | if (ohci->next_config_rom != ohci->config_rom) { |
1003 | free_rom = ohci->config_rom; | |
1004 | free_rom_bus = ohci->config_rom_bus; | |
1005 | } | |
ed568912 KH |
1006 | ohci->config_rom = ohci->next_config_rom; |
1007 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1008 | ohci->next_config_rom = NULL; | |
1009 | ||
c781c06d KH |
1010 | /* |
1011 | * Restore config_rom image and manually update | |
ed568912 KH |
1012 | * config_rom registers. Writing the header quadlet |
1013 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1014 | * do that last. |
1015 | */ | |
ed568912 KH |
1016 | reg_write(ohci, OHCI1394_BusOptions, |
1017 | be32_to_cpu(ohci->config_rom[2])); | |
1018 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
1019 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
1020 | } | |
1021 | ||
1022 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1023 | ||
4eaff7d6 SR |
1024 | if (free_rom) |
1025 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1026 | free_rom, free_rom_bus); | |
1027 | ||
e636fe25 | 1028 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1029 | self_id_count, ohci->self_id_buffer); |
1030 | } | |
1031 | ||
1032 | static irqreturn_t irq_handler(int irq, void *data) | |
1033 | { | |
1034 | struct fw_ohci *ohci = data; | |
d60d7f1d | 1035 | u32 event, iso_event, cycle_time; |
ed568912 KH |
1036 | int i; |
1037 | ||
1038 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1039 | ||
a515958d | 1040 | if (!event || !~event) |
ed568912 KH |
1041 | return IRQ_NONE; |
1042 | ||
1043 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
1044 | ||
1045 | if (event & OHCI1394_selfIDComplete) | |
1046 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1047 | ||
1048 | if (event & OHCI1394_RQPkt) | |
1049 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1050 | ||
1051 | if (event & OHCI1394_RSPkt) | |
1052 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1053 | ||
1054 | if (event & OHCI1394_reqTxComplete) | |
1055 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1056 | ||
1057 | if (event & OHCI1394_respTxComplete) | |
1058 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1059 | ||
c889475f | 1060 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1061 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1062 | ||
1063 | while (iso_event) { | |
1064 | i = ffs(iso_event) - 1; | |
30200739 | 1065 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1066 | iso_event &= ~(1 << i); |
1067 | } | |
1068 | ||
c889475f | 1069 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1070 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1071 | ||
1072 | while (iso_event) { | |
1073 | i = ffs(iso_event) - 1; | |
30200739 | 1074 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1075 | iso_event &= ~(1 << i); |
1076 | } | |
1077 | ||
e524f616 SR |
1078 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1079 | fw_error("PCI posted write error\n"); | |
1080 | ||
d60d7f1d KH |
1081 | if (event & OHCI1394_cycle64Seconds) { |
1082 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1083 | if ((cycle_time & 0x80000000) == 0) | |
1084 | ohci->bus_seconds++; | |
1085 | } | |
1086 | ||
ed568912 KH |
1087 | return IRQ_HANDLED; |
1088 | } | |
1089 | ||
2aef469a KH |
1090 | static int software_reset(struct fw_ohci *ohci) |
1091 | { | |
1092 | int i; | |
1093 | ||
1094 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1095 | ||
1096 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1097 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1098 | OHCI1394_HCControl_softReset) == 0) | |
1099 | return 0; | |
1100 | msleep(1); | |
1101 | } | |
1102 | ||
1103 | return -EBUSY; | |
1104 | } | |
1105 | ||
ed568912 KH |
1106 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) |
1107 | { | |
1108 | struct fw_ohci *ohci = fw_ohci(card); | |
1109 | struct pci_dev *dev = to_pci_dev(card->device); | |
1110 | ||
2aef469a KH |
1111 | if (software_reset(ohci)) { |
1112 | fw_error("Failed to reset ohci card.\n"); | |
1113 | return -EBUSY; | |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * Now enable LPS, which we need in order to start accessing | |
1118 | * most of the registers. In fact, on some cards (ALI M5251), | |
1119 | * accessing registers in the SClk domain without LPS enabled | |
1120 | * will lock up the machine. Wait 50msec to make sure we have | |
1121 | * full link enabled. | |
1122 | */ | |
1123 | reg_write(ohci, OHCI1394_HCControlSet, | |
1124 | OHCI1394_HCControl_LPS | | |
1125 | OHCI1394_HCControl_postedWriteEnable); | |
1126 | flush_writes(ohci); | |
1127 | msleep(50); | |
1128 | ||
1129 | reg_write(ohci, OHCI1394_HCControlClear, | |
1130 | OHCI1394_HCControl_noByteSwapData); | |
1131 | ||
1132 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1133 | OHCI1394_LinkControl_rcvSelfID | | |
1134 | OHCI1394_LinkControl_cycleTimerEnable | | |
1135 | OHCI1394_LinkControl_cycleMaster); | |
1136 | ||
1137 | reg_write(ohci, OHCI1394_ATRetries, | |
1138 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1139 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1140 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1141 | ||
1142 | ar_context_run(&ohci->ar_request_ctx); | |
1143 | ar_context_run(&ohci->ar_response_ctx); | |
1144 | ||
1145 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1146 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1147 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1148 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1149 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1150 | OHCI1394_selfIDComplete | | |
1151 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1152 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1153 | OHCI1394_isochRx | OHCI1394_isochTx | | |
e524f616 SR |
1154 | OHCI1394_postedWriteErr | OHCI1394_cycle64Seconds | |
1155 | OHCI1394_masterIntEnable); | |
2aef469a KH |
1156 | |
1157 | /* Activate link_on bit and contender bit in our self ID packets.*/ | |
1158 | if (ohci_update_phy_reg(card, 4, 0, | |
1159 | PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) | |
1160 | return -EIO; | |
1161 | ||
c781c06d KH |
1162 | /* |
1163 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1164 | * update mechanism described below in ohci_set_config_rom() |
1165 | * is not active. We have to update ConfigRomHeader and | |
1166 | * BusOptions manually, and the write to ConfigROMmap takes | |
1167 | * effect immediately. We tie this to the enabling of the | |
1168 | * link, so we have a valid config rom before enabling - the | |
1169 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1170 | * values before enabling. | |
1171 | * | |
1172 | * However, when the ConfigROMmap is written, some controllers | |
1173 | * always read back quadlets 0 and 2 from the config rom to | |
1174 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1175 | * They shouldn't do that in this initial case where the link | |
1176 | * isn't enabled. This means we have to use the same | |
1177 | * workaround here, setting the bus header to 0 and then write | |
1178 | * the right values in the bus reset tasklet. | |
1179 | */ | |
1180 | ||
0bd243c4 KH |
1181 | if (config_rom) { |
1182 | ohci->next_config_rom = | |
1183 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1184 | &ohci->next_config_rom_bus, | |
1185 | GFP_KERNEL); | |
1186 | if (ohci->next_config_rom == NULL) | |
1187 | return -ENOMEM; | |
ed568912 | 1188 | |
0bd243c4 KH |
1189 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); |
1190 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1191 | } else { | |
1192 | /* | |
1193 | * In the suspend case, config_rom is NULL, which | |
1194 | * means that we just reuse the old config rom. | |
1195 | */ | |
1196 | ohci->next_config_rom = ohci->config_rom; | |
1197 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1198 | } | |
ed568912 | 1199 | |
0bd243c4 | 1200 | ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]); |
ed568912 KH |
1201 | ohci->next_config_rom[0] = 0; |
1202 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1203 | reg_write(ohci, OHCI1394_BusOptions, |
1204 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1205 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1206 | ||
1207 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1208 | ||
1209 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1210 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1211 | fw_error("Failed to allocate shared interrupt %d.\n", |
1212 | dev->irq); | |
1213 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1214 | ohci->config_rom, ohci->config_rom_bus); | |
1215 | return -EIO; | |
1216 | } | |
1217 | ||
1218 | reg_write(ohci, OHCI1394_HCControlSet, | |
1219 | OHCI1394_HCControl_linkEnable | | |
1220 | OHCI1394_HCControl_BIBimageValid); | |
1221 | flush_writes(ohci); | |
1222 | ||
c781c06d KH |
1223 | /* |
1224 | * We are ready to go, initiate bus reset to finish the | |
1225 | * initialization. | |
1226 | */ | |
ed568912 KH |
1227 | |
1228 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static int | |
1234 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1235 | { | |
1236 | struct fw_ohci *ohci; | |
1237 | unsigned long flags; | |
4eaff7d6 | 1238 | int retval = -EBUSY; |
ed568912 KH |
1239 | __be32 *next_config_rom; |
1240 | dma_addr_t next_config_rom_bus; | |
1241 | ||
1242 | ohci = fw_ohci(card); | |
1243 | ||
c781c06d KH |
1244 | /* |
1245 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1246 | * mechanism is a bit tricky, but easy enough to use. See |
1247 | * section 5.5.6 in the OHCI specification. | |
1248 | * | |
1249 | * The OHCI controller caches the new config rom address in a | |
1250 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1251 | * for the changes to take place. When the bus reset is | |
1252 | * detected, the controller loads the new values for the | |
1253 | * ConfigRomHeader and BusOptions registers from the specified | |
1254 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1255 | * shadow register. All automatically and atomically. | |
1256 | * | |
1257 | * Now, there's a twist to this story. The automatic load of | |
1258 | * ConfigRomHeader and BusOptions doesn't honor the | |
1259 | * noByteSwapData bit, so with a be32 config rom, the | |
1260 | * controller will load be32 values in to these registers | |
1261 | * during the atomic update, even on litte endian | |
1262 | * architectures. The workaround we use is to put a 0 in the | |
1263 | * header quadlet; 0 is endian agnostic and means that the | |
1264 | * config rom isn't ready yet. In the bus reset tasklet we | |
1265 | * then set up the real values for the two registers. | |
1266 | * | |
1267 | * We use ohci->lock to avoid racing with the code that sets | |
1268 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1269 | */ | |
1270 | ||
1271 | next_config_rom = | |
1272 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1273 | &next_config_rom_bus, GFP_KERNEL); | |
1274 | if (next_config_rom == NULL) | |
1275 | return -ENOMEM; | |
1276 | ||
1277 | spin_lock_irqsave(&ohci->lock, flags); | |
1278 | ||
1279 | if (ohci->next_config_rom == NULL) { | |
1280 | ohci->next_config_rom = next_config_rom; | |
1281 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1282 | ||
1283 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1284 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1285 | length * 4); | |
1286 | ||
1287 | ohci->next_header = config_rom[0]; | |
1288 | ohci->next_config_rom[0] = 0; | |
1289 | ||
1290 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1291 | ohci->next_config_rom_bus); | |
4eaff7d6 | 1292 | retval = 0; |
ed568912 KH |
1293 | } |
1294 | ||
1295 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1296 | ||
c781c06d KH |
1297 | /* |
1298 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1299 | * effect. We clean up the old config rom memory and DMA |
1300 | * mappings in the bus reset tasklet, since the OHCI | |
1301 | * controller could need to access it before the bus reset | |
c781c06d KH |
1302 | * takes effect. |
1303 | */ | |
ed568912 KH |
1304 | if (retval == 0) |
1305 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
4eaff7d6 SR |
1306 | else |
1307 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1308 | next_config_rom, next_config_rom_bus); | |
ed568912 KH |
1309 | |
1310 | return retval; | |
1311 | } | |
1312 | ||
1313 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1314 | { | |
1315 | struct fw_ohci *ohci = fw_ohci(card); | |
1316 | ||
1317 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1318 | } | |
1319 | ||
1320 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1321 | { | |
1322 | struct fw_ohci *ohci = fw_ohci(card); | |
1323 | ||
1324 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1325 | } | |
1326 | ||
730c32f5 KH |
1327 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1328 | { | |
1329 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1330 | struct context *ctx = &ohci->at_request_ctx; |
1331 | struct driver_data *driver_data = packet->driver_data; | |
1332 | int retval = -ENOENT; | |
730c32f5 | 1333 | |
f319b6a0 | 1334 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1335 | |
f319b6a0 KH |
1336 | if (packet->ack != 0) |
1337 | goto out; | |
730c32f5 | 1338 | |
f319b6a0 KH |
1339 | driver_data->packet = NULL; |
1340 | packet->ack = RCODE_CANCELLED; | |
1341 | packet->callback(packet, &ohci->card, packet->ack); | |
1342 | retval = 0; | |
730c32f5 | 1343 | |
f319b6a0 KH |
1344 | out: |
1345 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1346 | |
f319b6a0 | 1347 | return retval; |
730c32f5 KH |
1348 | } |
1349 | ||
ed568912 KH |
1350 | static int |
1351 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1352 | { | |
1353 | struct fw_ohci *ohci = fw_ohci(card); | |
1354 | unsigned long flags; | |
907293d7 | 1355 | int n, retval = 0; |
ed568912 | 1356 | |
c781c06d KH |
1357 | /* |
1358 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1359 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1360 | */ | |
ed568912 KH |
1361 | |
1362 | spin_lock_irqsave(&ohci->lock, flags); | |
1363 | ||
1364 | if (ohci->generation != generation) { | |
1365 | retval = -ESTALE; | |
1366 | goto out; | |
1367 | } | |
1368 | ||
c781c06d KH |
1369 | /* |
1370 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1371 | * enabled for _all_ nodes on remote buses. | |
1372 | */ | |
907293d7 SR |
1373 | |
1374 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1375 | if (n < 32) | |
1376 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1377 | else | |
1378 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1379 | ||
ed568912 | 1380 | flush_writes(ohci); |
ed568912 | 1381 | out: |
6cad95fe | 1382 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1383 | return retval; |
1384 | } | |
373b2edd | 1385 | |
d60d7f1d KH |
1386 | static u64 |
1387 | ohci_get_bus_time(struct fw_card *card) | |
1388 | { | |
1389 | struct fw_ohci *ohci = fw_ohci(card); | |
1390 | u32 cycle_time; | |
1391 | u64 bus_time; | |
1392 | ||
1393 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1394 | bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time; | |
1395 | ||
1396 | return bus_time; | |
1397 | } | |
1398 | ||
d2746dc1 KH |
1399 | static int handle_ir_dualbuffer_packet(struct context *context, |
1400 | struct descriptor *d, | |
1401 | struct descriptor *last) | |
ed568912 | 1402 | { |
295e3feb KH |
1403 | struct iso_context *ctx = |
1404 | container_of(context, struct iso_context, context); | |
1405 | struct db_descriptor *db = (struct db_descriptor *) d; | |
c70dc788 | 1406 | __le32 *ir_header; |
9b32d5f3 | 1407 | size_t header_length; |
c70dc788 KH |
1408 | void *p, *end; |
1409 | int i; | |
d2746dc1 | 1410 | |
295e3feb KH |
1411 | if (db->first_res_count > 0 && db->second_res_count > 0) |
1412 | /* This descriptor isn't done yet, stop iteration. */ | |
1413 | return 0; | |
1414 | ||
c70dc788 KH |
1415 | header_length = le16_to_cpu(db->first_req_count) - |
1416 | le16_to_cpu(db->first_res_count); | |
1417 | ||
1418 | i = ctx->header_length; | |
1419 | p = db + 1; | |
1420 | end = p + header_length; | |
1421 | while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { | |
c781c06d KH |
1422 | /* |
1423 | * The iso header is byteswapped to little endian by | |
15536221 KH |
1424 | * the controller, but the remaining header quadlets |
1425 | * are big endian. We want to present all the headers | |
1426 | * as big endian, so we have to swap the first | |
c781c06d KH |
1427 | * quadlet. |
1428 | */ | |
15536221 KH |
1429 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); |
1430 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
c70dc788 KH |
1431 | i += ctx->base.header_size; |
1432 | p += ctx->base.header_size + 4; | |
1433 | } | |
1434 | ||
1435 | ctx->header_length = i; | |
9b32d5f3 | 1436 | |
a77754a7 | 1437 | if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788 KH |
1438 | ir_header = (__le32 *) (db + 1); |
1439 | ctx->base.callback(&ctx->base, | |
1440 | le32_to_cpu(ir_header[0]) & 0xffff, | |
9b32d5f3 | 1441 | ctx->header_length, ctx->header, |
295e3feb | 1442 | ctx->base.callback_data); |
9b32d5f3 KH |
1443 | ctx->header_length = 0; |
1444 | } | |
ed568912 | 1445 | |
295e3feb | 1446 | return 1; |
ed568912 KH |
1447 | } |
1448 | ||
a186b4a6 JW |
1449 | static int handle_ir_packet_per_buffer(struct context *context, |
1450 | struct descriptor *d, | |
1451 | struct descriptor *last) | |
1452 | { | |
1453 | struct iso_context *ctx = | |
1454 | container_of(context, struct iso_context, context); | |
1455 | struct descriptor *pd = d + 1; | |
1456 | __le32 *ir_header; | |
1457 | size_t header_length; | |
1458 | void *p, *end; | |
1459 | int i, z; | |
1460 | ||
1461 | if (pd->res_count == pd->req_count) | |
1462 | /* Descriptor(s) not done yet, stop iteration */ | |
1463 | return 0; | |
1464 | ||
1465 | header_length = le16_to_cpu(d->req_count); | |
1466 | ||
1467 | i = ctx->header_length; | |
1468 | z = le32_to_cpu(pd->branch_address) & 0xf; | |
1469 | p = d + z; | |
1470 | end = p + header_length; | |
1471 | ||
1472 | while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { | |
1473 | /* | |
1474 | * The iso header is byteswapped to little endian by | |
1475 | * the controller, but the remaining header quadlets | |
1476 | * are big endian. We want to present all the headers | |
1477 | * as big endian, so we have to swap the first quadlet. | |
1478 | */ | |
1479 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
1480 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
1481 | i += ctx->base.header_size; | |
1482 | p += ctx->base.header_size + 4; | |
1483 | } | |
1484 | ||
1485 | ctx->header_length = i; | |
1486 | ||
1487 | if (le16_to_cpu(pd->control) & DESCRIPTOR_IRQ_ALWAYS) { | |
1488 | ir_header = (__le32 *) (d + z); | |
1489 | ctx->base.callback(&ctx->base, | |
1490 | le32_to_cpu(ir_header[0]) & 0xffff, | |
1491 | ctx->header_length, ctx->header, | |
1492 | ctx->base.callback_data); | |
1493 | ctx->header_length = 0; | |
1494 | } | |
1495 | ||
1496 | ||
1497 | return 1; | |
1498 | } | |
1499 | ||
30200739 KH |
1500 | static int handle_it_packet(struct context *context, |
1501 | struct descriptor *d, | |
1502 | struct descriptor *last) | |
ed568912 | 1503 | { |
30200739 KH |
1504 | struct iso_context *ctx = |
1505 | container_of(context, struct iso_context, context); | |
373b2edd | 1506 | |
30200739 KH |
1507 | if (last->transfer_status == 0) |
1508 | /* This descriptor isn't done yet, stop iteration. */ | |
1509 | return 0; | |
1510 | ||
a77754a7 | 1511 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f3 KH |
1512 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1513 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1514 | |
1515 | return 1; | |
ed568912 KH |
1516 | } |
1517 | ||
30200739 | 1518 | static struct fw_iso_context * |
eb0306ea | 1519 | ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed568912 KH |
1520 | { |
1521 | struct fw_ohci *ohci = fw_ohci(card); | |
1522 | struct iso_context *ctx, *list; | |
30200739 | 1523 | descriptor_callback_t callback; |
295e3feb | 1524 | u32 *mask, regs; |
ed568912 | 1525 | unsigned long flags; |
9b32d5f3 | 1526 | int index, retval = -ENOMEM; |
ed568912 KH |
1527 | |
1528 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1529 | mask = &ohci->it_context_mask; | |
1530 | list = ohci->it_context_list; | |
30200739 | 1531 | callback = handle_it_packet; |
ed568912 | 1532 | } else { |
373b2edd SR |
1533 | mask = &ohci->ir_context_mask; |
1534 | list = ohci->ir_context_list; | |
a186b4a6 JW |
1535 | if (ohci->version >= OHCI_VERSION_1_1) |
1536 | callback = handle_ir_dualbuffer_packet; | |
1537 | else | |
1538 | callback = handle_ir_packet_per_buffer; | |
ed568912 KH |
1539 | } |
1540 | ||
1541 | spin_lock_irqsave(&ohci->lock, flags); | |
1542 | index = ffs(*mask) - 1; | |
1543 | if (index >= 0) | |
1544 | *mask &= ~(1 << index); | |
1545 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1546 | ||
1547 | if (index < 0) | |
1548 | return ERR_PTR(-EBUSY); | |
1549 | ||
373b2edd SR |
1550 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1551 | regs = OHCI1394_IsoXmitContextBase(index); | |
1552 | else | |
1553 | regs = OHCI1394_IsoRcvContextBase(index); | |
1554 | ||
ed568912 | 1555 | ctx = &list[index]; |
2d826cc5 | 1556 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
1557 | ctx->header_length = 0; |
1558 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1559 | if (ctx->header == NULL) | |
1560 | goto out; | |
1561 | ||
30200739 | 1562 | retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE, |
295e3feb | 1563 | regs, callback); |
9b32d5f3 KH |
1564 | if (retval < 0) |
1565 | goto out_with_header; | |
ed568912 KH |
1566 | |
1567 | return &ctx->base; | |
9b32d5f3 KH |
1568 | |
1569 | out_with_header: | |
1570 | free_page((unsigned long)ctx->header); | |
1571 | out: | |
1572 | spin_lock_irqsave(&ohci->lock, flags); | |
1573 | *mask |= 1 << index; | |
1574 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1575 | ||
1576 | return ERR_PTR(retval); | |
ed568912 KH |
1577 | } |
1578 | ||
eb0306ea KH |
1579 | static int ohci_start_iso(struct fw_iso_context *base, |
1580 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 1581 | { |
373b2edd | 1582 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1583 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 1584 | u32 control, match; |
ed568912 KH |
1585 | int index; |
1586 | ||
295e3feb KH |
1587 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1588 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
1589 | match = 0; |
1590 | if (cycle >= 0) | |
1591 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 1592 | (cycle & 0x7fff) << 16; |
21efb3cf | 1593 | |
295e3feb KH |
1594 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
1595 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 1596 | context_run(&ctx->context, match); |
295e3feb KH |
1597 | } else { |
1598 | index = ctx - ohci->ir_context_list; | |
a186b4a6 JW |
1599 | control = IR_CONTEXT_ISOCH_HEADER; |
1600 | if (ohci->version >= OHCI_VERSION_1_1) | |
1601 | control |= IR_CONTEXT_DUAL_BUFFER_MODE; | |
8a2f7d93 KH |
1602 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
1603 | if (cycle >= 0) { | |
1604 | match |= (cycle & 0x07fff) << 12; | |
1605 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
1606 | } | |
ed568912 | 1607 | |
295e3feb KH |
1608 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1609 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 1610 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 1611 | context_run(&ctx->context, control); |
295e3feb | 1612 | } |
ed568912 KH |
1613 | |
1614 | return 0; | |
1615 | } | |
1616 | ||
b8295668 KH |
1617 | static int ohci_stop_iso(struct fw_iso_context *base) |
1618 | { | |
1619 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1620 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
1621 | int index; |
1622 | ||
1623 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1624 | index = ctx - ohci->it_context_list; | |
1625 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1626 | } else { | |
1627 | index = ctx - ohci->ir_context_list; | |
1628 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1629 | } | |
1630 | flush_writes(ohci); | |
1631 | context_stop(&ctx->context); | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
ed568912 KH |
1636 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1637 | { | |
1638 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1639 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1640 | unsigned long flags; |
1641 | int index; | |
1642 | ||
b8295668 KH |
1643 | ohci_stop_iso(base); |
1644 | context_release(&ctx->context); | |
9b32d5f3 | 1645 | free_page((unsigned long)ctx->header); |
b8295668 | 1646 | |
ed568912 KH |
1647 | spin_lock_irqsave(&ohci->lock, flags); |
1648 | ||
1649 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1650 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
1651 | ohci->it_context_mask |= 1 << index; |
1652 | } else { | |
1653 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
1654 | ohci->ir_context_mask |= 1 << index; |
1655 | } | |
ed568912 KH |
1656 | |
1657 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1658 | } | |
1659 | ||
1660 | static int | |
295e3feb KH |
1661 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1662 | struct fw_iso_packet *packet, | |
1663 | struct fw_iso_buffer *buffer, | |
1664 | unsigned long payload) | |
ed568912 | 1665 | { |
373b2edd | 1666 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1667 | struct descriptor *d, *last, *pd; |
ed568912 KH |
1668 | struct fw_iso_packet *p; |
1669 | __le32 *header; | |
9aad8125 | 1670 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1671 | u32 z, header_z, payload_z, irq; |
1672 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1673 | int page, end_page, i, length, offset; |
ed568912 | 1674 | |
c781c06d KH |
1675 | /* |
1676 | * FIXME: Cycle lost behavior should be configurable: lose | |
1677 | * packet, retransmit or terminate.. | |
1678 | */ | |
ed568912 KH |
1679 | |
1680 | p = packet; | |
9aad8125 | 1681 | payload_index = payload; |
ed568912 KH |
1682 | |
1683 | if (p->skip) | |
1684 | z = 1; | |
1685 | else | |
1686 | z = 2; | |
1687 | if (p->header_length > 0) | |
1688 | z++; | |
1689 | ||
1690 | /* Determine the first page the payload isn't contained in. */ | |
1691 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1692 | if (p->payload_length > 0) | |
1693 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1694 | else | |
1695 | payload_z = 0; | |
1696 | ||
1697 | z += payload_z; | |
1698 | ||
1699 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 1700 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 1701 | |
30200739 KH |
1702 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
1703 | if (d == NULL) | |
1704 | return -ENOMEM; | |
ed568912 KH |
1705 | |
1706 | if (!p->skip) { | |
a77754a7 | 1707 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 KH |
1708 | d[0].req_count = cpu_to_le16(8); |
1709 | ||
1710 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
1711 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
1712 | IT_HEADER_TAG(p->tag) | | |
1713 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
1714 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
1715 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 1716 | header[1] = |
a77754a7 | 1717 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
1718 | p->payload_length)); |
1719 | } | |
1720 | ||
1721 | if (p->header_length > 0) { | |
1722 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 1723 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
1724 | memcpy(&d[z], p->header, p->header_length); |
1725 | } | |
1726 | ||
1727 | pd = d + z - payload_z; | |
1728 | payload_end_index = payload_index + p->payload_length; | |
1729 | for (i = 0; i < payload_z; i++) { | |
1730 | page = payload_index >> PAGE_SHIFT; | |
1731 | offset = payload_index & ~PAGE_MASK; | |
1732 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1733 | length = | |
1734 | min(next_page_index, payload_end_index) - payload_index; | |
1735 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
1736 | |
1737 | page_bus = page_private(buffer->pages[page]); | |
1738 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
1739 | |
1740 | payload_index += length; | |
1741 | } | |
1742 | ||
ed568912 | 1743 | if (p->interrupt) |
a77754a7 | 1744 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 1745 | else |
a77754a7 | 1746 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 1747 | |
30200739 | 1748 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
1749 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1750 | DESCRIPTOR_STATUS | | |
1751 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 1752 | irq); |
ed568912 | 1753 | |
30200739 | 1754 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
1755 | |
1756 | return 0; | |
1757 | } | |
373b2edd | 1758 | |
295e3feb | 1759 | static int |
d2746dc1 KH |
1760 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
1761 | struct fw_iso_packet *packet, | |
1762 | struct fw_iso_buffer *buffer, | |
1763 | unsigned long payload) | |
295e3feb KH |
1764 | { |
1765 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1766 | struct db_descriptor *db = NULL; | |
1767 | struct descriptor *d; | |
1768 | struct fw_iso_packet *p; | |
1769 | dma_addr_t d_bus, page_bus; | |
1770 | u32 z, header_z, length, rest; | |
c70dc788 | 1771 | int page, offset, packet_count, header_size; |
373b2edd | 1772 | |
c781c06d KH |
1773 | /* |
1774 | * FIXME: Cycle lost behavior should be configurable: lose | |
1775 | * packet, retransmit or terminate.. | |
1776 | */ | |
295e3feb | 1777 | |
c70dc788 KH |
1778 | if (packet->skip) { |
1779 | d = context_get_descriptors(&ctx->context, 2, &d_bus); | |
1780 | if (d == NULL) | |
1781 | return -ENOMEM; | |
1782 | ||
1783 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
1784 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
1785 | DESCRIPTOR_BRANCH_ALWAYS | | |
1786 | DESCRIPTOR_WAIT); | |
c70dc788 KH |
1787 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
1788 | context_append(&ctx->context, d, 2, 0); | |
1789 | } | |
98b6cbe8 | 1790 | |
295e3feb KH |
1791 | p = packet; |
1792 | z = 2; | |
1793 | ||
c781c06d KH |
1794 | /* |
1795 | * The OHCI controller puts the status word in the header | |
1796 | * buffer too, so we need 4 extra bytes per packet. | |
1797 | */ | |
c70dc788 KH |
1798 | packet_count = p->header_length / ctx->base.header_size; |
1799 | header_size = packet_count * (ctx->base.header_size + 4); | |
1800 | ||
295e3feb | 1801 | /* Get header size in number of descriptors. */ |
2d826cc5 | 1802 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb KH |
1803 | page = payload >> PAGE_SHIFT; |
1804 | offset = payload & ~PAGE_MASK; | |
1805 | rest = p->payload_length; | |
1806 | ||
295e3feb KH |
1807 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ |
1808 | while (rest > 0) { | |
1809 | d = context_get_descriptors(&ctx->context, | |
1810 | z + header_z, &d_bus); | |
1811 | if (d == NULL) | |
1812 | return -ENOMEM; | |
1813 | ||
1814 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
1815 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
1816 | DESCRIPTOR_BRANCH_ALWAYS); | |
c70dc788 KH |
1817 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
1818 | db->first_req_count = cpu_to_le16(header_size); | |
1e1d196b | 1819 | db->first_res_count = db->first_req_count; |
2d826cc5 | 1820 | db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd | 1821 | |
295e3feb KH |
1822 | if (offset + rest < PAGE_SIZE) |
1823 | length = rest; | |
1824 | else | |
1825 | length = PAGE_SIZE - offset; | |
1826 | ||
1e1d196b KH |
1827 | db->second_req_count = cpu_to_le16(length); |
1828 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
1829 | page_bus = page_private(buffer->pages[page]); |
1830 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
1831 | ||
cb2d2cdb | 1832 | if (p->interrupt && length == rest) |
a77754a7 | 1833 | db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdb | 1834 | |
295e3feb KH |
1835 | context_append(&ctx->context, d, z, header_z); |
1836 | offset = (offset + length) & ~PAGE_MASK; | |
1837 | rest -= length; | |
1838 | page++; | |
1839 | } | |
1840 | ||
d2746dc1 KH |
1841 | return 0; |
1842 | } | |
21efb3cf | 1843 | |
a186b4a6 JW |
1844 | static int |
1845 | ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, | |
1846 | struct fw_iso_packet *packet, | |
1847 | struct fw_iso_buffer *buffer, | |
1848 | unsigned long payload) | |
1849 | { | |
1850 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1851 | struct descriptor *d = NULL, *pd = NULL; | |
1852 | struct fw_iso_packet *p; | |
1853 | dma_addr_t d_bus, page_bus; | |
1854 | u32 z, header_z, rest; | |
1855 | int i, page, offset, packet_count, header_size; | |
1856 | ||
1857 | if (packet->skip) { | |
1858 | d = context_get_descriptors(&ctx->context, 1, &d_bus); | |
1859 | if (d == NULL) | |
1860 | return -ENOMEM; | |
1861 | ||
1862 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | | |
1863 | DESCRIPTOR_INPUT_LAST | | |
1864 | DESCRIPTOR_BRANCH_ALWAYS | | |
1865 | DESCRIPTOR_WAIT); | |
1866 | context_append(&ctx->context, d, 1, 0); | |
1867 | } | |
1868 | ||
1869 | /* one descriptor for header, one for payload */ | |
1870 | /* FIXME: handle cases where we need multiple desc. for payload */ | |
1871 | z = 2; | |
1872 | p = packet; | |
1873 | ||
1874 | /* | |
1875 | * The OHCI controller puts the status word in the | |
1876 | * buffer too, so we need 4 extra bytes per packet. | |
1877 | */ | |
1878 | packet_count = p->header_length / ctx->base.header_size; | |
1879 | header_size = packet_count * (ctx->base.header_size + 4); | |
1880 | ||
1881 | /* Get header size in number of descriptors. */ | |
1882 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
1883 | page = payload >> PAGE_SHIFT; | |
1884 | offset = payload & ~PAGE_MASK; | |
1885 | rest = p->payload_length; | |
1886 | ||
1887 | for (i = 0; i < packet_count; i++) { | |
1888 | /* d points to the header descriptor */ | |
1889 | d = context_get_descriptors(&ctx->context, | |
1890 | z + header_z, &d_bus); | |
1891 | if (d == NULL) | |
1892 | return -ENOMEM; | |
1893 | ||
1894 | d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE); | |
1895 | d->req_count = cpu_to_le16(header_size); | |
1896 | d->res_count = d->req_count; | |
1897 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); | |
1898 | ||
1899 | /* pd points to the payload descriptor */ | |
1900 | pd = d + 1; | |
1901 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | | |
1902 | DESCRIPTOR_INPUT_LAST | | |
1903 | DESCRIPTOR_BRANCH_ALWAYS); | |
1904 | if (p->interrupt) | |
1905 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); | |
1906 | ||
1907 | pd->req_count = cpu_to_le16(rest); | |
1908 | pd->res_count = pd->req_count; | |
1909 | ||
1910 | page_bus = page_private(buffer->pages[page]); | |
1911 | pd->data_address = cpu_to_le32(page_bus + offset); | |
1912 | ||
1913 | context_append(&ctx->context, d, z, header_z); | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
295e3feb KH |
1919 | static int |
1920 | ohci_queue_iso(struct fw_iso_context *base, | |
1921 | struct fw_iso_packet *packet, | |
1922 | struct fw_iso_buffer *buffer, | |
1923 | unsigned long payload) | |
1924 | { | |
e364cf4e KH |
1925 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1926 | ||
295e3feb KH |
1927 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
1928 | return ohci_queue_iso_transmit(base, packet, buffer, payload); | |
e364cf4e | 1929 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
d2746dc1 KH |
1930 | return ohci_queue_iso_receive_dualbuffer(base, packet, |
1931 | buffer, payload); | |
e364cf4e | 1932 | else |
a186b4a6 JW |
1933 | return ohci_queue_iso_receive_packet_per_buffer(base, packet, |
1934 | buffer, | |
1935 | payload); | |
295e3feb KH |
1936 | } |
1937 | ||
21ebcd12 | 1938 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1939 | .name = ohci_driver_name, |
1940 | .enable = ohci_enable, | |
1941 | .update_phy_reg = ohci_update_phy_reg, | |
1942 | .set_config_rom = ohci_set_config_rom, | |
1943 | .send_request = ohci_send_request, | |
1944 | .send_response = ohci_send_response, | |
730c32f5 | 1945 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 1946 | .enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d | 1947 | .get_bus_time = ohci_get_bus_time, |
ed568912 KH |
1948 | |
1949 | .allocate_iso_context = ohci_allocate_iso_context, | |
1950 | .free_iso_context = ohci_free_iso_context, | |
1951 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 1952 | .start_iso = ohci_start_iso, |
b8295668 | 1953 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
1954 | }; |
1955 | ||
ed568912 KH |
1956 | static int __devinit |
1957 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1958 | { | |
1959 | struct fw_ohci *ohci; | |
e364cf4e | 1960 | u32 bus_options, max_receive, link_speed; |
ed568912 | 1961 | u64 guid; |
d79406dd | 1962 | int err; |
ed568912 KH |
1963 | size_t size; |
1964 | ||
2d826cc5 | 1965 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 KH |
1966 | if (ohci == NULL) { |
1967 | fw_error("Could not malloc fw_ohci data.\n"); | |
1968 | return -ENOMEM; | |
1969 | } | |
1970 | ||
1971 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1972 | ||
d79406dd KH |
1973 | err = pci_enable_device(dev); |
1974 | if (err) { | |
ed568912 | 1975 | fw_error("Failed to enable OHCI hardware.\n"); |
d79406dd | 1976 | goto fail_put_card; |
ed568912 KH |
1977 | } |
1978 | ||
1979 | pci_set_master(dev); | |
1980 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1981 | pci_set_drvdata(dev, ohci); | |
1982 | ||
1983 | spin_lock_init(&ohci->lock); | |
1984 | ||
1985 | tasklet_init(&ohci->bus_reset_tasklet, | |
1986 | bus_reset_tasklet, (unsigned long)ohci); | |
1987 | ||
d79406dd KH |
1988 | err = pci_request_region(dev, 0, ohci_driver_name); |
1989 | if (err) { | |
ed568912 | 1990 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 1991 | goto fail_disable; |
ed568912 KH |
1992 | } |
1993 | ||
1994 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1995 | if (ohci->registers == NULL) { | |
1996 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
1997 | err = -ENXIO; |
1998 | goto fail_iomem; | |
ed568912 KH |
1999 | } |
2000 | ||
ed568912 KH |
2001 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2002 | OHCI1394_AsReqRcvContextControlSet); | |
2003 | ||
2004 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2005 | OHCI1394_AsRspRcvContextControlSet); | |
2006 | ||
f319b6a0 KH |
2007 | context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE, |
2008 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); | |
ed568912 | 2009 | |
f319b6a0 KH |
2010 | context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE, |
2011 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); | |
ed568912 | 2012 | |
ed568912 KH |
2013 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
2014 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
2015 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
2016 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
2017 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
2018 | ||
2019 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
2020 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
2021 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
2022 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
2023 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
2024 | ||
2025 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
2026 | fw_error("Out of memory for it/ir contexts.\n"); | |
d79406dd KH |
2027 | err = -ENOMEM; |
2028 | goto fail_registers; | |
ed568912 KH |
2029 | } |
2030 | ||
2031 | /* self-id dma buffer allocation */ | |
2032 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2033 | SELF_ID_BUF_SIZE, | |
2034 | &ohci->self_id_bus, | |
2035 | GFP_KERNEL); | |
2036 | if (ohci->self_id_cpu == NULL) { | |
2037 | fw_error("Out of memory for self ID buffer.\n"); | |
d79406dd KH |
2038 | err = -ENOMEM; |
2039 | goto fail_registers; | |
ed568912 KH |
2040 | } |
2041 | ||
ed568912 KH |
2042 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2043 | max_receive = (bus_options >> 12) & 0xf; | |
2044 | link_speed = bus_options & 0x7; | |
2045 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2046 | reg_read(ohci, OHCI1394_GUIDLo); | |
2047 | ||
d79406dd KH |
2048 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
2049 | if (err < 0) | |
2050 | goto fail_self_id; | |
ed568912 | 2051 | |
e364cf4e | 2052 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 2053 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 2054 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 | 2055 | return 0; |
d79406dd KH |
2056 | |
2057 | fail_self_id: | |
2058 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2059 | ohci->self_id_cpu, ohci->self_id_bus); | |
2060 | fail_registers: | |
2061 | kfree(ohci->it_context_list); | |
2062 | kfree(ohci->ir_context_list); | |
2063 | pci_iounmap(dev, ohci->registers); | |
2064 | fail_iomem: | |
2065 | pci_release_region(dev, 0); | |
2066 | fail_disable: | |
2067 | pci_disable_device(dev); | |
2068 | fail_put_card: | |
2069 | fw_card_put(&ohci->card); | |
2070 | ||
2071 | return err; | |
ed568912 KH |
2072 | } |
2073 | ||
2074 | static void pci_remove(struct pci_dev *dev) | |
2075 | { | |
2076 | struct fw_ohci *ohci; | |
2077 | ||
2078 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2079 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2080 | flush_writes(ohci); | |
ed568912 KH |
2081 | fw_core_remove_card(&ohci->card); |
2082 | ||
c781c06d KH |
2083 | /* |
2084 | * FIXME: Fail all pending packets here, now that the upper | |
2085 | * layers can't queue any more. | |
2086 | */ | |
ed568912 KH |
2087 | |
2088 | software_reset(ohci); | |
2089 | free_irq(dev->irq, ohci); | |
d79406dd KH |
2090 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2091 | ohci->self_id_cpu, ohci->self_id_bus); | |
2092 | kfree(ohci->it_context_list); | |
2093 | kfree(ohci->ir_context_list); | |
2094 | pci_iounmap(dev, ohci->registers); | |
2095 | pci_release_region(dev, 0); | |
2096 | pci_disable_device(dev); | |
2097 | fw_card_put(&ohci->card); | |
ed568912 KH |
2098 | |
2099 | fw_notify("Removed fw-ohci device.\n"); | |
2100 | } | |
2101 | ||
2aef469a KH |
2102 | #ifdef CONFIG_PM |
2103 | static int pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
2104 | { | |
2105 | struct fw_ohci *ohci = pci_get_drvdata(pdev); | |
2106 | int err; | |
2107 | ||
2108 | software_reset(ohci); | |
2109 | free_irq(pdev->irq, ohci); | |
2110 | err = pci_save_state(pdev); | |
2111 | if (err) { | |
8a8cea27 | 2112 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2113 | return err; |
2114 | } | |
2115 | err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
55111428 SR |
2116 | if (err) |
2117 | fw_error("pci_set_power_state failed with %d\n", err); | |
2aef469a KH |
2118 | |
2119 | return 0; | |
2120 | } | |
2121 | ||
2122 | static int pci_resume(struct pci_dev *pdev) | |
2123 | { | |
2124 | struct fw_ohci *ohci = pci_get_drvdata(pdev); | |
2125 | int err; | |
2126 | ||
2127 | pci_set_power_state(pdev, PCI_D0); | |
2128 | pci_restore_state(pdev); | |
2129 | err = pci_enable_device(pdev); | |
2130 | if (err) { | |
8a8cea27 | 2131 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2132 | return err; |
2133 | } | |
2134 | ||
0bd243c4 | 2135 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2136 | } |
2137 | #endif | |
2138 | ||
ed568912 KH |
2139 | static struct pci_device_id pci_table[] = { |
2140 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
2141 | { } | |
2142 | }; | |
2143 | ||
2144 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2145 | ||
2146 | static struct pci_driver fw_ohci_pci_driver = { | |
2147 | .name = ohci_driver_name, | |
2148 | .id_table = pci_table, | |
2149 | .probe = pci_probe, | |
2150 | .remove = pci_remove, | |
2aef469a KH |
2151 | #ifdef CONFIG_PM |
2152 | .resume = pci_resume, | |
2153 | .suspend = pci_suspend, | |
2154 | #endif | |
ed568912 KH |
2155 | }; |
2156 | ||
2157 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2158 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2159 | MODULE_LICENSE("GPL"); | |
2160 | ||
1e4c7b0d OH |
2161 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2162 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2163 | MODULE_ALIAS("ohci1394"); | |
2164 | #endif | |
2165 | ||
ed568912 KH |
2166 | static int __init fw_ohci_init(void) |
2167 | { | |
2168 | return pci_register_driver(&fw_ohci_pci_driver); | |
2169 | } | |
2170 | ||
2171 | static void __exit fw_ohci_cleanup(void) | |
2172 | { | |
2173 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2174 | } | |
2175 | ||
2176 | module_init(fw_ohci_init); | |
2177 | module_exit(fw_ohci_cleanup); |