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ed568912 KH |
1 | /* -*- c-basic-offset: 8 -*- |
2 | * | |
3 | * fw-ohci.c - Driver for OHCI 1394 boards | |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd AM |
28 | #include <linux/dma-mapping.h> |
29 | ||
ed568912 KH |
30 | #include <asm/uaccess.h> |
31 | #include <asm/semaphore.h> | |
32 | ||
33 | #include "fw-transaction.h" | |
34 | #include "fw-ohci.h" | |
35 | ||
36 | #define descriptor_output_more 0 | |
37 | #define descriptor_output_last (1 << 12) | |
38 | #define descriptor_input_more (2 << 12) | |
39 | #define descriptor_input_last (3 << 12) | |
40 | #define descriptor_status (1 << 11) | |
41 | #define descriptor_key_immediate (2 << 8) | |
42 | #define descriptor_ping (1 << 7) | |
43 | #define descriptor_yy (1 << 6) | |
44 | #define descriptor_no_irq (0 << 4) | |
45 | #define descriptor_irq_error (1 << 4) | |
46 | #define descriptor_irq_always (3 << 4) | |
47 | #define descriptor_branch_always (3 << 2) | |
295e3feb | 48 | #define descriptor_wait (3 << 0) |
ed568912 KH |
49 | |
50 | struct descriptor { | |
51 | __le16 req_count; | |
52 | __le16 control; | |
53 | __le32 data_address; | |
54 | __le32 branch_address; | |
55 | __le16 res_count; | |
56 | __le16 transfer_status; | |
57 | } __attribute__((aligned(16))); | |
58 | ||
295e3feb KH |
59 | struct db_descriptor { |
60 | __le16 first_size; | |
61 | __le16 control; | |
62 | __le16 second_req_count; | |
63 | __le16 first_req_count; | |
64 | __le32 branch_address; | |
65 | __le16 second_res_count; | |
66 | __le16 first_res_count; | |
67 | __le32 reserved0; | |
68 | __le32 first_buffer; | |
69 | __le32 second_buffer; | |
70 | __le32 reserved1; | |
71 | } __attribute__((aligned(16))); | |
72 | ||
72e318e0 KH |
73 | #define control_set(regs) (regs) |
74 | #define control_clear(regs) ((regs) + 4) | |
75 | #define command_ptr(regs) ((regs) + 12) | |
76 | #define context_match(regs) ((regs) + 16) | |
77 | ||
32b46093 | 78 | struct ar_buffer { |
ed568912 | 79 | struct descriptor descriptor; |
32b46093 KH |
80 | struct ar_buffer *next; |
81 | __le32 data[0]; | |
82 | }; | |
ed568912 | 83 | |
32b46093 KH |
84 | struct ar_context { |
85 | struct fw_ohci *ohci; | |
86 | struct ar_buffer *current_buffer; | |
87 | struct ar_buffer *last_buffer; | |
88 | void *pointer; | |
72e318e0 | 89 | u32 regs; |
ed568912 KH |
90 | struct tasklet_struct tasklet; |
91 | }; | |
92 | ||
30200739 KH |
93 | struct context; |
94 | ||
95 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
96 | struct descriptor *d, | |
97 | struct descriptor *last); | |
98 | struct context { | |
99 | struct fw_ohci *ohci; | |
100 | u32 regs; | |
101 | ||
102 | struct descriptor *buffer; | |
103 | dma_addr_t buffer_bus; | |
104 | size_t buffer_size; | |
105 | struct descriptor *head_descriptor; | |
106 | struct descriptor *tail_descriptor; | |
107 | struct descriptor *tail_descriptor_last; | |
108 | struct descriptor *prev_descriptor; | |
109 | ||
110 | descriptor_callback_t callback; | |
111 | ||
112 | struct tasklet_struct tasklet; | |
113 | }; | |
114 | ||
115 | ||
116 | ||
ed568912 KH |
117 | struct at_context { |
118 | struct fw_ohci *ohci; | |
119 | dma_addr_t descriptor_bus; | |
120 | dma_addr_t buffer_bus; | |
730c32f5 | 121 | struct fw_packet *current_packet; |
ed568912 KH |
122 | |
123 | struct list_head list; | |
124 | ||
125 | struct { | |
126 | struct descriptor more; | |
127 | __le32 header[4]; | |
128 | struct descriptor last; | |
129 | } d; | |
130 | ||
72e318e0 | 131 | u32 regs; |
ed568912 KH |
132 | |
133 | struct tasklet_struct tasklet; | |
134 | }; | |
135 | ||
136 | #define it_header_sy(v) ((v) << 0) | |
137 | #define it_header_tcode(v) ((v) << 4) | |
138 | #define it_header_channel(v) ((v) << 8) | |
139 | #define it_header_tag(v) ((v) << 14) | |
140 | #define it_header_speed(v) ((v) << 16) | |
141 | #define it_header_data_length(v) ((v) << 16) | |
142 | ||
143 | struct iso_context { | |
144 | struct fw_iso_context base; | |
30200739 | 145 | struct context context; |
ed568912 KH |
146 | }; |
147 | ||
148 | #define CONFIG_ROM_SIZE 1024 | |
149 | ||
150 | struct fw_ohci { | |
151 | struct fw_card card; | |
152 | ||
153 | __iomem char *registers; | |
154 | dma_addr_t self_id_bus; | |
155 | __le32 *self_id_cpu; | |
156 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 157 | int node_id; |
ed568912 KH |
158 | int generation; |
159 | int request_generation; | |
160 | ||
161 | /* Spinlock for accessing fw_ohci data. Never call out of | |
162 | * this driver with this lock held. */ | |
163 | spinlock_t lock; | |
164 | u32 self_id_buffer[512]; | |
165 | ||
166 | /* Config rom buffers */ | |
167 | __be32 *config_rom; | |
168 | dma_addr_t config_rom_bus; | |
169 | __be32 *next_config_rom; | |
170 | dma_addr_t next_config_rom_bus; | |
171 | u32 next_header; | |
172 | ||
173 | struct ar_context ar_request_ctx; | |
174 | struct ar_context ar_response_ctx; | |
175 | struct at_context at_request_ctx; | |
176 | struct at_context at_response_ctx; | |
177 | ||
178 | u32 it_context_mask; | |
179 | struct iso_context *it_context_list; | |
180 | u32 ir_context_mask; | |
181 | struct iso_context *ir_context_list; | |
182 | }; | |
183 | ||
95688e97 | 184 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
185 | { |
186 | return container_of(card, struct fw_ohci, card); | |
187 | } | |
188 | ||
295e3feb KH |
189 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
190 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
191 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
192 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
193 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
194 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
195 | |
196 | #define CONTEXT_RUN 0x8000 | |
197 | #define CONTEXT_WAKE 0x1000 | |
198 | #define CONTEXT_DEAD 0x0800 | |
199 | #define CONTEXT_ACTIVE 0x0400 | |
200 | ||
201 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
202 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
203 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
204 | ||
205 | #define FW_OHCI_MAJOR 240 | |
206 | #define OHCI1394_REGISTER_SIZE 0x800 | |
207 | #define OHCI_LOOP_COUNT 500 | |
208 | #define OHCI1394_PCI_HCI_Control 0x40 | |
209 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 210 | #define OHCI_TCODE_PHY_PACKET 0x0e |
0edeefd9 | 211 | |
ed568912 KH |
212 | static char ohci_driver_name[] = KBUILD_MODNAME; |
213 | ||
95688e97 | 214 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
215 | { |
216 | writel(data, ohci->registers + offset); | |
217 | } | |
218 | ||
95688e97 | 219 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
220 | { |
221 | return readl(ohci->registers + offset); | |
222 | } | |
223 | ||
95688e97 | 224 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
225 | { |
226 | /* Do a dummy read to flush writes. */ | |
227 | reg_read(ohci, OHCI1394_Version); | |
228 | } | |
229 | ||
230 | static int | |
231 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
232 | int clear_bits, int set_bits) | |
233 | { | |
234 | struct fw_ohci *ohci = fw_ohci(card); | |
235 | u32 val, old; | |
236 | ||
237 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
238 | msleep(2); | |
239 | val = reg_read(ohci, OHCI1394_PhyControl); | |
240 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
241 | fw_error("failed to set phy reg bits.\n"); | |
242 | return -EBUSY; | |
243 | } | |
244 | ||
245 | old = OHCI1394_PhyControl_ReadData(val); | |
246 | old = (old & ~clear_bits) | set_bits; | |
247 | reg_write(ohci, OHCI1394_PhyControl, | |
248 | OHCI1394_PhyControl_Write(addr, old)); | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
32b46093 | 253 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 254 | { |
32b46093 KH |
255 | struct device *dev = ctx->ohci->card.device; |
256 | struct ar_buffer *ab; | |
257 | dma_addr_t ab_bus; | |
258 | size_t offset; | |
259 | ||
260 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
261 | if (ab == NULL) | |
262 | return -ENOMEM; | |
263 | ||
264 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
265 | if (dma_mapping_error(ab_bus)) { | |
266 | free_page((unsigned long) ab); | |
267 | return -ENOMEM; | |
268 | } | |
269 | ||
270 | memset(&ab->descriptor, 0, sizeof ab->descriptor); | |
271 | ab->descriptor.control = cpu_to_le16(descriptor_input_more | | |
272 | descriptor_status | | |
273 | descriptor_branch_always); | |
274 | offset = offsetof(struct ar_buffer, data); | |
275 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
276 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
277 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
278 | ab->descriptor.branch_address = 0; | |
279 | ||
280 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
281 | ||
282 | ctx->last_buffer->descriptor.branch_address = ab_bus | 1; | |
283 | ctx->last_buffer->next = ab; | |
284 | ctx->last_buffer = ab; | |
285 | ||
72e318e0 | 286 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE); |
ed568912 | 287 | flush_writes(ctx->ohci); |
32b46093 KH |
288 | |
289 | return 0; | |
ed568912 KH |
290 | } |
291 | ||
32b46093 | 292 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 293 | { |
ed568912 | 294 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
295 | struct fw_packet p; |
296 | u32 status, length, tcode; | |
2639a6fb | 297 | |
32b46093 KH |
298 | p.header[0] = le32_to_cpu(buffer[0]); |
299 | p.header[1] = le32_to_cpu(buffer[1]); | |
300 | p.header[2] = le32_to_cpu(buffer[2]); | |
2639a6fb KH |
301 | |
302 | tcode = (p.header[0] >> 4) & 0x0f; | |
303 | switch (tcode) { | |
304 | case TCODE_WRITE_QUADLET_REQUEST: | |
305 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 306 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 307 | p.header_length = 16; |
32b46093 | 308 | p.payload_length = 0; |
2639a6fb KH |
309 | break; |
310 | ||
2639a6fb | 311 | case TCODE_READ_BLOCK_REQUEST : |
32b46093 KH |
312 | p.header[3] = le32_to_cpu(buffer[3]); |
313 | p.header_length = 16; | |
314 | p.payload_length = 0; | |
315 | break; | |
316 | ||
317 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
318 | case TCODE_READ_BLOCK_RESPONSE: |
319 | case TCODE_LOCK_REQUEST: | |
320 | case TCODE_LOCK_RESPONSE: | |
32b46093 | 321 | p.header[3] = le32_to_cpu(buffer[3]); |
2639a6fb | 322 | p.header_length = 16; |
32b46093 | 323 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
324 | break; |
325 | ||
326 | case TCODE_WRITE_RESPONSE: | |
327 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 328 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 329 | p.header_length = 12; |
32b46093 | 330 | p.payload_length = 0; |
2639a6fb KH |
331 | break; |
332 | } | |
ed568912 | 333 | |
32b46093 KH |
334 | p.payload = (void *) buffer + p.header_length; |
335 | ||
336 | /* FIXME: What to do about evt_* errors? */ | |
337 | length = (p.header_length + p.payload_length + 3) / 4; | |
338 | status = le32_to_cpu(buffer[length]); | |
339 | ||
340 | p.ack = ((status >> 16) & 0x1f) - 16; | |
341 | p.speed = (status >> 21) & 0x7; | |
342 | p.timestamp = status & 0xffff; | |
343 | p.generation = ohci->request_generation; | |
ed568912 KH |
344 | |
345 | /* The OHCI bus reset handler synthesizes a phy packet with | |
346 | * the new generation number when a bus reset happens (see | |
347 | * section 8.4.2.3). This helps us determine when a request | |
348 | * was received and make sure we send the response in the same | |
349 | * generation. We only need this for requests; for responses | |
350 | * we use the unique tlabel for finding the matching | |
351 | * request. */ | |
352 | ||
2639a6fb | 353 | if (p.ack + 16 == 0x09) |
32b46093 | 354 | ohci->request_generation = (buffer[2] >> 16) & 0xff; |
ed568912 | 355 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 356 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 357 | else |
2639a6fb | 358 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 359 | |
32b46093 KH |
360 | return buffer + length + 1; |
361 | } | |
ed568912 | 362 | |
32b46093 KH |
363 | static void ar_context_tasklet(unsigned long data) |
364 | { | |
365 | struct ar_context *ctx = (struct ar_context *)data; | |
366 | struct fw_ohci *ohci = ctx->ohci; | |
367 | struct ar_buffer *ab; | |
368 | struct descriptor *d; | |
369 | void *buffer, *end; | |
370 | ||
371 | ab = ctx->current_buffer; | |
372 | d = &ab->descriptor; | |
373 | ||
374 | if (d->res_count == 0) { | |
375 | size_t size, rest, offset; | |
376 | ||
377 | /* This descriptor is finished and we may have a | |
378 | * packet split across this and the next buffer. We | |
379 | * reuse the page for reassembling the split packet. */ | |
380 | ||
381 | offset = offsetof(struct ar_buffer, data); | |
382 | dma_unmap_single(ohci->card.device, | |
383 | ab->descriptor.data_address - offset, | |
384 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
385 | ||
386 | buffer = ab; | |
387 | ab = ab->next; | |
388 | d = &ab->descriptor; | |
389 | size = buffer + PAGE_SIZE - ctx->pointer; | |
390 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
391 | memmove(buffer, ctx->pointer, size); | |
392 | memcpy(buffer + size, ab->data, rest); | |
393 | ctx->current_buffer = ab; | |
394 | ctx->pointer = (void *) ab->data + rest; | |
395 | end = buffer + size + rest; | |
396 | ||
397 | while (buffer < end) | |
398 | buffer = handle_ar_packet(ctx, buffer); | |
399 | ||
400 | free_page((unsigned long)buffer); | |
401 | ar_context_add_page(ctx); | |
402 | } else { | |
403 | buffer = ctx->pointer; | |
404 | ctx->pointer = end = | |
405 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
406 | ||
407 | while (buffer < end) | |
408 | buffer = handle_ar_packet(ctx, buffer); | |
409 | } | |
ed568912 KH |
410 | } |
411 | ||
412 | static int | |
72e318e0 | 413 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 414 | { |
32b46093 | 415 | struct ar_buffer ab; |
ed568912 | 416 | |
72e318e0 KH |
417 | ctx->regs = regs; |
418 | ctx->ohci = ohci; | |
419 | ctx->last_buffer = &ab; | |
ed568912 KH |
420 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
421 | ||
32b46093 KH |
422 | ar_context_add_page(ctx); |
423 | ar_context_add_page(ctx); | |
424 | ctx->current_buffer = ab.next; | |
425 | ctx->pointer = ctx->current_buffer->data; | |
426 | ||
72e318e0 KH |
427 | reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address); |
428 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN); | |
32b46093 | 429 | flush_writes(ctx->ohci); |
ed568912 KH |
430 | |
431 | return 0; | |
432 | } | |
30200739 KH |
433 | |
434 | static void context_tasklet(unsigned long data) | |
435 | { | |
436 | struct context *ctx = (struct context *) data; | |
437 | struct fw_ohci *ohci = ctx->ohci; | |
438 | struct descriptor *d, *last; | |
439 | u32 address; | |
440 | int z; | |
441 | ||
442 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
443 | ctx->buffer_size, DMA_TO_DEVICE); | |
444 | ||
445 | d = ctx->tail_descriptor; | |
446 | last = ctx->tail_descriptor_last; | |
447 | ||
448 | while (last->branch_address != 0) { | |
449 | address = le32_to_cpu(last->branch_address); | |
450 | z = address & 0xf; | |
451 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d; | |
452 | last = (z == 2) ? d : d + z - 1; | |
453 | ||
454 | if (!ctx->callback(ctx, d, last)) | |
455 | break; | |
456 | ||
457 | ctx->tail_descriptor = d; | |
458 | ctx->tail_descriptor_last = last; | |
459 | } | |
460 | } | |
461 | ||
462 | static int | |
463 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
464 | size_t buffer_size, u32 regs, | |
465 | descriptor_callback_t callback) | |
466 | { | |
467 | ctx->ohci = ohci; | |
468 | ctx->regs = regs; | |
469 | ctx->buffer_size = buffer_size; | |
470 | ctx->buffer = kmalloc(buffer_size, GFP_KERNEL); | |
471 | if (ctx->buffer == NULL) | |
472 | return -ENOMEM; | |
473 | ||
474 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); | |
475 | ctx->callback = callback; | |
476 | ||
477 | ctx->buffer_bus = | |
478 | dma_map_single(ohci->card.device, ctx->buffer, | |
479 | buffer_size, DMA_TO_DEVICE); | |
480 | if (dma_mapping_error(ctx->buffer_bus)) { | |
481 | kfree(ctx->buffer); | |
482 | return -ENOMEM; | |
483 | } | |
484 | ||
485 | ctx->head_descriptor = ctx->buffer; | |
486 | ctx->prev_descriptor = ctx->buffer; | |
487 | ctx->tail_descriptor = ctx->buffer; | |
488 | ctx->tail_descriptor_last = ctx->buffer; | |
489 | ||
490 | /* We put a dummy descriptor in the buffer that has a NULL | |
491 | * branch address and looks like it's been sent. That way we | |
492 | * have a descriptor to append DMA programs to. Also, the | |
493 | * ring buffer invariant is that it always has at least one | |
494 | * element so that head == tail means buffer full. */ | |
495 | ||
496 | memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); | |
497 | ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); | |
498 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); | |
499 | ctx->head_descriptor++; | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | static void | |
505 | context_release(struct context *ctx) | |
506 | { | |
507 | struct fw_card *card = &ctx->ohci->card; | |
508 | ||
509 | dma_unmap_single(card->device, ctx->buffer_bus, | |
510 | ctx->buffer_size, DMA_TO_DEVICE); | |
511 | kfree(ctx->buffer); | |
512 | } | |
513 | ||
514 | static struct descriptor * | |
515 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
516 | { | |
517 | struct descriptor *d, *tail, *end; | |
518 | ||
519 | d = ctx->head_descriptor; | |
520 | tail = ctx->tail_descriptor; | |
521 | end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor); | |
522 | ||
523 | if (d + z <= tail) { | |
524 | goto has_space; | |
525 | } else if (d > tail && d + z <= end) { | |
526 | goto has_space; | |
527 | } else if (d > tail && ctx->buffer + z <= tail) { | |
528 | d = ctx->buffer; | |
529 | goto has_space; | |
530 | } | |
531 | ||
532 | return NULL; | |
533 | ||
534 | has_space: | |
535 | memset(d, 0, z * sizeof *d); | |
536 | *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
537 | ||
538 | return d; | |
539 | } | |
540 | ||
295e3feb | 541 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
542 | { |
543 | struct fw_ohci *ohci = ctx->ohci; | |
544 | ||
545 | reg_write(ohci, command_ptr(ctx->regs), | |
546 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); | |
547 | reg_write(ohci, control_clear(ctx->regs), ~0); | |
295e3feb | 548 | reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra); |
30200739 KH |
549 | flush_writes(ohci); |
550 | } | |
551 | ||
552 | static void context_append(struct context *ctx, | |
553 | struct descriptor *d, int z, int extra) | |
554 | { | |
555 | dma_addr_t d_bus; | |
556 | ||
557 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
558 | ||
559 | ctx->head_descriptor = d + z + extra; | |
560 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
561 | ctx->prev_descriptor = z == 2 ? d : d + z - 1; | |
562 | ||
563 | dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus, | |
564 | ctx->buffer_size, DMA_TO_DEVICE); | |
565 | ||
566 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE); | |
567 | flush_writes(ctx->ohci); | |
568 | } | |
569 | ||
570 | static void context_stop(struct context *ctx) | |
571 | { | |
572 | u32 reg; | |
573 | ||
574 | reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN); | |
575 | ||
576 | reg = reg_read(ctx->ohci, control_set(ctx->regs)); | |
577 | if (reg & CONTEXT_ACTIVE) | |
578 | fw_notify("Tried to stop context, but it is still active " | |
579 | "(0x%08x).\n", reg); | |
580 | } | |
ed568912 KH |
581 | |
582 | static void | |
583 | do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list) | |
584 | { | |
585 | struct fw_packet *p, *next; | |
586 | ||
587 | list_for_each_entry_safe(p, next, list, link) | |
2639a6fb | 588 | p->callback(p, &ohci->card, p->ack); |
ed568912 KH |
589 | } |
590 | ||
591 | static void | |
592 | complete_transmission(struct fw_packet *packet, | |
2639a6fb | 593 | int ack, struct list_head *list) |
ed568912 KH |
594 | { |
595 | list_move_tail(&packet->link, list); | |
2639a6fb | 596 | packet->ack = ack; |
ed568912 KH |
597 | } |
598 | ||
599 | /* This function prepares the first packet in the context queue for | |
600 | * transmission. Must always be called with the ochi->lock held to | |
601 | * ensure proper generation handling and locking around packet queue | |
602 | * manipulation. */ | |
603 | static void | |
604 | at_context_setup_packet(struct at_context *ctx, struct list_head *list) | |
605 | { | |
606 | struct fw_packet *packet; | |
607 | struct fw_ohci *ohci = ctx->ohci; | |
608 | int z, tcode; | |
609 | ||
610 | packet = fw_packet(ctx->list.next); | |
611 | ||
612 | memset(&ctx->d, 0, sizeof ctx->d); | |
613 | if (packet->payload_length > 0) { | |
614 | packet->payload_bus = dma_map_single(ohci->card.device, | |
615 | packet->payload, | |
616 | packet->payload_length, | |
617 | DMA_TO_DEVICE); | |
82eff9db | 618 | if (dma_mapping_error(packet->payload_bus)) { |
e5f49c3b | 619 | complete_transmission(packet, RCODE_SEND_ERROR, list); |
ed568912 KH |
620 | return; |
621 | } | |
622 | ||
623 | ctx->d.more.control = | |
624 | cpu_to_le16(descriptor_output_more | | |
625 | descriptor_key_immediate); | |
626 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
627 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
628 | ctx->d.last.control = | |
629 | cpu_to_le16(descriptor_output_last | | |
630 | descriptor_irq_always | | |
631 | descriptor_branch_always); | |
632 | ctx->d.last.req_count = cpu_to_le16(packet->payload_length); | |
633 | ctx->d.last.data_address = cpu_to_le32(packet->payload_bus); | |
634 | z = 3; | |
635 | } else { | |
636 | ctx->d.more.control = | |
637 | cpu_to_le16(descriptor_output_last | | |
638 | descriptor_key_immediate | | |
639 | descriptor_irq_always | | |
640 | descriptor_branch_always); | |
641 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
642 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
643 | z = 2; | |
644 | } | |
645 | ||
646 | /* The DMA format for asyncronous link packets is different | |
647 | * from the IEEE1394 layout, so shift the fields around | |
648 | * accordingly. If header_length is 8, it's a PHY packet, to | |
649 | * which we need to prepend an extra quadlet. */ | |
650 | if (packet->header_length > 8) { | |
651 | ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
652 | (packet->speed << 16)); | |
653 | ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
654 | (packet->header[0] & 0xffff0000)); | |
655 | ctx->d.header[2] = cpu_to_le32(packet->header[2]); | |
656 | ||
657 | tcode = (packet->header[0] >> 4) & 0x0f; | |
658 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
659 | ctx->d.header[3] = cpu_to_le32(packet->header[3]); | |
660 | else | |
661 | ctx->d.header[3] = packet->header[3]; | |
662 | } else { | |
663 | ctx->d.header[0] = | |
664 | cpu_to_le32((OHCI1394_phy_tcode << 4) | | |
665 | (packet->speed << 16)); | |
666 | ctx->d.header[1] = cpu_to_le32(packet->header[0]); | |
667 | ctx->d.header[2] = cpu_to_le32(packet->header[1]); | |
668 | ctx->d.more.req_count = cpu_to_le16(12); | |
669 | } | |
670 | ||
671 | /* FIXME: Document how the locking works. */ | |
672 | if (ohci->generation == packet->generation) { | |
72e318e0 | 673 | reg_write(ctx->ohci, command_ptr(ctx->regs), |
ed568912 | 674 | ctx->descriptor_bus | z); |
72e318e0 | 675 | reg_write(ctx->ohci, control_set(ctx->regs), |
ed568912 | 676 | CONTEXT_RUN | CONTEXT_WAKE); |
730c32f5 | 677 | ctx->current_packet = packet; |
ed568912 KH |
678 | } else { |
679 | /* We dont return error codes from this function; all | |
680 | * transmission errors are reported through the | |
681 | * callback. */ | |
e5f49c3b | 682 | complete_transmission(packet, RCODE_GENERATION, list); |
ed568912 KH |
683 | } |
684 | } | |
685 | ||
686 | static void at_context_stop(struct at_context *ctx) | |
687 | { | |
688 | u32 reg; | |
689 | ||
72e318e0 | 690 | reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN); |
ed568912 | 691 | |
72e318e0 | 692 | reg = reg_read(ctx->ohci, control_set(ctx->regs)); |
ed568912 KH |
693 | if (reg & CONTEXT_ACTIVE) |
694 | fw_notify("Tried to stop context, but it is still active " | |
695 | "(0x%08x).\n", reg); | |
696 | } | |
697 | ||
698 | static void at_context_tasklet(unsigned long data) | |
699 | { | |
700 | struct at_context *ctx = (struct at_context *)data; | |
701 | struct fw_ohci *ohci = ctx->ohci; | |
702 | struct fw_packet *packet; | |
703 | LIST_HEAD(list); | |
704 | unsigned long flags; | |
705 | int evt; | |
706 | ||
707 | spin_lock_irqsave(&ohci->lock, flags); | |
708 | ||
709 | packet = fw_packet(ctx->list.next); | |
710 | ||
711 | at_context_stop(ctx); | |
712 | ||
730c32f5 KH |
713 | /* If the head of the list isn't the packet that just got |
714 | * transmitted, the packet got cancelled before we finished | |
715 | * transmitting it. */ | |
716 | if (ctx->current_packet != packet) | |
717 | goto skip_to_next; | |
718 | ||
ed568912 KH |
719 | if (packet->payload_length > 0) { |
720 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
721 | packet->payload_length, DMA_TO_DEVICE); | |
722 | evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f; | |
723 | packet->timestamp = le16_to_cpu(ctx->d.last.res_count); | |
724 | } | |
725 | else { | |
726 | evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f; | |
727 | packet->timestamp = le16_to_cpu(ctx->d.more.res_count); | |
728 | } | |
729 | ||
730 | if (evt < 16) { | |
731 | switch (evt) { | |
732 | case OHCI1394_evt_timeout: | |
733 | /* Async response transmit timed out. */ | |
e5f49c3b | 734 | complete_transmission(packet, RCODE_CANCELLED, &list); |
ed568912 KH |
735 | break; |
736 | ||
737 | case OHCI1394_evt_flushed: | |
738 | /* The packet was flushed should give same | |
739 | * error as when we try to use a stale | |
740 | * generation count. */ | |
e5f49c3b KH |
741 | complete_transmission(packet, |
742 | RCODE_GENERATION, &list); | |
ed568912 KH |
743 | break; |
744 | ||
745 | case OHCI1394_evt_missing_ack: | |
e5f49c3b KH |
746 | /* Using a valid (current) generation count, |
747 | * but the node is not on the bus or not | |
748 | * sending acks. */ | |
749 | complete_transmission(packet, RCODE_NO_ACK, &list); | |
ed568912 KH |
750 | break; |
751 | ||
752 | default: | |
e5f49c3b | 753 | complete_transmission(packet, RCODE_SEND_ERROR, &list); |
ed568912 KH |
754 | break; |
755 | } | |
756 | } else | |
757 | complete_transmission(packet, evt - 16, &list); | |
758 | ||
730c32f5 | 759 | skip_to_next: |
ed568912 KH |
760 | /* If more packets are queued, set up the next one. */ |
761 | if (!list_empty(&ctx->list)) | |
762 | at_context_setup_packet(ctx, &list); | |
763 | ||
764 | spin_unlock_irqrestore(&ohci->lock, flags); | |
765 | ||
766 | do_packet_callbacks(ohci, &list); | |
767 | } | |
768 | ||
769 | static int | |
72e318e0 | 770 | at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 KH |
771 | { |
772 | INIT_LIST_HEAD(&ctx->list); | |
773 | ||
774 | ctx->descriptor_bus = | |
775 | dma_map_single(ohci->card.device, &ctx->d, | |
776 | sizeof ctx->d, DMA_TO_DEVICE); | |
82eff9db | 777 | if (dma_mapping_error(ctx->descriptor_bus)) |
ed568912 KH |
778 | return -ENOMEM; |
779 | ||
72e318e0 KH |
780 | ctx->regs = regs; |
781 | ctx->ohci = ohci; | |
ed568912 KH |
782 | |
783 | tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
e636fe25 | 788 | #define header_get_destination(q) (((q) >> 16) & 0xffff) |
93c4cceb KH |
789 | #define header_get_tcode(q) (((q) >> 4) & 0x0f) |
790 | #define header_get_offset_high(q) (((q) >> 0) & 0xffff) | |
791 | #define header_get_data_length(q) (((q) >> 16) & 0xffff) | |
792 | #define header_get_extended_tcode(q) (((q) >> 0) & 0xffff) | |
793 | ||
794 | static void | |
795 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
796 | { | |
797 | struct fw_packet response; | |
798 | int tcode, length, i; | |
799 | ||
800 | tcode = header_get_tcode(packet->header[0]); | |
801 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
802 | length = header_get_data_length(packet->header[3]); | |
803 | else | |
804 | length = 4; | |
805 | ||
806 | i = csr - CSR_CONFIG_ROM; | |
807 | if (i + length > CONFIG_ROM_SIZE) { | |
808 | fw_fill_response(&response, packet->header, | |
809 | RCODE_ADDRESS_ERROR, NULL, 0); | |
810 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
811 | fw_fill_response(&response, packet->header, | |
812 | RCODE_TYPE_ERROR, NULL, 0); | |
813 | } else { | |
814 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
815 | (void *) ohci->config_rom + i, length); | |
816 | } | |
817 | ||
818 | fw_core_handle_response(&ohci->card, &response); | |
819 | } | |
820 | ||
821 | static void | |
822 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
823 | { | |
824 | struct fw_packet response; | |
825 | int tcode, length, ext_tcode, sel; | |
826 | __be32 *payload, lock_old; | |
827 | u32 lock_arg, lock_data; | |
828 | ||
829 | tcode = header_get_tcode(packet->header[0]); | |
830 | length = header_get_data_length(packet->header[3]); | |
831 | payload = packet->payload; | |
832 | ext_tcode = header_get_extended_tcode(packet->header[3]); | |
833 | ||
834 | if (tcode == TCODE_LOCK_REQUEST && | |
835 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
836 | lock_arg = be32_to_cpu(payload[0]); | |
837 | lock_data = be32_to_cpu(payload[1]); | |
838 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
839 | lock_arg = 0; | |
840 | lock_data = 0; | |
841 | } else { | |
842 | fw_fill_response(&response, packet->header, | |
843 | RCODE_TYPE_ERROR, NULL, 0); | |
844 | goto out; | |
845 | } | |
846 | ||
847 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
848 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
849 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
850 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
851 | ||
852 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
853 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
854 | else | |
855 | fw_notify("swap not done yet\n"); | |
856 | ||
857 | fw_fill_response(&response, packet->header, | |
858 | RCODE_COMPLETE, &lock_old, sizeof lock_old); | |
859 | out: | |
860 | fw_core_handle_response(&ohci->card, &response); | |
861 | } | |
862 | ||
863 | static void | |
864 | handle_local_request(struct at_context *ctx, struct fw_packet *packet) | |
865 | { | |
866 | u64 offset; | |
867 | u32 csr; | |
868 | ||
869 | packet->ack = ACK_PENDING; | |
870 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
871 | ||
872 | offset = | |
873 | ((unsigned long long) | |
874 | header_get_offset_high(packet->header[1]) << 32) | | |
875 | packet->header[2]; | |
876 | csr = offset - CSR_REGISTER_BASE; | |
877 | ||
878 | /* Handle config rom reads. */ | |
879 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
880 | handle_local_rom(ctx->ohci, packet, csr); | |
881 | else switch (csr) { | |
882 | case CSR_BUS_MANAGER_ID: | |
883 | case CSR_BANDWIDTH_AVAILABLE: | |
884 | case CSR_CHANNELS_AVAILABLE_HI: | |
885 | case CSR_CHANNELS_AVAILABLE_LO: | |
886 | handle_local_lock(ctx->ohci, packet, csr); | |
887 | break; | |
888 | default: | |
889 | if (ctx == &ctx->ohci->at_request_ctx) | |
890 | fw_core_handle_request(&ctx->ohci->card, packet); | |
891 | else | |
892 | fw_core_handle_response(&ctx->ohci->card, packet); | |
893 | break; | |
894 | } | |
895 | } | |
e636fe25 | 896 | |
ed568912 KH |
897 | static void |
898 | at_context_transmit(struct at_context *ctx, struct fw_packet *packet) | |
899 | { | |
900 | LIST_HEAD(list); | |
901 | unsigned long flags; | |
ed568912 KH |
902 | |
903 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
904 | ||
e636fe25 KH |
905 | if (header_get_destination(packet->header[0]) == ctx->ohci->node_id && |
906 | ctx->ohci->generation == packet->generation) { | |
93c4cceb KH |
907 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
908 | handle_local_request(ctx, packet); | |
909 | return; | |
e636fe25 | 910 | } |
ed568912 | 911 | |
93c4cceb KH |
912 | list_add_tail(&packet->link, &ctx->list); |
913 | if (ctx->list.next == &packet->link) | |
914 | at_context_setup_packet(ctx, &list); | |
915 | ||
ed568912 KH |
916 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
917 | ||
918 | do_packet_callbacks(ctx->ohci, &list); | |
919 | } | |
920 | ||
921 | static void bus_reset_tasklet(unsigned long data) | |
922 | { | |
923 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 924 | int self_id_count, i, j, reg; |
ed568912 KH |
925 | int generation, new_generation; |
926 | unsigned long flags; | |
927 | ||
928 | reg = reg_read(ohci, OHCI1394_NodeID); | |
929 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
930 | fw_error("node ID not valid, new bus reset in progress\n"); | |
931 | return; | |
932 | } | |
e636fe25 | 933 | ohci->node_id = reg & 0xffff; |
ed568912 KH |
934 | |
935 | /* The count in the SelfIDCount register is the number of | |
936 | * bytes in the self ID receive buffer. Since we also receive | |
937 | * the inverted quadlets and a header quadlet, we shift one | |
938 | * bit extra to get the actual number of self IDs. */ | |
939 | ||
940 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
941 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
942 | ||
943 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
944 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
945 | fw_error("inconsistent self IDs\n"); | |
946 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
947 | } | |
948 | ||
949 | /* Check the consistency of the self IDs we just read. The | |
950 | * problem we face is that a new bus reset can start while we | |
951 | * read out the self IDs from the DMA buffer. If this happens, | |
952 | * the DMA buffer will be overwritten with new self IDs and we | |
953 | * will read out inconsistent data. The OHCI specification | |
954 | * (section 11.2) recommends a technique similar to | |
955 | * linux/seqlock.h, where we remember the generation of the | |
956 | * self IDs in the buffer before reading them out and compare | |
957 | * it to the current generation after reading them out. If | |
958 | * the two generations match we know we have a consistent set | |
959 | * of self IDs. */ | |
960 | ||
961 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
962 | if (new_generation != generation) { | |
963 | fw_notify("recursive bus reset detected, " | |
964 | "discarding self ids\n"); | |
965 | return; | |
966 | } | |
967 | ||
968 | /* FIXME: Document how the locking works. */ | |
969 | spin_lock_irqsave(&ohci->lock, flags); | |
970 | ||
971 | ohci->generation = generation; | |
972 | at_context_stop(&ohci->at_request_ctx); | |
973 | at_context_stop(&ohci->at_response_ctx); | |
974 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
975 | ||
976 | /* This next bit is unrelated to the AT context stuff but we | |
977 | * have to do it under the spinlock also. If a new config rom | |
978 | * was set up before this reset, the old one is now no longer | |
979 | * in use and we can free it. Update the config rom pointers | |
980 | * to point to the current config rom and clear the | |
981 | * next_config_rom pointer so a new udpate can take place. */ | |
982 | ||
983 | if (ohci->next_config_rom != NULL) { | |
984 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
985 | ohci->config_rom, ohci->config_rom_bus); | |
986 | ohci->config_rom = ohci->next_config_rom; | |
987 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
988 | ohci->next_config_rom = NULL; | |
989 | ||
990 | /* Restore config_rom image and manually update | |
991 | * config_rom registers. Writing the header quadlet | |
992 | * will indicate that the config rom is ready, so we | |
993 | * do that last. */ | |
994 | reg_write(ohci, OHCI1394_BusOptions, | |
995 | be32_to_cpu(ohci->config_rom[2])); | |
996 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
997 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
998 | } | |
999 | ||
1000 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1001 | ||
e636fe25 | 1002 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1003 | self_id_count, ohci->self_id_buffer); |
1004 | } | |
1005 | ||
1006 | static irqreturn_t irq_handler(int irq, void *data) | |
1007 | { | |
1008 | struct fw_ohci *ohci = data; | |
1009 | u32 event, iso_event; | |
1010 | int i; | |
1011 | ||
1012 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1013 | ||
1014 | if (!event) | |
1015 | return IRQ_NONE; | |
1016 | ||
1017 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
1018 | ||
1019 | if (event & OHCI1394_selfIDComplete) | |
1020 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1021 | ||
1022 | if (event & OHCI1394_RQPkt) | |
1023 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1024 | ||
1025 | if (event & OHCI1394_RSPkt) | |
1026 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1027 | ||
1028 | if (event & OHCI1394_reqTxComplete) | |
1029 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1030 | ||
1031 | if (event & OHCI1394_respTxComplete) | |
1032 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1033 | ||
c889475f | 1034 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1035 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1036 | ||
1037 | while (iso_event) { | |
1038 | i = ffs(iso_event) - 1; | |
30200739 | 1039 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1040 | iso_event &= ~(1 << i); |
1041 | } | |
1042 | ||
c889475f | 1043 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1044 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1045 | ||
1046 | while (iso_event) { | |
1047 | i = ffs(iso_event) - 1; | |
30200739 | 1048 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1049 | iso_event &= ~(1 << i); |
1050 | } | |
1051 | ||
1052 | return IRQ_HANDLED; | |
1053 | } | |
1054 | ||
1055 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |
1056 | { | |
1057 | struct fw_ohci *ohci = fw_ohci(card); | |
1058 | struct pci_dev *dev = to_pci_dev(card->device); | |
1059 | ||
1060 | /* When the link is not yet enabled, the atomic config rom | |
1061 | * update mechanism described below in ohci_set_config_rom() | |
1062 | * is not active. We have to update ConfigRomHeader and | |
1063 | * BusOptions manually, and the write to ConfigROMmap takes | |
1064 | * effect immediately. We tie this to the enabling of the | |
1065 | * link, so we have a valid config rom before enabling - the | |
1066 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1067 | * values before enabling. | |
1068 | * | |
1069 | * However, when the ConfigROMmap is written, some controllers | |
1070 | * always read back quadlets 0 and 2 from the config rom to | |
1071 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1072 | * They shouldn't do that in this initial case where the link | |
1073 | * isn't enabled. This means we have to use the same | |
1074 | * workaround here, setting the bus header to 0 and then write | |
1075 | * the right values in the bus reset tasklet. | |
1076 | */ | |
1077 | ||
1078 | ohci->next_config_rom = | |
1079 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1080 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
1081 | if (ohci->next_config_rom == NULL) | |
1082 | return -ENOMEM; | |
1083 | ||
1084 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1085 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1086 | ||
1087 | ohci->next_header = config_rom[0]; | |
1088 | ohci->next_config_rom[0] = 0; | |
1089 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
1090 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
1091 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
1092 | ||
1093 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1094 | ||
1095 | if (request_irq(dev->irq, irq_handler, | |
1096 | SA_SHIRQ, ohci_driver_name, ohci)) { | |
1097 | fw_error("Failed to allocate shared interrupt %d.\n", | |
1098 | dev->irq); | |
1099 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1100 | ohci->config_rom, ohci->config_rom_bus); | |
1101 | return -EIO; | |
1102 | } | |
1103 | ||
1104 | reg_write(ohci, OHCI1394_HCControlSet, | |
1105 | OHCI1394_HCControl_linkEnable | | |
1106 | OHCI1394_HCControl_BIBimageValid); | |
1107 | flush_writes(ohci); | |
1108 | ||
1109 | /* We are ready to go, initiate bus reset to finish the | |
1110 | * initialization. */ | |
1111 | ||
1112 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static int | |
1118 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1119 | { | |
1120 | struct fw_ohci *ohci; | |
1121 | unsigned long flags; | |
1122 | int retval = 0; | |
1123 | __be32 *next_config_rom; | |
1124 | dma_addr_t next_config_rom_bus; | |
1125 | ||
1126 | ohci = fw_ohci(card); | |
1127 | ||
1128 | /* When the OHCI controller is enabled, the config rom update | |
1129 | * mechanism is a bit tricky, but easy enough to use. See | |
1130 | * section 5.5.6 in the OHCI specification. | |
1131 | * | |
1132 | * The OHCI controller caches the new config rom address in a | |
1133 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1134 | * for the changes to take place. When the bus reset is | |
1135 | * detected, the controller loads the new values for the | |
1136 | * ConfigRomHeader and BusOptions registers from the specified | |
1137 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1138 | * shadow register. All automatically and atomically. | |
1139 | * | |
1140 | * Now, there's a twist to this story. The automatic load of | |
1141 | * ConfigRomHeader and BusOptions doesn't honor the | |
1142 | * noByteSwapData bit, so with a be32 config rom, the | |
1143 | * controller will load be32 values in to these registers | |
1144 | * during the atomic update, even on litte endian | |
1145 | * architectures. The workaround we use is to put a 0 in the | |
1146 | * header quadlet; 0 is endian agnostic and means that the | |
1147 | * config rom isn't ready yet. In the bus reset tasklet we | |
1148 | * then set up the real values for the two registers. | |
1149 | * | |
1150 | * We use ohci->lock to avoid racing with the code that sets | |
1151 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1152 | */ | |
1153 | ||
1154 | next_config_rom = | |
1155 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1156 | &next_config_rom_bus, GFP_KERNEL); | |
1157 | if (next_config_rom == NULL) | |
1158 | return -ENOMEM; | |
1159 | ||
1160 | spin_lock_irqsave(&ohci->lock, flags); | |
1161 | ||
1162 | if (ohci->next_config_rom == NULL) { | |
1163 | ohci->next_config_rom = next_config_rom; | |
1164 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1165 | ||
1166 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1167 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1168 | length * 4); | |
1169 | ||
1170 | ohci->next_header = config_rom[0]; | |
1171 | ohci->next_config_rom[0] = 0; | |
1172 | ||
1173 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1174 | ohci->next_config_rom_bus); | |
1175 | } else { | |
1176 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1177 | next_config_rom, next_config_rom_bus); | |
1178 | retval = -EBUSY; | |
1179 | } | |
1180 | ||
1181 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1182 | ||
1183 | /* Now initiate a bus reset to have the changes take | |
1184 | * effect. We clean up the old config rom memory and DMA | |
1185 | * mappings in the bus reset tasklet, since the OHCI | |
1186 | * controller could need to access it before the bus reset | |
1187 | * takes effect. */ | |
1188 | if (retval == 0) | |
1189 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1190 | ||
1191 | return retval; | |
1192 | } | |
1193 | ||
1194 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1195 | { | |
1196 | struct fw_ohci *ohci = fw_ohci(card); | |
1197 | ||
1198 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1199 | } | |
1200 | ||
1201 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1202 | { | |
1203 | struct fw_ohci *ohci = fw_ohci(card); | |
1204 | ||
1205 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1206 | } | |
1207 | ||
730c32f5 KH |
1208 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1209 | { | |
1210 | struct fw_ohci *ohci = fw_ohci(card); | |
1211 | LIST_HEAD(list); | |
1212 | unsigned long flags; | |
1213 | ||
1214 | spin_lock_irqsave(&ohci->lock, flags); | |
1215 | ||
1216 | if (packet->ack == 0) { | |
1217 | fw_notify("cancelling packet %p (header[0]=%08x)\n", | |
1218 | packet, packet->header[0]); | |
1219 | ||
1220 | complete_transmission(packet, RCODE_CANCELLED, &list); | |
1221 | } | |
1222 | ||
1223 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1224 | ||
1225 | do_packet_callbacks(ohci, &list); | |
1226 | ||
1227 | /* Return success if we actually cancelled something. */ | |
1228 | return list_empty(&list) ? -ENOENT : 0; | |
1229 | } | |
1230 | ||
ed568912 KH |
1231 | static int |
1232 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1233 | { | |
1234 | struct fw_ohci *ohci = fw_ohci(card); | |
1235 | unsigned long flags; | |
907293d7 | 1236 | int n, retval = 0; |
ed568912 | 1237 | |
907293d7 SR |
1238 | /* FIXME: Make sure this bitmask is cleared when we clear the busReset |
1239 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ | |
ed568912 KH |
1240 | |
1241 | spin_lock_irqsave(&ohci->lock, flags); | |
1242 | ||
1243 | if (ohci->generation != generation) { | |
1244 | retval = -ESTALE; | |
1245 | goto out; | |
1246 | } | |
1247 | ||
907293d7 SR |
1248 | /* NOTE, if the node ID contains a non-local bus ID, physical DMA is |
1249 | * enabled for _all_ nodes on remote buses. */ | |
1250 | ||
1251 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1252 | if (n < 32) | |
1253 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1254 | else | |
1255 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1256 | ||
ed568912 | 1257 | flush_writes(ohci); |
ed568912 | 1258 | out: |
6cad95fe | 1259 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1260 | return retval; |
1261 | } | |
1262 | ||
295e3feb KH |
1263 | static int handle_ir_packet(struct context *context, |
1264 | struct descriptor *d, | |
1265 | struct descriptor *last) | |
ed568912 | 1266 | { |
295e3feb KH |
1267 | struct iso_context *ctx = |
1268 | container_of(context, struct iso_context, context); | |
1269 | struct db_descriptor *db = (struct db_descriptor *) d; | |
1270 | ||
1271 | if (db->first_res_count > 0 && db->second_res_count > 0) | |
1272 | /* This descriptor isn't done yet, stop iteration. */ | |
1273 | return 0; | |
1274 | ||
1275 | if (le16_to_cpu(db->control) & descriptor_irq_always) | |
1276 | /* FIXME: we should pass payload address here. */ | |
1277 | ctx->base.callback(&ctx->base, | |
1278 | 0, 0, | |
1279 | ctx->base.callback_data); | |
ed568912 | 1280 | |
295e3feb | 1281 | return 1; |
ed568912 KH |
1282 | } |
1283 | ||
1284 | #define ISO_BUFFER_SIZE (64 * 1024) | |
1285 | ||
30200739 KH |
1286 | static int handle_it_packet(struct context *context, |
1287 | struct descriptor *d, | |
1288 | struct descriptor *last) | |
ed568912 | 1289 | { |
30200739 KH |
1290 | struct iso_context *ctx = |
1291 | container_of(context, struct iso_context, context); | |
1292 | ||
1293 | if (last->transfer_status == 0) | |
1294 | /* This descriptor isn't done yet, stop iteration. */ | |
1295 | return 0; | |
1296 | ||
1297 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
1298 | ctx->base.callback(&ctx->base, | |
1299 | 0, le16_to_cpu(last->res_count), | |
1300 | ctx->base.callback_data); | |
1301 | ||
1302 | return 1; | |
ed568912 KH |
1303 | } |
1304 | ||
30200739 KH |
1305 | static struct fw_iso_context * |
1306 | ohci_allocate_iso_context(struct fw_card *card, int type) | |
ed568912 KH |
1307 | { |
1308 | struct fw_ohci *ohci = fw_ohci(card); | |
1309 | struct iso_context *ctx, *list; | |
30200739 | 1310 | descriptor_callback_t callback; |
295e3feb | 1311 | u32 *mask, regs; |
ed568912 | 1312 | unsigned long flags; |
30200739 | 1313 | int index, retval; |
ed568912 KH |
1314 | |
1315 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1316 | mask = &ohci->it_context_mask; | |
1317 | list = ohci->it_context_list; | |
30200739 | 1318 | callback = handle_it_packet; |
ed568912 | 1319 | } else { |
295e3feb KH |
1320 | mask = &ohci->ir_context_mask; |
1321 | list = ohci->ir_context_list; | |
1322 | callback = handle_ir_packet; | |
ed568912 KH |
1323 | } |
1324 | ||
1325 | spin_lock_irqsave(&ohci->lock, flags); | |
1326 | index = ffs(*mask) - 1; | |
1327 | if (index >= 0) | |
1328 | *mask &= ~(1 << index); | |
1329 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1330 | ||
1331 | if (index < 0) | |
1332 | return ERR_PTR(-EBUSY); | |
1333 | ||
295e3feb KH |
1334 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1335 | regs = OHCI1394_IsoXmitContextBase(index); | |
1336 | else | |
1337 | regs = OHCI1394_IsoRcvContextBase(index); | |
1338 | ||
ed568912 KH |
1339 | ctx = &list[index]; |
1340 | memset(ctx, 0, sizeof *ctx); | |
30200739 | 1341 | retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE, |
295e3feb | 1342 | regs, callback); |
30200739 KH |
1343 | if (retval < 0) { |
1344 | spin_lock_irqsave(&ohci->lock, flags); | |
1345 | *mask |= 1 << index; | |
1346 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1347 | return ERR_PTR(retval); | |
1348 | } | |
ed568912 KH |
1349 | |
1350 | return &ctx->base; | |
1351 | } | |
1352 | ||
69cdb726 | 1353 | static int ohci_start_iso(struct fw_iso_context *base, s32 cycle) |
ed568912 | 1354 | { |
30200739 KH |
1355 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1356 | struct fw_ohci *ohci = ctx->context.ohci; | |
ed568912 KH |
1357 | u32 cycle_match = 0; |
1358 | int index; | |
1359 | ||
295e3feb KH |
1360 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1361 | index = ctx - ohci->it_context_list; | |
1362 | if (cycle > 0) | |
1363 | cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
1364 | (cycle & 0x7fff) << 16; | |
1365 | ||
1366 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); | |
1367 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
1368 | context_run(&ctx->context, cycle_match); | |
1369 | } else { | |
1370 | index = ctx - ohci->ir_context_list; | |
ed568912 | 1371 | |
295e3feb KH |
1372 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1373 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
1374 | reg_write(ohci, context_match(ctx->context.regs), | |
1375 | 0xf0000000 | ctx->base.channel); | |
1376 | context_run(&ctx->context, IR_CONTEXT_DUAL_BUFFER_MODE); | |
1377 | } | |
ed568912 KH |
1378 | |
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | static void ohci_free_iso_context(struct fw_iso_context *base) | |
1383 | { | |
1384 | struct fw_ohci *ohci = fw_ohci(base->card); | |
30200739 | 1385 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1386 | unsigned long flags; |
1387 | int index; | |
1388 | ||
ed568912 KH |
1389 | spin_lock_irqsave(&ohci->lock, flags); |
1390 | ||
1391 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1392 | index = ctx - ohci->it_context_list; | |
1393 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
1394 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1395 | ohci->it_context_mask |= 1 << index; | |
1396 | } else { | |
1397 | index = ctx - ohci->ir_context_list; | |
1398 | reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0); | |
1399 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1400 | ohci->ir_context_mask |= 1 << index; | |
1401 | } | |
1402 | flush_writes(ohci); | |
1403 | ||
30200739 | 1404 | context_release(&ctx->context); |
ed568912 KH |
1405 | |
1406 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1407 | } | |
1408 | ||
1409 | static int | |
295e3feb KH |
1410 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1411 | struct fw_iso_packet *packet, | |
1412 | struct fw_iso_buffer *buffer, | |
1413 | unsigned long payload) | |
ed568912 | 1414 | { |
30200739 KH |
1415 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1416 | struct descriptor *d, *last, *pd; | |
ed568912 KH |
1417 | struct fw_iso_packet *p; |
1418 | __le32 *header; | |
9aad8125 | 1419 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1420 | u32 z, header_z, payload_z, irq; |
1421 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1422 | int page, end_page, i, length, offset; |
ed568912 KH |
1423 | |
1424 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1425 | * packet, retransmit or terminate.. */ | |
1426 | ||
1427 | p = packet; | |
9aad8125 | 1428 | payload_index = payload; |
ed568912 KH |
1429 | |
1430 | if (p->skip) | |
1431 | z = 1; | |
1432 | else | |
1433 | z = 2; | |
1434 | if (p->header_length > 0) | |
1435 | z++; | |
1436 | ||
1437 | /* Determine the first page the payload isn't contained in. */ | |
1438 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1439 | if (p->payload_length > 0) | |
1440 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1441 | else | |
1442 | payload_z = 0; | |
1443 | ||
1444 | z += payload_z; | |
1445 | ||
1446 | /* Get header size in number of descriptors. */ | |
1447 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1448 | ||
30200739 KH |
1449 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
1450 | if (d == NULL) | |
1451 | return -ENOMEM; | |
ed568912 KH |
1452 | |
1453 | if (!p->skip) { | |
1454 | d[0].control = cpu_to_le16(descriptor_key_immediate); | |
1455 | d[0].req_count = cpu_to_le16(8); | |
1456 | ||
1457 | header = (__le32 *) &d[1]; | |
1458 | header[0] = cpu_to_le32(it_header_sy(p->sy) | | |
1459 | it_header_tag(p->tag) | | |
1460 | it_header_tcode(TCODE_STREAM_DATA) | | |
1461 | it_header_channel(ctx->base.channel) | | |
1462 | it_header_speed(ctx->base.speed)); | |
1463 | header[1] = | |
1464 | cpu_to_le32(it_header_data_length(p->header_length + | |
1465 | p->payload_length)); | |
1466 | } | |
1467 | ||
1468 | if (p->header_length > 0) { | |
1469 | d[2].req_count = cpu_to_le16(p->header_length); | |
1470 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d); | |
1471 | memcpy(&d[z], p->header, p->header_length); | |
1472 | } | |
1473 | ||
1474 | pd = d + z - payload_z; | |
1475 | payload_end_index = payload_index + p->payload_length; | |
1476 | for (i = 0; i < payload_z; i++) { | |
1477 | page = payload_index >> PAGE_SHIFT; | |
1478 | offset = payload_index & ~PAGE_MASK; | |
1479 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1480 | length = | |
1481 | min(next_page_index, payload_end_index) - payload_index; | |
1482 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
1483 | |
1484 | page_bus = page_private(buffer->pages[page]); | |
1485 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
1486 | |
1487 | payload_index += length; | |
1488 | } | |
1489 | ||
ed568912 KH |
1490 | if (p->interrupt) |
1491 | irq = descriptor_irq_always; | |
1492 | else | |
1493 | irq = descriptor_no_irq; | |
1494 | ||
30200739 | 1495 | last = z == 2 ? d : d + z - 1; |
cbb59da7 KH |
1496 | last->control |= cpu_to_le16(descriptor_output_last | |
1497 | descriptor_status | | |
1498 | descriptor_branch_always | | |
1499 | irq); | |
ed568912 | 1500 | |
30200739 | 1501 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
1502 | |
1503 | return 0; | |
1504 | } | |
1505 | ||
295e3feb KH |
1506 | static int |
1507 | ohci_queue_iso_receive(struct fw_iso_context *base, | |
1508 | struct fw_iso_packet *packet, | |
1509 | struct fw_iso_buffer *buffer, | |
1510 | unsigned long payload) | |
1511 | { | |
1512 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1513 | struct db_descriptor *db = NULL; | |
1514 | struct descriptor *d; | |
1515 | struct fw_iso_packet *p; | |
1516 | dma_addr_t d_bus, page_bus; | |
1517 | u32 z, header_z, length, rest; | |
1518 | int page, offset; | |
1519 | ||
1520 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1521 | * packet, retransmit or terminate.. */ | |
1522 | ||
1523 | p = packet; | |
1524 | z = 2; | |
1525 | ||
1526 | /* Get header size in number of descriptors. */ | |
1527 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1528 | page = payload >> PAGE_SHIFT; | |
1529 | offset = payload & ~PAGE_MASK; | |
1530 | rest = p->payload_length; | |
1531 | ||
1532 | /* FIXME: OHCI 1.0 doesn't support dual buffer receive */ | |
1533 | /* FIXME: handle descriptor_wait */ | |
1534 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ | |
1535 | while (rest > 0) { | |
1536 | d = context_get_descriptors(&ctx->context, | |
1537 | z + header_z, &d_bus); | |
1538 | if (d == NULL) | |
1539 | return -ENOMEM; | |
1540 | ||
1541 | db = (struct db_descriptor *) d; | |
1542 | db->control = cpu_to_le16(descriptor_status | | |
1543 | descriptor_branch_always); | |
1544 | db->first_size = cpu_to_le16(ctx->base.header_size); | |
1545 | db->first_req_count = cpu_to_le16(p->header_length); | |
1546 | db->second_req_count = cpu_to_le16(p->payload_length); | |
1547 | db->first_res_count = cpu_to_le16(db->first_req_count); | |
1548 | db->second_res_count = cpu_to_le16(db->second_req_count); | |
1549 | ||
1550 | db->first_buffer = cpu_to_le32(d_bus + sizeof *db); | |
1551 | ||
1552 | if (offset + rest < PAGE_SIZE) | |
1553 | length = rest; | |
1554 | else | |
1555 | length = PAGE_SIZE - offset; | |
1556 | ||
1557 | page_bus = page_private(buffer->pages[page]); | |
1558 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
1559 | ||
1560 | context_append(&ctx->context, d, z, header_z); | |
1561 | offset = (offset + length) & ~PAGE_MASK; | |
1562 | rest -= length; | |
1563 | page++; | |
1564 | } | |
1565 | ||
1566 | if (p->interrupt) | |
1567 | db->control |= cpu_to_le16(descriptor_irq_always); | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | static int | |
1573 | ohci_queue_iso(struct fw_iso_context *base, | |
1574 | struct fw_iso_packet *packet, | |
1575 | struct fw_iso_buffer *buffer, | |
1576 | unsigned long payload) | |
1577 | { | |
1578 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) | |
1579 | return ohci_queue_iso_transmit(base, packet, buffer, payload); | |
1580 | else | |
1581 | return ohci_queue_iso_receive(base, packet, buffer, payload); | |
1582 | } | |
1583 | ||
21ebcd12 | 1584 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1585 | .name = ohci_driver_name, |
1586 | .enable = ohci_enable, | |
1587 | .update_phy_reg = ohci_update_phy_reg, | |
1588 | .set_config_rom = ohci_set_config_rom, | |
1589 | .send_request = ohci_send_request, | |
1590 | .send_response = ohci_send_response, | |
730c32f5 | 1591 | .cancel_packet = ohci_cancel_packet, |
ed568912 KH |
1592 | .enable_phys_dma = ohci_enable_phys_dma, |
1593 | ||
1594 | .allocate_iso_context = ohci_allocate_iso_context, | |
1595 | .free_iso_context = ohci_free_iso_context, | |
1596 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 1597 | .start_iso = ohci_start_iso, |
ed568912 KH |
1598 | }; |
1599 | ||
1600 | static int software_reset(struct fw_ohci *ohci) | |
1601 | { | |
1602 | int i; | |
1603 | ||
1604 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1605 | ||
1606 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1607 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1608 | OHCI1394_HCControl_softReset) == 0) | |
1609 | return 0; | |
1610 | msleep(1); | |
1611 | } | |
1612 | ||
1613 | return -EBUSY; | |
1614 | } | |
1615 | ||
1616 | /* ---------- pci subsystem interface ---------- */ | |
1617 | ||
1618 | enum { | |
1619 | CLEANUP_SELF_ID, | |
1620 | CLEANUP_REGISTERS, | |
1621 | CLEANUP_IOMEM, | |
1622 | CLEANUP_DISABLE, | |
1623 | CLEANUP_PUT_CARD, | |
1624 | }; | |
1625 | ||
1626 | static int cleanup(struct fw_ohci *ohci, int stage, int code) | |
1627 | { | |
1628 | struct pci_dev *dev = to_pci_dev(ohci->card.device); | |
1629 | ||
1630 | switch (stage) { | |
1631 | case CLEANUP_SELF_ID: | |
1632 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1633 | ohci->self_id_cpu, ohci->self_id_bus); | |
1634 | case CLEANUP_REGISTERS: | |
1635 | kfree(ohci->it_context_list); | |
1636 | kfree(ohci->ir_context_list); | |
1637 | pci_iounmap(dev, ohci->registers); | |
1638 | case CLEANUP_IOMEM: | |
1639 | pci_release_region(dev, 0); | |
1640 | case CLEANUP_DISABLE: | |
1641 | pci_disable_device(dev); | |
1642 | case CLEANUP_PUT_CARD: | |
1643 | fw_card_put(&ohci->card); | |
1644 | } | |
1645 | ||
1646 | return code; | |
1647 | } | |
1648 | ||
1649 | static int __devinit | |
1650 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1651 | { | |
1652 | struct fw_ohci *ohci; | |
1653 | u32 bus_options, max_receive, link_speed; | |
1654 | u64 guid; | |
1655 | int error_code; | |
1656 | size_t size; | |
1657 | ||
1658 | ohci = kzalloc(sizeof *ohci, GFP_KERNEL); | |
1659 | if (ohci == NULL) { | |
1660 | fw_error("Could not malloc fw_ohci data.\n"); | |
1661 | return -ENOMEM; | |
1662 | } | |
1663 | ||
1664 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1665 | ||
1666 | if (pci_enable_device(dev)) { | |
1667 | fw_error("Failed to enable OHCI hardware.\n"); | |
1668 | return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV); | |
1669 | } | |
1670 | ||
1671 | pci_set_master(dev); | |
1672 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1673 | pci_set_drvdata(dev, ohci); | |
1674 | ||
1675 | spin_lock_init(&ohci->lock); | |
1676 | ||
1677 | tasklet_init(&ohci->bus_reset_tasklet, | |
1678 | bus_reset_tasklet, (unsigned long)ohci); | |
1679 | ||
1680 | if (pci_request_region(dev, 0, ohci_driver_name)) { | |
1681 | fw_error("MMIO resource unavailable\n"); | |
1682 | return cleanup(ohci, CLEANUP_DISABLE, -EBUSY); | |
1683 | } | |
1684 | ||
1685 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1686 | if (ohci->registers == NULL) { | |
1687 | fw_error("Failed to remap registers\n"); | |
1688 | return cleanup(ohci, CLEANUP_IOMEM, -ENXIO); | |
1689 | } | |
1690 | ||
1691 | if (software_reset(ohci)) { | |
1692 | fw_error("Failed to reset ohci card.\n"); | |
1693 | return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); | |
1694 | } | |
1695 | ||
1696 | /* Now enable LPS, which we need in order to start accessing | |
1697 | * most of the registers. In fact, on some cards (ALI M5251), | |
1698 | * accessing registers in the SClk domain without LPS enabled | |
1699 | * will lock up the machine. Wait 50msec to make sure we have | |
1700 | * full link enabled. */ | |
1701 | reg_write(ohci, OHCI1394_HCControlSet, | |
1702 | OHCI1394_HCControl_LPS | | |
1703 | OHCI1394_HCControl_postedWriteEnable); | |
1704 | flush_writes(ohci); | |
1705 | msleep(50); | |
1706 | ||
1707 | reg_write(ohci, OHCI1394_HCControlClear, | |
1708 | OHCI1394_HCControl_noByteSwapData); | |
1709 | ||
1710 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1711 | OHCI1394_LinkControl_rcvSelfID | | |
1712 | OHCI1394_LinkControl_cycleTimerEnable | | |
1713 | OHCI1394_LinkControl_cycleMaster); | |
1714 | ||
1715 | ar_context_init(&ohci->ar_request_ctx, ohci, | |
1716 | OHCI1394_AsReqRcvContextControlSet); | |
1717 | ||
1718 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1719 | OHCI1394_AsRspRcvContextControlSet); | |
1720 | ||
1721 | at_context_init(&ohci->at_request_ctx, ohci, | |
1722 | OHCI1394_AsReqTrContextControlSet); | |
1723 | ||
1724 | at_context_init(&ohci->at_response_ctx, ohci, | |
1725 | OHCI1394_AsRspTrContextControlSet); | |
1726 | ||
1727 | reg_write(ohci, OHCI1394_ATRetries, | |
1728 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1729 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1730 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1731 | ||
1732 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); | |
1733 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1734 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1735 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1736 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1737 | ||
1738 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1739 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1740 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1741 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1742 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1743 | ||
1744 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1745 | fw_error("Out of memory for it/ir contexts.\n"); | |
1746 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1747 | } | |
1748 | ||
1749 | /* self-id dma buffer allocation */ | |
1750 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1751 | SELF_ID_BUF_SIZE, | |
1752 | &ohci->self_id_bus, | |
1753 | GFP_KERNEL); | |
1754 | if (ohci->self_id_cpu == NULL) { | |
1755 | fw_error("Out of memory for self ID buffer.\n"); | |
1756 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1757 | } | |
1758 | ||
1759 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1760 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1761 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1762 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1763 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1764 | OHCI1394_selfIDComplete | | |
1765 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1766 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1767 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1768 | OHCI1394_masterIntEnable); | |
1769 | ||
1770 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
1771 | max_receive = (bus_options >> 12) & 0xf; | |
1772 | link_speed = bus_options & 0x7; | |
1773 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1774 | reg_read(ohci, OHCI1394_GUIDLo); | |
1775 | ||
1776 | error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid); | |
1777 | if (error_code < 0) | |
1778 | return cleanup(ohci, CLEANUP_SELF_ID, error_code); | |
1779 | ||
1780 | fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id); | |
1781 | ||
1782 | return 0; | |
1783 | } | |
1784 | ||
1785 | static void pci_remove(struct pci_dev *dev) | |
1786 | { | |
1787 | struct fw_ohci *ohci; | |
1788 | ||
1789 | ohci = pci_get_drvdata(dev); | |
1790 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable); | |
1791 | fw_core_remove_card(&ohci->card); | |
1792 | ||
1793 | /* FIXME: Fail all pending packets here, now that the upper | |
1794 | * layers can't queue any more. */ | |
1795 | ||
1796 | software_reset(ohci); | |
1797 | free_irq(dev->irq, ohci); | |
1798 | cleanup(ohci, CLEANUP_SELF_ID, 0); | |
1799 | ||
1800 | fw_notify("Removed fw-ohci device.\n"); | |
1801 | } | |
1802 | ||
1803 | static struct pci_device_id pci_table[] = { | |
1804 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1805 | { } | |
1806 | }; | |
1807 | ||
1808 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1809 | ||
1810 | static struct pci_driver fw_ohci_pci_driver = { | |
1811 | .name = ohci_driver_name, | |
1812 | .id_table = pci_table, | |
1813 | .probe = pci_probe, | |
1814 | .remove = pci_remove, | |
1815 | }; | |
1816 | ||
1817 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1818 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1819 | MODULE_LICENSE("GPL"); | |
1820 | ||
1821 | static int __init fw_ohci_init(void) | |
1822 | { | |
1823 | return pci_register_driver(&fw_ohci_pci_driver); | |
1824 | } | |
1825 | ||
1826 | static void __exit fw_ohci_cleanup(void) | |
1827 | { | |
1828 | pci_unregister_driver(&fw_ohci_pci_driver); | |
1829 | } | |
1830 | ||
1831 | module_init(fw_ohci_init); | |
1832 | module_exit(fw_ohci_cleanup); |