Commit | Line | Data |
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c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd | 28 | #include <linux/dma-mapping.h> |
faa2fb4e | 29 | #include <linux/mm.h> |
cf3e72fd | 30 | |
ed568912 KH |
31 | #include <asm/uaccess.h> |
32 | #include <asm/semaphore.h> | |
33 | ||
34 | #include "fw-transaction.h" | |
35 | #include "fw-ohci.h" | |
36 | ||
a77754a7 KH |
37 | #define DESCRIPTOR_OUTPUT_MORE 0 |
38 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
39 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
40 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
41 | #define DESCRIPTOR_STATUS (1 << 11) | |
42 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
43 | #define DESCRIPTOR_PING (1 << 7) | |
44 | #define DESCRIPTOR_YY (1 << 6) | |
45 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
46 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
47 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
48 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
49 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
50 | |
51 | struct descriptor { | |
52 | __le16 req_count; | |
53 | __le16 control; | |
54 | __le32 data_address; | |
55 | __le32 branch_address; | |
56 | __le16 res_count; | |
57 | __le16 transfer_status; | |
58 | } __attribute__((aligned(16))); | |
59 | ||
295e3feb KH |
60 | struct db_descriptor { |
61 | __le16 first_size; | |
62 | __le16 control; | |
63 | __le16 second_req_count; | |
64 | __le16 first_req_count; | |
65 | __le32 branch_address; | |
66 | __le16 second_res_count; | |
67 | __le16 first_res_count; | |
68 | __le32 reserved0; | |
69 | __le32 first_buffer; | |
70 | __le32 second_buffer; | |
71 | __le32 reserved1; | |
72 | } __attribute__((aligned(16))); | |
73 | ||
a77754a7 KH |
74 | #define CONTROL_SET(regs) (regs) |
75 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
76 | #define COMMAND_PTR(regs) ((regs) + 12) | |
77 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 78 | |
32b46093 | 79 | struct ar_buffer { |
ed568912 | 80 | struct descriptor descriptor; |
32b46093 KH |
81 | struct ar_buffer *next; |
82 | __le32 data[0]; | |
83 | }; | |
ed568912 | 84 | |
32b46093 KH |
85 | struct ar_context { |
86 | struct fw_ohci *ohci; | |
87 | struct ar_buffer *current_buffer; | |
88 | struct ar_buffer *last_buffer; | |
89 | void *pointer; | |
72e318e0 | 90 | u32 regs; |
ed568912 KH |
91 | struct tasklet_struct tasklet; |
92 | }; | |
93 | ||
30200739 KH |
94 | struct context; |
95 | ||
96 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
97 | struct descriptor *d, | |
98 | struct descriptor *last); | |
99 | struct context { | |
373b2edd | 100 | struct fw_ohci *ohci; |
30200739 | 101 | u32 regs; |
373b2edd | 102 | |
30200739 KH |
103 | struct descriptor *buffer; |
104 | dma_addr_t buffer_bus; | |
105 | size_t buffer_size; | |
106 | struct descriptor *head_descriptor; | |
107 | struct descriptor *tail_descriptor; | |
108 | struct descriptor *tail_descriptor_last; | |
109 | struct descriptor *prev_descriptor; | |
110 | ||
111 | descriptor_callback_t callback; | |
112 | ||
373b2edd | 113 | struct tasklet_struct tasklet; |
30200739 | 114 | }; |
30200739 | 115 | |
a77754a7 KH |
116 | #define IT_HEADER_SY(v) ((v) << 0) |
117 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
118 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
119 | #define IT_HEADER_TAG(v) ((v) << 14) | |
120 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
121 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
122 | |
123 | struct iso_context { | |
124 | struct fw_iso_context base; | |
30200739 | 125 | struct context context; |
9b32d5f3 KH |
126 | void *header; |
127 | size_t header_length; | |
ed568912 KH |
128 | }; |
129 | ||
130 | #define CONFIG_ROM_SIZE 1024 | |
131 | ||
132 | struct fw_ohci { | |
133 | struct fw_card card; | |
134 | ||
e364cf4e | 135 | u32 version; |
ed568912 KH |
136 | __iomem char *registers; |
137 | dma_addr_t self_id_bus; | |
138 | __le32 *self_id_cpu; | |
139 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 140 | int node_id; |
ed568912 KH |
141 | int generation; |
142 | int request_generation; | |
d60d7f1d | 143 | u32 bus_seconds; |
ed568912 | 144 | |
c781c06d KH |
145 | /* |
146 | * Spinlock for accessing fw_ohci data. Never call out of | |
147 | * this driver with this lock held. | |
148 | */ | |
ed568912 KH |
149 | spinlock_t lock; |
150 | u32 self_id_buffer[512]; | |
151 | ||
152 | /* Config rom buffers */ | |
153 | __be32 *config_rom; | |
154 | dma_addr_t config_rom_bus; | |
155 | __be32 *next_config_rom; | |
156 | dma_addr_t next_config_rom_bus; | |
157 | u32 next_header; | |
158 | ||
159 | struct ar_context ar_request_ctx; | |
160 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
161 | struct context at_request_ctx; |
162 | struct context at_response_ctx; | |
ed568912 KH |
163 | |
164 | u32 it_context_mask; | |
165 | struct iso_context *it_context_list; | |
166 | u32 ir_context_mask; | |
167 | struct iso_context *ir_context_list; | |
168 | }; | |
169 | ||
95688e97 | 170 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
171 | { |
172 | return container_of(card, struct fw_ohci, card); | |
173 | } | |
174 | ||
295e3feb KH |
175 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
176 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
177 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
178 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
179 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
180 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
181 | |
182 | #define CONTEXT_RUN 0x8000 | |
183 | #define CONTEXT_WAKE 0x1000 | |
184 | #define CONTEXT_DEAD 0x0800 | |
185 | #define CONTEXT_ACTIVE 0x0400 | |
186 | ||
187 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
188 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
189 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
190 | ||
191 | #define FW_OHCI_MAJOR 240 | |
192 | #define OHCI1394_REGISTER_SIZE 0x800 | |
193 | #define OHCI_LOOP_COUNT 500 | |
194 | #define OHCI1394_PCI_HCI_Control 0x40 | |
195 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 196 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 197 | #define OHCI_VERSION_1_1 0x010010 |
f319b6a0 KH |
198 | #define ISO_BUFFER_SIZE (64 * 1024) |
199 | #define AT_BUFFER_SIZE 4096 | |
0edeefd9 | 200 | |
ed568912 KH |
201 | static char ohci_driver_name[] = KBUILD_MODNAME; |
202 | ||
95688e97 | 203 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
204 | { |
205 | writel(data, ohci->registers + offset); | |
206 | } | |
207 | ||
95688e97 | 208 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
209 | { |
210 | return readl(ohci->registers + offset); | |
211 | } | |
212 | ||
95688e97 | 213 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
214 | { |
215 | /* Do a dummy read to flush writes. */ | |
216 | reg_read(ohci, OHCI1394_Version); | |
217 | } | |
218 | ||
219 | static int | |
220 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
221 | int clear_bits, int set_bits) | |
222 | { | |
223 | struct fw_ohci *ohci = fw_ohci(card); | |
224 | u32 val, old; | |
225 | ||
226 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
362e901c | 227 | flush_writes(ohci); |
ed568912 KH |
228 | msleep(2); |
229 | val = reg_read(ohci, OHCI1394_PhyControl); | |
230 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
231 | fw_error("failed to set phy reg bits.\n"); | |
232 | return -EBUSY; | |
233 | } | |
234 | ||
235 | old = OHCI1394_PhyControl_ReadData(val); | |
236 | old = (old & ~clear_bits) | set_bits; | |
237 | reg_write(ohci, OHCI1394_PhyControl, | |
238 | OHCI1394_PhyControl_Write(addr, old)); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
32b46093 | 243 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 244 | { |
32b46093 KH |
245 | struct device *dev = ctx->ohci->card.device; |
246 | struct ar_buffer *ab; | |
247 | dma_addr_t ab_bus; | |
248 | size_t offset; | |
249 | ||
250 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
251 | if (ab == NULL) | |
252 | return -ENOMEM; | |
253 | ||
254 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
255 | if (dma_mapping_error(ab_bus)) { | |
256 | free_page((unsigned long) ab); | |
257 | return -ENOMEM; | |
258 | } | |
259 | ||
2d826cc5 | 260 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
261 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
262 | DESCRIPTOR_STATUS | | |
263 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
264 | offset = offsetof(struct ar_buffer, data); |
265 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
266 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
267 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
268 | ab->descriptor.branch_address = 0; | |
269 | ||
270 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
271 | ||
ec839e43 | 272 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
273 | ctx->last_buffer->next = ab; |
274 | ctx->last_buffer = ab; | |
275 | ||
a77754a7 | 276 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 277 | flush_writes(ctx->ohci); |
32b46093 KH |
278 | |
279 | return 0; | |
ed568912 KH |
280 | } |
281 | ||
32b46093 | 282 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 283 | { |
ed568912 | 284 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
285 | struct fw_packet p; |
286 | u32 status, length, tcode; | |
2639a6fb | 287 | |
32b46093 KH |
288 | p.header[0] = le32_to_cpu(buffer[0]); |
289 | p.header[1] = le32_to_cpu(buffer[1]); | |
290 | p.header[2] = le32_to_cpu(buffer[2]); | |
2639a6fb KH |
291 | |
292 | tcode = (p.header[0] >> 4) & 0x0f; | |
293 | switch (tcode) { | |
294 | case TCODE_WRITE_QUADLET_REQUEST: | |
295 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 296 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 297 | p.header_length = 16; |
32b46093 | 298 | p.payload_length = 0; |
2639a6fb KH |
299 | break; |
300 | ||
2639a6fb | 301 | case TCODE_READ_BLOCK_REQUEST : |
32b46093 KH |
302 | p.header[3] = le32_to_cpu(buffer[3]); |
303 | p.header_length = 16; | |
304 | p.payload_length = 0; | |
305 | break; | |
306 | ||
307 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
308 | case TCODE_READ_BLOCK_RESPONSE: |
309 | case TCODE_LOCK_REQUEST: | |
310 | case TCODE_LOCK_RESPONSE: | |
32b46093 | 311 | p.header[3] = le32_to_cpu(buffer[3]); |
2639a6fb | 312 | p.header_length = 16; |
32b46093 | 313 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
314 | break; |
315 | ||
316 | case TCODE_WRITE_RESPONSE: | |
317 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 318 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 319 | p.header_length = 12; |
32b46093 | 320 | p.payload_length = 0; |
2639a6fb KH |
321 | break; |
322 | } | |
ed568912 | 323 | |
32b46093 KH |
324 | p.payload = (void *) buffer + p.header_length; |
325 | ||
326 | /* FIXME: What to do about evt_* errors? */ | |
327 | length = (p.header_length + p.payload_length + 3) / 4; | |
328 | status = le32_to_cpu(buffer[length]); | |
329 | ||
330 | p.ack = ((status >> 16) & 0x1f) - 16; | |
331 | p.speed = (status >> 21) & 0x7; | |
332 | p.timestamp = status & 0xffff; | |
333 | p.generation = ohci->request_generation; | |
ed568912 | 334 | |
c781c06d KH |
335 | /* |
336 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
337 | * the new generation number when a bus reset happens (see |
338 | * section 8.4.2.3). This helps us determine when a request | |
339 | * was received and make sure we send the response in the same | |
340 | * generation. We only need this for requests; for responses | |
341 | * we use the unique tlabel for finding the matching | |
c781c06d KH |
342 | * request. |
343 | */ | |
ed568912 | 344 | |
2639a6fb | 345 | if (p.ack + 16 == 0x09) |
32b46093 | 346 | ohci->request_generation = (buffer[2] >> 16) & 0xff; |
ed568912 | 347 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 348 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 349 | else |
2639a6fb | 350 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 351 | |
32b46093 KH |
352 | return buffer + length + 1; |
353 | } | |
ed568912 | 354 | |
32b46093 KH |
355 | static void ar_context_tasklet(unsigned long data) |
356 | { | |
357 | struct ar_context *ctx = (struct ar_context *)data; | |
358 | struct fw_ohci *ohci = ctx->ohci; | |
359 | struct ar_buffer *ab; | |
360 | struct descriptor *d; | |
361 | void *buffer, *end; | |
362 | ||
363 | ab = ctx->current_buffer; | |
364 | d = &ab->descriptor; | |
365 | ||
366 | if (d->res_count == 0) { | |
367 | size_t size, rest, offset; | |
368 | ||
c781c06d KH |
369 | /* |
370 | * This descriptor is finished and we may have a | |
32b46093 | 371 | * packet split across this and the next buffer. We |
c781c06d KH |
372 | * reuse the page for reassembling the split packet. |
373 | */ | |
32b46093 KH |
374 | |
375 | offset = offsetof(struct ar_buffer, data); | |
376 | dma_unmap_single(ohci->card.device, | |
0a9972ba SR |
377 | le32_to_cpu(ab->descriptor.data_address) - offset, |
378 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
32b46093 KH |
379 | |
380 | buffer = ab; | |
381 | ab = ab->next; | |
382 | d = &ab->descriptor; | |
383 | size = buffer + PAGE_SIZE - ctx->pointer; | |
384 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
385 | memmove(buffer, ctx->pointer, size); | |
386 | memcpy(buffer + size, ab->data, rest); | |
387 | ctx->current_buffer = ab; | |
388 | ctx->pointer = (void *) ab->data + rest; | |
389 | end = buffer + size + rest; | |
390 | ||
391 | while (buffer < end) | |
392 | buffer = handle_ar_packet(ctx, buffer); | |
393 | ||
394 | free_page((unsigned long)buffer); | |
395 | ar_context_add_page(ctx); | |
396 | } else { | |
397 | buffer = ctx->pointer; | |
398 | ctx->pointer = end = | |
399 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
400 | ||
401 | while (buffer < end) | |
402 | buffer = handle_ar_packet(ctx, buffer); | |
403 | } | |
ed568912 KH |
404 | } |
405 | ||
406 | static int | |
72e318e0 | 407 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 408 | { |
32b46093 | 409 | struct ar_buffer ab; |
ed568912 | 410 | |
72e318e0 KH |
411 | ctx->regs = regs; |
412 | ctx->ohci = ohci; | |
413 | ctx->last_buffer = &ab; | |
ed568912 KH |
414 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
415 | ||
32b46093 KH |
416 | ar_context_add_page(ctx); |
417 | ar_context_add_page(ctx); | |
418 | ctx->current_buffer = ab.next; | |
419 | ctx->pointer = ctx->current_buffer->data; | |
420 | ||
2aef469a KH |
421 | return 0; |
422 | } | |
423 | ||
424 | static void ar_context_run(struct ar_context *ctx) | |
425 | { | |
426 | struct ar_buffer *ab = ctx->current_buffer; | |
427 | dma_addr_t ab_bus; | |
428 | size_t offset; | |
429 | ||
430 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 431 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
432 | |
433 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 434 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 435 | flush_writes(ctx->ohci); |
ed568912 | 436 | } |
373b2edd | 437 | |
30200739 KH |
438 | static void context_tasklet(unsigned long data) |
439 | { | |
440 | struct context *ctx = (struct context *) data; | |
441 | struct fw_ohci *ohci = ctx->ohci; | |
442 | struct descriptor *d, *last; | |
443 | u32 address; | |
444 | int z; | |
445 | ||
446 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
447 | ctx->buffer_size, DMA_TO_DEVICE); | |
448 | ||
449 | d = ctx->tail_descriptor; | |
450 | last = ctx->tail_descriptor_last; | |
451 | ||
452 | while (last->branch_address != 0) { | |
453 | address = le32_to_cpu(last->branch_address); | |
454 | z = address & 0xf; | |
2d826cc5 | 455 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d); |
30200739 KH |
456 | last = (z == 2) ? d : d + z - 1; |
457 | ||
458 | if (!ctx->callback(ctx, d, last)) | |
459 | break; | |
460 | ||
461 | ctx->tail_descriptor = d; | |
462 | ctx->tail_descriptor_last = last; | |
463 | } | |
464 | } | |
465 | ||
466 | static int | |
467 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
468 | size_t buffer_size, u32 regs, | |
469 | descriptor_callback_t callback) | |
470 | { | |
471 | ctx->ohci = ohci; | |
472 | ctx->regs = regs; | |
473 | ctx->buffer_size = buffer_size; | |
474 | ctx->buffer = kmalloc(buffer_size, GFP_KERNEL); | |
475 | if (ctx->buffer == NULL) | |
476 | return -ENOMEM; | |
477 | ||
478 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); | |
479 | ctx->callback = callback; | |
480 | ||
481 | ctx->buffer_bus = | |
482 | dma_map_single(ohci->card.device, ctx->buffer, | |
483 | buffer_size, DMA_TO_DEVICE); | |
484 | if (dma_mapping_error(ctx->buffer_bus)) { | |
485 | kfree(ctx->buffer); | |
486 | return -ENOMEM; | |
487 | } | |
488 | ||
489 | ctx->head_descriptor = ctx->buffer; | |
490 | ctx->prev_descriptor = ctx->buffer; | |
491 | ctx->tail_descriptor = ctx->buffer; | |
492 | ctx->tail_descriptor_last = ctx->buffer; | |
493 | ||
c781c06d KH |
494 | /* |
495 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 KH |
496 | * branch address and looks like it's been sent. That way we |
497 | * have a descriptor to append DMA programs to. Also, the | |
498 | * ring buffer invariant is that it always has at least one | |
c781c06d KH |
499 | * element so that head == tail means buffer full. |
500 | */ | |
30200739 | 501 | |
2d826cc5 | 502 | memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor)); |
a77754a7 | 503 | ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); |
30200739 KH |
504 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); |
505 | ctx->head_descriptor++; | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
9b32d5f3 | 510 | static void |
30200739 KH |
511 | context_release(struct context *ctx) |
512 | { | |
513 | struct fw_card *card = &ctx->ohci->card; | |
514 | ||
515 | dma_unmap_single(card->device, ctx->buffer_bus, | |
516 | ctx->buffer_size, DMA_TO_DEVICE); | |
517 | kfree(ctx->buffer); | |
518 | } | |
519 | ||
520 | static struct descriptor * | |
521 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
522 | { | |
523 | struct descriptor *d, *tail, *end; | |
524 | ||
525 | d = ctx->head_descriptor; | |
526 | tail = ctx->tail_descriptor; | |
2d826cc5 | 527 | end = ctx->buffer + ctx->buffer_size / sizeof(*d); |
30200739 KH |
528 | |
529 | if (d + z <= tail) { | |
530 | goto has_space; | |
531 | } else if (d > tail && d + z <= end) { | |
532 | goto has_space; | |
533 | } else if (d > tail && ctx->buffer + z <= tail) { | |
534 | d = ctx->buffer; | |
535 | goto has_space; | |
536 | } | |
537 | ||
538 | return NULL; | |
539 | ||
540 | has_space: | |
2d826cc5 KH |
541 | memset(d, 0, z * sizeof(*d)); |
542 | *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d); | |
30200739 KH |
543 | |
544 | return d; | |
545 | } | |
546 | ||
295e3feb | 547 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
548 | { |
549 | struct fw_ohci *ohci = ctx->ohci; | |
550 | ||
a77754a7 | 551 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
30200739 | 552 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); |
a77754a7 KH |
553 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
554 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
555 | flush_writes(ohci); |
556 | } | |
557 | ||
558 | static void context_append(struct context *ctx, | |
559 | struct descriptor *d, int z, int extra) | |
560 | { | |
561 | dma_addr_t d_bus; | |
562 | ||
2d826cc5 | 563 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d); |
30200739 KH |
564 | |
565 | ctx->head_descriptor = d + z + extra; | |
566 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
567 | ctx->prev_descriptor = z == 2 ? d : d + z - 1; | |
568 | ||
569 | dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus, | |
570 | ctx->buffer_size, DMA_TO_DEVICE); | |
571 | ||
a77754a7 | 572 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
573 | flush_writes(ctx->ohci); |
574 | } | |
575 | ||
576 | static void context_stop(struct context *ctx) | |
577 | { | |
578 | u32 reg; | |
b8295668 | 579 | int i; |
30200739 | 580 | |
a77754a7 | 581 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 582 | flush_writes(ctx->ohci); |
30200739 | 583 | |
b8295668 | 584 | for (i = 0; i < 10; i++) { |
a77754a7 | 585 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 KH |
586 | if ((reg & CONTEXT_ACTIVE) == 0) |
587 | break; | |
588 | ||
589 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
b980f5a2 | 590 | mdelay(1); |
b8295668 | 591 | } |
30200739 | 592 | } |
ed568912 | 593 | |
f319b6a0 KH |
594 | struct driver_data { |
595 | struct fw_packet *packet; | |
596 | }; | |
ed568912 | 597 | |
c781c06d KH |
598 | /* |
599 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 600 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
601 | * generation handling and locking around packet queue manipulation. |
602 | */ | |
f319b6a0 KH |
603 | static int |
604 | at_context_queue_packet(struct context *ctx, struct fw_packet *packet) | |
ed568912 | 605 | { |
ed568912 | 606 | struct fw_ohci *ohci = ctx->ohci; |
f319b6a0 KH |
607 | dma_addr_t d_bus, payload_bus; |
608 | struct driver_data *driver_data; | |
609 | struct descriptor *d, *last; | |
610 | __le32 *header; | |
ed568912 | 611 | int z, tcode; |
f319b6a0 | 612 | u32 reg; |
ed568912 | 613 | |
f319b6a0 KH |
614 | d = context_get_descriptors(ctx, 4, &d_bus); |
615 | if (d == NULL) { | |
616 | packet->ack = RCODE_SEND_ERROR; | |
617 | return -1; | |
ed568912 KH |
618 | } |
619 | ||
a77754a7 | 620 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
621 | d[0].res_count = cpu_to_le16(packet->timestamp); |
622 | ||
c781c06d KH |
623 | /* |
624 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
625 | * from the IEEE1394 layout, so shift the fields around |
626 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
627 | * which we need to prepend an extra quadlet. |
628 | */ | |
f319b6a0 KH |
629 | |
630 | header = (__le32 *) &d[1]; | |
ed568912 | 631 | if (packet->header_length > 8) { |
f319b6a0 KH |
632 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
633 | (packet->speed << 16)); | |
634 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
635 | (packet->header[0] & 0xffff0000)); | |
636 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
637 | |
638 | tcode = (packet->header[0] >> 4) & 0x0f; | |
639 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 640 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 641 | else |
f319b6a0 KH |
642 | header[3] = (__force __le32) packet->header[3]; |
643 | ||
644 | d[0].req_count = cpu_to_le16(packet->header_length); | |
ed568912 | 645 | } else { |
f319b6a0 KH |
646 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
647 | (packet->speed << 16)); | |
648 | header[1] = cpu_to_le32(packet->header[0]); | |
649 | header[2] = cpu_to_le32(packet->header[1]); | |
650 | d[0].req_count = cpu_to_le16(12); | |
ed568912 KH |
651 | } |
652 | ||
f319b6a0 KH |
653 | driver_data = (struct driver_data *) &d[3]; |
654 | driver_data->packet = packet; | |
20d11673 | 655 | packet->driver_data = driver_data; |
f319b6a0 KH |
656 | |
657 | if (packet->payload_length > 0) { | |
658 | payload_bus = | |
659 | dma_map_single(ohci->card.device, packet->payload, | |
660 | packet->payload_length, DMA_TO_DEVICE); | |
661 | if (dma_mapping_error(payload_bus)) { | |
662 | packet->ack = RCODE_SEND_ERROR; | |
663 | return -1; | |
664 | } | |
665 | ||
666 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
667 | d[2].data_address = cpu_to_le32(payload_bus); | |
668 | last = &d[2]; | |
669 | z = 3; | |
ed568912 | 670 | } else { |
f319b6a0 KH |
671 | last = &d[0]; |
672 | z = 2; | |
ed568912 | 673 | } |
ed568912 | 674 | |
a77754a7 KH |
675 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
676 | DESCRIPTOR_IRQ_ALWAYS | | |
677 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 678 | |
f319b6a0 KH |
679 | /* FIXME: Document how the locking works. */ |
680 | if (ohci->generation != packet->generation) { | |
681 | packet->ack = RCODE_GENERATION; | |
682 | return -1; | |
683 | } | |
684 | ||
685 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 686 | |
f319b6a0 | 687 | /* If the context isn't already running, start it up. */ |
a77754a7 | 688 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 689 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
690 | context_run(ctx, 0); |
691 | ||
692 | return 0; | |
ed568912 KH |
693 | } |
694 | ||
f319b6a0 KH |
695 | static int handle_at_packet(struct context *context, |
696 | struct descriptor *d, | |
697 | struct descriptor *last) | |
ed568912 | 698 | { |
f319b6a0 | 699 | struct driver_data *driver_data; |
ed568912 | 700 | struct fw_packet *packet; |
f319b6a0 KH |
701 | struct fw_ohci *ohci = context->ohci; |
702 | dma_addr_t payload_bus; | |
ed568912 KH |
703 | int evt; |
704 | ||
f319b6a0 KH |
705 | if (last->transfer_status == 0) |
706 | /* This descriptor isn't done yet, stop iteration. */ | |
707 | return 0; | |
ed568912 | 708 | |
f319b6a0 KH |
709 | driver_data = (struct driver_data *) &d[3]; |
710 | packet = driver_data->packet; | |
711 | if (packet == NULL) | |
712 | /* This packet was cancelled, just continue. */ | |
713 | return 1; | |
730c32f5 | 714 | |
f319b6a0 KH |
715 | payload_bus = le32_to_cpu(last->data_address); |
716 | if (payload_bus != 0) | |
717 | dma_unmap_single(ohci->card.device, payload_bus, | |
ed568912 | 718 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 719 | |
f319b6a0 KH |
720 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
721 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 722 | |
f319b6a0 KH |
723 | switch (evt) { |
724 | case OHCI1394_evt_timeout: | |
725 | /* Async response transmit timed out. */ | |
726 | packet->ack = RCODE_CANCELLED; | |
727 | break; | |
ed568912 | 728 | |
f319b6a0 | 729 | case OHCI1394_evt_flushed: |
c781c06d KH |
730 | /* |
731 | * The packet was flushed should give same error as | |
732 | * when we try to use a stale generation count. | |
733 | */ | |
f319b6a0 KH |
734 | packet->ack = RCODE_GENERATION; |
735 | break; | |
ed568912 | 736 | |
f319b6a0 | 737 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
738 | /* |
739 | * Using a valid (current) generation count, but the | |
740 | * node is not on the bus or not sending acks. | |
741 | */ | |
f319b6a0 KH |
742 | packet->ack = RCODE_NO_ACK; |
743 | break; | |
ed568912 | 744 | |
f319b6a0 KH |
745 | case ACK_COMPLETE + 0x10: |
746 | case ACK_PENDING + 0x10: | |
747 | case ACK_BUSY_X + 0x10: | |
748 | case ACK_BUSY_A + 0x10: | |
749 | case ACK_BUSY_B + 0x10: | |
750 | case ACK_DATA_ERROR + 0x10: | |
751 | case ACK_TYPE_ERROR + 0x10: | |
752 | packet->ack = evt - 0x10; | |
753 | break; | |
ed568912 | 754 | |
f319b6a0 KH |
755 | default: |
756 | packet->ack = RCODE_SEND_ERROR; | |
757 | break; | |
758 | } | |
ed568912 | 759 | |
f319b6a0 | 760 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 761 | |
f319b6a0 | 762 | return 1; |
ed568912 KH |
763 | } |
764 | ||
a77754a7 KH |
765 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
766 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
767 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
768 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
769 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb KH |
770 | |
771 | static void | |
772 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
773 | { | |
774 | struct fw_packet response; | |
775 | int tcode, length, i; | |
776 | ||
a77754a7 | 777 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 778 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 779 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
780 | else |
781 | length = 4; | |
782 | ||
783 | i = csr - CSR_CONFIG_ROM; | |
784 | if (i + length > CONFIG_ROM_SIZE) { | |
785 | fw_fill_response(&response, packet->header, | |
786 | RCODE_ADDRESS_ERROR, NULL, 0); | |
787 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
788 | fw_fill_response(&response, packet->header, | |
789 | RCODE_TYPE_ERROR, NULL, 0); | |
790 | } else { | |
791 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
792 | (void *) ohci->config_rom + i, length); | |
793 | } | |
794 | ||
795 | fw_core_handle_response(&ohci->card, &response); | |
796 | } | |
797 | ||
798 | static void | |
799 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
800 | { | |
801 | struct fw_packet response; | |
802 | int tcode, length, ext_tcode, sel; | |
803 | __be32 *payload, lock_old; | |
804 | u32 lock_arg, lock_data; | |
805 | ||
a77754a7 KH |
806 | tcode = HEADER_GET_TCODE(packet->header[0]); |
807 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 808 | payload = packet->payload; |
a77754a7 | 809 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
810 | |
811 | if (tcode == TCODE_LOCK_REQUEST && | |
812 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
813 | lock_arg = be32_to_cpu(payload[0]); | |
814 | lock_data = be32_to_cpu(payload[1]); | |
815 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
816 | lock_arg = 0; | |
817 | lock_data = 0; | |
818 | } else { | |
819 | fw_fill_response(&response, packet->header, | |
820 | RCODE_TYPE_ERROR, NULL, 0); | |
821 | goto out; | |
822 | } | |
823 | ||
824 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
825 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
826 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
827 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
828 | ||
829 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
830 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
831 | else | |
832 | fw_notify("swap not done yet\n"); | |
833 | ||
834 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 835 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
836 | out: |
837 | fw_core_handle_response(&ohci->card, &response); | |
838 | } | |
839 | ||
840 | static void | |
f319b6a0 | 841 | handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
842 | { |
843 | u64 offset; | |
844 | u32 csr; | |
845 | ||
473d28c7 KH |
846 | if (ctx == &ctx->ohci->at_request_ctx) { |
847 | packet->ack = ACK_PENDING; | |
848 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
849 | } | |
93c4cceb KH |
850 | |
851 | offset = | |
852 | ((unsigned long long) | |
a77754a7 | 853 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
854 | packet->header[2]; |
855 | csr = offset - CSR_REGISTER_BASE; | |
856 | ||
857 | /* Handle config rom reads. */ | |
858 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
859 | handle_local_rom(ctx->ohci, packet, csr); | |
860 | else switch (csr) { | |
861 | case CSR_BUS_MANAGER_ID: | |
862 | case CSR_BANDWIDTH_AVAILABLE: | |
863 | case CSR_CHANNELS_AVAILABLE_HI: | |
864 | case CSR_CHANNELS_AVAILABLE_LO: | |
865 | handle_local_lock(ctx->ohci, packet, csr); | |
866 | break; | |
867 | default: | |
868 | if (ctx == &ctx->ohci->at_request_ctx) | |
869 | fw_core_handle_request(&ctx->ohci->card, packet); | |
870 | else | |
871 | fw_core_handle_response(&ctx->ohci->card, packet); | |
872 | break; | |
873 | } | |
473d28c7 KH |
874 | |
875 | if (ctx == &ctx->ohci->at_response_ctx) { | |
876 | packet->ack = ACK_COMPLETE; | |
877 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
878 | } | |
93c4cceb | 879 | } |
e636fe25 | 880 | |
ed568912 | 881 | static void |
f319b6a0 | 882 | at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 883 | { |
ed568912 | 884 | unsigned long flags; |
f319b6a0 | 885 | int retval; |
ed568912 KH |
886 | |
887 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
888 | ||
a77754a7 | 889 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 890 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
891 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
892 | handle_local_request(ctx, packet); | |
893 | return; | |
e636fe25 | 894 | } |
ed568912 | 895 | |
f319b6a0 | 896 | retval = at_context_queue_packet(ctx, packet); |
ed568912 KH |
897 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
898 | ||
f319b6a0 KH |
899 | if (retval < 0) |
900 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
901 | ||
ed568912 KH |
902 | } |
903 | ||
904 | static void bus_reset_tasklet(unsigned long data) | |
905 | { | |
906 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 907 | int self_id_count, i, j, reg; |
ed568912 KH |
908 | int generation, new_generation; |
909 | unsigned long flags; | |
4eaff7d6 SR |
910 | void *free_rom = NULL; |
911 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
912 | |
913 | reg = reg_read(ohci, OHCI1394_NodeID); | |
914 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
915 | fw_error("node ID not valid, new bus reset in progress\n"); | |
916 | return; | |
917 | } | |
e636fe25 | 918 | ohci->node_id = reg & 0xffff; |
ed568912 | 919 | |
c781c06d KH |
920 | /* |
921 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
922 | * bytes in the self ID receive buffer. Since we also receive |
923 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
924 | * bit extra to get the actual number of self IDs. |
925 | */ | |
ed568912 KH |
926 | |
927 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
928 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
929 | ||
930 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
931 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
932 | fw_error("inconsistent self IDs\n"); | |
933 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
934 | } | |
935 | ||
c781c06d KH |
936 | /* |
937 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
938 | * problem we face is that a new bus reset can start while we |
939 | * read out the self IDs from the DMA buffer. If this happens, | |
940 | * the DMA buffer will be overwritten with new self IDs and we | |
941 | * will read out inconsistent data. The OHCI specification | |
942 | * (section 11.2) recommends a technique similar to | |
943 | * linux/seqlock.h, where we remember the generation of the | |
944 | * self IDs in the buffer before reading them out and compare | |
945 | * it to the current generation after reading them out. If | |
946 | * the two generations match we know we have a consistent set | |
c781c06d KH |
947 | * of self IDs. |
948 | */ | |
ed568912 KH |
949 | |
950 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
951 | if (new_generation != generation) { | |
952 | fw_notify("recursive bus reset detected, " | |
953 | "discarding self ids\n"); | |
954 | return; | |
955 | } | |
956 | ||
957 | /* FIXME: Document how the locking works. */ | |
958 | spin_lock_irqsave(&ohci->lock, flags); | |
959 | ||
960 | ohci->generation = generation; | |
f319b6a0 KH |
961 | context_stop(&ohci->at_request_ctx); |
962 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
963 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
964 | ||
c781c06d KH |
965 | /* |
966 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
967 | * have to do it under the spinlock also. If a new config rom |
968 | * was set up before this reset, the old one is now no longer | |
969 | * in use and we can free it. Update the config rom pointers | |
970 | * to point to the current config rom and clear the | |
c781c06d KH |
971 | * next_config_rom pointer so a new udpate can take place. |
972 | */ | |
ed568912 KH |
973 | |
974 | if (ohci->next_config_rom != NULL) { | |
4eaff7d6 SR |
975 | free_rom = ohci->config_rom; |
976 | free_rom_bus = ohci->config_rom_bus; | |
ed568912 KH |
977 | ohci->config_rom = ohci->next_config_rom; |
978 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
979 | ohci->next_config_rom = NULL; | |
980 | ||
c781c06d KH |
981 | /* |
982 | * Restore config_rom image and manually update | |
ed568912 KH |
983 | * config_rom registers. Writing the header quadlet |
984 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
985 | * do that last. |
986 | */ | |
ed568912 KH |
987 | reg_write(ohci, OHCI1394_BusOptions, |
988 | be32_to_cpu(ohci->config_rom[2])); | |
989 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
990 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
991 | } | |
992 | ||
993 | spin_unlock_irqrestore(&ohci->lock, flags); | |
994 | ||
4eaff7d6 SR |
995 | if (free_rom) |
996 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
997 | free_rom, free_rom_bus); | |
998 | ||
e636fe25 | 999 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1000 | self_id_count, ohci->self_id_buffer); |
1001 | } | |
1002 | ||
1003 | static irqreturn_t irq_handler(int irq, void *data) | |
1004 | { | |
1005 | struct fw_ohci *ohci = data; | |
d60d7f1d | 1006 | u32 event, iso_event, cycle_time; |
ed568912 KH |
1007 | int i; |
1008 | ||
1009 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1010 | ||
a515958d | 1011 | if (!event || !~event) |
ed568912 KH |
1012 | return IRQ_NONE; |
1013 | ||
1014 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
1015 | ||
1016 | if (event & OHCI1394_selfIDComplete) | |
1017 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1018 | ||
1019 | if (event & OHCI1394_RQPkt) | |
1020 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1021 | ||
1022 | if (event & OHCI1394_RSPkt) | |
1023 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1024 | ||
1025 | if (event & OHCI1394_reqTxComplete) | |
1026 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1027 | ||
1028 | if (event & OHCI1394_respTxComplete) | |
1029 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1030 | ||
c889475f | 1031 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1032 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1033 | ||
1034 | while (iso_event) { | |
1035 | i = ffs(iso_event) - 1; | |
30200739 | 1036 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1037 | iso_event &= ~(1 << i); |
1038 | } | |
1039 | ||
c889475f | 1040 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1041 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1042 | ||
1043 | while (iso_event) { | |
1044 | i = ffs(iso_event) - 1; | |
30200739 | 1045 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1046 | iso_event &= ~(1 << i); |
1047 | } | |
1048 | ||
d60d7f1d KH |
1049 | if (event & OHCI1394_cycle64Seconds) { |
1050 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1051 | if ((cycle_time & 0x80000000) == 0) | |
1052 | ohci->bus_seconds++; | |
1053 | } | |
1054 | ||
ed568912 KH |
1055 | return IRQ_HANDLED; |
1056 | } | |
1057 | ||
2aef469a KH |
1058 | static int software_reset(struct fw_ohci *ohci) |
1059 | { | |
1060 | int i; | |
1061 | ||
1062 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1063 | ||
1064 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1065 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1066 | OHCI1394_HCControl_softReset) == 0) | |
1067 | return 0; | |
1068 | msleep(1); | |
1069 | } | |
1070 | ||
1071 | return -EBUSY; | |
1072 | } | |
1073 | ||
ed568912 KH |
1074 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) |
1075 | { | |
1076 | struct fw_ohci *ohci = fw_ohci(card); | |
1077 | struct pci_dev *dev = to_pci_dev(card->device); | |
1078 | ||
2aef469a KH |
1079 | if (software_reset(ohci)) { |
1080 | fw_error("Failed to reset ohci card.\n"); | |
1081 | return -EBUSY; | |
1082 | } | |
1083 | ||
1084 | /* | |
1085 | * Now enable LPS, which we need in order to start accessing | |
1086 | * most of the registers. In fact, on some cards (ALI M5251), | |
1087 | * accessing registers in the SClk domain without LPS enabled | |
1088 | * will lock up the machine. Wait 50msec to make sure we have | |
1089 | * full link enabled. | |
1090 | */ | |
1091 | reg_write(ohci, OHCI1394_HCControlSet, | |
1092 | OHCI1394_HCControl_LPS | | |
1093 | OHCI1394_HCControl_postedWriteEnable); | |
1094 | flush_writes(ohci); | |
1095 | msleep(50); | |
1096 | ||
1097 | reg_write(ohci, OHCI1394_HCControlClear, | |
1098 | OHCI1394_HCControl_noByteSwapData); | |
1099 | ||
1100 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1101 | OHCI1394_LinkControl_rcvSelfID | | |
1102 | OHCI1394_LinkControl_cycleTimerEnable | | |
1103 | OHCI1394_LinkControl_cycleMaster); | |
1104 | ||
1105 | reg_write(ohci, OHCI1394_ATRetries, | |
1106 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1107 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1108 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1109 | ||
1110 | ar_context_run(&ohci->ar_request_ctx); | |
1111 | ar_context_run(&ohci->ar_response_ctx); | |
1112 | ||
1113 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1114 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1115 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1116 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1117 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1118 | OHCI1394_selfIDComplete | | |
1119 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1120 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1121 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1122 | OHCI1394_masterIntEnable | | |
1123 | OHCI1394_cycle64Seconds); | |
1124 | ||
1125 | /* Activate link_on bit and contender bit in our self ID packets.*/ | |
1126 | if (ohci_update_phy_reg(card, 4, 0, | |
1127 | PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) | |
1128 | return -EIO; | |
1129 | ||
c781c06d KH |
1130 | /* |
1131 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1132 | * update mechanism described below in ohci_set_config_rom() |
1133 | * is not active. We have to update ConfigRomHeader and | |
1134 | * BusOptions manually, and the write to ConfigROMmap takes | |
1135 | * effect immediately. We tie this to the enabling of the | |
1136 | * link, so we have a valid config rom before enabling - the | |
1137 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1138 | * values before enabling. | |
1139 | * | |
1140 | * However, when the ConfigROMmap is written, some controllers | |
1141 | * always read back quadlets 0 and 2 from the config rom to | |
1142 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1143 | * They shouldn't do that in this initial case where the link | |
1144 | * isn't enabled. This means we have to use the same | |
1145 | * workaround here, setting the bus header to 0 and then write | |
1146 | * the right values in the bus reset tasklet. | |
1147 | */ | |
1148 | ||
1149 | ohci->next_config_rom = | |
1150 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1151 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
1152 | if (ohci->next_config_rom == NULL) | |
1153 | return -ENOMEM; | |
1154 | ||
1155 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1156 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1157 | ||
1158 | ohci->next_header = config_rom[0]; | |
1159 | ohci->next_config_rom[0] = 0; | |
1160 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
1161 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
1162 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
1163 | ||
1164 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1165 | ||
1166 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1167 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1168 | fw_error("Failed to allocate shared interrupt %d.\n", |
1169 | dev->irq); | |
1170 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1171 | ohci->config_rom, ohci->config_rom_bus); | |
1172 | return -EIO; | |
1173 | } | |
1174 | ||
1175 | reg_write(ohci, OHCI1394_HCControlSet, | |
1176 | OHCI1394_HCControl_linkEnable | | |
1177 | OHCI1394_HCControl_BIBimageValid); | |
1178 | flush_writes(ohci); | |
1179 | ||
c781c06d KH |
1180 | /* |
1181 | * We are ready to go, initiate bus reset to finish the | |
1182 | * initialization. | |
1183 | */ | |
ed568912 KH |
1184 | |
1185 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static int | |
1191 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1192 | { | |
1193 | struct fw_ohci *ohci; | |
1194 | unsigned long flags; | |
4eaff7d6 | 1195 | int retval = -EBUSY; |
ed568912 KH |
1196 | __be32 *next_config_rom; |
1197 | dma_addr_t next_config_rom_bus; | |
1198 | ||
1199 | ohci = fw_ohci(card); | |
1200 | ||
c781c06d KH |
1201 | /* |
1202 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1203 | * mechanism is a bit tricky, but easy enough to use. See |
1204 | * section 5.5.6 in the OHCI specification. | |
1205 | * | |
1206 | * The OHCI controller caches the new config rom address in a | |
1207 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1208 | * for the changes to take place. When the bus reset is | |
1209 | * detected, the controller loads the new values for the | |
1210 | * ConfigRomHeader and BusOptions registers from the specified | |
1211 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1212 | * shadow register. All automatically and atomically. | |
1213 | * | |
1214 | * Now, there's a twist to this story. The automatic load of | |
1215 | * ConfigRomHeader and BusOptions doesn't honor the | |
1216 | * noByteSwapData bit, so with a be32 config rom, the | |
1217 | * controller will load be32 values in to these registers | |
1218 | * during the atomic update, even on litte endian | |
1219 | * architectures. The workaround we use is to put a 0 in the | |
1220 | * header quadlet; 0 is endian agnostic and means that the | |
1221 | * config rom isn't ready yet. In the bus reset tasklet we | |
1222 | * then set up the real values for the two registers. | |
1223 | * | |
1224 | * We use ohci->lock to avoid racing with the code that sets | |
1225 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1226 | */ | |
1227 | ||
1228 | next_config_rom = | |
1229 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1230 | &next_config_rom_bus, GFP_KERNEL); | |
1231 | if (next_config_rom == NULL) | |
1232 | return -ENOMEM; | |
1233 | ||
1234 | spin_lock_irqsave(&ohci->lock, flags); | |
1235 | ||
1236 | if (ohci->next_config_rom == NULL) { | |
1237 | ohci->next_config_rom = next_config_rom; | |
1238 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1239 | ||
1240 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1241 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1242 | length * 4); | |
1243 | ||
1244 | ohci->next_header = config_rom[0]; | |
1245 | ohci->next_config_rom[0] = 0; | |
1246 | ||
1247 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1248 | ohci->next_config_rom_bus); | |
4eaff7d6 | 1249 | retval = 0; |
ed568912 KH |
1250 | } |
1251 | ||
1252 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1253 | ||
c781c06d KH |
1254 | /* |
1255 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1256 | * effect. We clean up the old config rom memory and DMA |
1257 | * mappings in the bus reset tasklet, since the OHCI | |
1258 | * controller could need to access it before the bus reset | |
c781c06d KH |
1259 | * takes effect. |
1260 | */ | |
ed568912 KH |
1261 | if (retval == 0) |
1262 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
4eaff7d6 SR |
1263 | else |
1264 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1265 | next_config_rom, next_config_rom_bus); | |
ed568912 KH |
1266 | |
1267 | return retval; | |
1268 | } | |
1269 | ||
1270 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1271 | { | |
1272 | struct fw_ohci *ohci = fw_ohci(card); | |
1273 | ||
1274 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1275 | } | |
1276 | ||
1277 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1278 | { | |
1279 | struct fw_ohci *ohci = fw_ohci(card); | |
1280 | ||
1281 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1282 | } | |
1283 | ||
730c32f5 KH |
1284 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1285 | { | |
1286 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1287 | struct context *ctx = &ohci->at_request_ctx; |
1288 | struct driver_data *driver_data = packet->driver_data; | |
1289 | int retval = -ENOENT; | |
730c32f5 | 1290 | |
f319b6a0 | 1291 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1292 | |
f319b6a0 KH |
1293 | if (packet->ack != 0) |
1294 | goto out; | |
730c32f5 | 1295 | |
f319b6a0 KH |
1296 | driver_data->packet = NULL; |
1297 | packet->ack = RCODE_CANCELLED; | |
1298 | packet->callback(packet, &ohci->card, packet->ack); | |
1299 | retval = 0; | |
730c32f5 | 1300 | |
f319b6a0 KH |
1301 | out: |
1302 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1303 | |
f319b6a0 | 1304 | return retval; |
730c32f5 KH |
1305 | } |
1306 | ||
ed568912 KH |
1307 | static int |
1308 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1309 | { | |
1310 | struct fw_ohci *ohci = fw_ohci(card); | |
1311 | unsigned long flags; | |
907293d7 | 1312 | int n, retval = 0; |
ed568912 | 1313 | |
c781c06d KH |
1314 | /* |
1315 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1316 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1317 | */ | |
ed568912 KH |
1318 | |
1319 | spin_lock_irqsave(&ohci->lock, flags); | |
1320 | ||
1321 | if (ohci->generation != generation) { | |
1322 | retval = -ESTALE; | |
1323 | goto out; | |
1324 | } | |
1325 | ||
c781c06d KH |
1326 | /* |
1327 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1328 | * enabled for _all_ nodes on remote buses. | |
1329 | */ | |
907293d7 SR |
1330 | |
1331 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1332 | if (n < 32) | |
1333 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1334 | else | |
1335 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1336 | ||
ed568912 | 1337 | flush_writes(ohci); |
ed568912 | 1338 | out: |
6cad95fe | 1339 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1340 | return retval; |
1341 | } | |
373b2edd | 1342 | |
d60d7f1d KH |
1343 | static u64 |
1344 | ohci_get_bus_time(struct fw_card *card) | |
1345 | { | |
1346 | struct fw_ohci *ohci = fw_ohci(card); | |
1347 | u32 cycle_time; | |
1348 | u64 bus_time; | |
1349 | ||
1350 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1351 | bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time; | |
1352 | ||
1353 | return bus_time; | |
1354 | } | |
1355 | ||
d2746dc1 KH |
1356 | static int handle_ir_dualbuffer_packet(struct context *context, |
1357 | struct descriptor *d, | |
1358 | struct descriptor *last) | |
ed568912 | 1359 | { |
295e3feb KH |
1360 | struct iso_context *ctx = |
1361 | container_of(context, struct iso_context, context); | |
1362 | struct db_descriptor *db = (struct db_descriptor *) d; | |
c70dc788 | 1363 | __le32 *ir_header; |
9b32d5f3 | 1364 | size_t header_length; |
c70dc788 KH |
1365 | void *p, *end; |
1366 | int i; | |
d2746dc1 | 1367 | |
295e3feb KH |
1368 | if (db->first_res_count > 0 && db->second_res_count > 0) |
1369 | /* This descriptor isn't done yet, stop iteration. */ | |
1370 | return 0; | |
1371 | ||
c70dc788 KH |
1372 | header_length = le16_to_cpu(db->first_req_count) - |
1373 | le16_to_cpu(db->first_res_count); | |
1374 | ||
1375 | i = ctx->header_length; | |
1376 | p = db + 1; | |
1377 | end = p + header_length; | |
1378 | while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { | |
c781c06d KH |
1379 | /* |
1380 | * The iso header is byteswapped to little endian by | |
15536221 KH |
1381 | * the controller, but the remaining header quadlets |
1382 | * are big endian. We want to present all the headers | |
1383 | * as big endian, so we have to swap the first | |
c781c06d KH |
1384 | * quadlet. |
1385 | */ | |
15536221 KH |
1386 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); |
1387 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
c70dc788 KH |
1388 | i += ctx->base.header_size; |
1389 | p += ctx->base.header_size + 4; | |
1390 | } | |
1391 | ||
1392 | ctx->header_length = i; | |
9b32d5f3 | 1393 | |
a77754a7 | 1394 | if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788 KH |
1395 | ir_header = (__le32 *) (db + 1); |
1396 | ctx->base.callback(&ctx->base, | |
1397 | le32_to_cpu(ir_header[0]) & 0xffff, | |
9b32d5f3 | 1398 | ctx->header_length, ctx->header, |
295e3feb | 1399 | ctx->base.callback_data); |
9b32d5f3 KH |
1400 | ctx->header_length = 0; |
1401 | } | |
ed568912 | 1402 | |
295e3feb | 1403 | return 1; |
ed568912 KH |
1404 | } |
1405 | ||
30200739 KH |
1406 | static int handle_it_packet(struct context *context, |
1407 | struct descriptor *d, | |
1408 | struct descriptor *last) | |
ed568912 | 1409 | { |
30200739 KH |
1410 | struct iso_context *ctx = |
1411 | container_of(context, struct iso_context, context); | |
373b2edd | 1412 | |
30200739 KH |
1413 | if (last->transfer_status == 0) |
1414 | /* This descriptor isn't done yet, stop iteration. */ | |
1415 | return 0; | |
1416 | ||
a77754a7 | 1417 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f3 KH |
1418 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1419 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1420 | |
1421 | return 1; | |
ed568912 KH |
1422 | } |
1423 | ||
30200739 | 1424 | static struct fw_iso_context * |
eb0306ea | 1425 | ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed568912 KH |
1426 | { |
1427 | struct fw_ohci *ohci = fw_ohci(card); | |
1428 | struct iso_context *ctx, *list; | |
30200739 | 1429 | descriptor_callback_t callback; |
295e3feb | 1430 | u32 *mask, regs; |
ed568912 | 1431 | unsigned long flags; |
9b32d5f3 | 1432 | int index, retval = -ENOMEM; |
ed568912 KH |
1433 | |
1434 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1435 | mask = &ohci->it_context_mask; | |
1436 | list = ohci->it_context_list; | |
30200739 | 1437 | callback = handle_it_packet; |
ed568912 | 1438 | } else { |
373b2edd SR |
1439 | mask = &ohci->ir_context_mask; |
1440 | list = ohci->ir_context_list; | |
c70dc788 | 1441 | callback = handle_ir_dualbuffer_packet; |
ed568912 KH |
1442 | } |
1443 | ||
c70dc788 | 1444 | /* FIXME: We need a fallback for pre 1.1 OHCI. */ |
e364cf4e KH |
1445 | if (callback == handle_ir_dualbuffer_packet && |
1446 | ohci->version < OHCI_VERSION_1_1) | |
1447 | return ERR_PTR(-EINVAL); | |
1448 | ||
ed568912 KH |
1449 | spin_lock_irqsave(&ohci->lock, flags); |
1450 | index = ffs(*mask) - 1; | |
1451 | if (index >= 0) | |
1452 | *mask &= ~(1 << index); | |
1453 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1454 | ||
1455 | if (index < 0) | |
1456 | return ERR_PTR(-EBUSY); | |
1457 | ||
373b2edd SR |
1458 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1459 | regs = OHCI1394_IsoXmitContextBase(index); | |
1460 | else | |
1461 | regs = OHCI1394_IsoRcvContextBase(index); | |
1462 | ||
ed568912 | 1463 | ctx = &list[index]; |
2d826cc5 | 1464 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
1465 | ctx->header_length = 0; |
1466 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1467 | if (ctx->header == NULL) | |
1468 | goto out; | |
1469 | ||
30200739 | 1470 | retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE, |
295e3feb | 1471 | regs, callback); |
9b32d5f3 KH |
1472 | if (retval < 0) |
1473 | goto out_with_header; | |
ed568912 KH |
1474 | |
1475 | return &ctx->base; | |
9b32d5f3 KH |
1476 | |
1477 | out_with_header: | |
1478 | free_page((unsigned long)ctx->header); | |
1479 | out: | |
1480 | spin_lock_irqsave(&ohci->lock, flags); | |
1481 | *mask |= 1 << index; | |
1482 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1483 | ||
1484 | return ERR_PTR(retval); | |
ed568912 KH |
1485 | } |
1486 | ||
eb0306ea KH |
1487 | static int ohci_start_iso(struct fw_iso_context *base, |
1488 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 1489 | { |
373b2edd | 1490 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1491 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 1492 | u32 control, match; |
ed568912 KH |
1493 | int index; |
1494 | ||
295e3feb KH |
1495 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1496 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
1497 | match = 0; |
1498 | if (cycle >= 0) | |
1499 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 1500 | (cycle & 0x7fff) << 16; |
21efb3cf | 1501 | |
295e3feb KH |
1502 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
1503 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 1504 | context_run(&ctx->context, match); |
295e3feb KH |
1505 | } else { |
1506 | index = ctx - ohci->ir_context_list; | |
8a2f7d93 KH |
1507 | control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER; |
1508 | match = (tags << 28) | (sync << 8) | ctx->base.channel; | |
1509 | if (cycle >= 0) { | |
1510 | match |= (cycle & 0x07fff) << 12; | |
1511 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
1512 | } | |
ed568912 | 1513 | |
295e3feb KH |
1514 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1515 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 1516 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 1517 | context_run(&ctx->context, control); |
295e3feb | 1518 | } |
ed568912 KH |
1519 | |
1520 | return 0; | |
1521 | } | |
1522 | ||
b8295668 KH |
1523 | static int ohci_stop_iso(struct fw_iso_context *base) |
1524 | { | |
1525 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1526 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
1527 | int index; |
1528 | ||
1529 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1530 | index = ctx - ohci->it_context_list; | |
1531 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1532 | } else { | |
1533 | index = ctx - ohci->ir_context_list; | |
1534 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1535 | } | |
1536 | flush_writes(ohci); | |
1537 | context_stop(&ctx->context); | |
1538 | ||
1539 | return 0; | |
1540 | } | |
1541 | ||
ed568912 KH |
1542 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1543 | { | |
1544 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1545 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1546 | unsigned long flags; |
1547 | int index; | |
1548 | ||
b8295668 KH |
1549 | ohci_stop_iso(base); |
1550 | context_release(&ctx->context); | |
9b32d5f3 | 1551 | free_page((unsigned long)ctx->header); |
b8295668 | 1552 | |
ed568912 KH |
1553 | spin_lock_irqsave(&ohci->lock, flags); |
1554 | ||
1555 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1556 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
1557 | ohci->it_context_mask |= 1 << index; |
1558 | } else { | |
1559 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
1560 | ohci->ir_context_mask |= 1 << index; |
1561 | } | |
ed568912 KH |
1562 | |
1563 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1564 | } | |
1565 | ||
1566 | static int | |
295e3feb KH |
1567 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1568 | struct fw_iso_packet *packet, | |
1569 | struct fw_iso_buffer *buffer, | |
1570 | unsigned long payload) | |
ed568912 | 1571 | { |
373b2edd | 1572 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1573 | struct descriptor *d, *last, *pd; |
ed568912 KH |
1574 | struct fw_iso_packet *p; |
1575 | __le32 *header; | |
9aad8125 | 1576 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1577 | u32 z, header_z, payload_z, irq; |
1578 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1579 | int page, end_page, i, length, offset; |
ed568912 | 1580 | |
c781c06d KH |
1581 | /* |
1582 | * FIXME: Cycle lost behavior should be configurable: lose | |
1583 | * packet, retransmit or terminate.. | |
1584 | */ | |
ed568912 KH |
1585 | |
1586 | p = packet; | |
9aad8125 | 1587 | payload_index = payload; |
ed568912 KH |
1588 | |
1589 | if (p->skip) | |
1590 | z = 1; | |
1591 | else | |
1592 | z = 2; | |
1593 | if (p->header_length > 0) | |
1594 | z++; | |
1595 | ||
1596 | /* Determine the first page the payload isn't contained in. */ | |
1597 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1598 | if (p->payload_length > 0) | |
1599 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1600 | else | |
1601 | payload_z = 0; | |
1602 | ||
1603 | z += payload_z; | |
1604 | ||
1605 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 1606 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 1607 | |
30200739 KH |
1608 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
1609 | if (d == NULL) | |
1610 | return -ENOMEM; | |
ed568912 KH |
1611 | |
1612 | if (!p->skip) { | |
a77754a7 | 1613 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 KH |
1614 | d[0].req_count = cpu_to_le16(8); |
1615 | ||
1616 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
1617 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
1618 | IT_HEADER_TAG(p->tag) | | |
1619 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
1620 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
1621 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 1622 | header[1] = |
a77754a7 | 1623 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
1624 | p->payload_length)); |
1625 | } | |
1626 | ||
1627 | if (p->header_length > 0) { | |
1628 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 1629 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
1630 | memcpy(&d[z], p->header, p->header_length); |
1631 | } | |
1632 | ||
1633 | pd = d + z - payload_z; | |
1634 | payload_end_index = payload_index + p->payload_length; | |
1635 | for (i = 0; i < payload_z; i++) { | |
1636 | page = payload_index >> PAGE_SHIFT; | |
1637 | offset = payload_index & ~PAGE_MASK; | |
1638 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1639 | length = | |
1640 | min(next_page_index, payload_end_index) - payload_index; | |
1641 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
1642 | |
1643 | page_bus = page_private(buffer->pages[page]); | |
1644 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
1645 | |
1646 | payload_index += length; | |
1647 | } | |
1648 | ||
ed568912 | 1649 | if (p->interrupt) |
a77754a7 | 1650 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 1651 | else |
a77754a7 | 1652 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 1653 | |
30200739 | 1654 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
1655 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1656 | DESCRIPTOR_STATUS | | |
1657 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 1658 | irq); |
ed568912 | 1659 | |
30200739 | 1660 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
1661 | |
1662 | return 0; | |
1663 | } | |
373b2edd | 1664 | |
295e3feb | 1665 | static int |
d2746dc1 KH |
1666 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
1667 | struct fw_iso_packet *packet, | |
1668 | struct fw_iso_buffer *buffer, | |
1669 | unsigned long payload) | |
295e3feb KH |
1670 | { |
1671 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1672 | struct db_descriptor *db = NULL; | |
1673 | struct descriptor *d; | |
1674 | struct fw_iso_packet *p; | |
1675 | dma_addr_t d_bus, page_bus; | |
1676 | u32 z, header_z, length, rest; | |
c70dc788 | 1677 | int page, offset, packet_count, header_size; |
373b2edd | 1678 | |
c781c06d KH |
1679 | /* |
1680 | * FIXME: Cycle lost behavior should be configurable: lose | |
1681 | * packet, retransmit or terminate.. | |
1682 | */ | |
295e3feb | 1683 | |
c70dc788 KH |
1684 | if (packet->skip) { |
1685 | d = context_get_descriptors(&ctx->context, 2, &d_bus); | |
1686 | if (d == NULL) | |
1687 | return -ENOMEM; | |
1688 | ||
1689 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
1690 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
1691 | DESCRIPTOR_BRANCH_ALWAYS | | |
1692 | DESCRIPTOR_WAIT); | |
c70dc788 KH |
1693 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
1694 | context_append(&ctx->context, d, 2, 0); | |
1695 | } | |
98b6cbe8 | 1696 | |
295e3feb KH |
1697 | p = packet; |
1698 | z = 2; | |
1699 | ||
c781c06d KH |
1700 | /* |
1701 | * The OHCI controller puts the status word in the header | |
1702 | * buffer too, so we need 4 extra bytes per packet. | |
1703 | */ | |
c70dc788 KH |
1704 | packet_count = p->header_length / ctx->base.header_size; |
1705 | header_size = packet_count * (ctx->base.header_size + 4); | |
1706 | ||
295e3feb | 1707 | /* Get header size in number of descriptors. */ |
2d826cc5 | 1708 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb KH |
1709 | page = payload >> PAGE_SHIFT; |
1710 | offset = payload & ~PAGE_MASK; | |
1711 | rest = p->payload_length; | |
1712 | ||
1713 | /* FIXME: OHCI 1.0 doesn't support dual buffer receive */ | |
295e3feb KH |
1714 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ |
1715 | while (rest > 0) { | |
1716 | d = context_get_descriptors(&ctx->context, | |
1717 | z + header_z, &d_bus); | |
1718 | if (d == NULL) | |
1719 | return -ENOMEM; | |
1720 | ||
1721 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
1722 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
1723 | DESCRIPTOR_BRANCH_ALWAYS); | |
c70dc788 KH |
1724 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
1725 | db->first_req_count = cpu_to_le16(header_size); | |
1e1d196b | 1726 | db->first_res_count = db->first_req_count; |
2d826cc5 | 1727 | db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd | 1728 | |
295e3feb KH |
1729 | if (offset + rest < PAGE_SIZE) |
1730 | length = rest; | |
1731 | else | |
1732 | length = PAGE_SIZE - offset; | |
1733 | ||
1e1d196b KH |
1734 | db->second_req_count = cpu_to_le16(length); |
1735 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
1736 | page_bus = page_private(buffer->pages[page]); |
1737 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
1738 | ||
cb2d2cdb | 1739 | if (p->interrupt && length == rest) |
a77754a7 | 1740 | db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdb | 1741 | |
295e3feb KH |
1742 | context_append(&ctx->context, d, z, header_z); |
1743 | offset = (offset + length) & ~PAGE_MASK; | |
1744 | rest -= length; | |
1745 | page++; | |
1746 | } | |
1747 | ||
d2746dc1 KH |
1748 | return 0; |
1749 | } | |
21efb3cf | 1750 | |
295e3feb KH |
1751 | static int |
1752 | ohci_queue_iso(struct fw_iso_context *base, | |
1753 | struct fw_iso_packet *packet, | |
1754 | struct fw_iso_buffer *buffer, | |
1755 | unsigned long payload) | |
1756 | { | |
e364cf4e KH |
1757 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1758 | ||
295e3feb KH |
1759 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
1760 | return ohci_queue_iso_transmit(base, packet, buffer, payload); | |
e364cf4e | 1761 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
d2746dc1 KH |
1762 | return ohci_queue_iso_receive_dualbuffer(base, packet, |
1763 | buffer, payload); | |
e364cf4e KH |
1764 | else |
1765 | /* FIXME: Implement fallback for OHCI 1.0 controllers. */ | |
1766 | return -EINVAL; | |
295e3feb KH |
1767 | } |
1768 | ||
21ebcd12 | 1769 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1770 | .name = ohci_driver_name, |
1771 | .enable = ohci_enable, | |
1772 | .update_phy_reg = ohci_update_phy_reg, | |
1773 | .set_config_rom = ohci_set_config_rom, | |
1774 | .send_request = ohci_send_request, | |
1775 | .send_response = ohci_send_response, | |
730c32f5 | 1776 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 1777 | .enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d | 1778 | .get_bus_time = ohci_get_bus_time, |
ed568912 KH |
1779 | |
1780 | .allocate_iso_context = ohci_allocate_iso_context, | |
1781 | .free_iso_context = ohci_free_iso_context, | |
1782 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 1783 | .start_iso = ohci_start_iso, |
b8295668 | 1784 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
1785 | }; |
1786 | ||
ed568912 KH |
1787 | static int __devinit |
1788 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1789 | { | |
1790 | struct fw_ohci *ohci; | |
e364cf4e | 1791 | u32 bus_options, max_receive, link_speed; |
ed568912 | 1792 | u64 guid; |
d79406dd | 1793 | int err; |
ed568912 KH |
1794 | size_t size; |
1795 | ||
2d826cc5 | 1796 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 KH |
1797 | if (ohci == NULL) { |
1798 | fw_error("Could not malloc fw_ohci data.\n"); | |
1799 | return -ENOMEM; | |
1800 | } | |
1801 | ||
1802 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1803 | ||
d79406dd KH |
1804 | err = pci_enable_device(dev); |
1805 | if (err) { | |
ed568912 | 1806 | fw_error("Failed to enable OHCI hardware.\n"); |
d79406dd | 1807 | goto fail_put_card; |
ed568912 KH |
1808 | } |
1809 | ||
1810 | pci_set_master(dev); | |
1811 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1812 | pci_set_drvdata(dev, ohci); | |
1813 | ||
1814 | spin_lock_init(&ohci->lock); | |
1815 | ||
1816 | tasklet_init(&ohci->bus_reset_tasklet, | |
1817 | bus_reset_tasklet, (unsigned long)ohci); | |
1818 | ||
d79406dd KH |
1819 | err = pci_request_region(dev, 0, ohci_driver_name); |
1820 | if (err) { | |
ed568912 | 1821 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 1822 | goto fail_disable; |
ed568912 KH |
1823 | } |
1824 | ||
1825 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1826 | if (ohci->registers == NULL) { | |
1827 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
1828 | err = -ENXIO; |
1829 | goto fail_iomem; | |
ed568912 KH |
1830 | } |
1831 | ||
ed568912 KH |
1832 | ar_context_init(&ohci->ar_request_ctx, ohci, |
1833 | OHCI1394_AsReqRcvContextControlSet); | |
1834 | ||
1835 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1836 | OHCI1394_AsRspRcvContextControlSet); | |
1837 | ||
f319b6a0 KH |
1838 | context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE, |
1839 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); | |
ed568912 | 1840 | |
f319b6a0 KH |
1841 | context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE, |
1842 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); | |
ed568912 | 1843 | |
ed568912 KH |
1844 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
1845 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1846 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1847 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1848 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1849 | ||
1850 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1851 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1852 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1853 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1854 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1855 | ||
1856 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1857 | fw_error("Out of memory for it/ir contexts.\n"); | |
d79406dd KH |
1858 | err = -ENOMEM; |
1859 | goto fail_registers; | |
ed568912 KH |
1860 | } |
1861 | ||
1862 | /* self-id dma buffer allocation */ | |
1863 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1864 | SELF_ID_BUF_SIZE, | |
1865 | &ohci->self_id_bus, | |
1866 | GFP_KERNEL); | |
1867 | if (ohci->self_id_cpu == NULL) { | |
1868 | fw_error("Out of memory for self ID buffer.\n"); | |
d79406dd KH |
1869 | err = -ENOMEM; |
1870 | goto fail_registers; | |
ed568912 KH |
1871 | } |
1872 | ||
ed568912 KH |
1873 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
1874 | max_receive = (bus_options >> 12) & 0xf; | |
1875 | link_speed = bus_options & 0x7; | |
1876 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1877 | reg_read(ohci, OHCI1394_GUIDLo); | |
1878 | ||
d79406dd KH |
1879 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
1880 | if (err < 0) | |
1881 | goto fail_self_id; | |
ed568912 | 1882 | |
e364cf4e | 1883 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 1884 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 1885 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 KH |
1886 | |
1887 | return 0; | |
d79406dd KH |
1888 | |
1889 | fail_self_id: | |
1890 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1891 | ohci->self_id_cpu, ohci->self_id_bus); | |
1892 | fail_registers: | |
1893 | kfree(ohci->it_context_list); | |
1894 | kfree(ohci->ir_context_list); | |
1895 | pci_iounmap(dev, ohci->registers); | |
1896 | fail_iomem: | |
1897 | pci_release_region(dev, 0); | |
1898 | fail_disable: | |
1899 | pci_disable_device(dev); | |
1900 | fail_put_card: | |
1901 | fw_card_put(&ohci->card); | |
1902 | ||
1903 | return err; | |
ed568912 KH |
1904 | } |
1905 | ||
1906 | static void pci_remove(struct pci_dev *dev) | |
1907 | { | |
1908 | struct fw_ohci *ohci; | |
1909 | ||
1910 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
1911 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
1912 | flush_writes(ohci); | |
ed568912 KH |
1913 | fw_core_remove_card(&ohci->card); |
1914 | ||
c781c06d KH |
1915 | /* |
1916 | * FIXME: Fail all pending packets here, now that the upper | |
1917 | * layers can't queue any more. | |
1918 | */ | |
ed568912 KH |
1919 | |
1920 | software_reset(ohci); | |
1921 | free_irq(dev->irq, ohci); | |
d79406dd KH |
1922 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
1923 | ohci->self_id_cpu, ohci->self_id_bus); | |
1924 | kfree(ohci->it_context_list); | |
1925 | kfree(ohci->ir_context_list); | |
1926 | pci_iounmap(dev, ohci->registers); | |
1927 | pci_release_region(dev, 0); | |
1928 | pci_disable_device(dev); | |
1929 | fw_card_put(&ohci->card); | |
ed568912 KH |
1930 | |
1931 | fw_notify("Removed fw-ohci device.\n"); | |
1932 | } | |
1933 | ||
2aef469a KH |
1934 | #ifdef CONFIG_PM |
1935 | static int pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
1936 | { | |
1937 | struct fw_ohci *ohci = pci_get_drvdata(pdev); | |
1938 | int err; | |
1939 | ||
1940 | software_reset(ohci); | |
1941 | free_irq(pdev->irq, ohci); | |
1942 | err = pci_save_state(pdev); | |
1943 | if (err) { | |
8a8cea27 | 1944 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
1945 | return err; |
1946 | } | |
1947 | err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
55111428 SR |
1948 | if (err) |
1949 | fw_error("pci_set_power_state failed with %d\n", err); | |
2aef469a KH |
1950 | |
1951 | return 0; | |
1952 | } | |
1953 | ||
1954 | static int pci_resume(struct pci_dev *pdev) | |
1955 | { | |
1956 | struct fw_ohci *ohci = pci_get_drvdata(pdev); | |
1957 | int err; | |
1958 | ||
1959 | pci_set_power_state(pdev, PCI_D0); | |
1960 | pci_restore_state(pdev); | |
1961 | err = pci_enable_device(pdev); | |
1962 | if (err) { | |
8a8cea27 | 1963 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
1964 | return err; |
1965 | } | |
1966 | ||
1967 | return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE); | |
1968 | } | |
1969 | #endif | |
1970 | ||
ed568912 KH |
1971 | static struct pci_device_id pci_table[] = { |
1972 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1973 | { } | |
1974 | }; | |
1975 | ||
1976 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1977 | ||
1978 | static struct pci_driver fw_ohci_pci_driver = { | |
1979 | .name = ohci_driver_name, | |
1980 | .id_table = pci_table, | |
1981 | .probe = pci_probe, | |
1982 | .remove = pci_remove, | |
2aef469a KH |
1983 | #ifdef CONFIG_PM |
1984 | .resume = pci_resume, | |
1985 | .suspend = pci_suspend, | |
1986 | #endif | |
ed568912 KH |
1987 | }; |
1988 | ||
1989 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1990 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1991 | MODULE_LICENSE("GPL"); | |
1992 | ||
1e4c7b0d OH |
1993 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
1994 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
1995 | MODULE_ALIAS("ohci1394"); | |
1996 | #endif | |
1997 | ||
ed568912 KH |
1998 | static int __init fw_ohci_init(void) |
1999 | { | |
2000 | return pci_register_driver(&fw_ohci_pci_driver); | |
2001 | } | |
2002 | ||
2003 | static void __exit fw_ohci_cleanup(void) | |
2004 | { | |
2005 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2006 | } | |
2007 | ||
2008 | module_init(fw_ohci_init); | |
2009 | module_exit(fw_ohci_cleanup); |