Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c781c06d | 2 | /* |
b1bda4cd JFSR |
3 | * Isochronous I/O functionality: |
4 | * - Isochronous DMA context management | |
5 | * - Isochronous bus resource management (channels, bandwidth), client side | |
3038e353 | 6 | * |
3038e353 | 7 | * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net> |
3038e353 KH |
8 | */ |
9 | ||
3038e353 | 10 | #include <linux/dma-mapping.h> |
b1bda4cd | 11 | #include <linux/errno.h> |
77c9a5da | 12 | #include <linux/firewire.h> |
b1bda4cd JFSR |
13 | #include <linux/firewire-constants.h> |
14 | #include <linux/kernel.h> | |
3038e353 | 15 | #include <linux/mm.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
b1bda4cd JFSR |
17 | #include <linux/spinlock.h> |
18 | #include <linux/vmalloc.h> | |
823467e5 | 19 | #include <linux/export.h> |
3038e353 | 20 | |
e8ca9702 SR |
21 | #include <asm/byteorder.h> |
22 | ||
77c9a5da | 23 | #include "core.h" |
b1bda4cd JFSR |
24 | |
25 | /* | |
26 | * Isochronous DMA context management | |
27 | */ | |
3038e353 | 28 | |
0b6c4857 | 29 | int fw_iso_buffer_alloc(struct fw_iso_buffer *buffer, int page_count) |
3038e353 | 30 | { |
0b6c4857 | 31 | int i; |
9aad8125 | 32 | |
0b6c4857 SR |
33 | buffer->page_count = 0; |
34 | buffer->page_count_mapped = 0; | |
6da2ec56 KC |
35 | buffer->pages = kmalloc_array(page_count, sizeof(buffer->pages[0]), |
36 | GFP_KERNEL); | |
9aad8125 | 37 | if (buffer->pages == NULL) |
0b6c4857 | 38 | return -ENOMEM; |
9aad8125 | 39 | |
0b6c4857 | 40 | for (i = 0; i < page_count; i++) { |
68be3fa1 | 41 | buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
9aad8125 | 42 | if (buffer->pages[i] == NULL) |
0b6c4857 SR |
43 | break; |
44 | } | |
45 | buffer->page_count = i; | |
46 | if (i < page_count) { | |
47 | fw_iso_buffer_destroy(buffer, NULL); | |
48 | return -ENOMEM; | |
49 | } | |
373b2edd | 50 | |
0b6c4857 SR |
51 | return 0; |
52 | } | |
53 | ||
54 | int fw_iso_buffer_map_dma(struct fw_iso_buffer *buffer, struct fw_card *card, | |
55 | enum dma_data_direction direction) | |
56 | { | |
57 | dma_addr_t address; | |
58 | int i; | |
59 | ||
60 | buffer->direction = direction; | |
61 | ||
62 | for (i = 0; i < buffer->page_count; i++) { | |
9aad8125 KH |
63 | address = dma_map_page(card->device, buffer->pages[i], |
64 | 0, PAGE_SIZE, direction); | |
0b6c4857 SR |
65 | if (dma_mapping_error(card->device, address)) |
66 | break; | |
67 | ||
9aad8125 | 68 | set_page_private(buffer->pages[i], address); |
3038e353 | 69 | } |
0b6c4857 SR |
70 | buffer->page_count_mapped = i; |
71 | if (i < buffer->page_count) | |
72 | return -ENOMEM; | |
3038e353 KH |
73 | |
74 | return 0; | |
0b6c4857 | 75 | } |
82eff9db | 76 | |
0b6c4857 SR |
77 | int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card, |
78 | int page_count, enum dma_data_direction direction) | |
79 | { | |
80 | int ret; | |
81 | ||
82 | ret = fw_iso_buffer_alloc(buffer, page_count); | |
83 | if (ret < 0) | |
84 | return ret; | |
e1eff7a3 | 85 | |
0b6c4857 SR |
86 | ret = fw_iso_buffer_map_dma(buffer, card, direction); |
87 | if (ret < 0) | |
88 | fw_iso_buffer_destroy(buffer, card); | |
89 | ||
90 | return ret; | |
9aad8125 | 91 | } |
c76acec6 | 92 | EXPORT_SYMBOL(fw_iso_buffer_init); |
9aad8125 | 93 | |
0b6c4857 SR |
94 | int fw_iso_buffer_map_vma(struct fw_iso_buffer *buffer, |
95 | struct vm_area_struct *vma) | |
9aad8125 | 96 | { |
22660db8 SJ |
97 | return vm_map_pages_zero(vma, buffer->pages, |
98 | buffer->page_count); | |
3038e353 KH |
99 | } |
100 | ||
9aad8125 KH |
101 | void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer, |
102 | struct fw_card *card) | |
3038e353 KH |
103 | { |
104 | int i; | |
9aad8125 | 105 | dma_addr_t address; |
3038e353 | 106 | |
0b6c4857 | 107 | for (i = 0; i < buffer->page_count_mapped; i++) { |
9aad8125 KH |
108 | address = page_private(buffer->pages[i]); |
109 | dma_unmap_page(card->device, address, | |
29ad14cd | 110 | PAGE_SIZE, buffer->direction); |
9aad8125 | 111 | } |
0b6c4857 SR |
112 | for (i = 0; i < buffer->page_count; i++) |
113 | __free_page(buffer->pages[i]); | |
3038e353 | 114 | |
9aad8125 KH |
115 | kfree(buffer->pages); |
116 | buffer->pages = NULL; | |
0b6c4857 SR |
117 | buffer->page_count = 0; |
118 | buffer->page_count_mapped = 0; | |
3038e353 | 119 | } |
c76acec6 | 120 | EXPORT_SYMBOL(fw_iso_buffer_destroy); |
3038e353 | 121 | |
872e330e SR |
122 | /* Convert DMA address to offset into virtually contiguous buffer. */ |
123 | size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed) | |
124 | { | |
9d23f9e9 | 125 | size_t i; |
872e330e SR |
126 | dma_addr_t address; |
127 | ssize_t offset; | |
128 | ||
129 | for (i = 0; i < buffer->page_count; i++) { | |
130 | address = page_private(buffer->pages[i]); | |
131 | offset = (ssize_t)completed - (ssize_t)address; | |
132 | if (offset > 0 && offset <= PAGE_SIZE) | |
133 | return (i << PAGE_SHIFT) + offset; | |
134 | } | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
53dca511 SR |
139 | struct fw_iso_context *fw_iso_context_create(struct fw_card *card, |
140 | int type, int channel, int speed, size_t header_size, | |
141 | fw_iso_callback_t callback, void *callback_data) | |
3038e353 KH |
142 | { |
143 | struct fw_iso_context *ctx; | |
3038e353 | 144 | |
4817ed24 SR |
145 | ctx = card->driver->allocate_iso_context(card, |
146 | type, channel, header_size); | |
3038e353 KH |
147 | if (IS_ERR(ctx)) |
148 | return ctx; | |
149 | ||
150 | ctx->card = card; | |
151 | ctx->type = type; | |
21efb3cf KH |
152 | ctx->channel = channel; |
153 | ctx->speed = speed; | |
295e3feb | 154 | ctx->header_size = header_size; |
872e330e | 155 | ctx->callback.sc = callback; |
3038e353 KH |
156 | ctx->callback_data = callback_data; |
157 | ||
3038e353 KH |
158 | return ctx; |
159 | } | |
c76acec6 | 160 | EXPORT_SYMBOL(fw_iso_context_create); |
3038e353 KH |
161 | |
162 | void fw_iso_context_destroy(struct fw_iso_context *ctx) | |
163 | { | |
872e330e | 164 | ctx->card->driver->free_iso_context(ctx); |
3038e353 | 165 | } |
c76acec6 | 166 | EXPORT_SYMBOL(fw_iso_context_destroy); |
3038e353 | 167 | |
53dca511 SR |
168 | int fw_iso_context_start(struct fw_iso_context *ctx, |
169 | int cycle, int sync, int tags) | |
3038e353 | 170 | { |
eb0306ea | 171 | return ctx->card->driver->start_iso(ctx, cycle, sync, tags); |
3038e353 | 172 | } |
c76acec6 | 173 | EXPORT_SYMBOL(fw_iso_context_start); |
3038e353 | 174 | |
872e330e SR |
175 | int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels) |
176 | { | |
177 | return ctx->card->driver->set_iso_channels(ctx, channels); | |
178 | } | |
179 | ||
53dca511 SR |
180 | int fw_iso_context_queue(struct fw_iso_context *ctx, |
181 | struct fw_iso_packet *packet, | |
182 | struct fw_iso_buffer *buffer, | |
183 | unsigned long payload) | |
3038e353 | 184 | { |
872e330e | 185 | return ctx->card->driver->queue_iso(ctx, packet, buffer, payload); |
3038e353 | 186 | } |
c76acec6 | 187 | EXPORT_SYMBOL(fw_iso_context_queue); |
b8295668 | 188 | |
13882a82 CL |
189 | void fw_iso_context_queue_flush(struct fw_iso_context *ctx) |
190 | { | |
191 | ctx->card->driver->flush_queue_iso(ctx); | |
192 | } | |
193 | EXPORT_SYMBOL(fw_iso_context_queue_flush); | |
194 | ||
d1bbd209 CL |
195 | int fw_iso_context_flush_completions(struct fw_iso_context *ctx) |
196 | { | |
197 | return ctx->card->driver->flush_iso_completions(ctx); | |
198 | } | |
199 | EXPORT_SYMBOL(fw_iso_context_flush_completions); | |
200 | ||
53dca511 | 201 | int fw_iso_context_stop(struct fw_iso_context *ctx) |
b8295668 KH |
202 | { |
203 | return ctx->card->driver->stop_iso(ctx); | |
204 | } | |
c76acec6 | 205 | EXPORT_SYMBOL(fw_iso_context_stop); |
b1bda4cd JFSR |
206 | |
207 | /* | |
208 | * Isochronous bus resource management (channels, bandwidth), client side | |
209 | */ | |
210 | ||
211 | static int manage_bandwidth(struct fw_card *card, int irm_id, int generation, | |
f30e6d3e | 212 | int bandwidth, bool allocate) |
b1bda4cd | 213 | { |
b1bda4cd | 214 | int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0; |
f30e6d3e | 215 | __be32 data[2]; |
b1bda4cd JFSR |
216 | |
217 | /* | |
218 | * On a 1394a IRM with low contention, try < 1 is enough. | |
219 | * On a 1394-1995 IRM, we need at least try < 2. | |
220 | * Let's just do try < 5. | |
221 | */ | |
222 | for (try = 0; try < 5; try++) { | |
223 | new = allocate ? old - bandwidth : old + bandwidth; | |
224 | if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL) | |
d6372b6e | 225 | return -EBUSY; |
b1bda4cd JFSR |
226 | |
227 | data[0] = cpu_to_be32(old); | |
228 | data[1] = cpu_to_be32(new); | |
229 | switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, | |
230 | irm_id, generation, SCODE_100, | |
231 | CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE, | |
1821bc19 | 232 | data, 8)) { |
b1bda4cd JFSR |
233 | case RCODE_GENERATION: |
234 | /* A generation change frees all bandwidth. */ | |
235 | return allocate ? -EAGAIN : bandwidth; | |
236 | ||
237 | case RCODE_COMPLETE: | |
238 | if (be32_to_cpup(data) == old) | |
239 | return bandwidth; | |
240 | ||
241 | old = be32_to_cpup(data); | |
242 | /* Fall through. */ | |
243 | } | |
244 | } | |
245 | ||
246 | return -EIO; | |
247 | } | |
248 | ||
249 | static int manage_channel(struct fw_card *card, int irm_id, int generation, | |
f30e6d3e | 250 | u32 channels_mask, u64 offset, bool allocate) |
b1bda4cd | 251 | { |
5aaffc65 | 252 | __be32 bit, all, old; |
f30e6d3e | 253 | __be32 data[2]; |
5aaffc65 | 254 | int channel, ret = -EIO, retry = 5; |
b1bda4cd | 255 | |
5d9cb7d2 SR |
256 | old = all = allocate ? cpu_to_be32(~0) : 0; |
257 | ||
5aaffc65 CL |
258 | for (channel = 0; channel < 32; channel++) { |
259 | if (!(channels_mask & 1 << channel)) | |
b1bda4cd JFSR |
260 | continue; |
261 | ||
d6372b6e CL |
262 | ret = -EBUSY; |
263 | ||
5aaffc65 CL |
264 | bit = cpu_to_be32(1 << (31 - channel)); |
265 | if ((old & bit) != (all & bit)) | |
b1bda4cd JFSR |
266 | continue; |
267 | ||
268 | data[0] = old; | |
5aaffc65 | 269 | data[1] = old ^ bit; |
b1bda4cd JFSR |
270 | switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, |
271 | irm_id, generation, SCODE_100, | |
1821bc19 | 272 | offset, data, 8)) { |
b1bda4cd JFSR |
273 | case RCODE_GENERATION: |
274 | /* A generation change frees all channels. */ | |
5aaffc65 | 275 | return allocate ? -EAGAIN : channel; |
b1bda4cd JFSR |
276 | |
277 | case RCODE_COMPLETE: | |
278 | if (data[0] == old) | |
5aaffc65 | 279 | return channel; |
b1bda4cd JFSR |
280 | |
281 | old = data[0]; | |
282 | ||
283 | /* Is the IRM 1394a-2000 compliant? */ | |
5aaffc65 | 284 | if ((data[0] & bit) == (data[1] & bit)) |
b1bda4cd JFSR |
285 | continue; |
286 | ||
287 | /* 1394-1995 IRM, fall through to retry. */ | |
288 | default: | |
3a1f0a0e CL |
289 | if (retry) { |
290 | retry--; | |
5aaffc65 | 291 | channel--; |
d6372b6e CL |
292 | } else { |
293 | ret = -EIO; | |
3a1f0a0e | 294 | } |
b1bda4cd JFSR |
295 | } |
296 | } | |
297 | ||
d6372b6e | 298 | return ret; |
b1bda4cd JFSR |
299 | } |
300 | ||
301 | static void deallocate_channel(struct fw_card *card, int irm_id, | |
f30e6d3e | 302 | int generation, int channel) |
b1bda4cd | 303 | { |
5d9cb7d2 | 304 | u32 mask; |
b1bda4cd JFSR |
305 | u64 offset; |
306 | ||
5d9cb7d2 | 307 | mask = channel < 32 ? 1 << channel : 1 << (channel - 32); |
b1bda4cd JFSR |
308 | offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI : |
309 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO; | |
310 | ||
f30e6d3e | 311 | manage_channel(card, irm_id, generation, mask, offset, false); |
b1bda4cd JFSR |
312 | } |
313 | ||
314 | /** | |
656b7afd | 315 | * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth |
48f02b88 RD |
316 | * @card: card interface for this action |
317 | * @generation: bus generation | |
318 | * @channels_mask: bitmask for channel allocation | |
319 | * @channel: pointer for returning channel allocation result | |
320 | * @bandwidth: pointer for returning bandwidth allocation result | |
321 | * @allocate: whether to allocate (true) or deallocate (false) | |
b1bda4cd JFSR |
322 | * |
323 | * In parameters: card, generation, channels_mask, bandwidth, allocate | |
324 | * Out parameters: channel, bandwidth | |
48f02b88 | 325 | * |
b1bda4cd | 326 | * This function blocks (sleeps) during communication with the IRM. |
5d9cb7d2 | 327 | * |
b1bda4cd | 328 | * Allocates or deallocates at most one channel out of channels_mask. |
5d9cb7d2 SR |
329 | * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0. |
330 | * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for | |
331 | * channel 0 and LSB for channel 63.) | |
332 | * Allocates or deallocates as many bandwidth allocation units as specified. | |
b1bda4cd JFSR |
333 | * |
334 | * Returns channel < 0 if no channel was allocated or deallocated. | |
335 | * Returns bandwidth = 0 if no bandwidth was allocated or deallocated. | |
336 | * | |
337 | * If generation is stale, deallocations succeed but allocations fail with | |
338 | * channel = -EAGAIN. | |
339 | * | |
5d9cb7d2 | 340 | * If channel allocation fails, no bandwidth will be allocated either. |
b1bda4cd | 341 | * If bandwidth allocation fails, no channel will be allocated either. |
5d9cb7d2 SR |
342 | * But deallocations of channel and bandwidth are tried independently |
343 | * of each other's success. | |
b1bda4cd JFSR |
344 | */ |
345 | void fw_iso_resource_manage(struct fw_card *card, int generation, | |
346 | u64 channels_mask, int *channel, int *bandwidth, | |
f30e6d3e | 347 | bool allocate) |
b1bda4cd | 348 | { |
5d9cb7d2 SR |
349 | u32 channels_hi = channels_mask; /* channels 31...0 */ |
350 | u32 channels_lo = channels_mask >> 32; /* channels 63...32 */ | |
b1bda4cd JFSR |
351 | int irm_id, ret, c = -EINVAL; |
352 | ||
353 | spin_lock_irq(&card->lock); | |
354 | irm_id = card->irm_node->node_id; | |
355 | spin_unlock_irq(&card->lock); | |
356 | ||
357 | if (channels_hi) | |
358 | c = manage_channel(card, irm_id, generation, channels_hi, | |
6fdc0370 | 359 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI, |
f30e6d3e | 360 | allocate); |
b1bda4cd JFSR |
361 | if (channels_lo && c < 0) { |
362 | c = manage_channel(card, irm_id, generation, channels_lo, | |
6fdc0370 | 363 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO, |
f30e6d3e | 364 | allocate); |
b1bda4cd JFSR |
365 | if (c >= 0) |
366 | c += 32; | |
367 | } | |
368 | *channel = c; | |
369 | ||
5d9cb7d2 | 370 | if (allocate && channels_mask != 0 && c < 0) |
b1bda4cd JFSR |
371 | *bandwidth = 0; |
372 | ||
373 | if (*bandwidth == 0) | |
374 | return; | |
375 | ||
f30e6d3e | 376 | ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate); |
b1bda4cd JFSR |
377 | if (ret < 0) |
378 | *bandwidth = 0; | |
379 | ||
cf36df6b CL |
380 | if (allocate && ret < 0) { |
381 | if (c >= 0) | |
f30e6d3e | 382 | deallocate_channel(card, irm_id, generation, c); |
b1bda4cd JFSR |
383 | *channel = ret; |
384 | } | |
385 | } | |
31ef9134 | 386 | EXPORT_SYMBOL(fw_iso_resource_manage); |