Commit | Line | Data |
---|---|---|
c781c06d | 1 | /* |
b1bda4cd JFSR |
2 | * Isochronous I/O functionality: |
3 | * - Isochronous DMA context management | |
4 | * - Isochronous bus resource management (channels, bandwidth), client side | |
3038e353 | 5 | * |
3038e353 KH |
6 | * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net> |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | ||
3038e353 | 23 | #include <linux/dma-mapping.h> |
b1bda4cd | 24 | #include <linux/errno.h> |
77c9a5da | 25 | #include <linux/firewire.h> |
b1bda4cd JFSR |
26 | #include <linux/firewire-constants.h> |
27 | #include <linux/kernel.h> | |
3038e353 | 28 | #include <linux/mm.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
b1bda4cd JFSR |
30 | #include <linux/spinlock.h> |
31 | #include <linux/vmalloc.h> | |
3038e353 | 32 | |
e8ca9702 SR |
33 | #include <asm/byteorder.h> |
34 | ||
77c9a5da | 35 | #include "core.h" |
b1bda4cd JFSR |
36 | |
37 | /* | |
38 | * Isochronous DMA context management | |
39 | */ | |
3038e353 | 40 | |
53dca511 SR |
41 | int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card, |
42 | int page_count, enum dma_data_direction direction) | |
3038e353 | 43 | { |
2dbd7d7e | 44 | int i, j; |
9aad8125 KH |
45 | dma_addr_t address; |
46 | ||
47 | buffer->page_count = page_count; | |
48 | buffer->direction = direction; | |
49 | ||
50 | buffer->pages = kmalloc(page_count * sizeof(buffer->pages[0]), | |
51 | GFP_KERNEL); | |
52 | if (buffer->pages == NULL) | |
53 | goto out; | |
54 | ||
55 | for (i = 0; i < buffer->page_count; i++) { | |
68be3fa1 | 56 | buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
9aad8125 KH |
57 | if (buffer->pages[i] == NULL) |
58 | goto out_pages; | |
373b2edd | 59 | |
9aad8125 KH |
60 | address = dma_map_page(card->device, buffer->pages[i], |
61 | 0, PAGE_SIZE, direction); | |
8d8bb39b | 62 | if (dma_mapping_error(card->device, address)) { |
9aad8125 KH |
63 | __free_page(buffer->pages[i]); |
64 | goto out_pages; | |
65 | } | |
66 | set_page_private(buffer->pages[i], address); | |
3038e353 KH |
67 | } |
68 | ||
69 | return 0; | |
82eff9db | 70 | |
9aad8125 KH |
71 | out_pages: |
72 | for (j = 0; j < i; j++) { | |
73 | address = page_private(buffer->pages[j]); | |
74 | dma_unmap_page(card->device, address, | |
29ad14cd | 75 | PAGE_SIZE, direction); |
9aad8125 KH |
76 | __free_page(buffer->pages[j]); |
77 | } | |
78 | kfree(buffer->pages); | |
79 | out: | |
80 | buffer->pages = NULL; | |
e1eff7a3 | 81 | |
2dbd7d7e | 82 | return -ENOMEM; |
9aad8125 | 83 | } |
c76acec6 | 84 | EXPORT_SYMBOL(fw_iso_buffer_init); |
9aad8125 KH |
85 | |
86 | int fw_iso_buffer_map(struct fw_iso_buffer *buffer, struct vm_area_struct *vma) | |
87 | { | |
88 | unsigned long uaddr; | |
e1eff7a3 | 89 | int i, err; |
9aad8125 KH |
90 | |
91 | uaddr = vma->vm_start; | |
92 | for (i = 0; i < buffer->page_count; i++) { | |
e1eff7a3 SR |
93 | err = vm_insert_page(vma, uaddr, buffer->pages[i]); |
94 | if (err) | |
95 | return err; | |
96 | ||
9aad8125 KH |
97 | uaddr += PAGE_SIZE; |
98 | } | |
99 | ||
100 | return 0; | |
3038e353 KH |
101 | } |
102 | ||
9aad8125 KH |
103 | void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer, |
104 | struct fw_card *card) | |
3038e353 KH |
105 | { |
106 | int i; | |
9aad8125 | 107 | dma_addr_t address; |
3038e353 | 108 | |
9aad8125 KH |
109 | for (i = 0; i < buffer->page_count; i++) { |
110 | address = page_private(buffer->pages[i]); | |
111 | dma_unmap_page(card->device, address, | |
29ad14cd | 112 | PAGE_SIZE, buffer->direction); |
9aad8125 KH |
113 | __free_page(buffer->pages[i]); |
114 | } | |
3038e353 | 115 | |
9aad8125 KH |
116 | kfree(buffer->pages); |
117 | buffer->pages = NULL; | |
3038e353 | 118 | } |
c76acec6 | 119 | EXPORT_SYMBOL(fw_iso_buffer_destroy); |
3038e353 | 120 | |
53dca511 SR |
121 | struct fw_iso_context *fw_iso_context_create(struct fw_card *card, |
122 | int type, int channel, int speed, size_t header_size, | |
123 | fw_iso_callback_t callback, void *callback_data) | |
3038e353 KH |
124 | { |
125 | struct fw_iso_context *ctx; | |
3038e353 | 126 | |
4817ed24 SR |
127 | ctx = card->driver->allocate_iso_context(card, |
128 | type, channel, header_size); | |
3038e353 KH |
129 | if (IS_ERR(ctx)) |
130 | return ctx; | |
131 | ||
132 | ctx->card = card; | |
133 | ctx->type = type; | |
21efb3cf KH |
134 | ctx->channel = channel; |
135 | ctx->speed = speed; | |
295e3feb | 136 | ctx->header_size = header_size; |
3038e353 KH |
137 | ctx->callback = callback; |
138 | ctx->callback_data = callback_data; | |
139 | ||
3038e353 KH |
140 | return ctx; |
141 | } | |
c76acec6 | 142 | EXPORT_SYMBOL(fw_iso_context_create); |
3038e353 KH |
143 | |
144 | void fw_iso_context_destroy(struct fw_iso_context *ctx) | |
145 | { | |
146 | struct fw_card *card = ctx->card; | |
147 | ||
3038e353 KH |
148 | card->driver->free_iso_context(ctx); |
149 | } | |
c76acec6 | 150 | EXPORT_SYMBOL(fw_iso_context_destroy); |
3038e353 | 151 | |
53dca511 SR |
152 | int fw_iso_context_start(struct fw_iso_context *ctx, |
153 | int cycle, int sync, int tags) | |
3038e353 | 154 | { |
eb0306ea | 155 | return ctx->card->driver->start_iso(ctx, cycle, sync, tags); |
3038e353 | 156 | } |
c76acec6 | 157 | EXPORT_SYMBOL(fw_iso_context_start); |
3038e353 | 158 | |
53dca511 SR |
159 | int fw_iso_context_queue(struct fw_iso_context *ctx, |
160 | struct fw_iso_packet *packet, | |
161 | struct fw_iso_buffer *buffer, | |
162 | unsigned long payload) | |
3038e353 KH |
163 | { |
164 | struct fw_card *card = ctx->card; | |
165 | ||
9aad8125 | 166 | return card->driver->queue_iso(ctx, packet, buffer, payload); |
3038e353 | 167 | } |
c76acec6 | 168 | EXPORT_SYMBOL(fw_iso_context_queue); |
b8295668 | 169 | |
53dca511 | 170 | int fw_iso_context_stop(struct fw_iso_context *ctx) |
b8295668 KH |
171 | { |
172 | return ctx->card->driver->stop_iso(ctx); | |
173 | } | |
c76acec6 | 174 | EXPORT_SYMBOL(fw_iso_context_stop); |
b1bda4cd JFSR |
175 | |
176 | /* | |
177 | * Isochronous bus resource management (channels, bandwidth), client side | |
178 | */ | |
179 | ||
180 | static int manage_bandwidth(struct fw_card *card, int irm_id, int generation, | |
6fdc0370 | 181 | int bandwidth, bool allocate, __be32 data[2]) |
b1bda4cd | 182 | { |
b1bda4cd JFSR |
183 | int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0; |
184 | ||
185 | /* | |
186 | * On a 1394a IRM with low contention, try < 1 is enough. | |
187 | * On a 1394-1995 IRM, we need at least try < 2. | |
188 | * Let's just do try < 5. | |
189 | */ | |
190 | for (try = 0; try < 5; try++) { | |
191 | new = allocate ? old - bandwidth : old + bandwidth; | |
192 | if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL) | |
d6372b6e | 193 | return -EBUSY; |
b1bda4cd JFSR |
194 | |
195 | data[0] = cpu_to_be32(old); | |
196 | data[1] = cpu_to_be32(new); | |
197 | switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, | |
198 | irm_id, generation, SCODE_100, | |
199 | CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE, | |
1821bc19 | 200 | data, 8)) { |
b1bda4cd JFSR |
201 | case RCODE_GENERATION: |
202 | /* A generation change frees all bandwidth. */ | |
203 | return allocate ? -EAGAIN : bandwidth; | |
204 | ||
205 | case RCODE_COMPLETE: | |
206 | if (be32_to_cpup(data) == old) | |
207 | return bandwidth; | |
208 | ||
209 | old = be32_to_cpup(data); | |
210 | /* Fall through. */ | |
211 | } | |
212 | } | |
213 | ||
214 | return -EIO; | |
215 | } | |
216 | ||
217 | static int manage_channel(struct fw_card *card, int irm_id, int generation, | |
6fdc0370 | 218 | u32 channels_mask, u64 offset, bool allocate, __be32 data[2]) |
b1bda4cd | 219 | { |
6fdc0370 | 220 | __be32 c, all, old; |
d6372b6e | 221 | int i, ret = -EIO, retry = 5; |
b1bda4cd | 222 | |
5d9cb7d2 SR |
223 | old = all = allocate ? cpu_to_be32(~0) : 0; |
224 | ||
b1bda4cd | 225 | for (i = 0; i < 32; i++) { |
5d9cb7d2 | 226 | if (!(channels_mask & 1 << i)) |
b1bda4cd JFSR |
227 | continue; |
228 | ||
d6372b6e CL |
229 | ret = -EBUSY; |
230 | ||
5d9cb7d2 SR |
231 | c = cpu_to_be32(1 << (31 - i)); |
232 | if ((old & c) != (all & c)) | |
b1bda4cd JFSR |
233 | continue; |
234 | ||
235 | data[0] = old; | |
236 | data[1] = old ^ c; | |
237 | switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, | |
238 | irm_id, generation, SCODE_100, | |
1821bc19 | 239 | offset, data, 8)) { |
b1bda4cd JFSR |
240 | case RCODE_GENERATION: |
241 | /* A generation change frees all channels. */ | |
242 | return allocate ? -EAGAIN : i; | |
243 | ||
244 | case RCODE_COMPLETE: | |
245 | if (data[0] == old) | |
246 | return i; | |
247 | ||
248 | old = data[0]; | |
249 | ||
250 | /* Is the IRM 1394a-2000 compliant? */ | |
5d9cb7d2 | 251 | if ((data[0] & c) == (data[1] & c)) |
b1bda4cd JFSR |
252 | continue; |
253 | ||
254 | /* 1394-1995 IRM, fall through to retry. */ | |
255 | default: | |
3a1f0a0e CL |
256 | if (retry) { |
257 | retry--; | |
b1bda4cd | 258 | i--; |
d6372b6e CL |
259 | } else { |
260 | ret = -EIO; | |
3a1f0a0e | 261 | } |
b1bda4cd JFSR |
262 | } |
263 | } | |
264 | ||
d6372b6e | 265 | return ret; |
b1bda4cd JFSR |
266 | } |
267 | ||
268 | static void deallocate_channel(struct fw_card *card, int irm_id, | |
6fdc0370 | 269 | int generation, int channel, __be32 buffer[2]) |
b1bda4cd | 270 | { |
5d9cb7d2 | 271 | u32 mask; |
b1bda4cd JFSR |
272 | u64 offset; |
273 | ||
5d9cb7d2 | 274 | mask = channel < 32 ? 1 << channel : 1 << (channel - 32); |
b1bda4cd JFSR |
275 | offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI : |
276 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO; | |
277 | ||
6fdc0370 | 278 | manage_channel(card, irm_id, generation, mask, offset, false, buffer); |
b1bda4cd JFSR |
279 | } |
280 | ||
281 | /** | |
282 | * fw_iso_resource_manage - Allocate or deallocate a channel and/or bandwidth | |
283 | * | |
284 | * In parameters: card, generation, channels_mask, bandwidth, allocate | |
285 | * Out parameters: channel, bandwidth | |
286 | * This function blocks (sleeps) during communication with the IRM. | |
5d9cb7d2 | 287 | * |
b1bda4cd | 288 | * Allocates or deallocates at most one channel out of channels_mask. |
5d9cb7d2 SR |
289 | * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0. |
290 | * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for | |
291 | * channel 0 and LSB for channel 63.) | |
292 | * Allocates or deallocates as many bandwidth allocation units as specified. | |
b1bda4cd JFSR |
293 | * |
294 | * Returns channel < 0 if no channel was allocated or deallocated. | |
295 | * Returns bandwidth = 0 if no bandwidth was allocated or deallocated. | |
296 | * | |
297 | * If generation is stale, deallocations succeed but allocations fail with | |
298 | * channel = -EAGAIN. | |
299 | * | |
5d9cb7d2 | 300 | * If channel allocation fails, no bandwidth will be allocated either. |
b1bda4cd | 301 | * If bandwidth allocation fails, no channel will be allocated either. |
5d9cb7d2 SR |
302 | * But deallocations of channel and bandwidth are tried independently |
303 | * of each other's success. | |
b1bda4cd JFSR |
304 | */ |
305 | void fw_iso_resource_manage(struct fw_card *card, int generation, | |
306 | u64 channels_mask, int *channel, int *bandwidth, | |
6fdc0370 | 307 | bool allocate, __be32 buffer[2]) |
b1bda4cd | 308 | { |
5d9cb7d2 SR |
309 | u32 channels_hi = channels_mask; /* channels 31...0 */ |
310 | u32 channels_lo = channels_mask >> 32; /* channels 63...32 */ | |
b1bda4cd JFSR |
311 | int irm_id, ret, c = -EINVAL; |
312 | ||
313 | spin_lock_irq(&card->lock); | |
314 | irm_id = card->irm_node->node_id; | |
315 | spin_unlock_irq(&card->lock); | |
316 | ||
317 | if (channels_hi) | |
318 | c = manage_channel(card, irm_id, generation, channels_hi, | |
6fdc0370 SR |
319 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI, |
320 | allocate, buffer); | |
b1bda4cd JFSR |
321 | if (channels_lo && c < 0) { |
322 | c = manage_channel(card, irm_id, generation, channels_lo, | |
6fdc0370 SR |
323 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO, |
324 | allocate, buffer); | |
b1bda4cd JFSR |
325 | if (c >= 0) |
326 | c += 32; | |
327 | } | |
328 | *channel = c; | |
329 | ||
5d9cb7d2 | 330 | if (allocate && channels_mask != 0 && c < 0) |
b1bda4cd JFSR |
331 | *bandwidth = 0; |
332 | ||
333 | if (*bandwidth == 0) | |
334 | return; | |
335 | ||
6fdc0370 SR |
336 | ret = manage_bandwidth(card, irm_id, generation, *bandwidth, |
337 | allocate, buffer); | |
b1bda4cd JFSR |
338 | if (ret < 0) |
339 | *bandwidth = 0; | |
340 | ||
cf36df6b CL |
341 | if (allocate && ret < 0) { |
342 | if (c >= 0) | |
343 | deallocate_channel(card, irm_id, generation, c, buffer); | |
b1bda4cd JFSR |
344 | *channel = ret; |
345 | } | |
346 | } |