[linux-2.6-block.git] / drivers / extcon / extcon-intel-cht-wc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
 *
 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
 * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
 */

#include <linux/extcon-provider.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#include "extcon-intel.h"

#define CHT_WC_PHYCTRL			0x5e07

#define CHT_WC_CHGRCTRL0		0x5e16
#define CHT_WC_CHGRCTRL0_CHGRRESET	BIT(0)
#define CHT_WC_CHGRCTRL0_EMRGCHREN	BIT(1)
#define CHT_WC_CHGRCTRL0_EXTCHRDIS	BIT(2)
#define CHT_WC_CHGRCTRL0_SWCONTROL	BIT(3)
#define CHT_WC_CHGRCTRL0_TTLCK		BIT(4)
#define CHT_WC_CHGRCTRL0_CCSM_OFF	BIT(5)
#define CHT_WC_CHGRCTRL0_DBPOFF		BIT(6)
#define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK	BIT(7)

#define CHT_WC_CHGRCTRL1			0x5e17
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_100		BIT(0)
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_150		BIT(1)
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_500		BIT(2)
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_900		BIT(3)
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500	BIT(4)
#define CHT_WC_CHGRCTRL1_FTEMP_EVENT		BIT(5)
#define CHT_WC_CHGRCTRL1_OTGMODE		BIT(6)
#define CHT_WC_CHGRCTRL1_DBPEN			BIT(7)

#define CHT_WC_USBSRC			0x5e29
#define CHT_WC_USBSRC_STS_MASK		GENMASK(1, 0)
#define CHT_WC_USBSRC_STS_SUCCESS	2
#define CHT_WC_USBSRC_STS_FAIL		3
#define CHT_WC_USBSRC_TYPE_SHIFT	2
#define CHT_WC_USBSRC_TYPE_MASK		GENMASK(5, 2)
#define CHT_WC_USBSRC_TYPE_NONE		0
#define CHT_WC_USBSRC_TYPE_SDP		1
#define CHT_WC_USBSRC_TYPE_DCP		2
#define CHT_WC_USBSRC_TYPE_CDP		3
#define CHT_WC_USBSRC_TYPE_ACA		4
#define CHT_WC_USBSRC_TYPE_SE1		5
#define CHT_WC_USBSRC_TYPE_MHL		6
#define CHT_WC_USBSRC_TYPE_FLOATING	7
#define CHT_WC_USBSRC_TYPE_OTHER	8
#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY	9

#define CHT_WC_CHGDISCTRL		0x5e2f
#define CHT_WC_CHGDISCTRL_OUT		BIT(0)
/* 0 - open drain, 1 - regular push-pull output */
#define CHT_WC_CHGDISCTRL_DRV		BIT(4)
/* 0 - pin is controlled by SW, 1 - by HW */
#define CHT_WC_CHGDISCTRL_FN		BIT(6)

#define CHT_WC_PWRSRC_IRQ		0x6e03
#define CHT_WC_PWRSRC_IRQ_MASK		0x6e0f
#define CHT_WC_PWRSRC_STS		0x6e1e
#define CHT_WC_PWRSRC_VBUS		BIT(0)
#define CHT_WC_PWRSRC_DC		BIT(1)
#define CHT_WC_PWRSRC_BATT		BIT(2)
#define CHT_WC_PWRSRC_USBID_MASK	GENMASK(4, 3)
#define CHT_WC_PWRSRC_USBID_SHIFT	3
#define CHT_WC_PWRSRC_RID_ACA		0
#define CHT_WC_PWRSRC_RID_GND		1
#define CHT_WC_PWRSRC_RID_FLOAT		2

#define CHT_WC_VBUS_GPIO_CTLO		0x6e2d
#define CHT_WC_VBUS_GPIO_CTLO_OUTPUT	BIT(0)
#define CHT_WC_VBUS_GPIO_CTLO_DRV_OD	BIT(4)
#define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT	BIT(5)

enum cht_wc_mux_select {
	MUX_SEL_PMIC = 0,
	MUX_SEL_SOC,
};

static const unsigned int cht_wc_extcon_cables[] = {
	EXTCON_USB,
	EXTCON_USB_HOST,
	EXTCON_CHG_USB_SDP,
	EXTCON_CHG_USB_CDP,
	EXTCON_CHG_USB_DCP,
	EXTCON_CHG_USB_ACA,
	EXTCON_NONE,
};

struct cht_wc_extcon_data {
	struct device *dev;
	struct regmap *regmap;
	struct extcon_dev *edev;
	unsigned int previous_cable;
	bool usb_host;
};

static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
{
	switch ((pwrsrc_sts & CHT_WC_PWRSRC_USBID_MASK) >> CHT_WC_PWRSRC_USBID_SHIFT) {
	case CHT_WC_PWRSRC_RID_GND:
		return INTEL_USB_ID_GND;
	case CHT_WC_PWRSRC_RID_FLOAT:
		return INTEL_USB_ID_FLOAT;
	case CHT_WC_PWRSRC_RID_ACA:
	default:
		/*
		 * Once we have IIO support for the GPADC we should read
		 * the USBID GPADC channel here and determine ACA role
		 * based on that.
		 */
		return INTEL_USB_ID_FLOAT;
	}
}

static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
				     bool ignore_errors)
{
	int ret, usbsrc, status;
	unsigned long timeout;

	/* Charger detection can take upto 600ms, wait 800ms max. */
	timeout = jiffies + msecs_to_jiffies(800);
	do {
		ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
		if (ret) {
			dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
			return ret;
		}

		status = usbsrc & CHT_WC_USBSRC_STS_MASK;
		if (status == CHT_WC_USBSRC_STS_SUCCESS ||
		    status == CHT_WC_USBSRC_STS_FAIL)
			break;

		msleep(50); /* Wait a bit before retrying */
	} while (time_before(jiffies, timeout));

	if (status != CHT_WC_USBSRC_STS_SUCCESS) {
		if (ignore_errors)
			return EXTCON_CHG_USB_SDP; /* Save fallback */

		if (status == CHT_WC_USBSRC_STS_FAIL)
			dev_warn(ext->dev, "Could not detect charger type\n");
		else
			dev_warn(ext->dev, "Timeout detecting charger type\n");
		return EXTCON_CHG_USB_SDP; /* Save fallback */
	}

	usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
	switch (usbsrc) {
	default:
		dev_warn(ext->dev,
			"Unhandled charger type %d, defaulting to SDP\n",
			 ret);
		return EXTCON_CHG_USB_SDP;
	case CHT_WC_USBSRC_TYPE_SDP:
	case CHT_WC_USBSRC_TYPE_FLOATING:
	case CHT_WC_USBSRC_TYPE_OTHER:
		return EXTCON_CHG_USB_SDP;
	case CHT_WC_USBSRC_TYPE_CDP:
		return EXTCON_CHG_USB_CDP;
	case CHT_WC_USBSRC_TYPE_DCP:
	case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
	case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
		return EXTCON_CHG_USB_DCP;
	case CHT_WC_USBSRC_TYPE_ACA:
		return EXTCON_CHG_USB_ACA;
	}
}

static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
{
	int ret;

	ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
	if (ret)
		dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
}

static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
				       bool enable)
{
	int ret, val;

	/*
	 * The 5V boost converter is enabled through a gpio on the PMIC, since
	 * there currently is no gpio driver we access the gpio reg directly.
	 */
	val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT;
	if (enable)
		val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT;

	ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val);
	if (ret)
		dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
}

static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
				      bool enable)
{
	unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0;
	int ret;

	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL1,
				 CHT_WC_CHGRCTRL1_OTGMODE, val);
	if (ret)
		dev_err(ext->dev, "Error updating CHGRCTRL1 reg: %d\n", ret);
}

static void cht_wc_extcon_enable_charging(struct cht_wc_extcon_data *ext,
					  bool enable)
{
	unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT;
	int ret;

	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
				 CHT_WC_CHGDISCTRL_OUT, val);
	if (ret)
		dev_err(ext->dev, "Error updating CHGDISCTRL reg: %d\n", ret);
}

/* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
				    unsigned int cable, bool state)
{
	extcon_set_state_sync(ext->edev, cable, state);
	if (cable == EXTCON_CHG_USB_SDP)
		extcon_set_state_sync(ext->edev, EXTCON_USB, state);
}

static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
{
	int ret, pwrsrc_sts, id;
	unsigned int cable = EXTCON_NONE;
	/* Ignore errors in host mode, as the 5v boost converter is on then */
	bool ignore_get_charger_errors = ext->usb_host;

	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
	if (ret) {
		dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
		return;
	}

	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
	if (id == INTEL_USB_ID_GND) {
		cht_wc_extcon_enable_charging(ext, false);
		cht_wc_extcon_set_otgmode(ext, true);

		/* The 5v boost causes a false VBUS / SDP detect, skip */
		goto charger_det_done;
	}

	cht_wc_extcon_set_otgmode(ext, false);
	cht_wc_extcon_enable_charging(ext, true);

	/* Plugged into a host/charger or not connected? */
	if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
		/* Route D+ and D- to PMIC for future charger detection */
		cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
		goto set_state;
	}

	ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors);
	if (ret >= 0)
		cable = ret;

charger_det_done:
	/* Route D+ and D- to SoC for the host or gadget controller */
	cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);

set_state:
	if (cable != ext->previous_cable) {
		cht_wc_extcon_set_state(ext, cable, true);
		cht_wc_extcon_set_state(ext, ext->previous_cable, false);
		ext->previous_cable = cable;
	}

	ext->usb_host = ((id == INTEL_USB_ID_GND) || (id == INTEL_USB_RID_A));
	extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
}

static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
{
	struct cht_wc_extcon_data *ext = data;
	int ret, irqs;

	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
	if (ret) {
		dev_err(ext->dev, "Error reading irqs: %d\n", ret);
		return IRQ_NONE;
	}

	cht_wc_extcon_pwrsrc_event(ext);

	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
	if (ret) {
		dev_err(ext->dev, "Error writing irqs: %d\n", ret);
		return IRQ_NONE;
	}

	return IRQ_HANDLED;
}

static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
{
	int ret, mask, val;

	val = enable ? 0 : CHT_WC_CHGDISCTRL_FN;
	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
				 CHT_WC_CHGDISCTRL_FN, val);
	if (ret)
		dev_err(ext->dev,
			"Error setting sw control for CHGDIS pin: %d\n",
			ret);

	mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF;
	val = enable ? mask : 0;
	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
	if (ret)
		dev_err(ext->dev, "Error setting sw control: %d\n", ret);

	return ret;
}

static int cht_wc_extcon_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
	struct cht_wc_extcon_data *ext;
	unsigned long mask = ~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_USBID_MASK);
	int pwrsrc_sts, id;
	int irq, ret;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
	if (!ext)
		return -ENOMEM;

	ext->dev = &pdev->dev;
	ext->regmap = pmic->regmap;
	ext->previous_cable = EXTCON_NONE;

	/* Initialize extcon device */
	ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
	if (IS_ERR(ext->edev))
		return PTR_ERR(ext->edev);

	switch (pmic->cht_wc_model) {
	case INTEL_CHT_WC_GPD_WIN_POCKET:
		/*
		 * When a host-cable is detected the BIOS enables an external 5v boost
		 * converter to power connected devices there are 2 problems with this:
		 * 1) This gets seen by the external battery charger as a valid Vbus
		 *    supply and it then tries to feed Vsys from this creating a
		 *    feedback loop which causes aprox. 300 mA extra battery drain
		 *    (and unless we drive the external-charger-disable pin high it
		 *    also tries to charge the battery causing even more feedback).
		 * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
		 * Since the external battery charger has its own 5v boost converter
		 * which does not have these issues, we simply turn the separate
		 * external 5v boost converter off and leave it off entirely.
		 */
		cht_wc_extcon_set_5v_boost(ext, false);
		break;
	default:
		break;
	}

	/* Enable sw control */
	ret = cht_wc_extcon_sw_control(ext, true);
	if (ret)
		goto disable_sw_control;

	/* Disable charging by external battery charger */
	cht_wc_extcon_enable_charging(ext, false);

	/* Register extcon device */
	ret = devm_extcon_dev_register(ext->dev, ext->edev);
	if (ret) {
		dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
		goto disable_sw_control;
	}

	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
	if (ret) {
		dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
		goto disable_sw_control;
	}

	/*
	 * If no USB host or device connected, route D+ and D- to PMIC for
	 * initial charger detection
	 */
	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
	if (id != INTEL_USB_ID_GND)
		cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);

	/* Get initial state */
	cht_wc_extcon_pwrsrc_event(ext);

	ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
					IRQF_ONESHOT, pdev->name, ext);
	if (ret) {
		dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
		goto disable_sw_control;
	}

	/* Unmask irqs */
	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, mask);
	if (ret) {
		dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
		goto disable_sw_control;
	}

	platform_set_drvdata(pdev, ext);

	return 0;

disable_sw_control:
	cht_wc_extcon_sw_control(ext, false);
	return ret;
}

static int cht_wc_extcon_remove(struct platform_device *pdev)
{
	struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);

	cht_wc_extcon_sw_control(ext, false);

	return 0;
}

static const struct platform_device_id cht_wc_extcon_table[] = {
	{ .name = "cht_wcove_pwrsrc" },
	{},
};
MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);

static struct platform_driver cht_wc_extcon_driver = {
	.probe = cht_wc_extcon_probe,
	.remove = cht_wc_extcon_remove,
	.id_table = cht_wc_extcon_table,
	.driver = {
		.name = "cht_wcove_pwrsrc",
	},
};
module_platform_driver(cht_wc_extcon_driver);

MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
900ed555	1	// SPDX-License-Identifier: GPL-2.0
db0f3baa HG	2	/*
	3	* Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
	4	* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
	5	*
	6	* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
	7	* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
db0f3baa HG	8	*/
db0f3baa HG	9
176aa360	10	#include <linux/extcon-provider.h>
db0f3baa HG	11	#include <linux/interrupt.h>
	12	#include <linux/kernel.h>
	13	#include <linux/mfd/intel_soc_pmic.h>
	14	#include <linux/module.h>
ac316725	15	#include <linux/mod_devicetable.h>
db0f3baa	16	#include <linux/platform_device.h>
b910a9ce	17	#include <linux/property.h>
db0f3baa HG	18	#include <linux/regmap.h>
	19	#include <linux/slab.h>
	20
098b7ae8 AS	21	#include "extcon-intel.h"
098b7ae8 AS	22
db0f3baa HG	23	#define CHT_WC_PHYCTRL 0x5e07
	24
	25	#define CHT_WC_CHGRCTRL0 0x5e16
	26	#define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
	27	#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
	28	#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
	29	#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
001d3ecc AS	30	#define CHT_WC_CHGRCTRL0_TTLCK BIT(4)
	31	#define CHT_WC_CHGRCTRL0_CCSM_OFF BIT(5)
	32	#define CHT_WC_CHGRCTRL0_DBPOFF BIT(6)
	33	#define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK BIT(7)
db0f3baa	34
3137301b YK	35	#define CHT_WC_CHGRCTRL1 0x5e17
	36	#define CHT_WC_CHGRCTRL1_FUSB_INLMT_100 BIT(0)
	37	#define CHT_WC_CHGRCTRL1_FUSB_INLMT_150 BIT(1)
	38	#define CHT_WC_CHGRCTRL1_FUSB_INLMT_500 BIT(2)
	39	#define CHT_WC_CHGRCTRL1_FUSB_INLMT_900 BIT(3)
	40	#define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500 BIT(4)
	41	#define CHT_WC_CHGRCTRL1_FTEMP_EVENT BIT(5)
	42	#define CHT_WC_CHGRCTRL1_OTGMODE BIT(6)
	43	#define CHT_WC_CHGRCTRL1_DBPEN BIT(7)
db0f3baa HG	44
	45	#define CHT_WC_USBSRC 0x5e29
	46	#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
	47	#define CHT_WC_USBSRC_STS_SUCCESS 2
	48	#define CHT_WC_USBSRC_STS_FAIL 3
	49	#define CHT_WC_USBSRC_TYPE_SHIFT 2
	50	#define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2)
	51	#define CHT_WC_USBSRC_TYPE_NONE 0
	52	#define CHT_WC_USBSRC_TYPE_SDP 1
	53	#define CHT_WC_USBSRC_TYPE_DCP 2
	54	#define CHT_WC_USBSRC_TYPE_CDP 3
	55	#define CHT_WC_USBSRC_TYPE_ACA 4
	56	#define CHT_WC_USBSRC_TYPE_SE1 5
	57	#define CHT_WC_USBSRC_TYPE_MHL 6
001d3ecc	58	#define CHT_WC_USBSRC_TYPE_FLOATING 7
db0f3baa HG	59	#define CHT_WC_USBSRC_TYPE_OTHER 8
	60	#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
	61
a72a1be0 YK	62	#define CHT_WC_CHGDISCTRL 0x5e2f
	63	#define CHT_WC_CHGDISCTRL_OUT BIT(0)
	64	/* 0 - open drain, 1 - regular push-pull output */
	65	#define CHT_WC_CHGDISCTRL_DRV BIT(4)
	66	/* 0 - pin is controlled by SW, 1 - by HW */
	67	#define CHT_WC_CHGDISCTRL_FN BIT(6)
	68
db0f3baa HG	69	#define CHT_WC_PWRSRC_IRQ 0x6e03
	70	#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
	71	#define CHT_WC_PWRSRC_STS 0x6e1e
	72	#define CHT_WC_PWRSRC_VBUS BIT(0)
	73	#define CHT_WC_PWRSRC_DC BIT(1)
001d3ecc	74	#define CHT_WC_PWRSRC_BATT BIT(2)
a4722503 AS	75	#define CHT_WC_PWRSRC_USBID_MASK GENMASK(4, 3)
	76	#define CHT_WC_PWRSRC_USBID_SHIFT 3
	77	#define CHT_WC_PWRSRC_RID_ACA 0
	78	#define CHT_WC_PWRSRC_RID_GND 1
	79	#define CHT_WC_PWRSRC_RID_FLOAT 2
db0f3baa	80
585cb239 HG	81	#define CHT_WC_VBUS_GPIO_CTLO 0x6e2d
585cb239 HG	82	#define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0)
ad49aee4 HG	83	#define CHT_WC_VBUS_GPIO_CTLO_DRV_OD BIT(4)
ad49aee4 HG	84	#define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT BIT(5)
585cb239	85
db0f3baa HG	86	enum cht_wc_mux_select {
	87	MUX_SEL_PMIC = 0,
	88	MUX_SEL_SOC,
	89	};
	90
	91	static const unsigned int cht_wc_extcon_cables[] = {
	92	EXTCON_USB,
	93	EXTCON_USB_HOST,
	94	EXTCON_CHG_USB_SDP,
	95	EXTCON_CHG_USB_CDP,
	96	EXTCON_CHG_USB_DCP,
	97	EXTCON_CHG_USB_ACA,
	98	EXTCON_NONE,
	99	};
	100
	101	struct cht_wc_extcon_data {
	102	struct device *dev;
	103	struct regmap *regmap;
	104	struct extcon_dev *edev;
	105	unsigned int previous_cable;
c42a880c	106	bool usb_host;
db0f3baa HG	107	};
	108
	109	static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
	110	{
a4722503 AS	111	switch ((pwrsrc_sts & CHT_WC_PWRSRC_USBID_MASK) >> CHT_WC_PWRSRC_USBID_SHIFT) {
a4722503 AS	112	case CHT_WC_PWRSRC_RID_GND:
098b7ae8	113	return INTEL_USB_ID_GND;
a4722503	114	case CHT_WC_PWRSRC_RID_FLOAT:
098b7ae8	115	return INTEL_USB_ID_FLOAT;
a4722503 AS	116	case CHT_WC_PWRSRC_RID_ACA:
	117	default:
	118	/*
	119	* Once we have IIO support for the GPADC we should read
	120	* the USBID GPADC channel here and determine ACA role
	121	* based on that.
	122	*/
098b7ae8	123	return INTEL_USB_ID_FLOAT;
a4722503	124	}
db0f3baa HG	125	}
db0f3baa HG	126
c42a880c HG	127	static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
c42a880c HG	128	bool ignore_errors)
db0f3baa HG	129	{
	130	int ret, usbsrc, status;
	131	unsigned long timeout;
	132
	133	/* Charger detection can take upto 600ms, wait 800ms max. */
	134	timeout = jiffies + msecs_to_jiffies(800);
	135	do {
	136	ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
	137	if (ret) {
	138	dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
	139	return ret;
	140	}
	141
	142	status = usbsrc & CHT_WC_USBSRC_STS_MASK;
	143	if (status == CHT_WC_USBSRC_STS_SUCCESS \|\|
	144	status == CHT_WC_USBSRC_STS_FAIL)
	145	break;
	146
	147	msleep(50); /* Wait a bit before retrying */
	148	} while (time_before(jiffies, timeout));
	149
	150	if (status != CHT_WC_USBSRC_STS_SUCCESS) {
c42a880c HG	151	if (ignore_errors)
	152	return EXTCON_CHG_USB_SDP; /* Save fallback */
	153
db0f3baa HG	154	if (status == CHT_WC_USBSRC_STS_FAIL)
	155	dev_warn(ext->dev, "Could not detect charger type\n");
	156	else
	157	dev_warn(ext->dev, "Timeout detecting charger type\n");
	158	return EXTCON_CHG_USB_SDP; /* Save fallback */
	159	}
	160
	161	usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
	162	switch (usbsrc) {
	163	default:
	164	dev_warn(ext->dev,
	165	"Unhandled charger type %d, defaulting to SDP\n",
	166	ret);
962341b5	167	return EXTCON_CHG_USB_SDP;
db0f3baa	168	case CHT_WC_USBSRC_TYPE_SDP:
001d3ecc	169	case CHT_WC_USBSRC_TYPE_FLOATING:
db0f3baa HG	170	case CHT_WC_USBSRC_TYPE_OTHER:
	171	return EXTCON_CHG_USB_SDP;
	172	case CHT_WC_USBSRC_TYPE_CDP:
	173	return EXTCON_CHG_USB_CDP;
	174	case CHT_WC_USBSRC_TYPE_DCP:
	175	case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
	176	case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
	177	return EXTCON_CHG_USB_DCP;
	178	case CHT_WC_USBSRC_TYPE_ACA:
	179	return EXTCON_CHG_USB_ACA;
	180	}
	181	}
	182
	183	static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
	184	{
	185	int ret;
	186
	187	ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
	188	if (ret)
	189	dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
	190	}
	191
585cb239 HG	192	static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
	193	bool enable)
	194	{
	195	int ret, val;
	196
585cb239 HG	197	/*
	198	* The 5V boost converter is enabled through a gpio on the PMIC, since
	199	* there currently is no gpio driver we access the gpio reg directly.
	200	*/
ad49aee4 HG	201	val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD \| CHT_WC_VBUS_GPIO_CTLO_DIR_OUT;
	202	if (enable)
	203	val \|= CHT_WC_VBUS_GPIO_CTLO_OUTPUT;
	204
	205	ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val);
585cb239 HG	206	if (ret)
	207	dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
	208	}
	209
3137301b YK	210	static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
	211	bool enable)
	212	{
	213	unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0;
	214	int ret;
	215
	216	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL1,
	217	CHT_WC_CHGRCTRL1_OTGMODE, val);
	218	if (ret)
	219	dev_err(ext->dev, "Error updating CHGRCTRL1 reg: %d\n", ret);
	220	}
	221
a72a1be0 YK	222	static void cht_wc_extcon_enable_charging(struct cht_wc_extcon_data *ext,
	223	bool enable)
	224	{
	225	unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT;
	226	int ret;
	227
	228	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
	229	CHT_WC_CHGDISCTRL_OUT, val);
	230	if (ret)
	231	dev_err(ext->dev, "Error updating CHGDISCTRL reg: %d\n", ret);
	232	}
	233
db0f3baa HG	234	/* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
	235	static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
	236	unsigned int cable, bool state)
	237	{
	238	extcon_set_state_sync(ext->edev, cable, state);
	239	if (cable == EXTCON_CHG_USB_SDP)
	240	extcon_set_state_sync(ext->edev, EXTCON_USB, state);
	241	}
	242
	243	static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
	244	{
	245	int ret, pwrsrc_sts, id;
	246	unsigned int cable = EXTCON_NONE;
c42a880c HG	247	/* Ignore errors in host mode, as the 5v boost converter is on then */
c42a880c HG	248	bool ignore_get_charger_errors = ext->usb_host;
db0f3baa HG	249
	250	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
	251	if (ret) {
	252	dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
	253	return;
	254	}
	255
	256	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
098b7ae8	257	if (id == INTEL_USB_ID_GND) {
a72a1be0	258	cht_wc_extcon_enable_charging(ext, false);
3137301b YK	259	cht_wc_extcon_set_otgmode(ext, true);
3137301b YK	260
db0f3baa HG	261	/* The 5v boost causes a false VBUS / SDP detect, skip */
	262	goto charger_det_done;
	263	}
	264
3137301b	265	cht_wc_extcon_set_otgmode(ext, false);
a72a1be0	266	cht_wc_extcon_enable_charging(ext, true);
3137301b	267
db0f3baa HG	268	/* Plugged into a host/charger or not connected? */
	269	if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
	270	/* Route D+ and D- to PMIC for future charger detection */
	271	cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
	272	goto set_state;
	273	}
	274
c42a880c	275	ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors);
db0f3baa HG	276	if (ret >= 0)
	277	cable = ret;
	278
	279	charger_det_done:
	280	/* Route D+ and D- to SoC for the host or gadget controller */
	281	cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);
	282
	283	set_state:
	284	if (cable != ext->previous_cable) {
	285	cht_wc_extcon_set_state(ext, cable, true);
	286	cht_wc_extcon_set_state(ext, ext->previous_cable, false);
	287	ext->previous_cable = cable;
	288	}
	289
098b7ae8	290	ext->usb_host = ((id == INTEL_USB_ID_GND) \|\| (id == INTEL_USB_RID_A));
c42a880c	291	extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
db0f3baa HG	292	}
	293
	294	static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
	295	{
	296	struct cht_wc_extcon_data *ext = data;
	297	int ret, irqs;
	298
	299	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
	300	if (ret) {
	301	dev_err(ext->dev, "Error reading irqs: %d\n", ret);
	302	return IRQ_NONE;
	303	}
	304
	305	cht_wc_extcon_pwrsrc_event(ext);
	306
	307	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
	308	if (ret) {
	309	dev_err(ext->dev, "Error writing irqs: %d\n", ret);
	310	return IRQ_NONE;
	311	}
	312
	313	return IRQ_HANDLED;
	314	}
	315
	316	static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
	317	{
	318	int ret, mask, val;
	319
a72a1be0 YK	320	val = enable ? 0 : CHT_WC_CHGDISCTRL_FN;
	321	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
	322	CHT_WC_CHGDISCTRL_FN, val);
	323	if (ret)
	324	dev_err(ext->dev,
	325	"Error setting sw control for CHGDIS pin: %d\n",
	326	ret);
	327
001d3ecc	328	mask = CHT_WC_CHGRCTRL0_SWCONTROL \| CHT_WC_CHGRCTRL0_CCSM_OFF;
db0f3baa HG	329	val = enable ? mask : 0;
	330	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
	331	if (ret)
	332	dev_err(ext->dev, "Error setting sw control: %d\n", ret);
	333
	334	return ret;
	335	}
	336
	337	static int cht_wc_extcon_probe(struct platform_device *pdev)
	338	{
	339	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
	340	struct cht_wc_extcon_data *ext;
a4722503	341	unsigned long mask = ~(CHT_WC_PWRSRC_VBUS \| CHT_WC_PWRSRC_USBID_MASK);
e81b8893	342	int pwrsrc_sts, id;
db0f3baa HG	343	int irq, ret;
	344
	345	irq = platform_get_irq(pdev, 0);
	346	if (irq < 0)
	347	return irq;
	348
	349	ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
	350	if (!ext)
	351	return -ENOMEM;
	352
	353	ext->dev = &pdev->dev;
	354	ext->regmap = pmic->regmap;
	355	ext->previous_cable = EXTCON_NONE;
	356
	357	/* Initialize extcon device */
	358	ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
	359	if (IS_ERR(ext->edev))
	360	return PTR_ERR(ext->edev);
	361
b910a9ce HG	362	switch (pmic->cht_wc_model) {
	363	case INTEL_CHT_WC_GPD_WIN_POCKET:
	364	/*
	365	* When a host-cable is detected the BIOS enables an external 5v boost
	366	* converter to power connected devices there are 2 problems with this:
	367	* 1) This gets seen by the external battery charger as a valid Vbus
	368	* supply and it then tries to feed Vsys from this creating a
	369	* feedback loop which causes aprox. 300 mA extra battery drain
	370	* (and unless we drive the external-charger-disable pin high it
	371	* also tries to charge the battery causing even more feedback).
	372	* 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
	373	* Since the external battery charger has its own 5v boost converter
	374	* which does not have these issues, we simply turn the separate
	375	* external 5v boost converter off and leave it off entirely.
	376	*/
	377	cht_wc_extcon_set_5v_boost(ext, false);
	378	break;
	379	default:
	380	break;
	381	}
585cb239	382
db0f3baa HG	383	/* Enable sw control */
	384	ret = cht_wc_extcon_sw_control(ext, true);
	385	if (ret)
a72a1be0 YK	386	goto disable_sw_control;
	387
	388	/* Disable charging by external battery charger */
	389	cht_wc_extcon_enable_charging(ext, false);
db0f3baa HG	390
	391	/* Register extcon device */
	392	ret = devm_extcon_dev_register(ext->dev, ext->edev);
	393	if (ret) {
	394	dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
	395	goto disable_sw_control;
	396	}
	397
e81b8893 YK	398	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
	399	if (ret) {
	400	dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
	401	goto disable_sw_control;
	402	}
	403
	404	/*
	405	* If no USB host or device connected, route D+ and D- to PMIC for
	406	* initial charger detection
	407	*/
	408	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
	409	if (id != INTEL_USB_ID_GND)
	410	cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
db0f3baa HG	411
	412	/* Get initial state */
	413	cht_wc_extcon_pwrsrc_event(ext);
	414
	415	ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
	416	IRQF_ONESHOT, pdev->name, ext);
	417	if (ret) {
	418	dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
	419	goto disable_sw_control;
	420	}
	421
	422	/* Unmask irqs */
a4722503	423	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, mask);
db0f3baa HG	424	if (ret) {
	425	dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
	426	goto disable_sw_control;
	427	}
	428
	429	platform_set_drvdata(pdev, ext);
	430
	431	return 0;
	432
	433	disable_sw_control:
	434	cht_wc_extcon_sw_control(ext, false);
	435	return ret;
	436	}
	437
	438	static int cht_wc_extcon_remove(struct platform_device *pdev)
	439	{
	440	struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);
	441
	442	cht_wc_extcon_sw_control(ext, false);
	443
	444	return 0;
	445	}
	446
	447	static const struct platform_device_id cht_wc_extcon_table[] = {
	448	{ .name = "cht_wcove_pwrsrc" },
	449	{},
	450	};
	451	MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
	452
	453	static struct platform_driver cht_wc_extcon_driver = {
	454	.probe = cht_wc_extcon_probe,
	455	.remove = cht_wc_extcon_remove,
	456	.id_table = cht_wc_extcon_table,
	457	.driver = {
	458	.name = "cht_wcove_pwrsrc",
	459	},
	460	};
	461	module_platform_driver(cht_wc_extcon_driver);
	462
	463	MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
	464	MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
	465	MODULE_LICENSE("GPL v2");