Commit | Line | Data |
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db0f3baa HG |
1 | /* |
2 | * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC | |
3 | * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> | |
4 | * | |
5 | * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: | |
6 | * Copyright (C) 2013-2015 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | */ | |
17 | ||
176aa360 | 18 | #include <linux/extcon-provider.h> |
db0f3baa HG |
19 | #include <linux/interrupt.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mfd/intel_soc_pmic.h> | |
22 | #include <linux/module.h> | |
ac316725 | 23 | #include <linux/mod_devicetable.h> |
db0f3baa HG |
24 | #include <linux/platform_device.h> |
25 | #include <linux/regmap.h> | |
26 | #include <linux/slab.h> | |
27 | ||
28 | #define CHT_WC_PHYCTRL 0x5e07 | |
29 | ||
30 | #define CHT_WC_CHGRCTRL0 0x5e16 | |
31 | #define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0) | |
32 | #define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1) | |
33 | #define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2) | |
34 | #define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3) | |
35 | #define CHT_WC_CHGRCTRL0_TTLCK_MASK BIT(4) | |
36 | #define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5) | |
37 | #define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6) | |
38 | #define CHT_WC_CHGRCTRL0_WDT_NOKICK BIT(7) | |
39 | ||
40 | #define CHT_WC_CHGRCTRL1 0x5e17 | |
41 | ||
42 | #define CHT_WC_USBSRC 0x5e29 | |
43 | #define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0) | |
44 | #define CHT_WC_USBSRC_STS_SUCCESS 2 | |
45 | #define CHT_WC_USBSRC_STS_FAIL 3 | |
46 | #define CHT_WC_USBSRC_TYPE_SHIFT 2 | |
47 | #define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2) | |
48 | #define CHT_WC_USBSRC_TYPE_NONE 0 | |
49 | #define CHT_WC_USBSRC_TYPE_SDP 1 | |
50 | #define CHT_WC_USBSRC_TYPE_DCP 2 | |
51 | #define CHT_WC_USBSRC_TYPE_CDP 3 | |
52 | #define CHT_WC_USBSRC_TYPE_ACA 4 | |
53 | #define CHT_WC_USBSRC_TYPE_SE1 5 | |
54 | #define CHT_WC_USBSRC_TYPE_MHL 6 | |
55 | #define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7 | |
56 | #define CHT_WC_USBSRC_TYPE_OTHER 8 | |
57 | #define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9 | |
58 | ||
59 | #define CHT_WC_PWRSRC_IRQ 0x6e03 | |
60 | #define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f | |
61 | #define CHT_WC_PWRSRC_STS 0x6e1e | |
62 | #define CHT_WC_PWRSRC_VBUS BIT(0) | |
63 | #define CHT_WC_PWRSRC_DC BIT(1) | |
64 | #define CHT_WC_PWRSRC_BAT BIT(2) | |
65 | #define CHT_WC_PWRSRC_ID_GND BIT(3) | |
66 | #define CHT_WC_PWRSRC_ID_FLOAT BIT(4) | |
67 | ||
585cb239 HG |
68 | #define CHT_WC_VBUS_GPIO_CTLO 0x6e2d |
69 | #define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0) | |
ad49aee4 HG |
70 | #define CHT_WC_VBUS_GPIO_CTLO_DRV_OD BIT(4) |
71 | #define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT BIT(5) | |
585cb239 | 72 | |
db0f3baa HG |
73 | enum cht_wc_usb_id { |
74 | USB_ID_OTG, | |
75 | USB_ID_GND, | |
76 | USB_ID_FLOAT, | |
77 | USB_RID_A, | |
78 | USB_RID_B, | |
79 | USB_RID_C, | |
80 | }; | |
81 | ||
82 | enum cht_wc_mux_select { | |
83 | MUX_SEL_PMIC = 0, | |
84 | MUX_SEL_SOC, | |
85 | }; | |
86 | ||
87 | static const unsigned int cht_wc_extcon_cables[] = { | |
88 | EXTCON_USB, | |
89 | EXTCON_USB_HOST, | |
90 | EXTCON_CHG_USB_SDP, | |
91 | EXTCON_CHG_USB_CDP, | |
92 | EXTCON_CHG_USB_DCP, | |
93 | EXTCON_CHG_USB_ACA, | |
94 | EXTCON_NONE, | |
95 | }; | |
96 | ||
97 | struct cht_wc_extcon_data { | |
98 | struct device *dev; | |
99 | struct regmap *regmap; | |
100 | struct extcon_dev *edev; | |
101 | unsigned int previous_cable; | |
c42a880c | 102 | bool usb_host; |
db0f3baa HG |
103 | }; |
104 | ||
105 | static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts) | |
106 | { | |
107 | if (pwrsrc_sts & CHT_WC_PWRSRC_ID_GND) | |
108 | return USB_ID_GND; | |
109 | if (pwrsrc_sts & CHT_WC_PWRSRC_ID_FLOAT) | |
110 | return USB_ID_FLOAT; | |
111 | ||
112 | /* | |
113 | * Once we have iio support for the gpadc we should read the USBID | |
114 | * gpadc channel here and determine ACA role based on that. | |
115 | */ | |
116 | return USB_ID_FLOAT; | |
117 | } | |
118 | ||
c42a880c HG |
119 | static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext, |
120 | bool ignore_errors) | |
db0f3baa HG |
121 | { |
122 | int ret, usbsrc, status; | |
123 | unsigned long timeout; | |
124 | ||
125 | /* Charger detection can take upto 600ms, wait 800ms max. */ | |
126 | timeout = jiffies + msecs_to_jiffies(800); | |
127 | do { | |
128 | ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc); | |
129 | if (ret) { | |
130 | dev_err(ext->dev, "Error reading usbsrc: %d\n", ret); | |
131 | return ret; | |
132 | } | |
133 | ||
134 | status = usbsrc & CHT_WC_USBSRC_STS_MASK; | |
135 | if (status == CHT_WC_USBSRC_STS_SUCCESS || | |
136 | status == CHT_WC_USBSRC_STS_FAIL) | |
137 | break; | |
138 | ||
139 | msleep(50); /* Wait a bit before retrying */ | |
140 | } while (time_before(jiffies, timeout)); | |
141 | ||
142 | if (status != CHT_WC_USBSRC_STS_SUCCESS) { | |
c42a880c HG |
143 | if (ignore_errors) |
144 | return EXTCON_CHG_USB_SDP; /* Save fallback */ | |
145 | ||
db0f3baa HG |
146 | if (status == CHT_WC_USBSRC_STS_FAIL) |
147 | dev_warn(ext->dev, "Could not detect charger type\n"); | |
148 | else | |
149 | dev_warn(ext->dev, "Timeout detecting charger type\n"); | |
150 | return EXTCON_CHG_USB_SDP; /* Save fallback */ | |
151 | } | |
152 | ||
153 | usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT; | |
154 | switch (usbsrc) { | |
155 | default: | |
156 | dev_warn(ext->dev, | |
157 | "Unhandled charger type %d, defaulting to SDP\n", | |
158 | ret); | |
159 | /* Fall through, treat as SDP */ | |
160 | case CHT_WC_USBSRC_TYPE_SDP: | |
161 | case CHT_WC_USBSRC_TYPE_FLOAT_DP_DN: | |
162 | case CHT_WC_USBSRC_TYPE_OTHER: | |
163 | return EXTCON_CHG_USB_SDP; | |
164 | case CHT_WC_USBSRC_TYPE_CDP: | |
165 | return EXTCON_CHG_USB_CDP; | |
166 | case CHT_WC_USBSRC_TYPE_DCP: | |
167 | case CHT_WC_USBSRC_TYPE_DCP_EXTPHY: | |
168 | case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */ | |
169 | return EXTCON_CHG_USB_DCP; | |
170 | case CHT_WC_USBSRC_TYPE_ACA: | |
171 | return EXTCON_CHG_USB_ACA; | |
172 | } | |
173 | } | |
174 | ||
175 | static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state) | |
176 | { | |
177 | int ret; | |
178 | ||
179 | ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state); | |
180 | if (ret) | |
181 | dev_err(ext->dev, "Error writing phyctrl: %d\n", ret); | |
182 | } | |
183 | ||
585cb239 HG |
184 | static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext, |
185 | bool enable) | |
186 | { | |
187 | int ret, val; | |
188 | ||
585cb239 HG |
189 | /* |
190 | * The 5V boost converter is enabled through a gpio on the PMIC, since | |
191 | * there currently is no gpio driver we access the gpio reg directly. | |
192 | */ | |
ad49aee4 HG |
193 | val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT; |
194 | if (enable) | |
195 | val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT; | |
196 | ||
197 | ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val); | |
585cb239 HG |
198 | if (ret) |
199 | dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret); | |
200 | } | |
201 | ||
db0f3baa HG |
202 | /* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */ |
203 | static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext, | |
204 | unsigned int cable, bool state) | |
205 | { | |
206 | extcon_set_state_sync(ext->edev, cable, state); | |
207 | if (cable == EXTCON_CHG_USB_SDP) | |
208 | extcon_set_state_sync(ext->edev, EXTCON_USB, state); | |
209 | } | |
210 | ||
211 | static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext) | |
212 | { | |
213 | int ret, pwrsrc_sts, id; | |
214 | unsigned int cable = EXTCON_NONE; | |
c42a880c HG |
215 | /* Ignore errors in host mode, as the 5v boost converter is on then */ |
216 | bool ignore_get_charger_errors = ext->usb_host; | |
db0f3baa HG |
217 | |
218 | ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts); | |
219 | if (ret) { | |
220 | dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret); | |
221 | return; | |
222 | } | |
223 | ||
224 | id = cht_wc_extcon_get_id(ext, pwrsrc_sts); | |
225 | if (id == USB_ID_GND) { | |
226 | /* The 5v boost causes a false VBUS / SDP detect, skip */ | |
227 | goto charger_det_done; | |
228 | } | |
229 | ||
230 | /* Plugged into a host/charger or not connected? */ | |
231 | if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) { | |
232 | /* Route D+ and D- to PMIC for future charger detection */ | |
233 | cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC); | |
234 | goto set_state; | |
235 | } | |
236 | ||
c42a880c | 237 | ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors); |
db0f3baa HG |
238 | if (ret >= 0) |
239 | cable = ret; | |
240 | ||
241 | charger_det_done: | |
242 | /* Route D+ and D- to SoC for the host or gadget controller */ | |
243 | cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC); | |
244 | ||
245 | set_state: | |
246 | if (cable != ext->previous_cable) { | |
247 | cht_wc_extcon_set_state(ext, cable, true); | |
248 | cht_wc_extcon_set_state(ext, ext->previous_cable, false); | |
249 | ext->previous_cable = cable; | |
250 | } | |
251 | ||
c42a880c HG |
252 | ext->usb_host = ((id == USB_ID_GND) || (id == USB_RID_A)); |
253 | extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host); | |
db0f3baa HG |
254 | } |
255 | ||
256 | static irqreturn_t cht_wc_extcon_isr(int irq, void *data) | |
257 | { | |
258 | struct cht_wc_extcon_data *ext = data; | |
259 | int ret, irqs; | |
260 | ||
261 | ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs); | |
262 | if (ret) { | |
263 | dev_err(ext->dev, "Error reading irqs: %d\n", ret); | |
264 | return IRQ_NONE; | |
265 | } | |
266 | ||
267 | cht_wc_extcon_pwrsrc_event(ext); | |
268 | ||
269 | ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs); | |
270 | if (ret) { | |
271 | dev_err(ext->dev, "Error writing irqs: %d\n", ret); | |
272 | return IRQ_NONE; | |
273 | } | |
274 | ||
275 | return IRQ_HANDLED; | |
276 | } | |
277 | ||
278 | static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable) | |
279 | { | |
280 | int ret, mask, val; | |
281 | ||
282 | mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF_MASK; | |
283 | val = enable ? mask : 0; | |
284 | ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val); | |
285 | if (ret) | |
286 | dev_err(ext->dev, "Error setting sw control: %d\n", ret); | |
287 | ||
288 | return ret; | |
289 | } | |
290 | ||
291 | static int cht_wc_extcon_probe(struct platform_device *pdev) | |
292 | { | |
293 | struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); | |
294 | struct cht_wc_extcon_data *ext; | |
295 | int irq, ret; | |
296 | ||
297 | irq = platform_get_irq(pdev, 0); | |
298 | if (irq < 0) | |
299 | return irq; | |
300 | ||
301 | ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL); | |
302 | if (!ext) | |
303 | return -ENOMEM; | |
304 | ||
305 | ext->dev = &pdev->dev; | |
306 | ext->regmap = pmic->regmap; | |
307 | ext->previous_cable = EXTCON_NONE; | |
308 | ||
309 | /* Initialize extcon device */ | |
310 | ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables); | |
311 | if (IS_ERR(ext->edev)) | |
312 | return PTR_ERR(ext->edev); | |
313 | ||
585cb239 HG |
314 | /* |
315 | * When a host-cable is detected the BIOS enables an external 5v boost | |
316 | * converter to power connected devices there are 2 problems with this: | |
317 | * 1) This gets seen by the external battery charger as a valid Vbus | |
318 | * supply and it then tries to feed Vsys from this creating a | |
319 | * feedback loop which causes aprox. 300 mA extra battery drain | |
320 | * (and unless we drive the external-charger-disable pin high it | |
321 | * also tries to charge the battery causing even more feedback). | |
322 | * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply | |
323 | * Since the external battery charger has its own 5v boost converter | |
324 | * which does not have these issues, we simply turn the separate | |
325 | * external 5v boost converter off and leave it off entirely. | |
326 | */ | |
327 | cht_wc_extcon_set_5v_boost(ext, false); | |
328 | ||
db0f3baa HG |
329 | /* Enable sw control */ |
330 | ret = cht_wc_extcon_sw_control(ext, true); | |
331 | if (ret) | |
332 | return ret; | |
333 | ||
334 | /* Register extcon device */ | |
335 | ret = devm_extcon_dev_register(ext->dev, ext->edev); | |
336 | if (ret) { | |
337 | dev_err(ext->dev, "Error registering extcon device: %d\n", ret); | |
338 | goto disable_sw_control; | |
339 | } | |
340 | ||
341 | /* Route D+ and D- to PMIC for initial charger detection */ | |
342 | cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC); | |
343 | ||
344 | /* Get initial state */ | |
345 | cht_wc_extcon_pwrsrc_event(ext); | |
346 | ||
347 | ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr, | |
348 | IRQF_ONESHOT, pdev->name, ext); | |
349 | if (ret) { | |
350 | dev_err(ext->dev, "Error requesting interrupt: %d\n", ret); | |
351 | goto disable_sw_control; | |
352 | } | |
353 | ||
354 | /* Unmask irqs */ | |
355 | ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, | |
356 | (int)~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_ID_GND | | |
357 | CHT_WC_PWRSRC_ID_FLOAT)); | |
358 | if (ret) { | |
359 | dev_err(ext->dev, "Error writing irq-mask: %d\n", ret); | |
360 | goto disable_sw_control; | |
361 | } | |
362 | ||
363 | platform_set_drvdata(pdev, ext); | |
364 | ||
365 | return 0; | |
366 | ||
367 | disable_sw_control: | |
368 | cht_wc_extcon_sw_control(ext, false); | |
369 | return ret; | |
370 | } | |
371 | ||
372 | static int cht_wc_extcon_remove(struct platform_device *pdev) | |
373 | { | |
374 | struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev); | |
375 | ||
376 | cht_wc_extcon_sw_control(ext, false); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static const struct platform_device_id cht_wc_extcon_table[] = { | |
382 | { .name = "cht_wcove_pwrsrc" }, | |
383 | {}, | |
384 | }; | |
385 | MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table); | |
386 | ||
387 | static struct platform_driver cht_wc_extcon_driver = { | |
388 | .probe = cht_wc_extcon_probe, | |
389 | .remove = cht_wc_extcon_remove, | |
390 | .id_table = cht_wc_extcon_table, | |
391 | .driver = { | |
392 | .name = "cht_wcove_pwrsrc", | |
393 | }, | |
394 | }; | |
395 | module_platform_driver(cht_wc_extcon_driver); | |
396 | ||
397 | MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver"); | |
398 | MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); | |
399 | MODULE_LICENSE("GPL v2"); |