[linux-block.git] / drivers / edac / skx_common.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
 * Originally split out from the skx_edac driver.
 *
 * Copyright (c) 2018, Intel Corporation.
 */

#ifndef _SKX_COMM_EDAC_H
#define _SKX_COMM_EDAC_H

#include <linux/bits.h>
#include <asm/mce.h>

#define MSG_SIZE		1024

/*
 * Debug macros
 */
#define skx_printk(level, fmt, arg...)			\
	edac_printk(level, "skx", fmt, ##arg)

#define skx_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)

/*
 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
 */
#define GET_BITFIELD(v, lo, hi) \
	(((v) & GENMASK_ULL((hi), (lo))) >> (lo))

#define SKX_NUM_IMC		2	/* Memory controllers per socket */
#define SKX_NUM_CHANNELS	3	/* Channels per memory controller */
#define SKX_NUM_DIMMS		2	/* Max DIMMS per channel */

#define I10NM_NUM_DDR_IMC	12
#define I10NM_NUM_DDR_CHANNELS	2
#define I10NM_NUM_DDR_DIMMS	2

#define I10NM_NUM_HBM_IMC	16
#define I10NM_NUM_HBM_CHANNELS	2
#define I10NM_NUM_HBM_DIMMS	1

#define I10NM_NUM_IMC		(I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
#define I10NM_NUM_CHANNELS	MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
#define I10NM_NUM_DIMMS		MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)

#define NUM_IMC		MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
#define NUM_CHANNELS	MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
#define NUM_DIMMS	MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)

#define IS_DIMM_PRESENT(r)		GET_BITFIELD(r, 15, 15)
#define IS_NVDIMM_PRESENT(r, i)		GET_BITFIELD(r, i, i)

#define MCI_MISC_ECC_MODE(m)	(((m) >> 59) & 15)
#define MCI_MISC_ECC_DDRT	8	/* read from DDRT */

/*
 * According to Intel Architecture spec vol 3B,
 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
 * memory errors should fit one of these masks:
 *	000f 0000 1mmm cccc (binary)
 *	000f 0010 1mmm cccc (binary)	[RAM used as cache]
 * where:
 *	f = Correction Report Filtering Bit. If 1, subsequent errors
 *	    won't be shown
 *	mmm = error type
 *	cccc = channel
 */
#define MCACOD_MEM_ERR_MASK	0xef80
/*
 * Errors from either the memory of the 1-level memory system or the
 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
 */
#define MCACOD_MEM_CTL_ERR	0x80
/*
 * Errors from the 1st level memory (the fast "near" memory as cache)
 * of the 2-level memory system.
 */
#define MCACOD_EXT_MEM_ERR	0x280

/*
 * Each cpu socket contains some pci devices that provide global
 * information, and also some that are local to each of the two
 * memory controllers on the die.
 */
struct skx_dev {
	struct list_head list;
	u8 bus[4];
	int seg;
	struct pci_dev *sad_all;
	struct pci_dev *util_all;
	struct pci_dev *uracu; /* for i10nm CPU */
	struct pci_dev *pcu_cr3; /* for HBM memory detection */
	u32 mcroute;
	struct skx_imc {
		struct mem_ctl_info *mci;
		struct pci_dev *mdev; /* for i10nm CPU */
		void __iomem *mbase;  /* for i10nm CPU */
		int chan_mmio_sz;     /* for i10nm CPU */
		int num_channels; /* channels per memory controller */
		int num_dimms; /* dimms per channel */
		bool hbm_mc;
		u8 mc;	/* system wide mc# */
		u8 lmc;	/* socket relative mc# */
		u8 src_id, node_id;
		struct skx_channel {
			struct pci_dev	*cdev;
			struct pci_dev	*edev;
			u32 retry_rd_err_log_s;
			u32 retry_rd_err_log_d;
			u32 retry_rd_err_log_d2;
			struct skx_dimm {
				u8 close_pg;
				u8 bank_xor_enable;
				u8 fine_grain_bank;
				u8 rowbits;
				u8 colbits;
			} dimms[NUM_DIMMS];
		} chan[NUM_CHANNELS];
	} imc[NUM_IMC];
};

struct skx_pvt {
	struct skx_imc	*imc;
};

enum type {
	SKX,
	I10NM,
	SPR,
	GNR
};

enum {
	INDEX_SOCKET,
	INDEX_MEMCTRL,
	INDEX_CHANNEL,
	INDEX_DIMM,
	INDEX_CS,
	INDEX_NM_FIRST,
	INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
	INDEX_NM_CHANNEL,
	INDEX_NM_DIMM,
	INDEX_NM_CS,
	INDEX_MAX
};

#define BIT_NM_MEMCTRL	BIT_ULL(INDEX_NM_MEMCTRL)
#define BIT_NM_CHANNEL	BIT_ULL(INDEX_NM_CHANNEL)
#define BIT_NM_DIMM	BIT_ULL(INDEX_NM_DIMM)
#define BIT_NM_CS	BIT_ULL(INDEX_NM_CS)

struct decoded_addr {
	struct mce *mce;
	struct skx_dev *dev;
	u64	addr;
	int	socket;
	int	imc;
	int	channel;
	u64	chan_addr;
	int	sktways;
	int	chanways;
	int	dimm;
	int	cs;
	int	rank;
	int	channel_rank;
	u64	rank_address;
	int	row;
	int	column;
	int	bank_address;
	int	bank_group;
	bool	decoded_by_adxl;
};

struct pci_bdf {
	u32 bus : 8;
	u32 dev : 5;
	u32 fun : 3;
};

struct res_config {
	enum type type;
	/* Configuration agent device ID */
	unsigned int decs_did;
	/* Default bus number configuration register offset */
	int busno_cfg_offset;
	/* DDR memory controllers per socket */
	int ddr_imc_num;
	/* DDR channels per DDR memory controller */
	int ddr_chan_num;
	/* DDR DIMMs per DDR memory channel */
	int ddr_dimm_num;
	/* Per DDR channel memory-mapped I/O size */
	int ddr_chan_mmio_sz;
	/* HBM memory controllers per socket */
	int hbm_imc_num;
	/* HBM channels per HBM memory controller */
	int hbm_chan_num;
	/* HBM DIMMs per HBM memory channel */
	int hbm_dimm_num;
	/* Per HBM channel memory-mapped I/O size */
	int hbm_chan_mmio_sz;
	bool support_ddr5;
	/* SAD device BDF */
	struct pci_bdf sad_all_bdf;
	/* PCU device BDF */
	struct pci_bdf pcu_cr3_bdf;
	/* UTIL device BDF */
	struct pci_bdf util_all_bdf;
	/* URACU device BDF */
	struct pci_bdf uracu_bdf;
	/* DDR mdev device BDF */
	struct pci_bdf ddr_mdev_bdf;
	/* HBM mdev device BDF */
	struct pci_bdf hbm_mdev_bdf;
	int sad_all_offset;
	/* Offsets of retry_rd_err_log registers */
	u32 *offsets_scrub;
	u32 *offsets_scrub_hbm0;
	u32 *offsets_scrub_hbm1;
	u32 *offsets_demand;
	u32 *offsets_demand2;
	u32 *offsets_demand_hbm0;
	u32 *offsets_demand_hbm1;
};

typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
				 struct res_config *cfg);
typedef bool (*skx_decode_f)(struct decoded_addr *res);
typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);

int skx_adxl_get(void);
void skx_adxl_put(void);
void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
void skx_set_mem_cfg(bool mem_cfg_2lm);

int skx_get_src_id(struct skx_dev *d, int off, u8 *id);
int skx_get_node_id(struct skx_dev *d, u8 *id);

int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);

int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);

int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
		      struct skx_imc *imc, int chan, int dimmno,
		      struct res_config *cfg);

int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
			int chan, int dimmno, const char *mod_str);

int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
		     const char *ctl_name, const char *mod_str,
		     get_dimm_config_f get_dimm_config,
		     struct res_config *cfg);

int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
			void *data);

void skx_remove(void);

#ifdef CONFIG_EDAC_DEBUG
void skx_setup_debug(const char *name);
void skx_teardown_debug(void);
#else
static inline void skx_setup_debug(const char *name) {}
static inline void skx_teardown_debug(void) {}
#endif

#endif /* _SKX_COMM_EDAC_H */
Commit	Line	Data
88a242c9 QZ	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
	4	* Originally split out from the skx_edac driver.
	5	*
	6	* Copyright (c) 2018, Intel Corporation.
	7	*/
	8
	9	#ifndef _SKX_COMM_EDAC_H
	10	#define _SKX_COMM_EDAC_H
	11
2f4348e5	12	#include <linux/bits.h>
2738c69a	13	#include <asm/mce.h>
2f4348e5	14
88a242c9 QZ	15	#define MSG_SIZE 1024
	16
	17	/*
	18	* Debug macros
	19	*/
	20	#define skx_printk(level, fmt, arg...) \
	21	edac_printk(level, "skx", fmt, ##arg)
	22
	23	#define skx_mc_printk(mci, level, fmt, arg...) \
	24	edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
	25
	26	/*
	27	* Get a bit field at register value <v>, from bit <lo> to bit <hi>
	28	*/
	29	#define GET_BITFIELD(v, lo, hi) \
	30	(((v) & GENMASK_ULL((hi), (lo))) >> (lo))
	31
	32	#define SKX_NUM_IMC 2 /* Memory controllers per socket */
	33	#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
	34	#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
	35
ba987eaa	36	#define I10NM_NUM_DDR_IMC 12
c9450883 QZ	37	#define I10NM_NUM_DDR_CHANNELS 2
	38	#define I10NM_NUM_DDR_DIMMS 2
	39
	40	#define I10NM_NUM_HBM_IMC 16
	41	#define I10NM_NUM_HBM_CHANNELS 2
	42	#define I10NM_NUM_HBM_DIMMS 1
	43
	44	#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
	45	#define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
	46	#define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
88a242c9	47
88a242c9 QZ	48	#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
	49	#define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
	50	#define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)
	51
	52	#define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)
	53	#define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)
	54
2738c69a YS	55	#define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15)
	56	#define MCI_MISC_ECC_DDRT 8 /* read from DDRT */
	57
6e8746cb QZ	58	/*
	59	* According to Intel Architecture spec vol 3B,
	60	* Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
	61	* memory errors should fit one of these masks:
	62	* 000f 0000 1mmm cccc (binary)
	63	* 000f 0010 1mmm cccc (binary) [RAM used as cache]
	64	* where:
	65	* f = Correction Report Filtering Bit. If 1, subsequent errors
	66	* won't be shown
	67	* mmm = error type
	68	* cccc = channel
	69	*/
	70	#define MCACOD_MEM_ERR_MASK 0xef80
	71	/*
	72	* Errors from either the memory of the 1-level memory system or the
	73	* 2nd level memory (the slow "far" memory) of the 2-level memory system.
	74	*/
	75	#define MCACOD_MEM_CTL_ERR 0x80
	76	/*
	77	* Errors from the 1st level memory (the fast "near" memory as cache)
	78	* of the 2-level memory system.
	79	*/
	80	#define MCACOD_EXT_MEM_ERR 0x280
	81
88a242c9 QZ	82	/*
	83	* Each cpu socket contains some pci devices that provide global
	84	* information, and also some that are local to each of the two
	85	* memory controllers on the die.
	86	*/
	87	struct skx_dev {
	88	struct list_head list;
	89	u8 bus[4];
	90	int seg;
	91	struct pci_dev *sad_all;
	92	struct pci_dev *util_all;
	93	struct pci_dev uracu; / for i10nm CPU */
c9450883	94	struct pci_dev pcu_cr3; / for HBM memory detection */
88a242c9 QZ	95	u32 mcroute;
	96	struct skx_imc {
	97	struct mem_ctl_info *mci;
	98	struct pci_dev mdev; / for i10nm CPU */
	99	void __iomem mbase; / for i10nm CPU */
479f58dd	100	int chan_mmio_sz; /* for i10nm CPU */
c9450883 QZ	101	int num_channels; /* channels per memory controller */
	102	int num_dimms; /* dimms per channel */
	103	bool hbm_mc;
88a242c9 QZ	104	u8 mc; /* system wide mc# */
	105	u8 lmc; /* socket relative mc# */
	106	u8 src_id, node_id;
	107	struct skx_channel {
	108	struct pci_dev *cdev;
e80634a7	109	struct pci_dev *edev;
cf4e6d52 YS	110	u32 retry_rd_err_log_s;
cf4e6d52 YS	111	u32 retry_rd_err_log_d;
d5f5e499	112	u32 retry_rd_err_log_d2;
88a242c9 QZ	113	struct skx_dimm {
	114	u8 close_pg;
	115	u8 bank_xor_enable;
	116	u8 fine_grain_bank;
	117	u8 rowbits;
	118	u8 colbits;
	119	} dimms[NUM_DIMMS];
	120	} chan[NUM_CHANNELS];
	121	} imc[NUM_IMC];
	122	};
	123
	124	struct skx_pvt {
	125	struct skx_imc *imc;
	126	};
	127
	128	enum type {
	129	SKX,
479f58dd	130	I10NM,
ba987eaa QZ	131	SPR,
ba987eaa QZ	132	GNR
88a242c9 QZ	133	};
	134
	135	enum {
	136	INDEX_SOCKET,
	137	INDEX_MEMCTRL,
	138	INDEX_CHANNEL,
	139	INDEX_DIMM,
14646de4	140	INDEX_CS,
2f4348e5 QZ	141	INDEX_NM_FIRST,
	142	INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
	143	INDEX_NM_CHANNEL,
	144	INDEX_NM_DIMM,
14646de4	145	INDEX_NM_CS,
88a242c9 QZ	146	INDEX_MAX
	147	};
	148
2f4348e5 QZ	149	#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
	150	#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
	151	#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
14646de4	152	#define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
2f4348e5	153
88a242c9	154	struct decoded_addr {
2738c69a	155	struct mce *mce;
88a242c9 QZ	156	struct skx_dev *dev;
	157	u64 addr;
	158	int socket;
	159	int imc;
	160	int channel;
	161	u64 chan_addr;
	162	int sktways;
	163	int chanways;
	164	int dimm;
14646de4	165	int cs;
88a242c9 QZ	166	int rank;
	167	int channel_rank;
	168	u64 rank_address;
	169	int row;
	170	int column;
	171	int bank_address;
	172	int bank_group;
fe32f366	173	bool decoded_by_adxl;
88a242c9 QZ	174	};
88a242c9 QZ	175
dd7814b7 QZ	176	struct pci_bdf {
	177	u32 bus : 8;
	178	u32 dev : 5;
	179	u32 fun : 3;
	180	};
	181
ee5340ab QZ	182	struct res_config {
	183	enum type type;
	184	/* Configuration agent device ID */
	185	unsigned int decs_did;
	186	/* Default bus number configuration register offset */
	187	int busno_cfg_offset;
dd7814b7 QZ	188	/* DDR memory controllers per socket */
	189	int ddr_imc_num;
	190	/* DDR channels per DDR memory controller */
	191	int ddr_chan_num;
	192	/* DDR DIMMs per DDR memory channel */
	193	int ddr_dimm_num;
479f58dd QZ	194	/* Per DDR channel memory-mapped I/O size */
479f58dd QZ	195	int ddr_chan_mmio_sz;
dd7814b7 QZ	196	/* HBM memory controllers per socket */
	197	int hbm_imc_num;
	198	/* HBM channels per HBM memory controller */
	199	int hbm_chan_num;
	200	/* HBM DIMMs per HBM memory channel */
	201	int hbm_dimm_num;
c9450883 QZ	202	/* Per HBM channel memory-mapped I/O size */
c9450883 QZ	203	int hbm_chan_mmio_sz;
479f58dd	204	bool support_ddr5;
dd7814b7 QZ	205	/* SAD device BDF */
	206	struct pci_bdf sad_all_bdf;
	207	/* PCU device BDF */
	208	struct pci_bdf pcu_cr3_bdf;
	209	/* UTIL device BDF */
	210	struct pci_bdf util_all_bdf;
	211	/* URACU device BDF */
	212	struct pci_bdf uracu_bdf;
	213	/* DDR mdev device BDF */
	214	struct pci_bdf ddr_mdev_bdf;
	215	/* HBM mdev device BDF */
	216	struct pci_bdf hbm_mdev_bdf;
4bd4d32e	217	int sad_all_offset;
cf4e6d52 YS	218	/* Offsets of retry_rd_err_log registers */
cf4e6d52 YS	219	u32 *offsets_scrub;
acd4cf68 QZ	220	u32 *offsets_scrub_hbm0;
acd4cf68 QZ	221	u32 *offsets_scrub_hbm1;
cf4e6d52	222	u32 *offsets_demand;
d5f5e499	223	u32 *offsets_demand2;
acd4cf68 QZ	224	u32 *offsets_demand_hbm0;
acd4cf68 QZ	225	u32 *offsets_demand_hbm1;
ee5340ab QZ	226	};
ee5340ab QZ	227
479f58dd QZ	228	typedef int (get_dimm_config_f)(struct mem_ctl_info mci,
479f58dd QZ	229	struct res_config *cfg);
88a242c9	230	typedef bool (skx_decode_f)(struct decoded_addr res);
cf4e6d52	231	typedef void (skx_show_retry_log_f)(struct decoded_addr res, char *msg, int len, bool scrub_err);
88a242c9	232
123b1586 AB	233	int skx_adxl_get(void);
123b1586 AB	234	void skx_adxl_put(void);
e80634a7	235	void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
2f4348e5	236	void skx_set_mem_cfg(bool mem_cfg_2lm);
88a242c9	237
1dc78f1f	238	int skx_get_src_id(struct skx_dev d, int off, u8 id);
88a242c9 QZ	239	int skx_get_node_id(struct skx_dev d, u8 id);
88a242c9 QZ	240
ee5340ab	241	int skx_get_all_bus_mappings(struct res_config cfg, struct list_head *list);
88a242c9 QZ	242
	243	int skx_get_hi_lo(unsigned int did, int off[], u64 tolm, u64 tohm);
	244
10320950	245	int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
479f58dd QZ	246	struct skx_imc *imc, int chan, int dimmno,
479f58dd QZ	247	struct res_config *cfg);
88a242c9 QZ	248
	249	int skx_get_nvdimm_info(struct dimm_info dimm, struct skx_imc imc,
	250	int chan, int dimmno, const char *mod_str);
	251
	252	int skx_register_mci(struct skx_imc imc, struct pci_dev pdev,
	253	const char ctl_name, const char mod_str,
479f58dd QZ	254	get_dimm_config_f get_dimm_config,
479f58dd QZ	255	struct res_config *cfg);
88a242c9 QZ	256
	257	int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
	258	void *data);
	259
	260	void skx_remove(void);
	261
8b935823 QZ	262	#ifdef CONFIG_EDAC_DEBUG
	263	void skx_setup_debug(const char *name);
	264	void skx_teardown_debug(void);
	265	#else
	266	static inline void skx_setup_debug(const char *name) {}
	267	static inline void skx_teardown_debug(void) {}
	268	#endif
	269
88a242c9	270	#endif /* _SKX_COMM_EDAC_H */