[linux-2.6-block.git] / drivers / edac / skx_common.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
 * Originally split out from the skx_edac driver.
 *
 * Copyright (c) 2018, Intel Corporation.
 */

#ifndef _SKX_COMM_EDAC_H
#define _SKX_COMM_EDAC_H

#include <linux/bits.h>
#include <asm/mce.h>

#define MSG_SIZE		1024

/*
 * Debug macros
 */
#define skx_printk(level, fmt, arg...)			\
	edac_printk(level, "skx", fmt, ##arg)

#define skx_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)

/*
 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
 */
#define GET_BITFIELD(v, lo, hi) \
	(((v) & GENMASK_ULL((hi), (lo))) >> (lo))

#define SKX_NUM_IMC		2	/* Memory controllers per socket */
#define SKX_NUM_CHANNELS	3	/* Channels per memory controller */
#define SKX_NUM_DIMMS		2	/* Max DIMMS per channel */

#define I10NM_NUM_DDR_IMC	12
#define I10NM_NUM_DDR_CHANNELS	2
#define I10NM_NUM_DDR_DIMMS	2

#define I10NM_NUM_HBM_IMC	16
#define I10NM_NUM_HBM_CHANNELS	2
#define I10NM_NUM_HBM_DIMMS	1

#define I10NM_NUM_IMC		(I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
#define I10NM_NUM_CHANNELS	MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
#define I10NM_NUM_DIMMS		MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)

#define NUM_IMC		MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
#define NUM_CHANNELS	MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
#define NUM_DIMMS	MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)

#define IS_DIMM_PRESENT(r)		GET_BITFIELD(r, 15, 15)
#define IS_NVDIMM_PRESENT(r, i)		GET_BITFIELD(r, i, i)

#define MCI_MISC_ECC_MODE(m)	(((m) >> 59) & 15)
#define MCI_MISC_ECC_DDRT	8	/* read from DDRT */

/*
 * According to Intel Architecture spec vol 3B,
 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
 * memory errors should fit one of these masks:
 *	000f 0000 1mmm cccc (binary)
 *	000f 0010 1mmm cccc (binary)	[RAM used as cache]
 * where:
 *	f = Correction Report Filtering Bit. If 1, subsequent errors
 *	    won't be shown
 *	mmm = error type
 *	cccc = channel
 */
#define MCACOD_MEM_ERR_MASK	0xef80
/*
 * Errors from either the memory of the 1-level memory system or the
 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
 */
#define MCACOD_MEM_CTL_ERR	0x80
/*
 * Errors from the 1st level memory (the fast "near" memory as cache)
 * of the 2-level memory system.
 */
#define MCACOD_EXT_MEM_ERR	0x280

/* Max RRL register sets per {,sub-,pseudo-}channel. */
#define NUM_RRL_SET		4
/* Max RRL registers per set. */
#define NUM_RRL_REG		6
/* Max correctable error count registers. */
#define NUM_CECNT_REG		8

/* Modes of RRL register set. */
enum rrl_mode {
	/* Last read error from patrol scrub. */
	LRE_SCRUB,
	/* Last read error from demand. */
	LRE_DEMAND,
	/* First read error from patrol scrub. */
	FRE_SCRUB,
	/* First read error from demand. */
	FRE_DEMAND,
};

/* RRL registers per {,sub-,pseudo-}channel. */
struct reg_rrl {
	/* RRL register parts. */
	int set_num, reg_num;
	enum rrl_mode modes[NUM_RRL_SET];
	u32 offsets[NUM_RRL_SET][NUM_RRL_REG];
	/* RRL register widths in byte per set. */
	u8 widths[NUM_RRL_REG];
	/* RRL control bits of the first register per set. */
	u32 v_mask;
	u32 uc_mask;
	u32 over_mask;
	u32 en_patspr_mask;
	u32 noover_mask;
	u32 en_mask;

	/* CORRERRCNT register parts. */
	int cecnt_num;
	u32 cecnt_offsets[NUM_CECNT_REG];
	u8 cecnt_widths[NUM_CECNT_REG];
};

/*
 * Each cpu socket contains some pci devices that provide global
 * information, and also some that are local to each of the two
 * memory controllers on the die.
 */
struct skx_dev {
	struct list_head list;
	u8 bus[4];
	int seg;
	struct pci_dev *sad_all;
	struct pci_dev *util_all;
	struct pci_dev *uracu; /* for i10nm CPU */
	struct pci_dev *pcu_cr3; /* for HBM memory detection */
	u32 mcroute;
	/*
	 * Some server BIOS may hide certain memory controllers, and the
	 * EDAC driver skips those hidden memory controllers. However, the
	 * ADXL still decodes memory error address using physical memory
	 * controller indices. The mapping table is used to convert the
	 * physical indices (reported by ADXL) to the logical indices
	 * (used the EDAC driver) of present memory controllers during the
	 * error handling process.
	 */
	u8 mc_mapping[NUM_IMC];
	struct skx_imc {
		struct mem_ctl_info *mci;
		struct pci_dev *mdev; /* for i10nm CPU */
		void __iomem *mbase;  /* for i10nm CPU */
		int chan_mmio_sz;     /* for i10nm CPU */
		int num_channels; /* channels per memory controller */
		int num_dimms; /* dimms per channel */
		bool hbm_mc;
		u8 mc;	/* system wide mc# */
		u8 lmc;	/* socket relative mc# */
		u8 src_id;
		struct skx_channel {
			struct pci_dev	*cdev;
			struct pci_dev	*edev;
			/*
			 * Two groups of RRL control registers per channel to save default RRL
			 * settings of two {sub-,pseudo-}channels in Linux RRL control mode.
			 */
			u32 rrl_ctl[2][NUM_RRL_SET];
			struct skx_dimm {
				u8 close_pg;
				u8 bank_xor_enable;
				u8 fine_grain_bank;
				u8 rowbits;
				u8 colbits;
			} dimms[NUM_DIMMS];
		} chan[NUM_CHANNELS];
	} imc[NUM_IMC];
};

struct skx_pvt {
	struct skx_imc	*imc;
};

enum type {
	SKX,
	I10NM,
	SPR,
	GNR
};

enum {
	INDEX_SOCKET,
	INDEX_MEMCTRL,
	INDEX_CHANNEL,
	INDEX_DIMM,
	INDEX_CS,
	INDEX_NM_FIRST,
	INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
	INDEX_NM_CHANNEL,
	INDEX_NM_DIMM,
	INDEX_NM_CS,
	INDEX_MAX
};

enum error_source {
	ERR_SRC_1LM,
	ERR_SRC_2LM_NM,
	ERR_SRC_2LM_FM,
	ERR_SRC_NOT_MEMORY,
};

#define BIT_NM_MEMCTRL	BIT_ULL(INDEX_NM_MEMCTRL)
#define BIT_NM_CHANNEL	BIT_ULL(INDEX_NM_CHANNEL)
#define BIT_NM_DIMM	BIT_ULL(INDEX_NM_DIMM)
#define BIT_NM_CS	BIT_ULL(INDEX_NM_CS)

struct decoded_addr {
	struct mce *mce;
	struct skx_dev *dev;
	u64	addr;
	int	socket;
	int	imc;
	int	channel;
	u64	chan_addr;
	int	sktways;
	int	chanways;
	int	dimm;
	int	cs;
	int	rank;
	int	channel_rank;
	u64	rank_address;
	int	row;
	int	column;
	int	bank_address;
	int	bank_group;
	bool	decoded_by_adxl;
};

struct pci_bdf {
	u32 bus : 8;
	u32 dev : 5;
	u32 fun : 3;
};

struct res_config {
	enum type type;
	/* Configuration agent device ID */
	unsigned int decs_did;
	/* Default bus number configuration register offset */
	int busno_cfg_offset;
	/* DDR memory controllers per socket */
	int ddr_imc_num;
	/* DDR channels per DDR memory controller */
	int ddr_chan_num;
	/* DDR DIMMs per DDR memory channel */
	int ddr_dimm_num;
	/* Per DDR channel memory-mapped I/O size */
	int ddr_chan_mmio_sz;
	/* HBM memory controllers per socket */
	int hbm_imc_num;
	/* HBM channels per HBM memory controller */
	int hbm_chan_num;
	/* HBM DIMMs per HBM memory channel */
	int hbm_dimm_num;
	/* Per HBM channel memory-mapped I/O size */
	int hbm_chan_mmio_sz;
	bool support_ddr5;
	/* SAD device BDF */
	struct pci_bdf sad_all_bdf;
	/* PCU device BDF */
	struct pci_bdf pcu_cr3_bdf;
	/* UTIL device BDF */
	struct pci_bdf util_all_bdf;
	/* URACU device BDF */
	struct pci_bdf uracu_bdf;
	/* DDR mdev device BDF */
	struct pci_bdf ddr_mdev_bdf;
	/* HBM mdev device BDF */
	struct pci_bdf hbm_mdev_bdf;
	int sad_all_offset;
	/* RRL register sets per DDR channel */
	struct reg_rrl *reg_rrl_ddr;
	/* RRL register sets per HBM channel */
	struct reg_rrl *reg_rrl_hbm[2];
};

typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
				 struct res_config *cfg);
typedef bool (*skx_decode_f)(struct decoded_addr *res);
typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);

int skx_adxl_get(void);
void skx_adxl_put(void);
void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
void skx_set_mem_cfg(bool mem_cfg_2lm);
void skx_set_res_cfg(struct res_config *cfg);
void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc);

int skx_get_src_id(struct skx_dev *d, int off, u8 *id);

int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);

int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);

int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
		      struct skx_imc *imc, int chan, int dimmno,
		      struct res_config *cfg);

int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
			int chan, int dimmno, const char *mod_str);

int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
		     const char *ctl_name, const char *mod_str,
		     get_dimm_config_f get_dimm_config,
		     struct res_config *cfg);

int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
			void *data);

void skx_remove(void);

#ifdef CONFIG_EDAC_DEBUG
void skx_setup_debug(const char *name);
void skx_teardown_debug(void);
#else
static inline void skx_setup_debug(const char *name) {}
static inline void skx_teardown_debug(void) {}
#endif

#endif /* _SKX_COMM_EDAC_H */
Commit	Line	Data
88a242c9 QZ	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
	4	* Originally split out from the skx_edac driver.
	5	*
	6	* Copyright (c) 2018, Intel Corporation.
	7	*/
	8
	9	#ifndef _SKX_COMM_EDAC_H
	10	#define _SKX_COMM_EDAC_H
	11
2f4348e5	12	#include <linux/bits.h>
2738c69a	13	#include <asm/mce.h>
2f4348e5	14
88a242c9 QZ	15	#define MSG_SIZE 1024
	16
	17	/*
	18	* Debug macros
	19	*/
	20	#define skx_printk(level, fmt, arg...) \
	21	edac_printk(level, "skx", fmt, ##arg)
	22
	23	#define skx_mc_printk(mci, level, fmt, arg...) \
	24	edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
	25
	26	/*
	27	* Get a bit field at register value <v>, from bit <lo> to bit <hi>
	28	*/
	29	#define GET_BITFIELD(v, lo, hi) \
	30	(((v) & GENMASK_ULL((hi), (lo))) >> (lo))
	31
	32	#define SKX_NUM_IMC 2 /* Memory controllers per socket */
	33	#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
	34	#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
	35
ba987eaa	36	#define I10NM_NUM_DDR_IMC 12
c9450883 QZ	37	#define I10NM_NUM_DDR_CHANNELS 2
	38	#define I10NM_NUM_DDR_DIMMS 2
	39
	40	#define I10NM_NUM_HBM_IMC 16
	41	#define I10NM_NUM_HBM_CHANNELS 2
	42	#define I10NM_NUM_HBM_DIMMS 1
	43
	44	#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
	45	#define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
	46	#define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
88a242c9	47
88a242c9 QZ	48	#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
	49	#define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
	50	#define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)
	51
	52	#define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)
	53	#define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)
	54
2738c69a YS	55	#define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15)
	56	#define MCI_MISC_ECC_DDRT 8 /* read from DDRT */
	57
6e8746cb QZ	58	/*
	59	* According to Intel Architecture spec vol 3B,
	60	* Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
	61	* memory errors should fit one of these masks:
	62	* 000f 0000 1mmm cccc (binary)
	63	* 000f 0010 1mmm cccc (binary) [RAM used as cache]
	64	* where:
	65	* f = Correction Report Filtering Bit. If 1, subsequent errors
	66	* won't be shown
	67	* mmm = error type
	68	* cccc = channel
	69	*/
	70	#define MCACOD_MEM_ERR_MASK 0xef80
	71	/*
	72	* Errors from either the memory of the 1-level memory system or the
	73	* 2nd level memory (the slow "far" memory) of the 2-level memory system.
	74	*/
	75	#define MCACOD_MEM_CTL_ERR 0x80
	76	/*
	77	* Errors from the 1st level memory (the fast "near" memory as cache)
	78	* of the 2-level memory system.
	79	*/
	80	#define MCACOD_EXT_MEM_ERR 0x280
	81
eeed3e03	82	/* Max RRL register sets per {,sub-,pseudo-}channel. */
5904dc56	83	#define NUM_RRL_SET 4
1a8a6af6 QZ	84	/* Max RRL registers per set. */
1a8a6af6 QZ	85	#define NUM_RRL_REG 6
126168fa	86	/* Max correctable error count registers. */
5904dc56	87	#define NUM_CECNT_REG 8
1a8a6af6	88
ba3985c1 QZ	89	/* Modes of RRL register set. */
	90	enum rrl_mode {
	91	/* Last read error from patrol scrub. */
	92	LRE_SCRUB,
	93	/* Last read error from demand. */
	94	LRE_DEMAND,
	95	/* First read error from patrol scrub. */
	96	FRE_SCRUB,
	97	/* First read error from demand. */
	98	FRE_DEMAND,
	99	};
	100
1a8a6af6 QZ	101	/* RRL registers per {,sub-,pseudo-}channel. */
	102	struct reg_rrl {
	103	/* RRL register parts. */
126168fa	104	int set_num, reg_num;
ba3985c1	105	enum rrl_mode modes[NUM_RRL_SET];
1a8a6af6	106	u32 offsets[NUM_RRL_SET][NUM_RRL_REG];
ba3985c1 QZ	107	/* RRL register widths in byte per set. */
	108	u8 widths[NUM_RRL_REG];
	109	/* RRL control bits of the first register per set. */
126168fa	110	u32 v_mask;
ba3985c1	111	u32 uc_mask;
126168fa	112	u32 over_mask;
ba3985c1 QZ	113	u32 en_patspr_mask;
	114	u32 noover_mask;
	115	u32 en_mask;
126168fa QZ	116
	117	/* CORRERRCNT register parts. */
	118	int cecnt_num;
	119	u32 cecnt_offsets[NUM_CECNT_REG];
	120	u8 cecnt_widths[NUM_CECNT_REG];
1a8a6af6	121	};
eeed3e03	122
88a242c9 QZ	123	/*
	124	* Each cpu socket contains some pci devices that provide global
	125	* information, and also some that are local to each of the two
	126	* memory controllers on the die.
	127	*/
	128	struct skx_dev {
	129	struct list_head list;
	130	u8 bus[4];
	131	int seg;
	132	struct pci_dev *sad_all;
	133	struct pci_dev *util_all;
	134	struct pci_dev uracu; / for i10nm CPU */
c9450883	135	struct pci_dev pcu_cr3; / for HBM memory detection */
88a242c9	136	u32 mcroute;
d9207cf7 QZ	137	/*
	138	* Some server BIOS may hide certain memory controllers, and the
	139	* EDAC driver skips those hidden memory controllers. However, the
	140	* ADXL still decodes memory error address using physical memory
	141	* controller indices. The mapping table is used to convert the
	142	* physical indices (reported by ADXL) to the logical indices
	143	* (used the EDAC driver) of present memory controllers during the
	144	* error handling process.
	145	*/
	146	u8 mc_mapping[NUM_IMC];
88a242c9 QZ	147	struct skx_imc {
	148	struct mem_ctl_info *mci;
	149	struct pci_dev mdev; / for i10nm CPU */
	150	void __iomem mbase; / for i10nm CPU */
479f58dd	151	int chan_mmio_sz; /* for i10nm CPU */
c9450883 QZ	152	int num_channels; /* channels per memory controller */
	153	int num_dimms; /* dimms per channel */
	154	bool hbm_mc;
88a242c9 QZ	155	u8 mc; /* system wide mc# */
88a242c9 QZ	156	u8 lmc; /* socket relative mc# */
584e0974	157	u8 src_id;
88a242c9 QZ	158	struct skx_channel {
88a242c9 QZ	159	struct pci_dev *cdev;
e80634a7	160	struct pci_dev *edev;
eeed3e03 QZ	161	/*
	162	* Two groups of RRL control registers per channel to save default RRL
	163	* settings of two {sub-,pseudo-}channels in Linux RRL control mode.
	164	*/
	165	u32 rrl_ctl[2][NUM_RRL_SET];
88a242c9 QZ	166	struct skx_dimm {
	167	u8 close_pg;
	168	u8 bank_xor_enable;
	169	u8 fine_grain_bank;
	170	u8 rowbits;
	171	u8 colbits;
	172	} dimms[NUM_DIMMS];
	173	} chan[NUM_CHANNELS];
	174	} imc[NUM_IMC];
	175	};
	176
	177	struct skx_pvt {
	178	struct skx_imc *imc;
	179	};
	180
	181	enum type {
	182	SKX,
479f58dd	183	I10NM,
ba987eaa QZ	184	SPR,
ba987eaa QZ	185	GNR
88a242c9 QZ	186	};
	187
	188	enum {
	189	INDEX_SOCKET,
	190	INDEX_MEMCTRL,
	191	INDEX_CHANNEL,
	192	INDEX_DIMM,
14646de4	193	INDEX_CS,
2f4348e5 QZ	194	INDEX_NM_FIRST,
	195	INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
	196	INDEX_NM_CHANNEL,
	197	INDEX_NM_DIMM,
14646de4	198	INDEX_NM_CS,
88a242c9 QZ	199	INDEX_MAX
	200	};
	201
2397f795 QZ	202	enum error_source {
	203	ERR_SRC_1LM,
	204	ERR_SRC_2LM_NM,
	205	ERR_SRC_2LM_FM,
	206	ERR_SRC_NOT_MEMORY,
	207	};
	208
2f4348e5 QZ	209	#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
	210	#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
	211	#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
14646de4	212	#define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
2f4348e5	213
88a242c9	214	struct decoded_addr {
2738c69a	215	struct mce *mce;
88a242c9 QZ	216	struct skx_dev *dev;
	217	u64 addr;
	218	int socket;
	219	int imc;
	220	int channel;
	221	u64 chan_addr;
	222	int sktways;
	223	int chanways;
	224	int dimm;
14646de4	225	int cs;
88a242c9 QZ	226	int rank;
	227	int channel_rank;
	228	u64 rank_address;
	229	int row;
	230	int column;
	231	int bank_address;
	232	int bank_group;
fe32f366	233	bool decoded_by_adxl;
88a242c9 QZ	234	};
88a242c9 QZ	235
dd7814b7 QZ	236	struct pci_bdf {
	237	u32 bus : 8;
	238	u32 dev : 5;
	239	u32 fun : 3;
	240	};
	241
ee5340ab QZ	242	struct res_config {
	243	enum type type;
	244	/* Configuration agent device ID */
	245	unsigned int decs_did;
	246	/* Default bus number configuration register offset */
	247	int busno_cfg_offset;
dd7814b7 QZ	248	/* DDR memory controllers per socket */
	249	int ddr_imc_num;
	250	/* DDR channels per DDR memory controller */
	251	int ddr_chan_num;
	252	/* DDR DIMMs per DDR memory channel */
	253	int ddr_dimm_num;
479f58dd QZ	254	/* Per DDR channel memory-mapped I/O size */
479f58dd QZ	255	int ddr_chan_mmio_sz;
dd7814b7 QZ	256	/* HBM memory controllers per socket */
	257	int hbm_imc_num;
	258	/* HBM channels per HBM memory controller */
	259	int hbm_chan_num;
	260	/* HBM DIMMs per HBM memory channel */
	261	int hbm_dimm_num;
c9450883 QZ	262	/* Per HBM channel memory-mapped I/O size */
c9450883 QZ	263	int hbm_chan_mmio_sz;
479f58dd	264	bool support_ddr5;
dd7814b7 QZ	265	/* SAD device BDF */
	266	struct pci_bdf sad_all_bdf;
	267	/* PCU device BDF */
	268	struct pci_bdf pcu_cr3_bdf;
	269	/* UTIL device BDF */
	270	struct pci_bdf util_all_bdf;
	271	/* URACU device BDF */
	272	struct pci_bdf uracu_bdf;
	273	/* DDR mdev device BDF */
	274	struct pci_bdf ddr_mdev_bdf;
	275	/* HBM mdev device BDF */
	276	struct pci_bdf hbm_mdev_bdf;
4bd4d32e	277	int sad_all_offset;
1a8a6af6 QZ	278	/* RRL register sets per DDR channel */
	279	struct reg_rrl *reg_rrl_ddr;
	280	/* RRL register sets per HBM channel */
	281	struct reg_rrl *reg_rrl_hbm[2];
ee5340ab QZ	282	};
ee5340ab QZ	283
479f58dd QZ	284	typedef int (get_dimm_config_f)(struct mem_ctl_info mci,
479f58dd QZ	285	struct res_config *cfg);
88a242c9	286	typedef bool (skx_decode_f)(struct decoded_addr res);
cf4e6d52	287	typedef void (skx_show_retry_log_f)(struct decoded_addr res, char *msg, int len, bool scrub_err);
88a242c9	288
123b1586 AB	289	int skx_adxl_get(void);
123b1586 AB	290	void skx_adxl_put(void);
e80634a7	291	void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
2f4348e5	292	void skx_set_mem_cfg(bool mem_cfg_2lm);
a3666703	293	void skx_set_res_cfg(struct res_config *cfg);
d9207cf7	294	void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc);
88a242c9	295
1dc78f1f	296	int skx_get_src_id(struct skx_dev d, int off, u8 id);
88a242c9	297
ee5340ab	298	int skx_get_all_bus_mappings(struct res_config cfg, struct list_head *list);
88a242c9 QZ	299
	300	int skx_get_hi_lo(unsigned int did, int off[], u64 tolm, u64 tohm);
	301
10320950	302	int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
479f58dd QZ	303	struct skx_imc *imc, int chan, int dimmno,
479f58dd QZ	304	struct res_config *cfg);
88a242c9 QZ	305
	306	int skx_get_nvdimm_info(struct dimm_info dimm, struct skx_imc imc,
	307	int chan, int dimmno, const char *mod_str);
	308
	309	int skx_register_mci(struct skx_imc imc, struct pci_dev pdev,
	310	const char ctl_name, const char mod_str,
479f58dd QZ	311	get_dimm_config_f get_dimm_config,
479f58dd QZ	312	struct res_config *cfg);
88a242c9 QZ	313
	314	int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
	315	void *data);
	316
	317	void skx_remove(void);
	318
8b935823 QZ	319	#ifdef CONFIG_EDAC_DEBUG
	320	void skx_setup_debug(const char *name);
	321	void skx_teardown_debug(void);
	322	#else
	323	static inline void skx_setup_debug(const char *name) {}
	324	static inline void skx_teardown_debug(void) {}
	325	#endif
	326
88a242c9	327	#endif /* _SKX_COMM_EDAC_H */