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88a242c9 QZ |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver. | |
4 | * Originally split out from the skx_edac driver. | |
5 | * | |
6 | * Copyright (c) 2018, Intel Corporation. | |
7 | */ | |
8 | ||
9 | #ifndef _SKX_COMM_EDAC_H | |
10 | #define _SKX_COMM_EDAC_H | |
11 | ||
2f4348e5 | 12 | #include <linux/bits.h> |
2738c69a | 13 | #include <asm/mce.h> |
2f4348e5 | 14 | |
88a242c9 QZ |
15 | #define MSG_SIZE 1024 |
16 | ||
17 | /* | |
18 | * Debug macros | |
19 | */ | |
20 | #define skx_printk(level, fmt, arg...) \ | |
21 | edac_printk(level, "skx", fmt, ##arg) | |
22 | ||
23 | #define skx_mc_printk(mci, level, fmt, arg...) \ | |
24 | edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) | |
25 | ||
26 | /* | |
27 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
28 | */ | |
29 | #define GET_BITFIELD(v, lo, hi) \ | |
30 | (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) | |
31 | ||
32 | #define SKX_NUM_IMC 2 /* Memory controllers per socket */ | |
33 | #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */ | |
34 | #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */ | |
35 | ||
c9450883 QZ |
36 | #define I10NM_NUM_DDR_IMC 4 |
37 | #define I10NM_NUM_DDR_CHANNELS 2 | |
38 | #define I10NM_NUM_DDR_DIMMS 2 | |
39 | ||
40 | #define I10NM_NUM_HBM_IMC 16 | |
41 | #define I10NM_NUM_HBM_CHANNELS 2 | |
42 | #define I10NM_NUM_HBM_DIMMS 1 | |
43 | ||
44 | #define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC) | |
45 | #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS) | |
46 | #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS) | |
88a242c9 QZ |
47 | |
48 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) | |
49 | #define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC) | |
50 | #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) | |
51 | #define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS) | |
52 | ||
53 | #define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15) | |
54 | #define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i) | |
55 | ||
2738c69a YS |
56 | #define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15) |
57 | #define MCI_MISC_ECC_DDRT 8 /* read from DDRT */ | |
58 | ||
88a242c9 QZ |
59 | /* |
60 | * Each cpu socket contains some pci devices that provide global | |
61 | * information, and also some that are local to each of the two | |
62 | * memory controllers on the die. | |
63 | */ | |
64 | struct skx_dev { | |
65 | struct list_head list; | |
66 | u8 bus[4]; | |
67 | int seg; | |
68 | struct pci_dev *sad_all; | |
69 | struct pci_dev *util_all; | |
70 | struct pci_dev *uracu; /* for i10nm CPU */ | |
c9450883 | 71 | struct pci_dev *pcu_cr3; /* for HBM memory detection */ |
88a242c9 QZ |
72 | u32 mcroute; |
73 | struct skx_imc { | |
74 | struct mem_ctl_info *mci; | |
75 | struct pci_dev *mdev; /* for i10nm CPU */ | |
76 | void __iomem *mbase; /* for i10nm CPU */ | |
479f58dd | 77 | int chan_mmio_sz; /* for i10nm CPU */ |
c9450883 QZ |
78 | int num_channels; /* channels per memory controller */ |
79 | int num_dimms; /* dimms per channel */ | |
80 | bool hbm_mc; | |
88a242c9 QZ |
81 | u8 mc; /* system wide mc# */ |
82 | u8 lmc; /* socket relative mc# */ | |
83 | u8 src_id, node_id; | |
84 | struct skx_channel { | |
85 | struct pci_dev *cdev; | |
e80634a7 | 86 | struct pci_dev *edev; |
cf4e6d52 YS |
87 | u32 retry_rd_err_log_s; |
88 | u32 retry_rd_err_log_d; | |
88a242c9 QZ |
89 | struct skx_dimm { |
90 | u8 close_pg; | |
91 | u8 bank_xor_enable; | |
92 | u8 fine_grain_bank; | |
93 | u8 rowbits; | |
94 | u8 colbits; | |
95 | } dimms[NUM_DIMMS]; | |
96 | } chan[NUM_CHANNELS]; | |
97 | } imc[NUM_IMC]; | |
98 | }; | |
99 | ||
100 | struct skx_pvt { | |
101 | struct skx_imc *imc; | |
102 | }; | |
103 | ||
104 | enum type { | |
105 | SKX, | |
479f58dd QZ |
106 | I10NM, |
107 | SPR | |
88a242c9 QZ |
108 | }; |
109 | ||
110 | enum { | |
111 | INDEX_SOCKET, | |
112 | INDEX_MEMCTRL, | |
113 | INDEX_CHANNEL, | |
114 | INDEX_DIMM, | |
14646de4 | 115 | INDEX_CS, |
2f4348e5 QZ |
116 | INDEX_NM_FIRST, |
117 | INDEX_NM_MEMCTRL = INDEX_NM_FIRST, | |
118 | INDEX_NM_CHANNEL, | |
119 | INDEX_NM_DIMM, | |
14646de4 | 120 | INDEX_NM_CS, |
88a242c9 QZ |
121 | INDEX_MAX |
122 | }; | |
123 | ||
2f4348e5 QZ |
124 | #define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL) |
125 | #define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL) | |
126 | #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM) | |
14646de4 | 127 | #define BIT_NM_CS BIT_ULL(INDEX_NM_CS) |
2f4348e5 | 128 | |
88a242c9 | 129 | struct decoded_addr { |
2738c69a | 130 | struct mce *mce; |
88a242c9 QZ |
131 | struct skx_dev *dev; |
132 | u64 addr; | |
133 | int socket; | |
134 | int imc; | |
135 | int channel; | |
136 | u64 chan_addr; | |
137 | int sktways; | |
138 | int chanways; | |
139 | int dimm; | |
14646de4 | 140 | int cs; |
88a242c9 QZ |
141 | int rank; |
142 | int channel_rank; | |
143 | u64 rank_address; | |
144 | int row; | |
145 | int column; | |
146 | int bank_address; | |
147 | int bank_group; | |
fe32f366 | 148 | bool decoded_by_adxl; |
88a242c9 QZ |
149 | }; |
150 | ||
ee5340ab QZ |
151 | struct res_config { |
152 | enum type type; | |
153 | /* Configuration agent device ID */ | |
154 | unsigned int decs_did; | |
155 | /* Default bus number configuration register offset */ | |
156 | int busno_cfg_offset; | |
479f58dd QZ |
157 | /* Per DDR channel memory-mapped I/O size */ |
158 | int ddr_chan_mmio_sz; | |
c9450883 QZ |
159 | /* Per HBM channel memory-mapped I/O size */ |
160 | int hbm_chan_mmio_sz; | |
479f58dd | 161 | bool support_ddr5; |
4bd4d32e QZ |
162 | /* SAD device number and function number */ |
163 | unsigned int sad_all_devfn; | |
164 | int sad_all_offset; | |
cf4e6d52 YS |
165 | /* Offsets of retry_rd_err_log registers */ |
166 | u32 *offsets_scrub; | |
167 | u32 *offsets_demand; | |
ee5340ab QZ |
168 | }; |
169 | ||
479f58dd QZ |
170 | typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, |
171 | struct res_config *cfg); | |
88a242c9 | 172 | typedef bool (*skx_decode_f)(struct decoded_addr *res); |
cf4e6d52 | 173 | typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err); |
88a242c9 QZ |
174 | |
175 | int __init skx_adxl_get(void); | |
176 | void __exit skx_adxl_put(void); | |
e80634a7 | 177 | void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); |
2f4348e5 | 178 | void skx_set_mem_cfg(bool mem_cfg_2lm); |
88a242c9 | 179 | |
1dc78f1f | 180 | int skx_get_src_id(struct skx_dev *d, int off, u8 *id); |
88a242c9 QZ |
181 | int skx_get_node_id(struct skx_dev *d, u8 *id); |
182 | ||
ee5340ab | 183 | int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list); |
88a242c9 QZ |
184 | |
185 | int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm); | |
186 | ||
10320950 | 187 | int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, |
479f58dd QZ |
188 | struct skx_imc *imc, int chan, int dimmno, |
189 | struct res_config *cfg); | |
88a242c9 QZ |
190 | |
191 | int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, | |
192 | int chan, int dimmno, const char *mod_str); | |
193 | ||
194 | int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, | |
195 | const char *ctl_name, const char *mod_str, | |
479f58dd QZ |
196 | get_dimm_config_f get_dimm_config, |
197 | struct res_config *cfg); | |
88a242c9 QZ |
198 | |
199 | int skx_mce_check_error(struct notifier_block *nb, unsigned long val, | |
200 | void *data); | |
201 | ||
202 | void skx_remove(void); | |
203 | ||
88a242c9 | 204 | #endif /* _SKX_COMM_EDAC_H */ |