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12237550 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
eebf11a0 MCC |
2 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
3 | * | |
4 | * This driver supports the memory controllers found on the Intel | |
5 | * processor family Sandy Bridge. | |
6 | * | |
eebf11a0 | 7 | * Copyright (c) 2011 by: |
37e59f87 | 8 | * Mauro Carvalho Chehab |
eebf11a0 MCC |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_ids.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/edac.h> | |
18 | #include <linux/mmzone.h> | |
eebf11a0 MCC |
19 | #include <linux/smp.h> |
20 | #include <linux/bitmap.h> | |
5b889e37 | 21 | #include <linux/math64.h> |
2c1ea4c7 TL |
22 | #include <linux/mod_devicetable.h> |
23 | #include <asm/cpu_device_id.h> | |
20f4d692 | 24 | #include <asm/intel-family.h> |
eebf11a0 | 25 | #include <asm/processor.h> |
3d78c9af | 26 | #include <asm/mce.h> |
eebf11a0 | 27 | |
78d88e8a | 28 | #include "edac_module.h" |
eebf11a0 MCC |
29 | |
30 | /* Static vars */ | |
31 | static LIST_HEAD(sbridge_edac_list); | |
eebf11a0 MCC |
32 | |
33 | /* | |
34 | * Alter this version for the module when modifications are made | |
35 | */ | |
d14e3a20 | 36 | #define SBRIDGE_REVISION " Ver: 1.1.2 " |
301375e7 | 37 | #define EDAC_MOD_STR "sb_edac" |
eebf11a0 MCC |
38 | |
39 | /* | |
40 | * Debug macros | |
41 | */ | |
42 | #define sbridge_printk(level, fmt, arg...) \ | |
43 | edac_printk(level, "sbridge", fmt, ##arg) | |
44 | ||
45 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ | |
46 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) | |
47 | ||
48 | /* | |
49 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
50 | */ | |
51 | #define GET_BITFIELD(v, lo, hi) \ | |
10ef6b0d | 52 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
eebf11a0 | 53 | |
eebf11a0 | 54 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
464f1d82 | 55 | static const u32 sbridge_dram_rule[] = { |
eebf11a0 MCC |
56 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
57 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, | |
58 | }; | |
eebf11a0 | 59 | |
4d715a80 AR |
60 | static const u32 ibridge_dram_rule[] = { |
61 | 0x60, 0x68, 0x70, 0x78, 0x80, | |
62 | 0x88, 0x90, 0x98, 0xa0, 0xa8, | |
63 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, | |
64 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, | |
65 | }; | |
eebf11a0 | 66 | |
d0cdf900 JS |
67 | static const u32 knl_dram_rule[] = { |
68 | 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */ | |
69 | 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */ | |
70 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */ | |
71 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */ | |
72 | 0x100, 0x108, 0x110, 0x118, /* 20-23 */ | |
73 | }; | |
74 | ||
eebf11a0 | 75 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) |
50d1bb93 | 76 | #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) |
eebf11a0 | 77 | |
c59f9c06 | 78 | static char *show_dram_attr(u32 attr) |
eebf11a0 | 79 | { |
c59f9c06 | 80 | switch (attr) { |
eebf11a0 MCC |
81 | case 0: |
82 | return "DRAM"; | |
83 | case 1: | |
84 | return "MMCFG"; | |
85 | case 2: | |
86 | return "NXM"; | |
87 | default: | |
88 | return "unknown"; | |
89 | } | |
90 | } | |
91 | ||
ef1ce51e | 92 | static const u32 sbridge_interleave_list[] = { |
eebf11a0 MCC |
93 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
94 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, | |
95 | }; | |
eebf11a0 | 96 | |
4d715a80 AR |
97 | static const u32 ibridge_interleave_list[] = { |
98 | 0x64, 0x6c, 0x74, 0x7c, 0x84, | |
99 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, | |
100 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, | |
101 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, | |
102 | }; | |
103 | ||
d0cdf900 JS |
104 | static const u32 knl_interleave_list[] = { |
105 | 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */ | |
106 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */ | |
107 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */ | |
108 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */ | |
109 | 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */ | |
110 | }; | |
6fd05266 GS |
111 | #define MAX_INTERLEAVE \ |
112 | (max_t(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \ | |
113 | max_t(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \ | |
114 | ARRAY_SIZE(knl_interleave_list)))) | |
d0cdf900 | 115 | |
cc311991 AR |
116 | struct interleave_pkg { |
117 | unsigned char start; | |
118 | unsigned char end; | |
119 | }; | |
120 | ||
121 | static const struct interleave_pkg sbridge_interleave_pkg[] = { | |
122 | { 0, 2 }, | |
123 | { 3, 5 }, | |
124 | { 8, 10 }, | |
125 | { 11, 13 }, | |
126 | { 16, 18 }, | |
127 | { 19, 21 }, | |
128 | { 24, 26 }, | |
129 | { 27, 29 }, | |
130 | }; | |
131 | ||
4d715a80 AR |
132 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
133 | { 0, 3 }, | |
134 | { 4, 7 }, | |
135 | { 8, 11 }, | |
136 | { 12, 15 }, | |
137 | { 16, 19 }, | |
138 | { 20, 23 }, | |
139 | { 24, 27 }, | |
140 | { 28, 31 }, | |
141 | }; | |
142 | ||
cc311991 AR |
143 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
144 | int interleave) | |
eebf11a0 | 145 | { |
cc311991 AR |
146 | return GET_BITFIELD(reg, table[interleave].start, |
147 | table[interleave].end); | |
eebf11a0 MCC |
148 | } |
149 | ||
150 | /* Devices 12 Function 7 */ | |
151 | ||
152 | #define TOLM 0x80 | |
d0cdf900 | 153 | #define TOHM 0x84 |
f7cf2a22 | 154 | #define HASWELL_TOLM 0xd0 |
50d1bb93 AR |
155 | #define HASWELL_TOHM_0 0xd4 |
156 | #define HASWELL_TOHM_1 0xd8 | |
d0cdf900 JS |
157 | #define KNL_TOLM 0xd0 |
158 | #define KNL_TOHM_0 0xd4 | |
159 | #define KNL_TOHM_1 0xd8 | |
eebf11a0 MCC |
160 | |
161 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) | |
162 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) | |
163 | ||
164 | /* Device 13 Function 6 */ | |
165 | ||
166 | #define SAD_TARGET 0xf0 | |
167 | ||
168 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) | |
169 | ||
d0cdf900 JS |
170 | #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14) |
171 | ||
eebf11a0 MCC |
172 | #define SAD_CONTROL 0xf4 |
173 | ||
eebf11a0 MCC |
174 | /* Device 14 function 0 */ |
175 | ||
176 | static const u32 tad_dram_rule[] = { | |
177 | 0x40, 0x44, 0x48, 0x4c, | |
178 | 0x50, 0x54, 0x58, 0x5c, | |
179 | 0x60, 0x64, 0x68, 0x6c, | |
180 | }; | |
181 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) | |
182 | ||
183 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) | |
184 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) | |
185 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) | |
186 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) | |
187 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) | |
188 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) | |
189 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) | |
190 | ||
191 | /* Device 15, function 0 */ | |
192 | ||
193 | #define MCMTR 0x7c | |
d0cdf900 | 194 | #define KNL_MCMTR 0x624 |
eebf11a0 MCC |
195 | |
196 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) | |
197 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) | |
198 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) | |
199 | ||
200 | /* Device 15, function 1 */ | |
201 | ||
202 | #define RASENABLES 0xac | |
203 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) | |
204 | ||
205 | /* Device 15, functions 2-5 */ | |
206 | ||
207 | static const int mtr_regs[] = { | |
208 | 0x80, 0x84, 0x88, | |
209 | }; | |
210 | ||
d0cdf900 JS |
211 | static const int knl_mtr_reg = 0xb60; |
212 | ||
eebf11a0 MCC |
213 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) |
214 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) | |
215 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) | |
216 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) | |
217 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) | |
218 | ||
219 | static const u32 tad_ch_nilv_offset[] = { | |
220 | 0x90, 0x94, 0x98, 0x9c, | |
221 | 0xa0, 0xa4, 0xa8, 0xac, | |
222 | 0xb0, 0xb4, 0xb8, 0xbc, | |
223 | }; | |
224 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) | |
225 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) | |
226 | ||
227 | static const u32 rir_way_limit[] = { | |
228 | 0x108, 0x10c, 0x110, 0x114, 0x118, | |
229 | }; | |
230 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) | |
231 | ||
232 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) | |
233 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) | |
eebf11a0 MCC |
234 | |
235 | #define MAX_RIR_WAY 8 | |
236 | ||
237 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { | |
238 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, | |
239 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, | |
240 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, | |
241 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, | |
242 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
243 | }; | |
244 | ||
c7103f65 TL |
245 | #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ |
246 | GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) | |
247 | ||
248 | #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ | |
249 | GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) | |
eebf11a0 MCC |
250 | |
251 | /* Device 16, functions 2-7 */ | |
252 | ||
253 | /* | |
254 | * FIXME: Implement the error count reads directly | |
255 | */ | |
256 | ||
eebf11a0 MCC |
257 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) |
258 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) | |
259 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) | |
260 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) | |
261 | ||
323014d8 MCC |
262 | #if 0 /* Currently unused*/ |
263 | static const u32 correrrcnt[] = { | |
264 | 0x104, 0x108, 0x10c, 0x110, | |
265 | }; | |
266 | ||
eebf11a0 MCC |
267 | static const u32 correrrthrsld[] = { |
268 | 0x11c, 0x120, 0x124, 0x128, | |
269 | }; | |
323014d8 | 270 | #endif |
eebf11a0 MCC |
271 | |
272 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) | |
273 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) | |
274 | ||
275 | ||
276 | /* Device 17, function 0 */ | |
277 | ||
ef1e8d03 | 278 | #define SB_RANK_CFG_A 0x0328 |
eebf11a0 | 279 | |
4d715a80 | 280 | #define IB_RANK_CFG_A 0x0320 |
eebf11a0 | 281 | |
eebf11a0 MCC |
282 | /* |
283 | * sbridge structs | |
284 | */ | |
285 | ||
bf848670 | 286 | #define NUM_CHANNELS 6 /* Max channels per MC */ |
351fc4a9 | 287 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
d0cdf900 JS |
288 | #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */ |
289 | #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */ | |
290 | #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */ | |
351fc4a9 | 291 | #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ |
eebf11a0 | 292 | |
4d715a80 AR |
293 | enum type { |
294 | SANDY_BRIDGE, | |
295 | IVY_BRIDGE, | |
50d1bb93 | 296 | HASWELL, |
1f39581a | 297 | BROADWELL, |
d0cdf900 | 298 | KNIGHTS_LANDING, |
4d715a80 AR |
299 | }; |
300 | ||
00cf50d9 QZ |
301 | enum domain { |
302 | IMC0 = 0, | |
303 | IMC1, | |
304 | SOCK, | |
305 | }; | |
306 | ||
039d7af6 QZ |
307 | enum mirroring_mode { |
308 | NON_MIRRORING, | |
309 | ADDR_RANGE_MIRRORING, | |
310 | FULL_MIRRORING, | |
311 | }; | |
312 | ||
fb79a509 | 313 | struct sbridge_pvt; |
eebf11a0 | 314 | struct sbridge_info { |
4d715a80 | 315 | enum type type; |
464f1d82 AR |
316 | u32 mcmtr; |
317 | u32 rankcfgr; | |
318 | u64 (*get_tolm)(struct sbridge_pvt *pvt); | |
319 | u64 (*get_tohm)(struct sbridge_pvt *pvt); | |
b976bcf2 | 320 | u64 (*rir_limit)(u32 reg); |
c59f9c06 JS |
321 | u64 (*sad_limit)(u32 reg); |
322 | u32 (*interleave_mode)(u32 reg); | |
c59f9c06 | 323 | u32 (*dram_attr)(u32 reg); |
464f1d82 | 324 | const u32 *dram_rule; |
ef1ce51e | 325 | const u32 *interleave_list; |
cc311991 | 326 | const struct interleave_pkg *interleave_pkg; |
464f1d82 | 327 | u8 max_sad; |
f14d6892 | 328 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
8489b17c | 329 | u8 (*get_ha)(u8 bank); |
9e375446 | 330 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
12f0721c | 331 | enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); |
50d1bb93 | 332 | struct pci_dev *pci_vtd; |
eebf11a0 MCC |
333 | }; |
334 | ||
335 | struct sbridge_channel { | |
336 | u32 ranks; | |
337 | u32 dimms; | |
338 | }; | |
339 | ||
340 | struct pci_id_descr { | |
c41afdca | 341 | int dev_id; |
eebf11a0 | 342 | int optional; |
00cf50d9 | 343 | enum domain dom; |
eebf11a0 MCC |
344 | }; |
345 | ||
346 | struct pci_id_table { | |
347 | const struct pci_id_descr *descr; | |
00cf50d9 QZ |
348 | int n_devs_per_imc; |
349 | int n_devs_per_sock; | |
350 | int n_imcs_per_sock; | |
665f05e0 | 351 | enum type type; |
eebf11a0 MCC |
352 | }; |
353 | ||
354 | struct sbridge_dev { | |
355 | struct list_head list; | |
190bd6e9 | 356 | int seg; |
eebf11a0 MCC |
357 | u8 bus, mc; |
358 | u8 node_id, source_id; | |
359 | struct pci_dev **pdev; | |
00cf50d9 | 360 | enum domain dom; |
eebf11a0 | 361 | int n_devs; |
e2f747b1 | 362 | int i_devs; |
eebf11a0 MCC |
363 | struct mem_ctl_info *mci; |
364 | }; | |
365 | ||
d0cdf900 JS |
366 | struct knl_pvt { |
367 | struct pci_dev *pci_cha[KNL_MAX_CHAS]; | |
368 | struct pci_dev *pci_channel[KNL_MAX_CHANNELS]; | |
369 | struct pci_dev *pci_mc0; | |
370 | struct pci_dev *pci_mc1; | |
371 | struct pci_dev *pci_mc0_misc; | |
372 | struct pci_dev *pci_mc1_misc; | |
373 | struct pci_dev *pci_mc_info; /* tolm, tohm */ | |
374 | }; | |
375 | ||
eebf11a0 | 376 | struct sbridge_pvt { |
e2f747b1 QZ |
377 | /* Devices per socket */ |
378 | struct pci_dev *pci_ddrio; | |
4d715a80 | 379 | struct pci_dev *pci_sad0, *pci_sad1; |
4d715a80 | 380 | struct pci_dev *pci_br0, *pci_br1; |
e2f747b1 QZ |
381 | /* Devices per memory controller */ |
382 | struct pci_dev *pci_ha, *pci_ta, *pci_ras; | |
eebf11a0 MCC |
383 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
384 | ||
385 | struct sbridge_dev *sbridge_dev; | |
386 | ||
387 | struct sbridge_info info; | |
388 | struct sbridge_channel channel[NUM_CHANNELS]; | |
389 | ||
eebf11a0 | 390 | /* Memory type detection */ |
039d7af6 | 391 | bool is_cur_addr_mirrored, is_lockstep, is_close_pg; |
ea5dfb5f | 392 | bool is_chan_hash; |
039d7af6 | 393 | enum mirroring_mode mirror_mode; |
eebf11a0 | 394 | |
eebf11a0 MCC |
395 | /* Memory description */ |
396 | u64 tolm, tohm; | |
d0cdf900 | 397 | struct knl_pvt knl; |
eebf11a0 MCC |
398 | }; |
399 | ||
00cf50d9 | 400 | #define PCI_DESCR(device_id, opt, domain) \ |
dbc954dd | 401 | .dev_id = (device_id), \ |
00cf50d9 QZ |
402 | .optional = opt, \ |
403 | .dom = domain | |
eebf11a0 MCC |
404 | |
405 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { | |
406 | /* Processor Home Agent */ | |
00cf50d9 | 407 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) }, |
eebf11a0 MCC |
408 | |
409 | /* Memory controller */ | |
00cf50d9 QZ |
410 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) }, |
411 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) }, | |
412 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) }, | |
413 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) }, | |
414 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) }, | |
415 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) }, | |
416 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) }, | |
eebf11a0 MCC |
417 | |
418 | /* System Address Decoder */ | |
00cf50d9 QZ |
419 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) }, |
420 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) }, | |
eebf11a0 MCC |
421 | |
422 | /* Broadcast Registers */ | |
00cf50d9 | 423 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) }, |
eebf11a0 MCC |
424 | }; |
425 | ||
00cf50d9 | 426 | #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \ |
665f05e0 | 427 | .descr = A, \ |
00cf50d9 QZ |
428 | .n_devs_per_imc = N, \ |
429 | .n_devs_per_sock = ARRAY_SIZE(A), \ | |
430 | .n_imcs_per_sock = M, \ | |
665f05e0 TL |
431 | .type = T \ |
432 | } | |
433 | ||
eebf11a0 | 434 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { |
00cf50d9 | 435 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE), |
eebf11a0 MCC |
436 | {0,} /* 0 terminated list. */ |
437 | }; | |
438 | ||
4d715a80 AR |
439 | /* This changes depending if 1HA or 2HA: |
440 | * 1HA: | |
441 | * 0x0eb8 (17.0) is DDRIO0 | |
442 | * 2HA: | |
443 | * 0x0ebc (17.4) is DDRIO0 | |
444 | */ | |
445 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 | |
446 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc | |
447 | ||
448 | /* pci ids */ | |
449 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 | |
450 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 | |
451 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 | |
452 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa | |
453 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab | |
454 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac | |
455 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead | |
456 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 | |
457 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 | |
458 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca | |
459 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 | |
460 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 | |
461 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 | |
462 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a | |
463 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b | |
7d375bff TL |
464 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c |
465 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d | |
4d715a80 AR |
466 | |
467 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { | |
468 | /* Processor Home Agent */ | |
00cf50d9 | 469 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) }, |
15cc3ae0 | 470 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) }, |
4d715a80 AR |
471 | |
472 | /* Memory controller */ | |
00cf50d9 QZ |
473 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) }, |
474 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) }, | |
475 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) }, | |
476 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) }, | |
477 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) }, | |
478 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) }, | |
479 | ||
480 | /* Optional, mode 2HA */ | |
00cf50d9 QZ |
481 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) }, |
482 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) }, | |
483 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) }, | |
484 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) }, | |
485 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) }, | |
486 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) }, | |
487 | ||
488 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) }, | |
489 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) }, | |
4d715a80 AR |
490 | |
491 | /* System Address Decoder */ | |
00cf50d9 | 492 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) }, |
4d715a80 AR |
493 | |
494 | /* Broadcast Registers */ | |
00cf50d9 QZ |
495 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) }, |
496 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) }, | |
4d715a80 | 497 | |
4d715a80 AR |
498 | }; |
499 | ||
500 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { | |
00cf50d9 | 501 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE), |
4d715a80 AR |
502 | {0,} /* 0 terminated list. */ |
503 | }; | |
504 | ||
50d1bb93 AR |
505 | /* Haswell support */ |
506 | /* EN processor: | |
507 | * - 1 IMC | |
508 | * - 3 DDR3 channels, 2 DPC per channel | |
509 | * EP processor: | |
510 | * - 1 or 2 IMC | |
511 | * - 4 DDR4 channels, 3 DPC per channel | |
512 | * EP 4S processor: | |
513 | * - 2 IMC | |
514 | * - 4 DDR4 channels, 3 DPC per channel | |
515 | * EX processor: | |
516 | * - 2 IMC | |
517 | * - each IMC interfaces with a SMI 2 channel | |
518 | * - each SMI channel interfaces with a scalable memory buffer | |
519 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
520 | */ | |
1f39581a | 521 | #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ |
50d1bb93 AR |
522 | #define HASWELL_HASYSDEFEATURE2 0x84 |
523 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 | |
524 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 | |
525 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 | |
526 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 | |
00cf50d9 | 527 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71 |
50d1bb93 | 528 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 |
00cf50d9 | 529 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79 |
50d1bb93 AR |
530 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc |
531 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd | |
532 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa | |
533 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab | |
534 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac | |
535 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad | |
536 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a | |
537 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b | |
538 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c | |
539 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d | |
540 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd | |
7179385a AR |
541 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf |
542 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9 | |
543 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb | |
50d1bb93 AR |
544 | static const struct pci_id_descr pci_dev_descr_haswell[] = { |
545 | /* first item must be the HA */ | |
00cf50d9 QZ |
546 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) }, |
547 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) }, | |
548 | ||
549 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) }, | |
550 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) }, | |
551 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) }, | |
552 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) }, | |
553 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) }, | |
554 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) }, | |
555 | ||
556 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) }, | |
557 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) }, | |
558 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) }, | |
559 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) }, | |
560 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) }, | |
561 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) }, | |
562 | ||
563 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) }, | |
564 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) }, | |
565 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) }, | |
566 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) }, | |
567 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) }, | |
568 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) }, | |
50d1bb93 AR |
569 | }; |
570 | ||
571 | static const struct pci_id_table pci_dev_descr_haswell_table[] = { | |
00cf50d9 | 572 | PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL), |
50d1bb93 AR |
573 | {0,} /* 0 terminated list. */ |
574 | }; | |
575 | ||
d0cdf900 JS |
576 | /* Knight's Landing Support */ |
577 | /* | |
578 | * KNL's memory channels are swizzled between memory controllers. | |
c5b48fa7 | 579 | * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2 |
d0cdf900 | 580 | */ |
c5b48fa7 | 581 | #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3) |
d0cdf900 JS |
582 | |
583 | /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ | |
584 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840 | |
585 | /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ | |
00cf50d9 | 586 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843 |
d0cdf900 JS |
587 | /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ |
588 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844 | |
589 | /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ | |
590 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a | |
591 | /* SAD target - 1-29-1 (1 of these) */ | |
592 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b | |
593 | /* Caching / Home Agent */ | |
594 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c | |
595 | /* Device with TOLM and TOHM, 0-5-0 (1 of these) */ | |
596 | #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810 | |
597 | ||
598 | /* | |
599 | * KNL differs from SB, IB, and Haswell in that it has multiple | |
600 | * instances of the same device with the same device ID, so we handle that | |
601 | * by creating as many copies in the table as we expect to find. | |
602 | * (Like device ID must be grouped together.) | |
603 | */ | |
604 | ||
605 | static const struct pci_id_descr pci_dev_descr_knl[] = { | |
00cf50d9 QZ |
606 | [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)}, |
607 | [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) }, | |
608 | [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) }, | |
609 | [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) }, | |
610 | [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) }, | |
611 | [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) }, | |
612 | [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) }, | |
d0cdf900 JS |
613 | }; |
614 | ||
615 | static const struct pci_id_table pci_dev_descr_knl_table[] = { | |
00cf50d9 | 616 | PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING), |
d0cdf900 JS |
617 | {0,} |
618 | }; | |
619 | ||
1f39581a TL |
620 | /* |
621 | * Broadwell support | |
622 | * | |
623 | * DE processor: | |
624 | * - 1 IMC | |
625 | * - 2 DDR3 channels, 2 DPC per channel | |
fa2ce64f TL |
626 | * EP processor: |
627 | * - 1 or 2 IMC | |
628 | * - 4 DDR4 channels, 3 DPC per channel | |
629 | * EP 4S processor: | |
630 | * - 2 IMC | |
631 | * - 4 DDR4 channels, 3 DPC per channel | |
632 | * EX processor: | |
633 | * - 2 IMC | |
634 | * - each IMC interfaces with a SMI 2 channel | |
635 | * - each SMI channel interfaces with a scalable memory buffer | |
636 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
1f39581a TL |
637 | */ |
638 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 | |
639 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 | |
fa2ce64f | 640 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 |
1f39581a | 641 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 |
00cf50d9 | 642 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71 |
fa2ce64f | 643 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 |
00cf50d9 | 644 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79 |
1f39581a TL |
645 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc |
646 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd | |
647 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa | |
648 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab | |
649 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac | |
650 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad | |
fa2ce64f TL |
651 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a |
652 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b | |
653 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c | |
654 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d | |
1f39581a TL |
655 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf |
656 | ||
657 | static const struct pci_id_descr pci_dev_descr_broadwell[] = { | |
658 | /* first item must be the HA */ | |
00cf50d9 QZ |
659 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) }, |
660 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) }, | |
661 | ||
662 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) }, | |
663 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) }, | |
664 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) }, | |
665 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) }, | |
666 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) }, | |
667 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) }, | |
668 | ||
669 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) }, | |
670 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) }, | |
671 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) }, | |
672 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) }, | |
673 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) }, | |
674 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) }, | |
675 | ||
676 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) }, | |
677 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) }, | |
678 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) }, | |
1f39581a TL |
679 | }; |
680 | ||
681 | static const struct pci_id_table pci_dev_descr_broadwell_table[] = { | |
00cf50d9 | 682 | PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL), |
1f39581a TL |
683 | {0,} /* 0 terminated list. */ |
684 | }; | |
685 | ||
eebf11a0 MCC |
686 | |
687 | /**************************************************************************** | |
15ed103a | 688 | Ancillary status routines |
eebf11a0 MCC |
689 | ****************************************************************************/ |
690 | ||
50d1bb93 | 691 | static inline int numrank(enum type type, u32 mtr) |
eebf11a0 MCC |
692 | { |
693 | int ranks = (1 << RANK_CNT_BITS(mtr)); | |
50d1bb93 AR |
694 | int max = 4; |
695 | ||
d0cdf900 | 696 | if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING) |
50d1bb93 | 697 | max = 8; |
eebf11a0 | 698 | |
50d1bb93 AR |
699 | if (ranks > max) { |
700 | edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", | |
701 | ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); | |
eebf11a0 MCC |
702 | return -EINVAL; |
703 | } | |
704 | ||
705 | return ranks; | |
706 | } | |
707 | ||
708 | static inline int numrow(u32 mtr) | |
709 | { | |
710 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | |
711 | ||
712 | if (rows < 13 || rows > 18) { | |
956b9ba1 JP |
713 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
714 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
715 | return -EINVAL; |
716 | } | |
717 | ||
718 | return 1 << rows; | |
719 | } | |
720 | ||
721 | static inline int numcol(u32 mtr) | |
722 | { | |
723 | int cols = (COL_WIDTH_BITS(mtr) + 10); | |
724 | ||
725 | if (cols > 12) { | |
956b9ba1 JP |
726 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
727 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
728 | return -EINVAL; |
729 | } | |
730 | ||
731 | return 1 << cols; | |
732 | } | |
733 | ||
190bd6e9 MM |
734 | static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom, |
735 | int multi_bus, | |
e2f747b1 | 736 | struct sbridge_dev *prev) |
eebf11a0 MCC |
737 | { |
738 | struct sbridge_dev *sbridge_dev; | |
739 | ||
c1979ba2 JS |
740 | /* |
741 | * If we have devices scattered across several busses that pertain | |
742 | * to the same memory controller, we'll lump them all together. | |
743 | */ | |
744 | if (multi_bus) { | |
745 | return list_first_entry_or_null(&sbridge_edac_list, | |
746 | struct sbridge_dev, list); | |
747 | } | |
748 | ||
e2f747b1 QZ |
749 | sbridge_dev = list_entry(prev ? prev->list.next |
750 | : sbridge_edac_list.next, struct sbridge_dev, list); | |
751 | ||
752 | list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) { | |
190bd6e9 MM |
753 | if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && |
754 | (dom == SOCK || dom == sbridge_dev->dom)) | |
eebf11a0 MCC |
755 | return sbridge_dev; |
756 | } | |
757 | ||
758 | return NULL; | |
759 | } | |
760 | ||
190bd6e9 | 761 | static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom, |
e2f747b1 | 762 | const struct pci_id_table *table) |
eebf11a0 MCC |
763 | { |
764 | struct sbridge_dev *sbridge_dev; | |
765 | ||
766 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); | |
767 | if (!sbridge_dev) | |
768 | return NULL; | |
769 | ||
e2f747b1 QZ |
770 | sbridge_dev->pdev = kcalloc(table->n_devs_per_imc, |
771 | sizeof(*sbridge_dev->pdev), | |
772 | GFP_KERNEL); | |
eebf11a0 MCC |
773 | if (!sbridge_dev->pdev) { |
774 | kfree(sbridge_dev); | |
775 | return NULL; | |
776 | } | |
777 | ||
190bd6e9 | 778 | sbridge_dev->seg = seg; |
eebf11a0 | 779 | sbridge_dev->bus = bus; |
00cf50d9 | 780 | sbridge_dev->dom = dom; |
e2f747b1 | 781 | sbridge_dev->n_devs = table->n_devs_per_imc; |
eebf11a0 MCC |
782 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); |
783 | ||
784 | return sbridge_dev; | |
785 | } | |
786 | ||
787 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) | |
788 | { | |
789 | list_del(&sbridge_dev->list); | |
790 | kfree(sbridge_dev->pdev); | |
791 | kfree(sbridge_dev); | |
792 | } | |
793 | ||
fb79a509 AR |
794 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
795 | { | |
796 | u32 reg; | |
797 | ||
798 | /* Address range is 32:28 */ | |
799 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); | |
800 | return GET_TOLM(reg); | |
801 | } | |
802 | ||
8fd6a43a AR |
803 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
804 | { | |
805 | u32 reg; | |
806 | ||
807 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); | |
808 | return GET_TOHM(reg); | |
809 | } | |
810 | ||
4d715a80 AR |
811 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
812 | { | |
813 | u32 reg; | |
814 | ||
815 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); | |
816 | ||
817 | return GET_TOLM(reg); | |
818 | } | |
819 | ||
820 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) | |
821 | { | |
822 | u32 reg; | |
823 | ||
824 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); | |
825 | ||
826 | return GET_TOHM(reg); | |
827 | } | |
828 | ||
b976bcf2 AR |
829 | static u64 rir_limit(u32 reg) |
830 | { | |
831 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; | |
832 | } | |
833 | ||
c59f9c06 JS |
834 | static u64 sad_limit(u32 reg) |
835 | { | |
836 | return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; | |
837 | } | |
838 | ||
839 | static u32 interleave_mode(u32 reg) | |
840 | { | |
841 | return GET_BITFIELD(reg, 1, 1); | |
842 | } | |
843 | ||
c59f9c06 JS |
844 | static u32 dram_attr(u32 reg) |
845 | { | |
846 | return GET_BITFIELD(reg, 2, 3); | |
847 | } | |
848 | ||
d0cdf900 JS |
849 | static u64 knl_sad_limit(u32 reg) |
850 | { | |
851 | return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff; | |
852 | } | |
853 | ||
854 | static u32 knl_interleave_mode(u32 reg) | |
855 | { | |
856 | return GET_BITFIELD(reg, 1, 2); | |
857 | } | |
858 | ||
127c1225 NI |
859 | static const char * const knl_intlv_mode[] = { |
860 | "[8:6]", "[10:8]", "[14:12]", "[32:30]" | |
861 | }; | |
d0cdf900 | 862 | |
127c1225 NI |
863 | static const char *get_intlv_mode_str(u32 reg, enum type t) |
864 | { | |
865 | if (t == KNIGHTS_LANDING) | |
866 | return knl_intlv_mode[knl_interleave_mode(reg)]; | |
867 | else | |
868 | return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]"; | |
d0cdf900 JS |
869 | } |
870 | ||
871 | static u32 dram_attr_knl(u32 reg) | |
872 | { | |
873 | return GET_BITFIELD(reg, 3, 4); | |
874 | } | |
875 | ||
876 | ||
9e375446 AR |
877 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
878 | { | |
879 | u32 reg; | |
880 | enum mem_type mtype; | |
881 | ||
882 | if (pvt->pci_ddrio) { | |
883 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, | |
884 | ®); | |
885 | if (GET_BITFIELD(reg, 11, 11)) | |
886 | /* FIXME: Can also be LRDIMM */ | |
887 | mtype = MEM_RDDR3; | |
888 | else | |
889 | mtype = MEM_DDR3; | |
890 | } else | |
891 | mtype = MEM_UNKNOWN; | |
892 | ||
893 | return mtype; | |
894 | } | |
895 | ||
50d1bb93 AR |
896 | static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) |
897 | { | |
898 | u32 reg; | |
899 | bool registered = false; | |
900 | enum mem_type mtype = MEM_UNKNOWN; | |
901 | ||
902 | if (!pvt->pci_ddrio) | |
903 | goto out; | |
904 | ||
905 | pci_read_config_dword(pvt->pci_ddrio, | |
906 | HASWELL_DDRCRCLKCONTROLS, ®); | |
907 | /* Is_Rdimm */ | |
908 | if (GET_BITFIELD(reg, 16, 16)) | |
909 | registered = true; | |
910 | ||
911 | pci_read_config_dword(pvt->pci_ta, MCMTR, ®); | |
912 | if (GET_BITFIELD(reg, 14, 14)) { | |
913 | if (registered) | |
914 | mtype = MEM_RDDR4; | |
915 | else | |
916 | mtype = MEM_DDR4; | |
917 | } else { | |
918 | if (registered) | |
919 | mtype = MEM_RDDR3; | |
920 | else | |
921 | mtype = MEM_DDR3; | |
922 | } | |
923 | ||
924 | out: | |
925 | return mtype; | |
926 | } | |
927 | ||
45f4d3ab HC |
928 | static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) |
929 | { | |
930 | /* for KNL value is fixed */ | |
931 | return DEV_X16; | |
932 | } | |
933 | ||
12f0721c AR |
934 | static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) |
935 | { | |
936 | /* there's no way to figure out */ | |
937 | return DEV_UNKNOWN; | |
938 | } | |
939 | ||
940 | static enum dev_type __ibridge_get_width(u32 mtr) | |
941 | { | |
fbd4ab78 | 942 | enum dev_type type = DEV_UNKNOWN; |
12f0721c AR |
943 | |
944 | switch (mtr) { | |
12f0721c AR |
945 | case 2: |
946 | type = DEV_X16; | |
947 | break; | |
948 | case 1: | |
949 | type = DEV_X8; | |
950 | break; | |
951 | case 0: | |
952 | type = DEV_X4; | |
953 | break; | |
954 | } | |
955 | ||
956 | return type; | |
957 | } | |
958 | ||
959 | static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) | |
960 | { | |
961 | /* | |
962 | * ddr3_width on the documentation but also valid for DDR4 on | |
963 | * Haswell | |
964 | */ | |
965 | return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); | |
966 | } | |
967 | ||
968 | static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) | |
969 | { | |
970 | /* ddr3_width on the documentation but also valid for DDR4 */ | |
971 | return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); | |
972 | } | |
973 | ||
d0cdf900 JS |
974 | static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) |
975 | { | |
976 | /* DDR4 RDIMMS and LRDIMMS are supported */ | |
977 | return MEM_RDDR4; | |
978 | } | |
979 | ||
f14d6892 AR |
980 | static u8 get_node_id(struct sbridge_pvt *pvt) |
981 | { | |
982 | u32 reg; | |
983 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); | |
984 | return GET_BITFIELD(reg, 0, 2); | |
985 | } | |
986 | ||
50d1bb93 AR |
987 | static u8 haswell_get_node_id(struct sbridge_pvt *pvt) |
988 | { | |
989 | u32 reg; | |
990 | ||
991 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
992 | return GET_BITFIELD(reg, 0, 3); | |
993 | } | |
994 | ||
d0cdf900 JS |
995 | static u8 knl_get_node_id(struct sbridge_pvt *pvt) |
996 | { | |
997 | u32 reg; | |
998 | ||
999 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
1000 | return GET_BITFIELD(reg, 0, 2); | |
1001 | } | |
1002 | ||
8489b17c QZ |
1003 | /* |
1004 | * Use the reporting bank number to determine which memory | |
1005 | * controller (also known as "ha" for "home agent"). Sandy | |
1006 | * Bridge only has one memory controller per socket, so the | |
1007 | * answer is always zero. | |
1008 | */ | |
1009 | static u8 sbridge_get_ha(u8 bank) | |
1010 | { | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * On Ivy Bridge, Haswell and Broadwell the error may be in a | |
1016 | * home agent bank (7, 8), or one of the per-channel memory | |
1017 | * controller banks (9 .. 16). | |
1018 | */ | |
1019 | static u8 ibridge_get_ha(u8 bank) | |
1020 | { | |
1021 | switch (bank) { | |
1022 | case 7 ... 8: | |
1023 | return bank - 7; | |
1024 | case 9 ... 16: | |
1025 | return (bank - 9) / 4; | |
1026 | default: | |
c968ed08 | 1027 | return 0xff; |
8489b17c QZ |
1028 | } |
1029 | } | |
1030 | ||
1031 | /* Not used, but included for safety/symmetry */ | |
1032 | static u8 knl_get_ha(u8 bank) | |
1033 | { | |
c968ed08 | 1034 | return 0xff; |
8489b17c | 1035 | } |
d0cdf900 | 1036 | |
50d1bb93 AR |
1037 | static u64 haswell_get_tolm(struct sbridge_pvt *pvt) |
1038 | { | |
1039 | u32 reg; | |
1040 | ||
f7cf2a22 TL |
1041 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); |
1042 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; | |
50d1bb93 AR |
1043 | } |
1044 | ||
1045 | static u64 haswell_get_tohm(struct sbridge_pvt *pvt) | |
1046 | { | |
1047 | u64 rc; | |
1048 | u32 reg; | |
1049 | ||
1050 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); | |
1051 | rc = GET_BITFIELD(reg, 26, 31); | |
1052 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); | |
1053 | rc = ((reg << 6) | rc) << 26; | |
1054 | ||
537bddd0 | 1055 | return rc | 0x3ffffff; |
50d1bb93 AR |
1056 | } |
1057 | ||
d0cdf900 JS |
1058 | static u64 knl_get_tolm(struct sbridge_pvt *pvt) |
1059 | { | |
1060 | u32 reg; | |
1061 | ||
1062 | pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); | |
1063 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; | |
1064 | } | |
1065 | ||
1066 | static u64 knl_get_tohm(struct sbridge_pvt *pvt) | |
1067 | { | |
1068 | u64 rc; | |
1069 | u32 reg_lo, reg_hi; | |
1070 | ||
1071 | pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); | |
1072 | pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); | |
1073 | rc = ((u64)reg_hi << 32) | reg_lo; | |
1074 | return rc | 0x3ffffff; | |
1075 | } | |
1076 | ||
1077 | ||
50d1bb93 AR |
1078 | static u64 haswell_rir_limit(u32 reg) |
1079 | { | |
1080 | return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; | |
1081 | } | |
1082 | ||
4d715a80 AR |
1083 | static inline u8 sad_pkg_socket(u8 pkg) |
1084 | { | |
1085 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ | |
2ff3a308 | 1086 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
4d715a80 AR |
1087 | } |
1088 | ||
1089 | static inline u8 sad_pkg_ha(u8 pkg) | |
1090 | { | |
1091 | return (pkg >> 2) & 0x1; | |
1092 | } | |
1093 | ||
ea5dfb5f TL |
1094 | static int haswell_chan_hash(int idx, u64 addr) |
1095 | { | |
1096 | int i; | |
1097 | ||
1098 | /* | |
1099 | * XOR even bits from 12:26 to bit0 of idx, | |
1100 | * odd bits from 13:27 to bit1 | |
1101 | */ | |
1102 | for (i = 12; i < 28; i += 2) | |
1103 | idx ^= (addr >> i) & 3; | |
1104 | ||
1105 | return idx; | |
1106 | } | |
1107 | ||
d0cdf900 JS |
1108 | /* Low bits of TAD limit, and some metadata. */ |
1109 | static const u32 knl_tad_dram_limit_lo[] = { | |
1110 | 0x400, 0x500, 0x600, 0x700, | |
1111 | 0x800, 0x900, 0xa00, 0xb00, | |
1112 | }; | |
1113 | ||
1114 | /* Low bits of TAD offset. */ | |
1115 | static const u32 knl_tad_dram_offset_lo[] = { | |
1116 | 0x404, 0x504, 0x604, 0x704, | |
1117 | 0x804, 0x904, 0xa04, 0xb04, | |
1118 | }; | |
1119 | ||
1120 | /* High 16 bits of TAD limit and offset. */ | |
1121 | static const u32 knl_tad_dram_hi[] = { | |
1122 | 0x408, 0x508, 0x608, 0x708, | |
1123 | 0x808, 0x908, 0xa08, 0xb08, | |
1124 | }; | |
1125 | ||
1126 | /* Number of ways a tad entry is interleaved. */ | |
1127 | static const u32 knl_tad_ways[] = { | |
1128 | 8, 6, 4, 3, 2, 1, | |
1129 | }; | |
1130 | ||
1131 | /* | |
1132 | * Retrieve the n'th Target Address Decode table entry | |
1133 | * from the memory controller's TAD table. | |
1134 | * | |
1135 | * @pvt: driver private data | |
1136 | * @entry: which entry you want to retrieve | |
1137 | * @mc: which memory controller (0 or 1) | |
1138 | * @offset: output tad range offset | |
1139 | * @limit: output address of first byte above tad range | |
1140 | * @ways: output number of interleave ways | |
1141 | * | |
1142 | * The offset value has curious semantics. It's a sort of running total | |
1143 | * of the sizes of all the memory regions that aren't mapped in this | |
1144 | * tad table. | |
1145 | */ | |
1146 | static int knl_get_tad(const struct sbridge_pvt *pvt, | |
1147 | const int entry, | |
1148 | const int mc, | |
1149 | u64 *offset, | |
1150 | u64 *limit, | |
1151 | int *ways) | |
1152 | { | |
1153 | u32 reg_limit_lo, reg_offset_lo, reg_hi; | |
1154 | struct pci_dev *pci_mc; | |
1155 | int way_id; | |
1156 | ||
1157 | switch (mc) { | |
1158 | case 0: | |
1159 | pci_mc = pvt->knl.pci_mc0; | |
1160 | break; | |
1161 | case 1: | |
1162 | pci_mc = pvt->knl.pci_mc1; | |
1163 | break; | |
1164 | default: | |
1165 | WARN_ON(1); | |
1166 | return -EINVAL; | |
1167 | } | |
1168 | ||
1169 | pci_read_config_dword(pci_mc, | |
1170 | knl_tad_dram_limit_lo[entry], ®_limit_lo); | |
1171 | pci_read_config_dword(pci_mc, | |
1172 | knl_tad_dram_offset_lo[entry], ®_offset_lo); | |
1173 | pci_read_config_dword(pci_mc, | |
1174 | knl_tad_dram_hi[entry], ®_hi); | |
1175 | ||
1176 | /* Is this TAD entry enabled? */ | |
1177 | if (!GET_BITFIELD(reg_limit_lo, 0, 0)) | |
1178 | return -ENODEV; | |
1179 | ||
1180 | way_id = GET_BITFIELD(reg_limit_lo, 3, 5); | |
1181 | ||
1182 | if (way_id < ARRAY_SIZE(knl_tad_ways)) { | |
1183 | *ways = knl_tad_ways[way_id]; | |
1184 | } else { | |
1185 | *ways = 0; | |
1186 | sbridge_printk(KERN_ERR, | |
1187 | "Unexpected value %d in mc_tad_limit_lo wayness field\n", | |
1188 | way_id); | |
1189 | return -ENODEV; | |
1190 | } | |
1191 | ||
1192 | /* | |
1193 | * The least significant 6 bits of base and limit are truncated. | |
1194 | * For limit, we fill the missing bits with 1s. | |
1195 | */ | |
1196 | *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) | | |
1197 | ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32); | |
1198 | *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 | | |
1199 | ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32); | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | /* Determine which memory controller is responsible for a given channel. */ | |
1205 | static int knl_channel_mc(int channel) | |
1206 | { | |
1207 | WARN_ON(channel < 0 || channel >= 6); | |
1208 | ||
1209 | return channel < 3 ? 1 : 0; | |
1210 | } | |
1211 | ||
1212 | /* | |
1213 | * Get the Nth entry from EDC_ROUTE_TABLE register. | |
1214 | * (This is the per-tile mapping of logical interleave targets to | |
1215 | * physical EDC modules.) | |
1216 | * | |
1217 | * entry 0: 0:2 | |
1218 | * 1: 3:5 | |
1219 | * 2: 6:8 | |
1220 | * 3: 9:11 | |
1221 | * 4: 12:14 | |
1222 | * 5: 15:17 | |
1223 | * 6: 18:20 | |
1224 | * 7: 21:23 | |
1225 | * reserved: 24:31 | |
1226 | */ | |
1227 | static u32 knl_get_edc_route(int entry, u32 reg) | |
1228 | { | |
1229 | WARN_ON(entry >= KNL_MAX_EDCS); | |
1230 | return GET_BITFIELD(reg, entry*3, (entry*3)+2); | |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * Get the Nth entry from MC_ROUTE_TABLE register. | |
1235 | * (This is the per-tile mapping of logical interleave targets to | |
1236 | * physical DRAM channels modules.) | |
1237 | * | |
1238 | * entry 0: mc 0:2 channel 18:19 | |
1239 | * 1: mc 3:5 channel 20:21 | |
1240 | * 2: mc 6:8 channel 22:23 | |
1241 | * 3: mc 9:11 channel 24:25 | |
1242 | * 4: mc 12:14 channel 26:27 | |
1243 | * 5: mc 15:17 channel 28:29 | |
1244 | * reserved: 30:31 | |
1245 | * | |
1246 | * Though we have 3 bits to identify the MC, we should only see | |
1247 | * the values 0 or 1. | |
1248 | */ | |
1249 | ||
1250 | static u32 knl_get_mc_route(int entry, u32 reg) | |
1251 | { | |
1252 | int mc, chan; | |
1253 | ||
1254 | WARN_ON(entry >= KNL_MAX_CHANNELS); | |
1255 | ||
1256 | mc = GET_BITFIELD(reg, entry*3, (entry*3)+2); | |
1257 | chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1); | |
1258 | ||
c5b48fa7 | 1259 | return knl_channel_remap(mc, chan); |
d0cdf900 JS |
1260 | } |
1261 | ||
1262 | /* | |
1263 | * Render the EDC_ROUTE register in human-readable form. | |
1264 | * Output string s should be at least KNL_MAX_EDCS*2 bytes. | |
1265 | */ | |
1266 | static void knl_show_edc_route(u32 reg, char *s) | |
1267 | { | |
1268 | int i; | |
1269 | ||
1270 | for (i = 0; i < KNL_MAX_EDCS; i++) { | |
1271 | s[i*2] = knl_get_edc_route(i, reg) + '0'; | |
1272 | s[i*2+1] = '-'; | |
1273 | } | |
1274 | ||
1275 | s[KNL_MAX_EDCS*2 - 1] = '\0'; | |
1276 | } | |
1277 | ||
1278 | /* | |
1279 | * Render the MC_ROUTE register in human-readable form. | |
1280 | * Output string s should be at least KNL_MAX_CHANNELS*2 bytes. | |
1281 | */ | |
1282 | static void knl_show_mc_route(u32 reg, char *s) | |
1283 | { | |
1284 | int i; | |
1285 | ||
1286 | for (i = 0; i < KNL_MAX_CHANNELS; i++) { | |
1287 | s[i*2] = knl_get_mc_route(i, reg) + '0'; | |
1288 | s[i*2+1] = '-'; | |
1289 | } | |
1290 | ||
1291 | s[KNL_MAX_CHANNELS*2 - 1] = '\0'; | |
1292 | } | |
1293 | ||
1294 | #define KNL_EDC_ROUTE 0xb8 | |
1295 | #define KNL_MC_ROUTE 0xb4 | |
1296 | ||
1297 | /* Is this dram rule backed by regular DRAM in flat mode? */ | |
1298 | #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29) | |
1299 | ||
1300 | /* Is this dram rule cached? */ | |
1301 | #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) | |
1302 | ||
1303 | /* Is this rule backed by edc ? */ | |
1304 | #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29) | |
1305 | ||
1306 | /* Is this rule backed by DRAM, cacheable in EDRAM? */ | |
1307 | #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) | |
1308 | ||
1309 | /* Is this rule mod3? */ | |
1310 | #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27) | |
1311 | ||
1312 | /* | |
1313 | * Figure out how big our RAM modules are. | |
1314 | * | |
1315 | * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we | |
1316 | * have to figure this out from the SAD rules, interleave lists, route tables, | |
1317 | * and TAD rules. | |
1318 | * | |
1319 | * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to | |
1320 | * inspect the TAD rules to figure out how large the SAD regions really are. | |
1321 | * | |
1322 | * When we know the real size of a SAD region and how many ways it's | |
1323 | * interleaved, we know the individual contribution of each channel to | |
1324 | * TAD is size/ways. | |
1325 | * | |
1326 | * Finally, we have to check whether each channel participates in each SAD | |
1327 | * region. | |
1328 | * | |
1329 | * Fortunately, KNL only supports one DIMM per channel, so once we know how | |
1330 | * much memory the channel uses, we know the DIMM is at least that large. | |
1331 | * (The BIOS might possibly choose not to map all available memory, in which | |
1332 | * case we will underreport the size of the DIMM.) | |
1333 | * | |
1334 | * In theory, we could try to determine the EDC sizes as well, but that would | |
1335 | * only work in flat mode, not in cache mode. | |
1336 | * | |
1337 | * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS | |
1338 | * elements) | |
1339 | */ | |
1340 | static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) | |
1341 | { | |
323014d8 | 1342 | u64 sad_base, sad_limit = 0; |
d0cdf900 JS |
1343 | u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace; |
1344 | int sad_rule = 0; | |
1345 | int tad_rule = 0; | |
1346 | int intrlv_ways, tad_ways; | |
1347 | u32 first_pkg, pkg; | |
1348 | int i; | |
1349 | u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */ | |
1350 | u32 dram_rule, interleave_reg; | |
1351 | u32 mc_route_reg[KNL_MAX_CHAS]; | |
1352 | u32 edc_route_reg[KNL_MAX_CHAS]; | |
1353 | int edram_only; | |
1354 | char edc_route_string[KNL_MAX_EDCS*2]; | |
1355 | char mc_route_string[KNL_MAX_CHANNELS*2]; | |
1356 | int cur_reg_start; | |
1357 | int mc; | |
1358 | int channel; | |
d0cdf900 | 1359 | int participants[KNL_MAX_CHANNELS]; |
d0cdf900 JS |
1360 | |
1361 | for (i = 0; i < KNL_MAX_CHANNELS; i++) | |
1362 | mc_sizes[i] = 0; | |
1363 | ||
1364 | /* Read the EDC route table in each CHA. */ | |
1365 | cur_reg_start = 0; | |
1366 | for (i = 0; i < KNL_MAX_CHAS; i++) { | |
1367 | pci_read_config_dword(pvt->knl.pci_cha[i], | |
1368 | KNL_EDC_ROUTE, &edc_route_reg[i]); | |
1369 | ||
1370 | if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { | |
1371 | knl_show_edc_route(edc_route_reg[i-1], | |
1372 | edc_route_string); | |
1373 | if (cur_reg_start == i-1) | |
1374 | edac_dbg(0, "edc route table for CHA %d: %s\n", | |
1375 | cur_reg_start, edc_route_string); | |
1376 | else | |
1377 | edac_dbg(0, "edc route table for CHA %d-%d: %s\n", | |
1378 | cur_reg_start, i-1, edc_route_string); | |
1379 | cur_reg_start = i; | |
1380 | } | |
1381 | } | |
1382 | knl_show_edc_route(edc_route_reg[i-1], edc_route_string); | |
1383 | if (cur_reg_start == i-1) | |
1384 | edac_dbg(0, "edc route table for CHA %d: %s\n", | |
1385 | cur_reg_start, edc_route_string); | |
1386 | else | |
1387 | edac_dbg(0, "edc route table for CHA %d-%d: %s\n", | |
1388 | cur_reg_start, i-1, edc_route_string); | |
1389 | ||
1390 | /* Read the MC route table in each CHA. */ | |
1391 | cur_reg_start = 0; | |
1392 | for (i = 0; i < KNL_MAX_CHAS; i++) { | |
1393 | pci_read_config_dword(pvt->knl.pci_cha[i], | |
1394 | KNL_MC_ROUTE, &mc_route_reg[i]); | |
1395 | ||
1396 | if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { | |
1397 | knl_show_mc_route(mc_route_reg[i-1], mc_route_string); | |
1398 | if (cur_reg_start == i-1) | |
1399 | edac_dbg(0, "mc route table for CHA %d: %s\n", | |
1400 | cur_reg_start, mc_route_string); | |
1401 | else | |
1402 | edac_dbg(0, "mc route table for CHA %d-%d: %s\n", | |
1403 | cur_reg_start, i-1, mc_route_string); | |
1404 | cur_reg_start = i; | |
1405 | } | |
1406 | } | |
1407 | knl_show_mc_route(mc_route_reg[i-1], mc_route_string); | |
1408 | if (cur_reg_start == i-1) | |
1409 | edac_dbg(0, "mc route table for CHA %d: %s\n", | |
1410 | cur_reg_start, mc_route_string); | |
1411 | else | |
1412 | edac_dbg(0, "mc route table for CHA %d-%d: %s\n", | |
1413 | cur_reg_start, i-1, mc_route_string); | |
1414 | ||
1415 | /* Process DRAM rules */ | |
1416 | for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { | |
1417 | /* previous limit becomes the new base */ | |
1418 | sad_base = sad_limit; | |
1419 | ||
1420 | pci_read_config_dword(pvt->pci_sad0, | |
1421 | pvt->info.dram_rule[sad_rule], &dram_rule); | |
1422 | ||
1423 | if (!DRAM_RULE_ENABLE(dram_rule)) | |
1424 | break; | |
1425 | ||
1426 | edram_only = KNL_EDRAM_ONLY(dram_rule); | |
1427 | ||
1428 | sad_limit = pvt->info.sad_limit(dram_rule)+1; | |
d0cdf900 JS |
1429 | |
1430 | pci_read_config_dword(pvt->pci_sad0, | |
1431 | pvt->info.interleave_list[sad_rule], &interleave_reg); | |
1432 | ||
1433 | /* | |
1434 | * Find out how many ways this dram rule is interleaved. | |
1435 | * We stop when we see the first channel again. | |
1436 | */ | |
1437 | first_pkg = sad_pkg(pvt->info.interleave_pkg, | |
1438 | interleave_reg, 0); | |
1439 | for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) { | |
1440 | pkg = sad_pkg(pvt->info.interleave_pkg, | |
1441 | interleave_reg, intrlv_ways); | |
1442 | ||
1443 | if ((pkg & 0x8) == 0) { | |
1444 | /* | |
1445 | * 0 bit means memory is non-local, | |
1446 | * which KNL doesn't support | |
1447 | */ | |
1448 | edac_dbg(0, "Unexpected interleave target %d\n", | |
1449 | pkg); | |
1450 | return -1; | |
1451 | } | |
1452 | ||
1453 | if (pkg == first_pkg) | |
1454 | break; | |
1455 | } | |
1456 | if (KNL_MOD3(dram_rule)) | |
1457 | intrlv_ways *= 3; | |
1458 | ||
1459 | edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", | |
1460 | sad_rule, | |
1461 | sad_base, | |
1462 | sad_limit, | |
1463 | intrlv_ways, | |
1464 | edram_only ? ", EDRAM" : ""); | |
1465 | ||
1466 | /* | |
1467 | * Find out how big the SAD region really is by iterating | |
1468 | * over TAD tables (SAD regions may contain holes). | |
1469 | * Each memory controller might have a different TAD table, so | |
1470 | * we have to look at both. | |
1471 | * | |
1472 | * Livespace is the memory that's mapped in this TAD table, | |
1473 | * deadspace is the holes (this could be the MMIO hole, or it | |
1474 | * could be memory that's mapped by the other TAD table but | |
1475 | * not this one). | |
1476 | */ | |
1477 | for (mc = 0; mc < 2; mc++) { | |
1478 | sad_actual_size[mc] = 0; | |
1479 | tad_livespace = 0; | |
1480 | for (tad_rule = 0; | |
1481 | tad_rule < ARRAY_SIZE( | |
1482 | knl_tad_dram_limit_lo); | |
1483 | tad_rule++) { | |
1484 | if (knl_get_tad(pvt, | |
1485 | tad_rule, | |
1486 | mc, | |
1487 | &tad_deadspace, | |
1488 | &tad_limit, | |
1489 | &tad_ways)) | |
1490 | break; | |
1491 | ||
1492 | tad_size = (tad_limit+1) - | |
1493 | (tad_livespace + tad_deadspace); | |
1494 | tad_livespace += tad_size; | |
1495 | tad_base = (tad_limit+1) - tad_size; | |
1496 | ||
1497 | if (tad_base < sad_base) { | |
1498 | if (tad_limit > sad_base) | |
1499 | edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n"); | |
1500 | } else if (tad_base < sad_limit) { | |
1501 | if (tad_limit+1 > sad_limit) { | |
1502 | edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n"); | |
1503 | } else { | |
1504 | /* TAD region is completely inside SAD region */ | |
1505 | edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", | |
1506 | tad_rule, tad_base, | |
1507 | tad_limit, tad_size, | |
1508 | mc); | |
1509 | sad_actual_size[mc] += tad_size; | |
1510 | } | |
1511 | } | |
d0cdf900 JS |
1512 | } |
1513 | } | |
1514 | ||
1515 | for (mc = 0; mc < 2; mc++) { | |
1516 | edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n", | |
1517 | mc, sad_actual_size[mc], sad_actual_size[mc]); | |
1518 | } | |
1519 | ||
1520 | /* Ignore EDRAM rule */ | |
1521 | if (edram_only) | |
1522 | continue; | |
1523 | ||
1524 | /* Figure out which channels participate in interleave. */ | |
1525 | for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) | |
1526 | participants[channel] = 0; | |
1527 | ||
1528 | /* For each channel, does at least one CHA have | |
1529 | * this channel mapped to the given target? | |
1530 | */ | |
1531 | for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { | |
24281a2f LFSC |
1532 | int target; |
1533 | int cha; | |
d0cdf900 | 1534 | |
24281a2f | 1535 | for (target = 0; target < KNL_MAX_CHANNELS; target++) { |
d0cdf900 JS |
1536 | for (cha = 0; cha < KNL_MAX_CHAS; cha++) { |
1537 | if (knl_get_mc_route(target, | |
1538 | mc_route_reg[cha]) == channel | |
83bdaad4 | 1539 | && !participants[channel]) { |
d0cdf900 JS |
1540 | participants[channel] = 1; |
1541 | break; | |
1542 | } | |
1543 | } | |
1544 | } | |
1545 | } | |
1546 | ||
d0cdf900 JS |
1547 | for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { |
1548 | mc = knl_channel_mc(channel); | |
1549 | if (participants[channel]) { | |
1550 | edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n", | |
1551 | channel, | |
1552 | sad_actual_size[mc]/intrlv_ways, | |
1553 | sad_rule); | |
1554 | mc_sizes[channel] += | |
1555 | sad_actual_size[mc]/intrlv_ways; | |
1556 | } | |
1557 | } | |
1558 | } | |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | ||
7fd562b7 TL |
1563 | static void get_source_id(struct mem_ctl_info *mci) |
1564 | { | |
1565 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1566 | u32 reg; | |
1567 | ||
1568 | if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || | |
1569 | pvt->info.type == KNIGHTS_LANDING) | |
1570 | pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); | |
1571 | else | |
1572 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); | |
1573 | ||
1574 | if (pvt->info.type == KNIGHTS_LANDING) | |
1575 | pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); | |
1576 | else | |
1577 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); | |
1578 | } | |
1579 | ||
4d475dde QZ |
1580 | static int __populate_dimms(struct mem_ctl_info *mci, |
1581 | u64 knl_mc_sizes[KNL_MAX_CHANNELS], | |
1582 | enum edac_type mode) | |
eebf11a0 MCC |
1583 | { |
1584 | struct sbridge_pvt *pvt = mci->pvt_info; | |
66965229 BP |
1585 | int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS |
1586 | : NUM_CHANNELS; | |
1587 | unsigned int i, j, banks, ranks, rows, cols, npages; | |
c36e3e77 | 1588 | struct dimm_info *dimm; |
c6e13b52 | 1589 | enum mem_type mtype; |
66965229 | 1590 | u64 size; |
eebf11a0 | 1591 | |
9e375446 | 1592 | mtype = pvt->info.get_memory_type(pvt); |
50d1bb93 | 1593 | if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) |
9e375446 AR |
1594 | edac_dbg(0, "Memory is registered\n"); |
1595 | else if (mtype == MEM_UNKNOWN) | |
de4772c6 | 1596 | edac_dbg(0, "Cannot determine memory type\n"); |
9e375446 AR |
1597 | else |
1598 | edac_dbg(0, "Memory is unregistered\n"); | |
eebf11a0 | 1599 | |
fec53af5 | 1600 | if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) |
50d1bb93 AR |
1601 | banks = 16; |
1602 | else | |
1603 | banks = 8; | |
eebf11a0 | 1604 | |
d0cdf900 | 1605 | for (i = 0; i < channels; i++) { |
eebf11a0 MCC |
1606 | u32 mtr; |
1607 | ||
d0cdf900 JS |
1608 | int max_dimms_per_channel; |
1609 | ||
1610 | if (pvt->info.type == KNIGHTS_LANDING) { | |
1611 | max_dimms_per_channel = 1; | |
1612 | if (!pvt->knl.pci_channel[i]) | |
1613 | continue; | |
1614 | } else { | |
1615 | max_dimms_per_channel = ARRAY_SIZE(mtr_regs); | |
1616 | if (!pvt->pci_tad[i]) | |
1617 | continue; | |
1618 | } | |
1619 | ||
1620 | for (j = 0; j < max_dimms_per_channel; j++) { | |
bc9ad9e4 | 1621 | dimm = edac_get_dimm(mci, i, j, 0); |
d0cdf900 JS |
1622 | if (pvt->info.type == KNIGHTS_LANDING) { |
1623 | pci_read_config_dword(pvt->knl.pci_channel[i], | |
1624 | knl_mtr_reg, &mtr); | |
1625 | } else { | |
1626 | pci_read_config_dword(pvt->pci_tad[i], | |
1627 | mtr_regs[j], &mtr); | |
1628 | } | |
956b9ba1 | 1629 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
eebf11a0 | 1630 | if (IS_DIMM_PRESENT(mtr)) { |
4d475dde QZ |
1631 | if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { |
1632 | sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n", | |
1633 | pvt->sbridge_dev->source_id, | |
1634 | pvt->sbridge_dev->dom, i); | |
1635 | return -ENODEV; | |
1636 | } | |
eebf11a0 MCC |
1637 | pvt->channel[i].dimms++; |
1638 | ||
50d1bb93 | 1639 | ranks = numrank(pvt->info.type, mtr); |
d0cdf900 JS |
1640 | |
1641 | if (pvt->info.type == KNIGHTS_LANDING) { | |
1642 | /* For DDR4, this is fixed. */ | |
1643 | cols = 1 << 10; | |
1644 | rows = knl_mc_sizes[i] / | |
1645 | ((u64) cols * ranks * banks * 8); | |
1646 | } else { | |
1647 | rows = numrow(mtr); | |
1648 | cols = numcol(mtr); | |
1649 | } | |
eebf11a0 | 1650 | |
deb09dda | 1651 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
eebf11a0 MCC |
1652 | npages = MiB_TO_PAGES(size); |
1653 | ||
6f6da136 | 1654 | edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
e2f747b1 | 1655 | pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, |
956b9ba1 JP |
1656 | size, npages, |
1657 | banks, ranks, rows, cols); | |
eebf11a0 | 1658 | |
a895bf8b | 1659 | dimm->nr_pages = npages; |
084a4fcc | 1660 | dimm->grain = 32; |
12f0721c | 1661 | dimm->dtype = pvt->info.get_width(pvt, mtr); |
084a4fcc MCC |
1662 | dimm->mtype = mtype; |
1663 | dimm->edac_mode = mode; | |
1664 | snprintf(dimm->label, sizeof(dimm->label), | |
e2f747b1 QZ |
1665 | "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", |
1666 | pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); | |
eebf11a0 MCC |
1667 | } |
1668 | } | |
1669 | } | |
4d475dde QZ |
1670 | |
1671 | return 0; | |
66965229 BP |
1672 | } |
1673 | ||
1674 | static int get_dimm_config(struct mem_ctl_info *mci) | |
1675 | { | |
1676 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1677 | u64 knl_mc_sizes[KNL_MAX_CHANNELS]; | |
1678 | enum edac_type mode; | |
1679 | u32 reg; | |
1680 | ||
66965229 BP |
1681 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
1682 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", | |
1683 | pvt->sbridge_dev->mc, | |
1684 | pvt->sbridge_dev->node_id, | |
1685 | pvt->sbridge_dev->source_id); | |
1686 | ||
1687 | /* KNL doesn't support mirroring or lockstep, | |
1688 | * and is always closed page | |
1689 | */ | |
1690 | if (pvt->info.type == KNIGHTS_LANDING) { | |
1691 | mode = EDAC_S4ECD4ED; | |
039d7af6 QZ |
1692 | pvt->mirror_mode = NON_MIRRORING; |
1693 | pvt->is_cur_addr_mirrored = false; | |
66965229 BP |
1694 | |
1695 | if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) | |
1696 | return -1; | |
039d7af6 QZ |
1697 | if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { |
1698 | edac_dbg(0, "Failed to read KNL_MCMTR register\n"); | |
1699 | return -ENODEV; | |
1700 | } | |
66965229 | 1701 | } else { |
039d7af6 QZ |
1702 | if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { |
1703 | if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { | |
1704 | edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n"); | |
1705 | return -ENODEV; | |
1706 | } | |
1707 | pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); | |
1708 | if (GET_BITFIELD(reg, 28, 28)) { | |
1709 | pvt->mirror_mode = ADDR_RANGE_MIRRORING; | |
1710 | edac_dbg(0, "Address range partial memory mirroring is enabled\n"); | |
1711 | goto next; | |
1712 | } | |
1713 | } | |
1714 | if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { | |
1715 | edac_dbg(0, "Failed to read RASENABLES register\n"); | |
1716 | return -ENODEV; | |
1717 | } | |
66965229 | 1718 | if (IS_MIRROR_ENABLED(reg)) { |
039d7af6 QZ |
1719 | pvt->mirror_mode = FULL_MIRRORING; |
1720 | edac_dbg(0, "Full memory mirroring is enabled\n"); | |
66965229 | 1721 | } else { |
039d7af6 QZ |
1722 | pvt->mirror_mode = NON_MIRRORING; |
1723 | edac_dbg(0, "Memory mirroring is disabled\n"); | |
66965229 BP |
1724 | } |
1725 | ||
039d7af6 QZ |
1726 | next: |
1727 | if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { | |
1728 | edac_dbg(0, "Failed to read MCMTR register\n"); | |
1729 | return -ENODEV; | |
1730 | } | |
66965229 BP |
1731 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { |
1732 | edac_dbg(0, "Lockstep is enabled\n"); | |
1733 | mode = EDAC_S8ECD8ED; | |
1734 | pvt->is_lockstep = true; | |
1735 | } else { | |
1736 | edac_dbg(0, "Lockstep is disabled\n"); | |
1737 | mode = EDAC_S4ECD4ED; | |
1738 | pvt->is_lockstep = false; | |
1739 | } | |
1740 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | |
1741 | edac_dbg(0, "address map is on closed page mode\n"); | |
1742 | pvt->is_close_pg = true; | |
1743 | } else { | |
1744 | edac_dbg(0, "address map is on open page mode\n"); | |
1745 | pvt->is_close_pg = false; | |
1746 | } | |
1747 | } | |
1748 | ||
4d475dde | 1749 | return __populate_dimms(mci, knl_mc_sizes, mode); |
eebf11a0 MCC |
1750 | } |
1751 | ||
1752 | static void get_memory_layout(const struct mem_ctl_info *mci) | |
1753 | { | |
1754 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1755 | int i, j, k, n_sads, n_tads, sad_interl; | |
1756 | u32 reg; | |
1757 | u64 limit, prv = 0; | |
1758 | u64 tmp_mb; | |
8c009100 | 1759 | u32 gb, mb; |
eebf11a0 MCC |
1760 | u32 rir_way; |
1761 | ||
1762 | /* | |
1763 | * Step 1) Get TOLM/TOHM ranges | |
1764 | */ | |
1765 | ||
fb79a509 | 1766 | pvt->tolm = pvt->info.get_tolm(pvt); |
eebf11a0 MCC |
1767 | tmp_mb = (1 + pvt->tolm) >> 20; |
1768 | ||
8c009100 JS |
1769 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
1770 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", | |
1771 | gb, (mb*1000)/1024, (u64)pvt->tolm); | |
eebf11a0 MCC |
1772 | |
1773 | /* Address range is already 45:25 */ | |
8fd6a43a | 1774 | pvt->tohm = pvt->info.get_tohm(pvt); |
eebf11a0 MCC |
1775 | tmp_mb = (1 + pvt->tohm) >> 20; |
1776 | ||
8c009100 JS |
1777 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
1778 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", | |
1779 | gb, (mb*1000)/1024, (u64)pvt->tohm); | |
eebf11a0 MCC |
1780 | |
1781 | /* | |
1782 | * Step 2) Get SAD range and SAD Interleave list | |
1783 | * TAD registers contain the interleave wayness. However, it | |
1784 | * seems simpler to just discover it indirectly, with the | |
1785 | * algorithm bellow. | |
1786 | */ | |
1787 | prv = 0; | |
464f1d82 | 1788 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
eebf11a0 | 1789 | /* SAD_LIMIT Address range is 45:26 */ |
464f1d82 | 1790 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
eebf11a0 | 1791 | ®); |
c59f9c06 | 1792 | limit = pvt->info.sad_limit(reg); |
eebf11a0 MCC |
1793 | |
1794 | if (!DRAM_RULE_ENABLE(reg)) | |
1795 | continue; | |
1796 | ||
1797 | if (limit <= prv) | |
1798 | break; | |
1799 | ||
1800 | tmp_mb = (limit + 1) >> 20; | |
8c009100 | 1801 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1802 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
1803 | n_sads, | |
c59f9c06 | 1804 | show_dram_attr(pvt->info.dram_attr(reg)), |
8c009100 | 1805 | gb, (mb*1000)/1024, |
956b9ba1 | 1806 | ((u64)tmp_mb) << 20L, |
127c1225 | 1807 | get_intlv_mode_str(reg, pvt->info.type), |
956b9ba1 | 1808 | reg); |
eebf11a0 MCC |
1809 | prv = limit; |
1810 | ||
ef1ce51e | 1811 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1812 | ®); |
cc311991 | 1813 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 1814 | for (j = 0; j < 8; j++) { |
cc311991 AR |
1815 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
1816 | if (j > 0 && sad_interl == pkg) | |
eebf11a0 MCC |
1817 | break; |
1818 | ||
956b9ba1 | 1819 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
cc311991 | 1820 | n_sads, j, pkg); |
eebf11a0 MCC |
1821 | } |
1822 | } | |
1823 | ||
d0cdf900 JS |
1824 | if (pvt->info.type == KNIGHTS_LANDING) |
1825 | return; | |
1826 | ||
eebf11a0 MCC |
1827 | /* |
1828 | * Step 3) Get TAD range | |
1829 | */ | |
1830 | prv = 0; | |
1831 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
e2f747b1 | 1832 | pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); |
eebf11a0 MCC |
1833 | limit = TAD_LIMIT(reg); |
1834 | if (limit <= prv) | |
1835 | break; | |
1836 | tmp_mb = (limit + 1) >> 20; | |
1837 | ||
8c009100 | 1838 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 | 1839 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
8c009100 | 1840 | n_tads, gb, (mb*1000)/1024, |
956b9ba1 | 1841 | ((u64)tmp_mb) << 20L, |
eb1af3b7 LT |
1842 | (u32)(1 << TAD_SOCK(reg)), |
1843 | (u32)TAD_CH(reg) + 1, | |
956b9ba1 JP |
1844 | (u32)TAD_TGT0(reg), |
1845 | (u32)TAD_TGT1(reg), | |
1846 | (u32)TAD_TGT2(reg), | |
1847 | (u32)TAD_TGT3(reg), | |
1848 | reg); | |
7fae0db4 | 1849 | prv = limit; |
eebf11a0 MCC |
1850 | } |
1851 | ||
1852 | /* | |
1853 | * Step 4) Get TAD offsets, per each channel | |
1854 | */ | |
1855 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1856 | if (!pvt->channel[i].dimms) | |
1857 | continue; | |
1858 | for (j = 0; j < n_tads; j++) { | |
1859 | pci_read_config_dword(pvt->pci_tad[i], | |
1860 | tad_ch_nilv_offset[j], | |
1861 | ®); | |
1862 | tmp_mb = TAD_OFFSET(reg) >> 20; | |
8c009100 | 1863 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1864 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
1865 | i, j, | |
8c009100 | 1866 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1867 | ((u64)tmp_mb) << 20L, |
1868 | reg); | |
eebf11a0 MCC |
1869 | } |
1870 | } | |
1871 | ||
1872 | /* | |
1873 | * Step 6) Get RIR Wayness/Limit, per each channel | |
1874 | */ | |
1875 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1876 | if (!pvt->channel[i].dimms) | |
1877 | continue; | |
1878 | for (j = 0; j < MAX_RIR_RANGES; j++) { | |
1879 | pci_read_config_dword(pvt->pci_tad[i], | |
1880 | rir_way_limit[j], | |
1881 | ®); | |
1882 | ||
1883 | if (!IS_RIR_VALID(reg)) | |
1884 | continue; | |
1885 | ||
b976bcf2 | 1886 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
eebf11a0 | 1887 | rir_way = 1 << RIR_WAY(reg); |
8c009100 | 1888 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1889 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
1890 | i, j, | |
8c009100 | 1891 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1892 | ((u64)tmp_mb) << 20L, |
1893 | rir_way, | |
1894 | reg); | |
eebf11a0 MCC |
1895 | |
1896 | for (k = 0; k < rir_way; k++) { | |
1897 | pci_read_config_dword(pvt->pci_tad[i], | |
1898 | rir_offset[j][k], | |
1899 | ®); | |
c7103f65 | 1900 | tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; |
eebf11a0 | 1901 | |
8c009100 | 1902 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1903 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
1904 | i, j, k, | |
8c009100 | 1905 | gb, (mb*1000)/1024, |
956b9ba1 | 1906 | ((u64)tmp_mb) << 20L, |
c7103f65 | 1907 | (u32)RIR_RNK_TGT(pvt->info.type, reg), |
956b9ba1 | 1908 | reg); |
eebf11a0 MCC |
1909 | } |
1910 | } | |
1911 | } | |
1912 | } | |
1913 | ||
e2f747b1 | 1914 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha) |
eebf11a0 MCC |
1915 | { |
1916 | struct sbridge_dev *sbridge_dev; | |
1917 | ||
1918 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
e2f747b1 | 1919 | if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) |
eebf11a0 MCC |
1920 | return sbridge_dev->mci; |
1921 | } | |
1922 | return NULL; | |
1923 | } | |
1924 | ||
1925 | static int get_memory_error_data(struct mem_ctl_info *mci, | |
1926 | u64 addr, | |
7d375bff | 1927 | u8 *socket, u8 *ha, |
eebf11a0 MCC |
1928 | long *channel_mask, |
1929 | u8 *rank, | |
e17a2f42 | 1930 | char **area_type, char *msg) |
eebf11a0 MCC |
1931 | { |
1932 | struct mem_ctl_info *new_mci; | |
1933 | struct sbridge_pvt *pvt = mci->pvt_info; | |
4d715a80 | 1934 | struct pci_dev *pci_ha; |
c41afdca | 1935 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
eebf11a0 | 1936 | int sad_interl, idx, base_ch; |
50d1bb93 | 1937 | int interleave_mode, shiftup = 0; |
6fd05266 | 1938 | unsigned int sad_interleave[MAX_INTERLEAVE]; |
50d1bb93 | 1939 | u32 reg, dram_rule; |
e2f747b1 | 1940 | u8 ch_way, sck_way, pkg, sad_ha = 0; |
eebf11a0 MCC |
1941 | u32 tad_offset; |
1942 | u32 rir_way; | |
8c009100 | 1943 | u32 mb, gb; |
bd4b9683 | 1944 | u64 ch_addr, offset, limit = 0, prv = 0; |
eebf11a0 MCC |
1945 | |
1946 | ||
1947 | /* | |
1948 | * Step 0) Check if the address is at special memory ranges | |
1949 | * The check bellow is probably enough to fill all cases where | |
1950 | * the error is not inside a memory, except for the legacy | |
1951 | * range (e. g. VGA addresses). It is unlikely, however, that the | |
1952 | * memory controller would generate an error on that range. | |
1953 | */ | |
5b889e37 | 1954 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
eebf11a0 | 1955 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
eebf11a0 MCC |
1956 | return -EINVAL; |
1957 | } | |
1958 | if (addr >= (u64)pvt->tohm) { | |
1959 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); | |
eebf11a0 MCC |
1960 | return -EINVAL; |
1961 | } | |
1962 | ||
1963 | /* | |
1964 | * Step 1) Get socket | |
1965 | */ | |
464f1d82 AR |
1966 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
1967 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], | |
eebf11a0 MCC |
1968 | ®); |
1969 | ||
1970 | if (!DRAM_RULE_ENABLE(reg)) | |
1971 | continue; | |
1972 | ||
c59f9c06 | 1973 | limit = pvt->info.sad_limit(reg); |
eebf11a0 MCC |
1974 | if (limit <= prv) { |
1975 | sprintf(msg, "Can't discover the memory socket"); | |
eebf11a0 MCC |
1976 | return -EINVAL; |
1977 | } | |
1978 | if (addr <= limit) | |
1979 | break; | |
1980 | prv = limit; | |
1981 | } | |
464f1d82 | 1982 | if (n_sads == pvt->info.max_sad) { |
eebf11a0 | 1983 | sprintf(msg, "Can't discover the memory socket"); |
eebf11a0 MCC |
1984 | return -EINVAL; |
1985 | } | |
50d1bb93 | 1986 | dram_rule = reg; |
c59f9c06 JS |
1987 | *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); |
1988 | interleave_mode = pvt->info.interleave_mode(dram_rule); | |
eebf11a0 | 1989 | |
ef1ce51e | 1990 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1991 | ®); |
4d715a80 AR |
1992 | |
1993 | if (pvt->info.type == SANDY_BRIDGE) { | |
1994 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); | |
1995 | for (sad_way = 0; sad_way < 8; sad_way++) { | |
1996 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); | |
1997 | if (sad_way > 0 && sad_interl == pkg) | |
1998 | break; | |
1999 | sad_interleave[sad_way] = pkg; | |
2000 | edac_dbg(0, "SAD interleave #%d: %d\n", | |
2001 | sad_way, sad_interleave[sad_way]); | |
2002 | } | |
2003 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", | |
2004 | pvt->sbridge_dev->mc, | |
2005 | n_sads, | |
2006 | addr, | |
2007 | limit, | |
2008 | sad_way + 7, | |
2009 | !interleave_mode ? "" : "XOR[18:16]"); | |
2010 | if (interleave_mode) | |
2011 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | |
2012 | else | |
2013 | idx = (addr >> 6) & 7; | |
2014 | switch (sad_way) { | |
2015 | case 1: | |
2016 | idx = 0; | |
eebf11a0 | 2017 | break; |
4d715a80 AR |
2018 | case 2: |
2019 | idx = idx & 1; | |
2020 | break; | |
2021 | case 4: | |
2022 | idx = idx & 3; | |
2023 | break; | |
2024 | case 8: | |
2025 | break; | |
2026 | default: | |
2027 | sprintf(msg, "Can't discover socket interleave"); | |
2028 | return -EINVAL; | |
2029 | } | |
2030 | *socket = sad_interleave[idx]; | |
2031 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", | |
2032 | idx, sad_way, *socket); | |
1f39581a | 2033 | } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { |
50d1bb93 AR |
2034 | int bits, a7mode = A7MODE(dram_rule); |
2035 | ||
2036 | if (a7mode) { | |
2037 | /* A7 mode swaps P9 with P6 */ | |
2038 | bits = GET_BITFIELD(addr, 7, 8) << 1; | |
2039 | bits |= GET_BITFIELD(addr, 9, 9); | |
2040 | } else | |
bb89e714 | 2041 | bits = GET_BITFIELD(addr, 6, 8); |
50d1bb93 | 2042 | |
bb89e714 | 2043 | if (interleave_mode == 0) { |
50d1bb93 AR |
2044 | /* interleave mode will XOR {8,7,6} with {18,17,16} */ |
2045 | idx = GET_BITFIELD(addr, 16, 18); | |
2046 | idx ^= bits; | |
2047 | } else | |
2048 | idx = bits; | |
2049 | ||
2050 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); | |
2051 | *socket = sad_pkg_socket(pkg); | |
2052 | sad_ha = sad_pkg_ha(pkg); | |
2053 | ||
2054 | if (a7mode) { | |
2055 | /* MCChanShiftUpEnable */ | |
e2f747b1 | 2056 | pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); |
50d1bb93 AR |
2057 | shiftup = GET_BITFIELD(reg, 22, 22); |
2058 | } | |
2059 | ||
2060 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", | |
2061 | idx, *socket, sad_ha, shiftup); | |
4d715a80 AR |
2062 | } else { |
2063 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ | |
eebf11a0 | 2064 | idx = (addr >> 6) & 7; |
4d715a80 AR |
2065 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
2066 | *socket = sad_pkg_socket(pkg); | |
2067 | sad_ha = sad_pkg_ha(pkg); | |
2068 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", | |
2069 | idx, *socket, sad_ha); | |
eebf11a0 | 2070 | } |
eebf11a0 | 2071 | |
7d375bff TL |
2072 | *ha = sad_ha; |
2073 | ||
eebf11a0 MCC |
2074 | /* |
2075 | * Move to the proper node structure, in order to access the | |
2076 | * right PCI registers | |
2077 | */ | |
e2f747b1 | 2078 | new_mci = get_mci_for_node_id(*socket, sad_ha); |
eebf11a0 MCC |
2079 | if (!new_mci) { |
2080 | sprintf(msg, "Struct for socket #%u wasn't initialized", | |
2081 | *socket); | |
eebf11a0 MCC |
2082 | return -EINVAL; |
2083 | } | |
2084 | mci = new_mci; | |
2085 | pvt = mci->pvt_info; | |
2086 | ||
2087 | /* | |
2088 | * Step 2) Get memory channel | |
2089 | */ | |
2090 | prv = 0; | |
e2f747b1 | 2091 | pci_ha = pvt->pci_ha; |
eebf11a0 | 2092 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
4d715a80 | 2093 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
eebf11a0 MCC |
2094 | limit = TAD_LIMIT(reg); |
2095 | if (limit <= prv) { | |
2096 | sprintf(msg, "Can't discover the memory channel"); | |
eebf11a0 MCC |
2097 | return -EINVAL; |
2098 | } | |
2099 | if (addr <= limit) | |
2100 | break; | |
2101 | prv = limit; | |
2102 | } | |
4d715a80 AR |
2103 | if (n_tads == MAX_TAD) { |
2104 | sprintf(msg, "Can't discover the memory channel"); | |
2105 | return -EINVAL; | |
2106 | } | |
2107 | ||
eebf11a0 | 2108 | ch_way = TAD_CH(reg) + 1; |
ff15e95c | 2109 | sck_way = TAD_SOCK(reg); |
eebf11a0 MCC |
2110 | |
2111 | if (ch_way == 3) | |
2112 | idx = addr >> 6; | |
ea5dfb5f | 2113 | else { |
50d1bb93 | 2114 | idx = (addr >> (6 + sck_way + shiftup)) & 0x3; |
ea5dfb5f TL |
2115 | if (pvt->is_chan_hash) |
2116 | idx = haswell_chan_hash(idx, addr); | |
2117 | } | |
eebf11a0 MCC |
2118 | idx = idx % ch_way; |
2119 | ||
2120 | /* | |
2121 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? | |
2122 | */ | |
2123 | switch (idx) { | |
2124 | case 0: | |
2125 | base_ch = TAD_TGT0(reg); | |
2126 | break; | |
2127 | case 1: | |
2128 | base_ch = TAD_TGT1(reg); | |
2129 | break; | |
2130 | case 2: | |
2131 | base_ch = TAD_TGT2(reg); | |
2132 | break; | |
2133 | case 3: | |
2134 | base_ch = TAD_TGT3(reg); | |
2135 | break; | |
2136 | default: | |
2137 | sprintf(msg, "Can't discover the TAD target"); | |
eebf11a0 MCC |
2138 | return -EINVAL; |
2139 | } | |
2140 | *channel_mask = 1 << base_ch; | |
2141 | ||
e2f747b1 | 2142 | pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); |
4d715a80 | 2143 | |
039d7af6 QZ |
2144 | if (pvt->mirror_mode == FULL_MIRRORING || |
2145 | (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { | |
eebf11a0 MCC |
2146 | *channel_mask |= 1 << ((base_ch + 2) % 4); |
2147 | switch(ch_way) { | |
2148 | case 2: | |
2149 | case 4: | |
ff15e95c | 2150 | sck_xch = (1 << sck_way) * (ch_way >> 1); |
eebf11a0 MCC |
2151 | break; |
2152 | default: | |
2153 | sprintf(msg, "Invalid mirror set. Can't decode addr"); | |
eebf11a0 MCC |
2154 | return -EINVAL; |
2155 | } | |
039d7af6 QZ |
2156 | |
2157 | pvt->is_cur_addr_mirrored = true; | |
2158 | } else { | |
eebf11a0 | 2159 | sck_xch = (1 << sck_way) * ch_way; |
039d7af6 QZ |
2160 | pvt->is_cur_addr_mirrored = false; |
2161 | } | |
eebf11a0 MCC |
2162 | |
2163 | if (pvt->is_lockstep) | |
2164 | *channel_mask |= 1 << ((base_ch + 1) % 4); | |
2165 | ||
2166 | offset = TAD_OFFSET(tad_offset); | |
2167 | ||
956b9ba1 JP |
2168 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
2169 | n_tads, | |
2170 | addr, | |
2171 | limit, | |
eb1af3b7 | 2172 | sck_way, |
956b9ba1 JP |
2173 | ch_way, |
2174 | offset, | |
2175 | idx, | |
2176 | base_ch, | |
2177 | *channel_mask); | |
eebf11a0 MCC |
2178 | |
2179 | /* Calculate channel address */ | |
2180 | /* Remove the TAD offset */ | |
2181 | ||
2182 | if (offset > addr) { | |
2183 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", | |
2184 | offset, addr); | |
eebf11a0 MCC |
2185 | return -EINVAL; |
2186 | } | |
eb1af3b7 LT |
2187 | |
2188 | ch_addr = addr - offset; | |
2189 | ch_addr >>= (6 + shiftup); | |
ff15e95c | 2190 | ch_addr /= sck_xch; |
eb1af3b7 LT |
2191 | ch_addr <<= (6 + shiftup); |
2192 | ch_addr |= addr & ((1 << (6 + shiftup)) - 1); | |
eebf11a0 MCC |
2193 | |
2194 | /* | |
2195 | * Step 3) Decode rank | |
2196 | */ | |
2197 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { | |
e2f747b1 | 2198 | pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); |
eebf11a0 MCC |
2199 | |
2200 | if (!IS_RIR_VALID(reg)) | |
2201 | continue; | |
2202 | ||
b976bcf2 | 2203 | limit = pvt->info.rir_limit(reg); |
8c009100 | 2204 | gb = div_u64_rem(limit >> 20, 1024, &mb); |
956b9ba1 JP |
2205 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
2206 | n_rir, | |
8c009100 | 2207 | gb, (mb*1000)/1024, |
956b9ba1 JP |
2208 | limit, |
2209 | 1 << RIR_WAY(reg)); | |
eebf11a0 MCC |
2210 | if (ch_addr <= limit) |
2211 | break; | |
2212 | } | |
2213 | if (n_rir == MAX_RIR_RANGES) { | |
2214 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", | |
2215 | ch_addr); | |
eebf11a0 MCC |
2216 | return -EINVAL; |
2217 | } | |
2218 | rir_way = RIR_WAY(reg); | |
50d1bb93 | 2219 | |
eebf11a0 MCC |
2220 | if (pvt->is_close_pg) |
2221 | idx = (ch_addr >> 6); | |
2222 | else | |
2223 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ | |
2224 | idx %= 1 << rir_way; | |
2225 | ||
e2f747b1 | 2226 | pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); |
c7103f65 | 2227 | *rank = RIR_RNK_TGT(pvt->info.type, reg); |
eebf11a0 | 2228 | |
956b9ba1 JP |
2229 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
2230 | n_rir, | |
2231 | ch_addr, | |
2232 | limit, | |
2233 | rir_way, | |
2234 | idx); | |
eebf11a0 MCC |
2235 | |
2236 | return 0; | |
2237 | } | |
2238 | ||
8489b17c QZ |
2239 | static int get_memory_error_data_from_mce(struct mem_ctl_info *mci, |
2240 | const struct mce *m, u8 *socket, | |
2241 | u8 *ha, long *channel_mask, | |
2242 | char *msg) | |
2243 | { | |
2244 | u32 reg, channel = GET_BITFIELD(m->status, 0, 3); | |
2245 | struct mem_ctl_info *new_mci; | |
2246 | struct sbridge_pvt *pvt; | |
2247 | struct pci_dev *pci_ha; | |
2248 | bool tad0; | |
2249 | ||
2250 | if (channel >= NUM_CHANNELS) { | |
2251 | sprintf(msg, "Invalid channel 0x%x", channel); | |
2252 | return -EINVAL; | |
2253 | } | |
2254 | ||
2255 | pvt = mci->pvt_info; | |
2256 | if (!pvt->info.get_ha) { | |
2257 | sprintf(msg, "No get_ha()"); | |
2258 | return -EINVAL; | |
2259 | } | |
2260 | *ha = pvt->info.get_ha(m->bank); | |
2261 | if (*ha != 0 && *ha != 1) { | |
2262 | sprintf(msg, "Impossible bank %d", m->bank); | |
2263 | return -EINVAL; | |
2264 | } | |
2265 | ||
2266 | *socket = m->socketid; | |
2267 | new_mci = get_mci_for_node_id(*socket, *ha); | |
2268 | if (!new_mci) { | |
2269 | strcpy(msg, "mci socket got corrupted!"); | |
2270 | return -EINVAL; | |
2271 | } | |
2272 | ||
2273 | pvt = new_mci->pvt_info; | |
2274 | pci_ha = pvt->pci_ha; | |
2275 | pci_read_config_dword(pci_ha, tad_dram_rule[0], ®); | |
2276 | tad0 = m->addr <= TAD_LIMIT(reg); | |
2277 | ||
2278 | *channel_mask = 1 << channel; | |
2279 | if (pvt->mirror_mode == FULL_MIRRORING || | |
2280 | (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { | |
2281 | *channel_mask |= 1 << ((channel + 2) % 4); | |
2282 | pvt->is_cur_addr_mirrored = true; | |
2283 | } else { | |
2284 | pvt->is_cur_addr_mirrored = false; | |
2285 | } | |
2286 | ||
2287 | if (pvt->is_lockstep) | |
2288 | *channel_mask |= 1 << ((channel + 1) % 4); | |
2289 | ||
2290 | return 0; | |
2291 | } | |
2292 | ||
eebf11a0 MCC |
2293 | /**************************************************************************** |
2294 | Device initialization routines: put/get, init/exit | |
2295 | ****************************************************************************/ | |
2296 | ||
2297 | /* | |
2298 | * sbridge_put_all_devices 'put' all the devices that we have | |
2299 | * reserved via 'get' | |
2300 | */ | |
2301 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |
2302 | { | |
2303 | int i; | |
2304 | ||
956b9ba1 | 2305 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
2306 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
2307 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | |
2308 | if (!pdev) | |
2309 | continue; | |
956b9ba1 JP |
2310 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
2311 | pdev->bus->number, | |
2312 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
eebf11a0 MCC |
2313 | pci_dev_put(pdev); |
2314 | } | |
2315 | } | |
2316 | ||
2317 | static void sbridge_put_all_devices(void) | |
2318 | { | |
2319 | struct sbridge_dev *sbridge_dev, *tmp; | |
2320 | ||
2321 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { | |
2322 | sbridge_put_devices(sbridge_dev); | |
2323 | free_sbridge_dev(sbridge_dev); | |
2324 | } | |
2325 | } | |
2326 | ||
eebf11a0 MCC |
2327 | static int sbridge_get_onedevice(struct pci_dev **prev, |
2328 | u8 *num_mc, | |
2329 | const struct pci_id_table *table, | |
c1979ba2 JS |
2330 | const unsigned devno, |
2331 | const int multi_bus) | |
eebf11a0 | 2332 | { |
e2f747b1 | 2333 | struct sbridge_dev *sbridge_dev = NULL; |
eebf11a0 | 2334 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
eebf11a0 | 2335 | struct pci_dev *pdev = NULL; |
190bd6e9 | 2336 | int seg = 0; |
eebf11a0 | 2337 | u8 bus = 0; |
e2f747b1 | 2338 | int i = 0; |
eebf11a0 | 2339 | |
ec5a0b38 | 2340 | sbridge_printk(KERN_DEBUG, |
dbc954dd | 2341 | "Seeking for: PCI ID %04x:%04x\n", |
eebf11a0 MCC |
2342 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2343 | ||
2344 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
2345 | dev_descr->dev_id, *prev); | |
2346 | ||
2347 | if (!pdev) { | |
2348 | if (*prev) { | |
2349 | *prev = pdev; | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | if (dev_descr->optional) | |
2354 | return 0; | |
2355 | ||
dbc954dd | 2356 | /* if the HA wasn't found */ |
eebf11a0 MCC |
2357 | if (devno == 0) |
2358 | return -ENODEV; | |
2359 | ||
2360 | sbridge_printk(KERN_INFO, | |
dbc954dd | 2361 | "Device not found: %04x:%04x\n", |
eebf11a0 MCC |
2362 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2363 | ||
2364 | /* End of list, leave */ | |
2365 | return -ENODEV; | |
2366 | } | |
190bd6e9 | 2367 | seg = pci_domain_nr(pdev->bus); |
eebf11a0 MCC |
2368 | bus = pdev->bus->number; |
2369 | ||
e2f747b1 | 2370 | next_imc: |
190bd6e9 MM |
2371 | sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, |
2372 | multi_bus, sbridge_dev); | |
eebf11a0 | 2373 | if (!sbridge_dev) { |
15cc3ae0 QZ |
2374 | /* If the HA1 wasn't found, don't create EDAC second memory controller */ |
2375 | if (dev_descr->dom == IMC1 && devno != 1) { | |
2376 | edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n", | |
2377 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
2378 | pci_dev_put(pdev); | |
2379 | return 0; | |
2380 | } | |
133e4455 QZ |
2381 | |
2382 | if (dev_descr->dom == SOCK) | |
2383 | goto out_imc; | |
2384 | ||
190bd6e9 | 2385 | sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); |
eebf11a0 MCC |
2386 | if (!sbridge_dev) { |
2387 | pci_dev_put(pdev); | |
2388 | return -ENOMEM; | |
2389 | } | |
2390 | (*num_mc)++; | |
2391 | } | |
2392 | ||
e2f747b1 | 2393 | if (sbridge_dev->pdev[sbridge_dev->i_devs]) { |
eebf11a0 | 2394 | sbridge_printk(KERN_ERR, |
dbc954dd | 2395 | "Duplicated device for %04x:%04x\n", |
eebf11a0 MCC |
2396 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2397 | pci_dev_put(pdev); | |
2398 | return -ENODEV; | |
2399 | } | |
2400 | ||
e2f747b1 QZ |
2401 | sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; |
2402 | ||
2403 | /* pdev belongs to more than one IMC, do extra gets */ | |
2404 | if (++i > 1) | |
2405 | pci_dev_get(pdev); | |
2406 | ||
2407 | if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) | |
2408 | goto next_imc; | |
eebf11a0 | 2409 | |
133e4455 | 2410 | out_imc: |
eebf11a0 MCC |
2411 | /* Be sure that the device is enabled */ |
2412 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
2413 | sbridge_printk(KERN_ERR, | |
dbc954dd | 2414 | "Couldn't enable %04x:%04x\n", |
eebf11a0 MCC |
2415 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
2416 | return -ENODEV; | |
2417 | } | |
2418 | ||
dbc954dd | 2419 | edac_dbg(0, "Detected %04x:%04x\n", |
956b9ba1 | 2420 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
eebf11a0 MCC |
2421 | |
2422 | /* | |
2423 | * As stated on drivers/pci/search.c, the reference count for | |
2424 | * @from is always decremented if it is not %NULL. So, as we need | |
2425 | * to get all devices up to null, we need to do a get for the device | |
2426 | */ | |
2427 | pci_dev_get(pdev); | |
2428 | ||
2429 | *prev = pdev; | |
2430 | ||
2431 | return 0; | |
2432 | } | |
2433 | ||
5153a0f9 AR |
2434 | /* |
2435 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's | |
dbc954dd | 2436 | * devices we want to reference for this driver. |
5153a0f9 | 2437 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
c41afdca | 2438 | * of success. |
5153a0f9 AR |
2439 | * @table: model specific table |
2440 | * | |
2441 | * returns 0 in case of success or error code | |
2442 | */ | |
0ba169ac TL |
2443 | static int sbridge_get_all_devices(u8 *num_mc, |
2444 | const struct pci_id_table *table) | |
eebf11a0 MCC |
2445 | { |
2446 | int i, rc; | |
2447 | struct pci_dev *pdev = NULL; | |
0ba169ac TL |
2448 | int allow_dups = 0; |
2449 | int multi_bus = 0; | |
eebf11a0 | 2450 | |
0ba169ac TL |
2451 | if (table->type == KNIGHTS_LANDING) |
2452 | allow_dups = multi_bus = 1; | |
eebf11a0 | 2453 | while (table && table->descr) { |
00cf50d9 | 2454 | for (i = 0; i < table->n_devs_per_sock; i++) { |
c1979ba2 JS |
2455 | if (!allow_dups || i == 0 || |
2456 | table->descr[i].dev_id != | |
2457 | table->descr[i-1].dev_id) { | |
2458 | pdev = NULL; | |
2459 | } | |
eebf11a0 MCC |
2460 | do { |
2461 | rc = sbridge_get_onedevice(&pdev, num_mc, | |
c1979ba2 | 2462 | table, i, multi_bus); |
eebf11a0 MCC |
2463 | if (rc < 0) { |
2464 | if (i == 0) { | |
00cf50d9 | 2465 | i = table->n_devs_per_sock; |
eebf11a0 MCC |
2466 | break; |
2467 | } | |
2468 | sbridge_put_all_devices(); | |
2469 | return -ENODEV; | |
2470 | } | |
c1979ba2 | 2471 | } while (pdev && !allow_dups); |
eebf11a0 MCC |
2472 | } |
2473 | table++; | |
2474 | } | |
2475 | ||
2476 | return 0; | |
2477 | } | |
2478 | ||
d14e3a20 QZ |
2479 | /* |
2480 | * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in | |
2481 | * the format: XXXa. So we can convert from a device to the corresponding | |
2482 | * channel like this | |
2483 | */ | |
2484 | #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa) | |
2485 | ||
ea779b5a AR |
2486 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
2487 | struct sbridge_dev *sbridge_dev) | |
eebf11a0 MCC |
2488 | { |
2489 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2490 | struct pci_dev *pdev; | |
2900ea60 | 2491 | u8 saw_chan_mask = 0; |
dbc954dd | 2492 | int i; |
eebf11a0 MCC |
2493 | |
2494 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2495 | pdev = sbridge_dev->pdev[i]; | |
2496 | if (!pdev) | |
2497 | continue; | |
dbc954dd AR |
2498 | |
2499 | switch (pdev->device) { | |
2500 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: | |
2501 | pvt->pci_sad0 = pdev; | |
eebf11a0 | 2502 | break; |
dbc954dd AR |
2503 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
2504 | pvt->pci_sad1 = pdev; | |
eebf11a0 | 2505 | break; |
dbc954dd AR |
2506 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
2507 | pvt->pci_br0 = pdev; | |
eebf11a0 | 2508 | break; |
dbc954dd | 2509 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
e2f747b1 | 2510 | pvt->pci_ha = pdev; |
eebf11a0 | 2511 | break; |
dbc954dd AR |
2512 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
2513 | pvt->pci_ta = pdev; | |
2514 | break; | |
2515 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: | |
2516 | pvt->pci_ras = pdev; | |
2517 | break; | |
2518 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: | |
2519 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: | |
2520 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: | |
2521 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: | |
2522 | { | |
d14e3a20 | 2523 | int id = TAD_DEV_TO_CHAN(pdev->device); |
dbc954dd | 2524 | pvt->pci_tad[id] = pdev; |
2900ea60 | 2525 | saw_chan_mask |= 1 << id; |
dbc954dd AR |
2526 | } |
2527 | break; | |
2528 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: | |
2529 | pvt->pci_ddrio = pdev; | |
eebf11a0 MCC |
2530 | break; |
2531 | default: | |
2532 | goto error; | |
2533 | } | |
2534 | ||
dbc954dd AR |
2535 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
2536 | pdev->vendor, pdev->device, | |
956b9ba1 | 2537 | sbridge_dev->bus, |
956b9ba1 | 2538 | pdev); |
eebf11a0 MCC |
2539 | } |
2540 | ||
2541 | /* Check if everything were registered */ | |
e2f747b1 | 2542 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || |
c7c35407 | 2543 | !pvt->pci_ras || !pvt->pci_ta) |
eebf11a0 MCC |
2544 | goto enodev; |
2545 | ||
2900ea60 SJ |
2546 | if (saw_chan_mask != 0x0f) |
2547 | goto enodev; | |
eebf11a0 MCC |
2548 | return 0; |
2549 | ||
2550 | enodev: | |
2551 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2552 | return -ENODEV; | |
2553 | ||
2554 | error: | |
dbc954dd AR |
2555 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
2556 | PCI_VENDOR_ID_INTEL, pdev->device); | |
eebf11a0 MCC |
2557 | return -EINVAL; |
2558 | } | |
2559 | ||
4d715a80 AR |
2560 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
2561 | struct sbridge_dev *sbridge_dev) | |
2562 | { | |
2563 | struct sbridge_pvt *pvt = mci->pvt_info; | |
7d375bff TL |
2564 | struct pci_dev *pdev; |
2565 | u8 saw_chan_mask = 0; | |
dbc954dd | 2566 | int i; |
4d715a80 AR |
2567 | |
2568 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2569 | pdev = sbridge_dev->pdev[i]; | |
2570 | if (!pdev) | |
2571 | continue; | |
4d715a80 | 2572 | |
dbc954dd AR |
2573 | switch (pdev->device) { |
2574 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: | |
d14e3a20 | 2575 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: |
e2f747b1 | 2576 | pvt->pci_ha = pdev; |
dbc954dd AR |
2577 | break; |
2578 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
e2f747b1 | 2579 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA: |
dbc954dd | 2580 | pvt->pci_ta = pdev; |
a8e9b186 | 2581 | break; |
dbc954dd | 2582 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: |
e2f747b1 | 2583 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS: |
dbc954dd AR |
2584 | pvt->pci_ras = pdev; |
2585 | break; | |
dbc954dd AR |
2586 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: |
2587 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: | |
7d375bff TL |
2588 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: |
2589 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: | |
d14e3a20 QZ |
2590 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: |
2591 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: | |
2592 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: | |
2593 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: | |
dbc954dd | 2594 | { |
d14e3a20 | 2595 | int id = TAD_DEV_TO_CHAN(pdev->device); |
dbc954dd | 2596 | pvt->pci_tad[id] = pdev; |
7d375bff | 2597 | saw_chan_mask |= 1 << id; |
dbc954dd | 2598 | } |
4d715a80 | 2599 | break; |
dbc954dd AR |
2600 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
2601 | pvt->pci_ddrio = pdev; | |
2602 | break; | |
2603 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: | |
7d375bff | 2604 | pvt->pci_ddrio = pdev; |
4d715a80 | 2605 | break; |
dbc954dd AR |
2606 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
2607 | pvt->pci_sad0 = pdev; | |
2608 | break; | |
2609 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: | |
2610 | pvt->pci_br0 = pdev; | |
2611 | break; | |
2612 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: | |
2613 | pvt->pci_br1 = pdev; | |
2614 | break; | |
4d715a80 AR |
2615 | default: |
2616 | goto error; | |
2617 | } | |
2618 | ||
2619 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2620 | sbridge_dev->bus, | |
2621 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2622 | pdev); | |
2623 | } | |
2624 | ||
2625 | /* Check if everything were registered */ | |
e2f747b1 | 2626 | if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || |
c7c35407 | 2627 | !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) |
4d715a80 AR |
2628 | goto enodev; |
2629 | ||
e2f747b1 QZ |
2630 | if (saw_chan_mask != 0x0f && /* -EN/-EX */ |
2631 | saw_chan_mask != 0x03) /* -EP */ | |
7d375bff | 2632 | goto enodev; |
4d715a80 AR |
2633 | return 0; |
2634 | ||
2635 | enodev: | |
2636 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2637 | return -ENODEV; | |
2638 | ||
2639 | error: | |
2640 | sbridge_printk(KERN_ERR, | |
dbc954dd AR |
2641 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
2642 | pdev->device); | |
4d715a80 AR |
2643 | return -EINVAL; |
2644 | } | |
2645 | ||
50d1bb93 AR |
2646 | static int haswell_mci_bind_devs(struct mem_ctl_info *mci, |
2647 | struct sbridge_dev *sbridge_dev) | |
2648 | { | |
2649 | struct sbridge_pvt *pvt = mci->pvt_info; | |
7d375bff TL |
2650 | struct pci_dev *pdev; |
2651 | u8 saw_chan_mask = 0; | |
50d1bb93 | 2652 | int i; |
50d1bb93 AR |
2653 | |
2654 | /* there's only one device per system; not tied to any bus */ | |
2655 | if (pvt->info.pci_vtd == NULL) | |
2656 | /* result will be checked later */ | |
2657 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
2658 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, | |
2659 | NULL); | |
2660 | ||
2661 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2662 | pdev = sbridge_dev->pdev[i]; | |
2663 | if (!pdev) | |
2664 | continue; | |
2665 | ||
2666 | switch (pdev->device) { | |
2667 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: | |
2668 | pvt->pci_sad0 = pdev; | |
2669 | break; | |
2670 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: | |
2671 | pvt->pci_sad1 = pdev; | |
2672 | break; | |
2673 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
d14e3a20 | 2674 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: |
e2f747b1 | 2675 | pvt->pci_ha = pdev; |
50d1bb93 AR |
2676 | break; |
2677 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: | |
d14e3a20 | 2678 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: |
50d1bb93 AR |
2679 | pvt->pci_ta = pdev; |
2680 | break; | |
00cf50d9 | 2681 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM: |
e2f747b1 | 2682 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM: |
50d1bb93 AR |
2683 | pvt->pci_ras = pdev; |
2684 | break; | |
2685 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: | |
50d1bb93 | 2686 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: |
50d1bb93 | 2687 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: |
50d1bb93 | 2688 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: |
7d375bff TL |
2689 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: |
2690 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: | |
2691 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: | |
2692 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: | |
2693 | { | |
d14e3a20 | 2694 | int id = TAD_DEV_TO_CHAN(pdev->device); |
7d375bff TL |
2695 | pvt->pci_tad[id] = pdev; |
2696 | saw_chan_mask |= 1 << id; | |
2697 | } | |
50d1bb93 AR |
2698 | break; |
2699 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: | |
7179385a AR |
2700 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1: |
2701 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2: | |
2702 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3: | |
2703 | if (!pvt->pci_ddrio) | |
2704 | pvt->pci_ddrio = pdev; | |
50d1bb93 | 2705 | break; |
50d1bb93 AR |
2706 | default: |
2707 | break; | |
2708 | } | |
2709 | ||
2710 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2711 | sbridge_dev->bus, | |
2712 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2713 | pdev); | |
2714 | } | |
2715 | ||
2716 | /* Check if everything were registered */ | |
e2f747b1 | 2717 | if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || |
50d1bb93 AR |
2718 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) |
2719 | goto enodev; | |
2720 | ||
e2f747b1 QZ |
2721 | if (saw_chan_mask != 0x0f && /* -EN/-EX */ |
2722 | saw_chan_mask != 0x03) /* -EP */ | |
7d375bff | 2723 | goto enodev; |
50d1bb93 AR |
2724 | return 0; |
2725 | ||
2726 | enodev: | |
2727 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2728 | return -ENODEV; | |
2729 | } | |
2730 | ||
1f39581a TL |
2731 | static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, |
2732 | struct sbridge_dev *sbridge_dev) | |
2733 | { | |
2734 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2735 | struct pci_dev *pdev; | |
fa2ce64f | 2736 | u8 saw_chan_mask = 0; |
1f39581a TL |
2737 | int i; |
2738 | ||
2739 | /* there's only one device per system; not tied to any bus */ | |
2740 | if (pvt->info.pci_vtd == NULL) | |
2741 | /* result will be checked later */ | |
2742 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
2743 | PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, | |
2744 | NULL); | |
2745 | ||
2746 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2747 | pdev = sbridge_dev->pdev[i]; | |
2748 | if (!pdev) | |
2749 | continue; | |
2750 | ||
2751 | switch (pdev->device) { | |
2752 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: | |
2753 | pvt->pci_sad0 = pdev; | |
2754 | break; | |
2755 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: | |
2756 | pvt->pci_sad1 = pdev; | |
2757 | break; | |
2758 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: | |
d14e3a20 | 2759 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1: |
e2f747b1 | 2760 | pvt->pci_ha = pdev; |
1f39581a TL |
2761 | break; |
2762 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: | |
d14e3a20 | 2763 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA: |
1f39581a TL |
2764 | pvt->pci_ta = pdev; |
2765 | break; | |
00cf50d9 | 2766 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM: |
e2f747b1 | 2767 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM: |
1f39581a TL |
2768 | pvt->pci_ras = pdev; |
2769 | break; | |
2770 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: | |
1f39581a | 2771 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: |
1f39581a | 2772 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: |
1f39581a | 2773 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: |
fa2ce64f TL |
2774 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0: |
2775 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1: | |
2776 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2: | |
2777 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3: | |
2778 | { | |
d14e3a20 | 2779 | int id = TAD_DEV_TO_CHAN(pdev->device); |
fa2ce64f TL |
2780 | pvt->pci_tad[id] = pdev; |
2781 | saw_chan_mask |= 1 << id; | |
2782 | } | |
1f39581a TL |
2783 | break; |
2784 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: | |
2785 | pvt->pci_ddrio = pdev; | |
2786 | break; | |
2787 | default: | |
2788 | break; | |
2789 | } | |
2790 | ||
2791 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2792 | sbridge_dev->bus, | |
2793 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2794 | pdev); | |
2795 | } | |
2796 | ||
2797 | /* Check if everything were registered */ | |
e2f747b1 | 2798 | if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || |
1f39581a TL |
2799 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) |
2800 | goto enodev; | |
2801 | ||
e2f747b1 QZ |
2802 | if (saw_chan_mask != 0x0f && /* -EN/-EX */ |
2803 | saw_chan_mask != 0x03) /* -EP */ | |
fa2ce64f | 2804 | goto enodev; |
1f39581a TL |
2805 | return 0; |
2806 | ||
2807 | enodev: | |
2808 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2809 | return -ENODEV; | |
2810 | } | |
2811 | ||
d0cdf900 JS |
2812 | static int knl_mci_bind_devs(struct mem_ctl_info *mci, |
2813 | struct sbridge_dev *sbridge_dev) | |
2814 | { | |
2815 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2816 | struct pci_dev *pdev; | |
2817 | int dev, func; | |
2818 | ||
2819 | int i; | |
2820 | int devidx; | |
2821 | ||
2822 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
2823 | pdev = sbridge_dev->pdev[i]; | |
2824 | if (!pdev) | |
2825 | continue; | |
2826 | ||
2827 | /* Extract PCI device and function. */ | |
2828 | dev = (pdev->devfn >> 3) & 0x1f; | |
2829 | func = pdev->devfn & 0x7; | |
2830 | ||
2831 | switch (pdev->device) { | |
2832 | case PCI_DEVICE_ID_INTEL_KNL_IMC_MC: | |
2833 | if (dev == 8) | |
2834 | pvt->knl.pci_mc0 = pdev; | |
2835 | else if (dev == 9) | |
2836 | pvt->knl.pci_mc1 = pdev; | |
2837 | else { | |
2838 | sbridge_printk(KERN_ERR, | |
2839 | "Memory controller in unexpected place! (dev %d, fn %d)\n", | |
2840 | dev, func); | |
2841 | continue; | |
2842 | } | |
2843 | break; | |
2844 | ||
2845 | case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0: | |
2846 | pvt->pci_sad0 = pdev; | |
2847 | break; | |
2848 | ||
2849 | case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1: | |
2850 | pvt->pci_sad1 = pdev; | |
2851 | break; | |
2852 | ||
2853 | case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA: | |
2854 | /* There are one of these per tile, and range from | |
2855 | * 1.14.0 to 1.18.5. | |
2856 | */ | |
2857 | devidx = ((dev-14)*8)+func; | |
2858 | ||
2859 | if (devidx < 0 || devidx >= KNL_MAX_CHAS) { | |
2860 | sbridge_printk(KERN_ERR, | |
2861 | "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n", | |
2862 | dev, func); | |
2863 | continue; | |
2864 | } | |
2865 | ||
2866 | WARN_ON(pvt->knl.pci_cha[devidx] != NULL); | |
2867 | ||
2868 | pvt->knl.pci_cha[devidx] = pdev; | |
2869 | break; | |
2870 | ||
00cf50d9 | 2871 | case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN: |
d0cdf900 JS |
2872 | devidx = -1; |
2873 | ||
2874 | /* | |
2875 | * MC0 channels 0-2 are device 9 function 2-4, | |
2876 | * MC1 channels 3-5 are device 8 function 2-4. | |
2877 | */ | |
2878 | ||
2879 | if (dev == 9) | |
2880 | devidx = func-2; | |
2881 | else if (dev == 8) | |
2882 | devidx = 3 + (func-2); | |
2883 | ||
2884 | if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) { | |
2885 | sbridge_printk(KERN_ERR, | |
2886 | "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n", | |
2887 | dev, func); | |
2888 | continue; | |
2889 | } | |
2890 | ||
2891 | WARN_ON(pvt->knl.pci_channel[devidx] != NULL); | |
2892 | pvt->knl.pci_channel[devidx] = pdev; | |
2893 | break; | |
2894 | ||
2895 | case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM: | |
2896 | pvt->knl.pci_mc_info = pdev; | |
2897 | break; | |
2898 | ||
2899 | case PCI_DEVICE_ID_INTEL_KNL_IMC_TA: | |
2900 | pvt->pci_ta = pdev; | |
2901 | break; | |
2902 | ||
2903 | default: | |
2904 | sbridge_printk(KERN_ERR, "Unexpected device %d\n", | |
2905 | pdev->device); | |
2906 | break; | |
2907 | } | |
2908 | } | |
2909 | ||
2910 | if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || | |
2911 | !pvt->pci_sad0 || !pvt->pci_sad1 || | |
2912 | !pvt->pci_ta) { | |
2913 | goto enodev; | |
2914 | } | |
2915 | ||
2916 | for (i = 0; i < KNL_MAX_CHANNELS; i++) { | |
2917 | if (!pvt->knl.pci_channel[i]) { | |
2918 | sbridge_printk(KERN_ERR, "Missing channel %d\n", i); | |
2919 | goto enodev; | |
2920 | } | |
2921 | } | |
2922 | ||
2923 | for (i = 0; i < KNL_MAX_CHAS; i++) { | |
2924 | if (!pvt->knl.pci_cha[i]) { | |
2925 | sbridge_printk(KERN_ERR, "Missing CHA %d\n", i); | |
2926 | goto enodev; | |
2927 | } | |
2928 | } | |
2929 | ||
2930 | return 0; | |
2931 | ||
2932 | enodev: | |
2933 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2934 | return -ENODEV; | |
2935 | } | |
2936 | ||
eebf11a0 MCC |
2937 | /**************************************************************************** |
2938 | Error check routines | |
2939 | ****************************************************************************/ | |
2940 | ||
2941 | /* | |
2942 | * While Sandy Bridge has error count registers, SMI BIOS read values from | |
2943 | * and resets the counters. So, they are not reliable for the OS to read | |
2944 | * from them. So, we have no option but to just trust on whatever MCE is | |
2945 | * telling us about the errors. | |
2946 | */ | |
2947 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |
2948 | const struct mce *m) | |
2949 | { | |
2950 | struct mem_ctl_info *new_mci; | |
2951 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 2952 | enum hw_event_mc_err_type tp_event; |
323014d8 | 2953 | char *optype, msg[256]; |
eebf11a0 MCC |
2954 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
2955 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
2956 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
4d715a80 | 2957 | bool recoverable; |
eebf11a0 MCC |
2958 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
2959 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
2960 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
2961 | u32 channel = GET_BITFIELD(m->status, 0, 3); | |
2962 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
8489b17c QZ |
2963 | /* |
2964 | * Bits 5-0 of MCi_MISC give the least significant bit that is valid. | |
2965 | * A value 6 is for cache line aligned address, a value 12 is for page | |
2966 | * aligned address reported by patrol scrubber. | |
2967 | */ | |
2968 | u32 lsb = GET_BITFIELD(m->misc, 0, 5); | |
eebf11a0 | 2969 | long channel_mask, first_channel; |
8489b17c | 2970 | u8 rank = 0xff, socket, ha; |
c36e3e77 | 2971 | int rc, dimm; |
8489b17c | 2972 | char *area_type = "DRAM"; |
eebf11a0 | 2973 | |
fa2ce64f | 2974 | if (pvt->info.type != SANDY_BRIDGE) |
4d715a80 AR |
2975 | recoverable = true; |
2976 | else | |
2977 | recoverable = GET_BITFIELD(m->status, 56, 56); | |
2978 | ||
c36e3e77 | 2979 | if (uncorrected_error) { |
432de7fd | 2980 | core_err_cnt = 1; |
c36e3e77 | 2981 | if (ripv) { |
c36e3e77 | 2982 | tp_event = HW_EVENT_ERR_UNCORRECTED; |
45bc6098 TL |
2983 | } else { |
2984 | tp_event = HW_EVENT_ERR_FATAL; | |
c36e3e77 MCC |
2985 | } |
2986 | } else { | |
c36e3e77 MCC |
2987 | tp_event = HW_EVENT_ERR_CORRECTED; |
2988 | } | |
eebf11a0 MCC |
2989 | |
2990 | /* | |
15ed103a | 2991 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
eebf11a0 MCC |
2992 | * memory errors should fit in this mask: |
2993 | * 000f 0000 1mmm cccc (binary) | |
2994 | * where: | |
2995 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
2996 | * won't be shown | |
2997 | * mmm = error type | |
2998 | * cccc = channel | |
2999 | * If the mask doesn't match, report an error to the parsing logic | |
3000 | */ | |
dcc960b2 QZ |
3001 | switch (optypenum) { |
3002 | case 0: | |
3003 | optype = "generic undef request error"; | |
3004 | break; | |
3005 | case 1: | |
3006 | optype = "memory read error"; | |
3007 | break; | |
3008 | case 2: | |
3009 | optype = "memory write error"; | |
3010 | break; | |
3011 | case 3: | |
3012 | optype = "addr/cmd error"; | |
3013 | break; | |
3014 | case 4: | |
3015 | optype = "memory scrubbing error"; | |
3016 | break; | |
3017 | default: | |
3018 | optype = "reserved"; | |
3019 | break; | |
eebf11a0 MCC |
3020 | } |
3021 | ||
d0cdf900 JS |
3022 | if (pvt->info.type == KNIGHTS_LANDING) { |
3023 | if (channel == 14) { | |
3024 | edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n", | |
3025 | overflow ? " OVERFLOW" : "", | |
3026 | (uncorrected_error && recoverable) | |
3027 | ? " recoverable" : "", | |
3028 | mscod, errcode, | |
3029 | m->bank); | |
3030 | } else { | |
3031 | char A = *("A"); | |
3032 | ||
c5b48fa7 LO |
3033 | /* |
3034 | * Reported channel is in range 0-2, so we can't map it | |
3035 | * back to mc. To figure out mc we check machine check | |
3036 | * bank register that reported this error. | |
3037 | * bank15 means mc0 and bank16 means mc1. | |
3038 | */ | |
3039 | channel = knl_channel_remap(m->bank == 16, channel); | |
d0cdf900 | 3040 | channel_mask = 1 << channel; |
c5b48fa7 | 3041 | |
d0cdf900 JS |
3042 | snprintf(msg, sizeof(msg), |
3043 | "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)", | |
3044 | overflow ? " OVERFLOW" : "", | |
3045 | (uncorrected_error && recoverable) | |
3046 | ? " recoverable" : " ", | |
3047 | mscod, errcode, channel, A + channel); | |
3048 | edac_mc_handle_error(tp_event, mci, core_err_cnt, | |
3049 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, | |
3050 | channel, 0, -1, | |
3051 | optype, msg); | |
3052 | } | |
3053 | return; | |
8489b17c | 3054 | } else if (lsb < 12) { |
d0cdf900 | 3055 | rc = get_memory_error_data(mci, m->addr, &socket, &ha, |
8489b17c QZ |
3056 | &channel_mask, &rank, |
3057 | &area_type, msg); | |
3058 | } else { | |
3059 | rc = get_memory_error_data_from_mce(mci, m, &socket, &ha, | |
3060 | &channel_mask, msg); | |
d0cdf900 JS |
3061 | } |
3062 | ||
eebf11a0 | 3063 | if (rc < 0) |
c36e3e77 | 3064 | goto err_parsing; |
e2f747b1 | 3065 | new_mci = get_mci_for_node_id(socket, ha); |
eebf11a0 | 3066 | if (!new_mci) { |
c36e3e77 MCC |
3067 | strcpy(msg, "Error: socket got corrupted!"); |
3068 | goto err_parsing; | |
eebf11a0 MCC |
3069 | } |
3070 | mci = new_mci; | |
3071 | pvt = mci->pvt_info; | |
3072 | ||
3073 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); | |
3074 | ||
8489b17c QZ |
3075 | if (rank == 0xff) |
3076 | dimm = -1; | |
3077 | else if (rank < 4) | |
eebf11a0 MCC |
3078 | dimm = 0; |
3079 | else if (rank < 8) | |
3080 | dimm = 1; | |
3081 | else | |
3082 | dimm = 2; | |
3083 | ||
eebf11a0 | 3084 | /* |
e17a2f42 MCC |
3085 | * FIXME: On some memory configurations (mirror, lockstep), the |
3086 | * Memory Controller can't point the error to a single DIMM. The | |
3087 | * EDAC core should be handling the channel mask, in order to point | |
3088 | * to the group of dimm's where the error may be happening. | |
eebf11a0 | 3089 | */ |
039d7af6 | 3090 | if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) |
d7c660b7 AR |
3091 | channel = first_channel; |
3092 | ||
c36e3e77 | 3093 | snprintf(msg, sizeof(msg), |
7d375bff | 3094 | "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d", |
e17a2f42 MCC |
3095 | overflow ? " OVERFLOW" : "", |
3096 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
3097 | area_type, | |
3098 | mscod, errcode, | |
7d375bff | 3099 | socket, ha, |
e17a2f42 MCC |
3100 | channel_mask, |
3101 | rank); | |
eebf11a0 | 3102 | |
956b9ba1 | 3103 | edac_dbg(0, "%s\n", msg); |
eebf11a0 | 3104 | |
c36e3e77 MCC |
3105 | /* FIXME: need support for channel mask */ |
3106 | ||
351fc4a9 SJ |
3107 | if (channel == CHANNEL_UNSPECIFIED) |
3108 | channel = -1; | |
3109 | ||
eebf11a0 | 3110 | /* Call the helper to output message */ |
c1053839 | 3111 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
c36e3e77 | 3112 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
e2f747b1 | 3113 | channel, dimm, -1, |
03f7eae8 | 3114 | optype, msg); |
c36e3e77 MCC |
3115 | return; |
3116 | err_parsing: | |
c1053839 | 3117 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
c36e3e77 | 3118 | -1, -1, -1, |
03f7eae8 | 3119 | msg, ""); |
eebf11a0 | 3120 | |
eebf11a0 MCC |
3121 | } |
3122 | ||
3123 | /* | |
ad08c4e9 TL |
3124 | * Check that logging is enabled and that this is the right type |
3125 | * of error for us to handle. | |
eebf11a0 | 3126 | */ |
3d78c9af MCC |
3127 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
3128 | void *data) | |
eebf11a0 | 3129 | { |
3d78c9af MCC |
3130 | struct mce *mce = (struct mce *)data; |
3131 | struct mem_ctl_info *mci; | |
cf40f80c | 3132 | char *type; |
3d78c9af | 3133 | |
23ba710a TL |
3134 | if (mce->kflags & MCE_HANDLED_CEC) |
3135 | return NOTIFY_DONE; | |
fd521039 | 3136 | |
eebf11a0 MCC |
3137 | /* |
3138 | * Just let mcelog handle it if the error is | |
3139 | * outside the memory controller. A memory error | |
3140 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. | |
3141 | * bit 12 has an special meaning. | |
3142 | */ | |
3143 | if ((mce->status & 0xefff) >> 7 != 1) | |
3d78c9af | 3144 | return NOTIFY_DONE; |
eebf11a0 | 3145 | |
dcc960b2 QZ |
3146 | /* Check ADDRV bit in STATUS */ |
3147 | if (!GET_BITFIELD(mce->status, 58, 58)) | |
3148 | return NOTIFY_DONE; | |
3149 | ||
3150 | /* Check MISCV bit in STATUS */ | |
3151 | if (!GET_BITFIELD(mce->status, 59, 59)) | |
3152 | return NOTIFY_DONE; | |
3153 | ||
3154 | /* Check address type in MISC (physical address only) */ | |
3155 | if (GET_BITFIELD(mce->misc, 6, 8) != 2) | |
3156 | return NOTIFY_DONE; | |
3157 | ||
3158 | mci = get_mci_for_node_id(mce->socketid, IMC0); | |
3159 | if (!mci) | |
3160 | return NOTIFY_DONE; | |
3161 | ||
cf40f80c AR |
3162 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
3163 | type = "Exception"; | |
3164 | else | |
3165 | type = "Event"; | |
3166 | ||
49856dc9 | 3167 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
eebf11a0 | 3168 | |
49856dc9 AR |
3169 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
3170 | "Bank %d: %016Lx\n", mce->extcpu, type, | |
3171 | mce->mcgstatus, mce->bank, mce->status); | |
3172 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); | |
3173 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); | |
3174 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); | |
eebf11a0 | 3175 | |
49856dc9 AR |
3176 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
3177 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, | |
3178 | mce->time, mce->socketid, mce->apicid); | |
eebf11a0 | 3179 | |
ad08c4e9 | 3180 | sbridge_mce_output_error(mci, mce); |
eebf11a0 MCC |
3181 | |
3182 | /* Advice mcelog that the error were handled */ | |
23ba710a TL |
3183 | mce->kflags |= MCE_HANDLED_EDAC; |
3184 | return NOTIFY_OK; | |
eebf11a0 MCC |
3185 | } |
3186 | ||
3d78c9af | 3187 | static struct notifier_block sbridge_mce_dec = { |
9026cc82 BP |
3188 | .notifier_call = sbridge_mce_check_error, |
3189 | .priority = MCE_PRIO_EDAC, | |
3d78c9af MCC |
3190 | }; |
3191 | ||
eebf11a0 MCC |
3192 | /**************************************************************************** |
3193 | EDAC register/unregister logic | |
3194 | ****************************************************************************/ | |
3195 | ||
3196 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |
3197 | { | |
3198 | struct mem_ctl_info *mci = sbridge_dev->mci; | |
eebf11a0 MCC |
3199 | |
3200 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 3201 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
eebf11a0 MCC |
3202 | |
3203 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
3204 | return; | |
3205 | } | |
3206 | ||
956b9ba1 JP |
3207 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
3208 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 | 3209 | |
eebf11a0 | 3210 | /* Remove MC sysfs nodes */ |
fd687502 | 3211 | edac_mc_del_mc(mci->pdev); |
eebf11a0 | 3212 | |
956b9ba1 | 3213 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
eebf11a0 MCC |
3214 | kfree(mci->ctl_name); |
3215 | edac_mc_free(mci); | |
3216 | sbridge_dev->mci = NULL; | |
3217 | } | |
3218 | ||
4d715a80 | 3219 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
eebf11a0 MCC |
3220 | { |
3221 | struct mem_ctl_info *mci; | |
c36e3e77 | 3222 | struct edac_mc_layer layers[2]; |
eebf11a0 | 3223 | struct sbridge_pvt *pvt; |
4d715a80 | 3224 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
c36e3e77 | 3225 | int rc; |
eebf11a0 | 3226 | |
eebf11a0 | 3227 | /* allocate a new MC control structure */ |
c36e3e77 | 3228 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
d0cdf900 JS |
3229 | layers[0].size = type == KNIGHTS_LANDING ? |
3230 | KNL_MAX_CHANNELS : NUM_CHANNELS; | |
c36e3e77 MCC |
3231 | layers[0].is_virt_csrow = false; |
3232 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
d0cdf900 | 3233 | layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; |
c36e3e77 | 3234 | layers[1].is_virt_csrow = true; |
ca0907b9 | 3235 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
c36e3e77 MCC |
3236 | sizeof(*pvt)); |
3237 | ||
eebf11a0 MCC |
3238 | if (unlikely(!mci)) |
3239 | return -ENOMEM; | |
3240 | ||
956b9ba1 | 3241 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
4d715a80 | 3242 | mci, &pdev->dev); |
eebf11a0 MCC |
3243 | |
3244 | pvt = mci->pvt_info; | |
3245 | memset(pvt, 0, sizeof(*pvt)); | |
3246 | ||
3247 | /* Associate sbridge_dev and mci for future usage */ | |
3248 | pvt->sbridge_dev = sbridge_dev; | |
3249 | sbridge_dev->mci = mci; | |
3250 | ||
d0cdf900 JS |
3251 | mci->mtype_cap = type == KNIGHTS_LANDING ? |
3252 | MEM_FLAG_DDR4 : MEM_FLAG_DDR3; | |
eebf11a0 MCC |
3253 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
3254 | mci->edac_cap = EDAC_FLAG_NONE; | |
301375e7 | 3255 | mci->mod_name = EDAC_MOD_STR; |
4d715a80 | 3256 | mci->dev_name = pci_name(pdev); |
eebf11a0 MCC |
3257 | mci->ctl_page_to_phys = NULL; |
3258 | ||
4d715a80 | 3259 | pvt->info.type = type; |
50d1bb93 AR |
3260 | switch (type) { |
3261 | case IVY_BRIDGE: | |
4d715a80 AR |
3262 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
3263 | pvt->info.get_tolm = ibridge_get_tolm; | |
3264 | pvt->info.get_tohm = ibridge_get_tohm; | |
3265 | pvt->info.dram_rule = ibridge_dram_rule; | |
9e375446 | 3266 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 3267 | pvt->info.get_node_id = get_node_id; |
8489b17c | 3268 | pvt->info.get_ha = ibridge_get_ha; |
b976bcf2 | 3269 | pvt->info.rir_limit = rir_limit; |
c59f9c06 JS |
3270 | pvt->info.sad_limit = sad_limit; |
3271 | pvt->info.interleave_mode = interleave_mode; | |
c59f9c06 | 3272 | pvt->info.dram_attr = dram_attr; |
4d715a80 AR |
3273 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
3274 | pvt->info.interleave_list = ibridge_interleave_list; | |
4d715a80 | 3275 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
12f0721c | 3276 | pvt->info.get_width = ibridge_get_width; |
4d715a80 AR |
3277 | |
3278 | /* Store pci devices at mci for faster access */ | |
3279 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); | |
3280 | if (unlikely(rc < 0)) | |
3281 | goto fail0; | |
7fd562b7 | 3282 | get_source_id(mci); |
e2f747b1 QZ |
3283 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", |
3284 | pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); | |
50d1bb93 AR |
3285 | break; |
3286 | case SANDY_BRIDGE: | |
4d715a80 AR |
3287 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
3288 | pvt->info.get_tolm = sbridge_get_tolm; | |
3289 | pvt->info.get_tohm = sbridge_get_tohm; | |
3290 | pvt->info.dram_rule = sbridge_dram_rule; | |
9e375446 | 3291 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 3292 | pvt->info.get_node_id = get_node_id; |
8489b17c | 3293 | pvt->info.get_ha = sbridge_get_ha; |
b976bcf2 | 3294 | pvt->info.rir_limit = rir_limit; |
c59f9c06 JS |
3295 | pvt->info.sad_limit = sad_limit; |
3296 | pvt->info.interleave_mode = interleave_mode; | |
c59f9c06 | 3297 | pvt->info.dram_attr = dram_attr; |
4d715a80 AR |
3298 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
3299 | pvt->info.interleave_list = sbridge_interleave_list; | |
4d715a80 | 3300 | pvt->info.interleave_pkg = sbridge_interleave_pkg; |
12f0721c | 3301 | pvt->info.get_width = sbridge_get_width; |
4d715a80 AR |
3302 | |
3303 | /* Store pci devices at mci for faster access */ | |
3304 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); | |
3305 | if (unlikely(rc < 0)) | |
3306 | goto fail0; | |
7fd562b7 | 3307 | get_source_id(mci); |
e2f747b1 QZ |
3308 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", |
3309 | pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); | |
50d1bb93 AR |
3310 | break; |
3311 | case HASWELL: | |
3312 | /* rankcfgr isn't used */ | |
3313 | pvt->info.get_tolm = haswell_get_tolm; | |
3314 | pvt->info.get_tohm = haswell_get_tohm; | |
3315 | pvt->info.dram_rule = ibridge_dram_rule; | |
3316 | pvt->info.get_memory_type = haswell_get_memory_type; | |
3317 | pvt->info.get_node_id = haswell_get_node_id; | |
8489b17c | 3318 | pvt->info.get_ha = ibridge_get_ha; |
50d1bb93 | 3319 | pvt->info.rir_limit = haswell_rir_limit; |
c59f9c06 JS |
3320 | pvt->info.sad_limit = sad_limit; |
3321 | pvt->info.interleave_mode = interleave_mode; | |
c59f9c06 | 3322 | pvt->info.dram_attr = dram_attr; |
50d1bb93 AR |
3323 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
3324 | pvt->info.interleave_list = ibridge_interleave_list; | |
50d1bb93 | 3325 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
12f0721c | 3326 | pvt->info.get_width = ibridge_get_width; |
4d715a80 | 3327 | |
50d1bb93 AR |
3328 | /* Store pci devices at mci for faster access */ |
3329 | rc = haswell_mci_bind_devs(mci, sbridge_dev); | |
3330 | if (unlikely(rc < 0)) | |
3331 | goto fail0; | |
7fd562b7 | 3332 | get_source_id(mci); |
e2f747b1 QZ |
3333 | mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", |
3334 | pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); | |
50d1bb93 | 3335 | break; |
1f39581a TL |
3336 | case BROADWELL: |
3337 | /* rankcfgr isn't used */ | |
3338 | pvt->info.get_tolm = haswell_get_tolm; | |
3339 | pvt->info.get_tohm = haswell_get_tohm; | |
3340 | pvt->info.dram_rule = ibridge_dram_rule; | |
3341 | pvt->info.get_memory_type = haswell_get_memory_type; | |
3342 | pvt->info.get_node_id = haswell_get_node_id; | |
8489b17c | 3343 | pvt->info.get_ha = ibridge_get_ha; |
1f39581a | 3344 | pvt->info.rir_limit = haswell_rir_limit; |
c59f9c06 JS |
3345 | pvt->info.sad_limit = sad_limit; |
3346 | pvt->info.interleave_mode = interleave_mode; | |
c59f9c06 | 3347 | pvt->info.dram_attr = dram_attr; |
1f39581a TL |
3348 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
3349 | pvt->info.interleave_list = ibridge_interleave_list; | |
1f39581a | 3350 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
12f0721c | 3351 | pvt->info.get_width = broadwell_get_width; |
1f39581a TL |
3352 | |
3353 | /* Store pci devices at mci for faster access */ | |
3354 | rc = broadwell_mci_bind_devs(mci, sbridge_dev); | |
3355 | if (unlikely(rc < 0)) | |
3356 | goto fail0; | |
7fd562b7 | 3357 | get_source_id(mci); |
e2f747b1 QZ |
3358 | mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", |
3359 | pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); | |
1f39581a | 3360 | break; |
d0cdf900 JS |
3361 | case KNIGHTS_LANDING: |
3362 | /* pvt->info.rankcfgr == ??? */ | |
3363 | pvt->info.get_tolm = knl_get_tolm; | |
3364 | pvt->info.get_tohm = knl_get_tohm; | |
3365 | pvt->info.dram_rule = knl_dram_rule; | |
3366 | pvt->info.get_memory_type = knl_get_memory_type; | |
3367 | pvt->info.get_node_id = knl_get_node_id; | |
8489b17c | 3368 | pvt->info.get_ha = knl_get_ha; |
d0cdf900 JS |
3369 | pvt->info.rir_limit = NULL; |
3370 | pvt->info.sad_limit = knl_sad_limit; | |
3371 | pvt->info.interleave_mode = knl_interleave_mode; | |
d0cdf900 JS |
3372 | pvt->info.dram_attr = dram_attr_knl; |
3373 | pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); | |
3374 | pvt->info.interleave_list = knl_interleave_list; | |
d0cdf900 | 3375 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
45f4d3ab | 3376 | pvt->info.get_width = knl_get_width; |
d0cdf900 JS |
3377 | |
3378 | rc = knl_mci_bind_devs(mci, sbridge_dev); | |
3379 | if (unlikely(rc < 0)) | |
3380 | goto fail0; | |
7fd562b7 | 3381 | get_source_id(mci); |
e2f747b1 QZ |
3382 | mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", |
3383 | pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); | |
d0cdf900 | 3384 | break; |
50d1bb93 | 3385 | } |
eebf11a0 | 3386 | |
75f029c3 AY |
3387 | if (!mci->ctl_name) { |
3388 | rc = -ENOMEM; | |
3389 | goto fail0; | |
3390 | } | |
3391 | ||
eebf11a0 | 3392 | /* Get dimm basic config and the memory layout */ |
4d475dde QZ |
3393 | rc = get_dimm_config(mci); |
3394 | if (rc < 0) { | |
3395 | edac_dbg(0, "MC: failed to get_dimm_config()\n"); | |
3396 | goto fail; | |
3397 | } | |
eebf11a0 MCC |
3398 | get_memory_layout(mci); |
3399 | ||
3400 | /* record ptr to the generic device */ | |
4d715a80 | 3401 | mci->pdev = &pdev->dev; |
eebf11a0 MCC |
3402 | |
3403 | /* add this new MC control structure to EDAC's list of MCs */ | |
3404 | if (unlikely(edac_mc_add_mc(mci))) { | |
956b9ba1 | 3405 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
eebf11a0 | 3406 | rc = -EINVAL; |
7fd562b7 | 3407 | goto fail; |
eebf11a0 MCC |
3408 | } |
3409 | ||
eebf11a0 | 3410 | return 0; |
eebf11a0 | 3411 | |
7fd562b7 | 3412 | fail: |
eebf11a0 | 3413 | kfree(mci->ctl_name); |
7fd562b7 | 3414 | fail0: |
eebf11a0 MCC |
3415 | edac_mc_free(mci); |
3416 | sbridge_dev->mci = NULL; | |
3417 | return rc; | |
3418 | } | |
3419 | ||
2c1ea4c7 | 3420 | static const struct x86_cpu_id sbridge_cpuids[] = { |
29842621 TG |
3421 | X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &pci_dev_descr_sbridge_table), |
3422 | X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &pci_dev_descr_ibridge_table), | |
3423 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &pci_dev_descr_haswell_table), | |
3424 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &pci_dev_descr_broadwell_table), | |
3425 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &pci_dev_descr_broadwell_table), | |
3426 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &pci_dev_descr_knl_table), | |
3427 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &pci_dev_descr_knl_table), | |
2c1ea4c7 TL |
3428 | { } |
3429 | }; | |
3430 | MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids); | |
3431 | ||
eebf11a0 | 3432 | /* |
2c1ea4c7 | 3433 | * sbridge_probe Get all devices and register memory controllers |
eebf11a0 MCC |
3434 | * present. |
3435 | * return: | |
3436 | * 0 for FOUND a device | |
3437 | * < 0 for error code | |
3438 | */ | |
3439 | ||
2c1ea4c7 | 3440 | static int sbridge_probe(const struct x86_cpu_id *id) |
eebf11a0 | 3441 | { |
567617ba | 3442 | int rc; |
eebf11a0 MCC |
3443 | u8 mc, num_mc = 0; |
3444 | struct sbridge_dev *sbridge_dev; | |
2c1ea4c7 | 3445 | struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; |
eebf11a0 MCC |
3446 | |
3447 | /* get the pci devices we want to reserve for our use */ | |
2c1ea4c7 | 3448 | rc = sbridge_get_all_devices(&num_mc, ptable); |
eebf11a0 | 3449 | |
11249e73 | 3450 | if (unlikely(rc < 0)) { |
2c1ea4c7 | 3451 | edac_dbg(0, "couldn't get all devices\n"); |
eebf11a0 | 3452 | goto fail0; |
11249e73 BP |
3453 | } |
3454 | ||
eebf11a0 MCC |
3455 | mc = 0; |
3456 | ||
3457 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
956b9ba1 JP |
3458 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
3459 | mc, mc + 1, num_mc); | |
50d1bb93 | 3460 | |
eebf11a0 | 3461 | sbridge_dev->mc = mc++; |
665f05e0 | 3462 | rc = sbridge_register_mci(sbridge_dev, ptable->type); |
eebf11a0 MCC |
3463 | if (unlikely(rc < 0)) |
3464 | goto fail1; | |
3465 | } | |
3466 | ||
11249e73 | 3467 | sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); |
eebf11a0 | 3468 | |
eebf11a0 MCC |
3469 | return 0; |
3470 | ||
3471 | fail1: | |
3472 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
3473 | sbridge_unregister_mci(sbridge_dev); | |
3474 | ||
3475 | sbridge_put_all_devices(); | |
3476 | fail0: | |
eebf11a0 MCC |
3477 | return rc; |
3478 | } | |
3479 | ||
3480 | /* | |
2c1ea4c7 | 3481 | * sbridge_remove cleanup |
eebf11a0 MCC |
3482 | * |
3483 | */ | |
2c1ea4c7 | 3484 | static void sbridge_remove(void) |
eebf11a0 MCC |
3485 | { |
3486 | struct sbridge_dev *sbridge_dev; | |
3487 | ||
956b9ba1 | 3488 | edac_dbg(0, "\n"); |
eebf11a0 | 3489 | |
eebf11a0 MCC |
3490 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
3491 | sbridge_unregister_mci(sbridge_dev); | |
3492 | ||
3493 | /* Release PCI resources */ | |
3494 | sbridge_put_all_devices(); | |
eebf11a0 MCC |
3495 | } |
3496 | ||
eebf11a0 MCC |
3497 | /* |
3498 | * sbridge_init Module entry function | |
3499 | * Try to initialize this module for its devices | |
3500 | */ | |
3501 | static int __init sbridge_init(void) | |
3502 | { | |
2c1ea4c7 | 3503 | const struct x86_cpu_id *id; |
301375e7 | 3504 | const char *owner; |
2c1ea4c7 | 3505 | int rc; |
eebf11a0 | 3506 | |
956b9ba1 | 3507 | edac_dbg(2, "\n"); |
eebf11a0 | 3508 | |
301375e7 TK |
3509 | owner = edac_get_owner(); |
3510 | if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) | |
3511 | return -EBUSY; | |
3512 | ||
f0a029ff LT |
3513 | if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) |
3514 | return -ENODEV; | |
3515 | ||
2c1ea4c7 TL |
3516 | id = x86_match_cpu(sbridge_cpuids); |
3517 | if (!id) | |
3518 | return -ENODEV; | |
3519 | ||
eebf11a0 MCC |
3520 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
3521 | opstate_init(); | |
3522 | ||
2c1ea4c7 TL |
3523 | rc = sbridge_probe(id); |
3524 | ||
3525 | if (rc >= 0) { | |
e35fca47 | 3526 | mce_register_decode_chain(&sbridge_mce_dec); |
eebf11a0 | 3527 | return 0; |
e35fca47 | 3528 | } |
eebf11a0 MCC |
3529 | |
3530 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2c1ea4c7 | 3531 | rc); |
eebf11a0 | 3532 | |
2c1ea4c7 | 3533 | return rc; |
eebf11a0 MCC |
3534 | } |
3535 | ||
3536 | /* | |
3537 | * sbridge_exit() Module exit function | |
3538 | * Unregister the driver | |
3539 | */ | |
3540 | static void __exit sbridge_exit(void) | |
3541 | { | |
956b9ba1 | 3542 | edac_dbg(2, "\n"); |
2c1ea4c7 | 3543 | sbridge_remove(); |
e35fca47 | 3544 | mce_unregister_decode_chain(&sbridge_mce_dec); |
eebf11a0 MCC |
3545 | } |
3546 | ||
3547 | module_init(sbridge_init); | |
3548 | module_exit(sbridge_exit); | |
3549 | ||
3550 | module_param(edac_op_state, int, 0444); | |
3551 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
3552 | ||
3553 | MODULE_LICENSE("GPL"); | |
37e59f87 | 3554 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
7d4c1ea2 | 3555 | MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)"); |
4d715a80 | 3556 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
eebf11a0 | 3557 | SBRIDGE_REVISION); |