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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
dba7a77c GE |
2 | /* |
3 | * Copyright (c) 2008 Nuovation System Designs, LLC | |
4 | * Grant Erickson <gerickson@nuovations.com> | |
dba7a77c GE |
5 | */ |
6 | ||
7 | #include <linux/edac.h> | |
8 | #include <linux/interrupt.h> | |
9 | #include <linux/irq.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of_device.h> | |
14 | #include <linux/of_platform.h> | |
15 | #include <linux/types.h> | |
16 | ||
17 | #include <asm/dcr.h> | |
18 | ||
78d88e8a | 19 | #include "edac_module.h" |
dba7a77c GE |
20 | #include "ppc4xx_edac.h" |
21 | ||
22 | /* | |
23 | * This file implements a driver for monitoring and handling events | |
24 | * associated with the IMB DDR2 ECC controller found in the AMCC/IBM | |
25 | * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX. | |
26 | * | |
27 | * As realized in the 405EX[r], this controller features: | |
28 | * | |
29 | * - Support for registered- and non-registered DDR1 and DDR2 memory. | |
30 | * - 32-bit or 16-bit memory interface with optional ECC. | |
31 | * | |
32 | * o ECC support includes: | |
33 | * | |
34 | * - 4-bit SEC/DED | |
35 | * - Aligned-nibble error detect | |
36 | * - Bypass mode | |
37 | * | |
38 | * - Two (2) memory banks/ranks. | |
39 | * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per | |
40 | * bank/rank in 16-bit mode. | |
41 | * | |
42 | * As realized in the 440SP and 440SPe, this controller changes/adds: | |
43 | * | |
44 | * - 64-bit or 32-bit memory interface with optional ECC. | |
45 | * | |
46 | * o ECC support includes: | |
47 | * | |
48 | * - 8-bit SEC/DED | |
49 | * - Aligned-nibble error detect | |
50 | * - Bypass mode | |
51 | * | |
52 | * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB | |
53 | * per bank/rank in 32-bit mode. | |
54 | * | |
55 | * As realized in the 460EX and 460GT, this controller changes/adds: | |
56 | * | |
57 | * - 64-bit or 32-bit memory interface with optional ECC. | |
58 | * | |
59 | * o ECC support includes: | |
60 | * | |
61 | * - 8-bit SEC/DED | |
62 | * - Aligned-nibble error detect | |
63 | * - Bypass mode | |
64 | * | |
65 | * - Four (4) memory banks/ranks. | |
66 | * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB | |
67 | * per bank/rank in 32-bit mode. | |
68 | * | |
69 | * At present, this driver has ONLY been tested against the controller | |
70 | * realization in the 405EX[r] on the AMCC Kilauea and Haleakala | |
71 | * boards (256 MiB w/o ECC memory soldered onto the board) and a | |
72 | * proprietary board based on those designs (128 MiB ECC memory, also | |
73 | * soldered onto the board). | |
74 | * | |
75 | * Dynamic feature detection and handling needs to be added for the | |
76 | * other realizations of this controller listed above. | |
77 | * | |
78 | * Eventually, this driver will likely be adapted to the above variant | |
79 | * realizations of this controller as well as broken apart to handle | |
80 | * the other known ECC-capable controllers prevalent in other 4xx | |
81 | * processors: | |
82 | * | |
83 | * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx" | |
84 | * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr" | |
85 | * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2" | |
86 | * | |
87 | * For this controller, unfortunately, correctable errors report | |
88 | * nothing more than the beat/cycle and byte/lane the correction | |
89 | * occurred on and the check bit group that covered the error. | |
90 | * | |
91 | * In contrast, uncorrectable errors also report the failing address, | |
92 | * the bus master and the transaction direction (i.e. read or write) | |
93 | * | |
94 | * Regardless of whether the error is a CE or a UE, we report the | |
95 | * following pieces of information in the driver-unique message to the | |
96 | * EDAC subsystem: | |
97 | * | |
98 | * - Device tree path | |
99 | * - Bank(s) | |
100 | * - Check bit error group | |
101 | * - Beat(s)/lane(s) | |
102 | */ | |
103 | ||
104 | /* Preprocessor Definitions */ | |
105 | ||
106 | #define EDAC_OPSTATE_INT_STR "interrupt" | |
107 | #define EDAC_OPSTATE_POLL_STR "polled" | |
108 | #define EDAC_OPSTATE_UNKNOWN_STR "unknown" | |
109 | ||
110 | #define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac" | |
152ba394 | 111 | #define PPC4XX_EDAC_MODULE_REVISION "v1.0.0" |
dba7a77c GE |
112 | |
113 | #define PPC4XX_EDAC_MESSAGE_SIZE 256 | |
114 | ||
115 | /* | |
116 | * Kernel logging without an EDAC instance | |
117 | */ | |
118 | #define ppc4xx_edac_printk(level, fmt, arg...) \ | |
119 | edac_printk(level, "PPC4xx MC", fmt, ##arg) | |
120 | ||
121 | /* | |
122 | * Kernel logging with an EDAC instance | |
123 | */ | |
124 | #define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \ | |
125 | edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg) | |
126 | ||
127 | /* | |
128 | * Macros to convert bank configuration size enumerations into MiB and | |
129 | * page values. | |
130 | */ | |
131 | #define SDRAM_MBCF_SZ_MiB_MIN 4 | |
132 | #define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \ | |
133 | << (SDRAM_MBCF_SZ_DECODE(n))) | |
134 | #define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \ | |
135 | << (20 - PAGE_SHIFT + \ | |
136 | SDRAM_MBCF_SZ_DECODE(n))) | |
137 | ||
138 | /* | |
139 | * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are | |
42b2aa86 | 140 | * indirectly accessed and have a base and length defined by the |
dba7a77c GE |
141 | * device tree. The base can be anything; however, we expect the |
142 | * length to be precisely two registers, the first for the address | |
143 | * window and the second for the data window. | |
144 | */ | |
145 | #define SDRAM_DCR_RESOURCE_LEN 2 | |
146 | #define SDRAM_DCR_ADDR_OFFSET 0 | |
147 | #define SDRAM_DCR_DATA_OFFSET 1 | |
148 | ||
149 | /* | |
150 | * Device tree interrupt indices | |
151 | */ | |
152 | #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */ | |
153 | #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */ | |
154 | ||
155 | /* Type Definitions */ | |
156 | ||
157 | /* | |
158 | * PPC4xx SDRAM memory controller private instance data | |
159 | */ | |
160 | struct ppc4xx_edac_pdata { | |
161 | dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */ | |
162 | struct { | |
163 | int sec; /* Single-bit correctable error IRQ assigned */ | |
164 | int ded; /* Double-bit detectable error IRQ assigned */ | |
165 | } irqs; | |
166 | }; | |
167 | ||
168 | /* | |
169 | * Various status data gathered and manipulated when checking and | |
170 | * reporting ECC status. | |
171 | */ | |
172 | struct ppc4xx_ecc_status { | |
173 | u32 ecces; | |
174 | u32 besr; | |
175 | u32 bearh; | |
176 | u32 bearl; | |
177 | u32 wmirq; | |
178 | }; | |
179 | ||
180 | /* Function Prototypes */ | |
181 | ||
b877763e | 182 | static int ppc4xx_edac_probe(struct platform_device *device); |
2dc11581 | 183 | static int ppc4xx_edac_remove(struct platform_device *device); |
dba7a77c GE |
184 | |
185 | /* Global Variables */ | |
186 | ||
187 | /* | |
188 | * Device tree node type and compatible tuples this driver can match | |
189 | * on. | |
190 | */ | |
1afaa055 | 191 | static const struct of_device_id ppc4xx_edac_match[] = { |
dba7a77c GE |
192 | { |
193 | .compatible = "ibm,sdram-4xx-ddr2" | |
194 | }, | |
195 | { } | |
196 | }; | |
90b3b373 | 197 | MODULE_DEVICE_TABLE(of, ppc4xx_edac_match); |
dba7a77c | 198 | |
00006124 | 199 | static struct platform_driver ppc4xx_edac_driver = { |
dba7a77c GE |
200 | .probe = ppc4xx_edac_probe, |
201 | .remove = ppc4xx_edac_remove, | |
4018294b | 202 | .driver = { |
e57b708b | 203 | .name = PPC4XX_EDAC_MODULE_NAME, |
4018294b GL |
204 | .of_match_table = ppc4xx_edac_match, |
205 | }, | |
dba7a77c GE |
206 | }; |
207 | ||
208 | /* | |
209 | * TODO: The row and channel parameters likely need to be dynamically | |
210 | * set based on the aforementioned variant controller realizations. | |
211 | */ | |
212 | static const unsigned ppc4xx_edac_nr_csrows = 2; | |
213 | static const unsigned ppc4xx_edac_nr_chans = 1; | |
214 | ||
215 | /* | |
216 | * Strings associated with PLB master IDs capable of being posted in | |
217 | * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors. | |
218 | */ | |
219 | static const char * const ppc4xx_plb_masters[9] = { | |
220 | [SDRAM_PLB_M0ID_ICU] = "ICU", | |
221 | [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0", | |
222 | [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1", | |
223 | [SDRAM_PLB_M0ID_DMA] = "DMA", | |
224 | [SDRAM_PLB_M0ID_DCU] = "DCU", | |
225 | [SDRAM_PLB_M0ID_OPB] = "OPB", | |
226 | [SDRAM_PLB_M0ID_MAL] = "MAL", | |
227 | [SDRAM_PLB_M0ID_SEC] = "SEC", | |
228 | [SDRAM_PLB_M0ID_AHB] = "AHB" | |
229 | }; | |
230 | ||
231 | /** | |
232 | * mfsdram - read and return controller register data | |
233 | * @dcr_host: A pointer to the DCR mapping. | |
234 | * @idcr_n: The indirect DCR register to read. | |
235 | * | |
236 | * This routine reads and returns the data associated with the | |
237 | * controller's specified indirect DCR register. | |
238 | * | |
239 | * Returns the read data. | |
240 | */ | |
241 | static inline u32 | |
242 | mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n) | |
243 | { | |
244 | return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, | |
245 | dcr_host->base + SDRAM_DCR_DATA_OFFSET, | |
246 | idcr_n); | |
247 | } | |
248 | ||
249 | /** | |
250 | * mtsdram - write controller register data | |
251 | * @dcr_host: A pointer to the DCR mapping. | |
252 | * @idcr_n: The indirect DCR register to write. | |
253 | * @value: The data to write. | |
254 | * | |
255 | * This routine writes the provided data to the controller's specified | |
256 | * indirect DCR register. | |
257 | */ | |
258 | static inline void | |
259 | mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value) | |
260 | { | |
261 | return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, | |
262 | dcr_host->base + SDRAM_DCR_DATA_OFFSET, | |
263 | idcr_n, | |
264 | value); | |
265 | } | |
266 | ||
267 | /** | |
268 | * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error | |
269 | * @status: A pointer to the ECC status structure to check for an | |
270 | * ECC bank error. | |
271 | * @bank: The bank to check for an ECC error. | |
272 | * | |
273 | * This routine determines whether the specified bank has an ECC | |
274 | * error. | |
275 | * | |
276 | * Returns true if the specified bank has an ECC error; otherwise, | |
277 | * false. | |
278 | */ | |
279 | static bool | |
280 | ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status, | |
281 | unsigned int bank) | |
282 | { | |
283 | switch (bank) { | |
284 | case 0: | |
285 | return status->ecces & SDRAM_ECCES_BK0ER; | |
286 | case 1: | |
287 | return status->ecces & SDRAM_ECCES_BK1ER; | |
288 | default: | |
289 | return false; | |
290 | } | |
291 | } | |
292 | ||
293 | /** | |
294 | * ppc4xx_edac_generate_bank_message - generate interpretted bank status message | |
295 | * @mci: A pointer to the EDAC memory controller instance associated | |
296 | * with the bank message being generated. | |
297 | * @status: A pointer to the ECC status structure to generate the | |
298 | * message from. | |
299 | * @buffer: A pointer to the buffer in which to generate the | |
300 | * message. | |
301 | * @size: The size, in bytes, of space available in buffer. | |
302 | * | |
303 | * This routine generates to the provided buffer the portion of the | |
304 | * driver-unique report message associated with the ECCESS[BKNER] | |
305 | * field of the specified ECC status. | |
306 | * | |
307 | * Returns the number of characters generated on success; otherwise, < | |
308 | * 0 on error. | |
309 | */ | |
310 | static int | |
311 | ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci, | |
312 | const struct ppc4xx_ecc_status *status, | |
313 | char *buffer, | |
314 | size_t size) | |
315 | { | |
316 | int n, total = 0; | |
317 | unsigned int row, rows; | |
318 | ||
319 | n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name); | |
320 | ||
321 | if (n < 0 || n >= size) | |
322 | goto fail; | |
323 | ||
324 | buffer += n; | |
325 | size -= n; | |
326 | total += n; | |
327 | ||
328 | for (rows = 0, row = 0; row < mci->nr_csrows; row++) { | |
329 | if (ppc4xx_edac_check_bank_error(status, row)) { | |
330 | n = snprintf(buffer, size, "%s%u", | |
331 | (rows++ ? ", " : ""), row); | |
332 | ||
333 | if (n < 0 || n >= size) | |
334 | goto fail; | |
335 | ||
336 | buffer += n; | |
337 | size -= n; | |
338 | total += n; | |
339 | } | |
340 | } | |
341 | ||
342 | n = snprintf(buffer, size, "%s; ", rows ? "" : "None"); | |
343 | ||
344 | if (n < 0 || n >= size) | |
345 | goto fail; | |
346 | ||
347 | buffer += n; | |
348 | size -= n; | |
349 | total += n; | |
350 | ||
351 | fail: | |
352 | return total; | |
353 | } | |
354 | ||
355 | /** | |
356 | * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message | |
357 | * @mci: A pointer to the EDAC memory controller instance associated | |
358 | * with the checkbit message being generated. | |
359 | * @status: A pointer to the ECC status structure to generate the | |
360 | * message from. | |
361 | * @buffer: A pointer to the buffer in which to generate the | |
362 | * message. | |
363 | * @size: The size, in bytes, of space available in buffer. | |
364 | * | |
365 | * This routine generates to the provided buffer the portion of the | |
366 | * driver-unique report message associated with the ECCESS[CKBER] | |
367 | * field of the specified ECC status. | |
368 | * | |
369 | * Returns the number of characters generated on success; otherwise, < | |
370 | * 0 on error. | |
371 | */ | |
372 | static int | |
373 | ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci, | |
374 | const struct ppc4xx_ecc_status *status, | |
375 | char *buffer, | |
376 | size_t size) | |
377 | { | |
378 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
379 | const char *ckber = NULL; | |
380 | ||
381 | switch (status->ecces & SDRAM_ECCES_CKBER_MASK) { | |
382 | case SDRAM_ECCES_CKBER_NONE: | |
383 | ckber = "None"; | |
384 | break; | |
385 | case SDRAM_ECCES_CKBER_32_ECC_0_3: | |
386 | ckber = "ECC0:3"; | |
387 | break; | |
388 | case SDRAM_ECCES_CKBER_32_ECC_4_8: | |
389 | switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) & | |
390 | SDRAM_MCOPT1_WDTH_MASK) { | |
391 | case SDRAM_MCOPT1_WDTH_16: | |
392 | ckber = "ECC0:3"; | |
393 | break; | |
394 | case SDRAM_MCOPT1_WDTH_32: | |
395 | ckber = "ECC4:8"; | |
396 | break; | |
397 | default: | |
398 | ckber = "Unknown"; | |
399 | break; | |
400 | } | |
401 | break; | |
402 | case SDRAM_ECCES_CKBER_32_ECC_0_8: | |
403 | ckber = "ECC0:8"; | |
404 | break; | |
405 | default: | |
406 | ckber = "Unknown"; | |
407 | break; | |
408 | } | |
409 | ||
410 | return snprintf(buffer, size, "Checkbit Error: %s", ckber); | |
411 | } | |
412 | ||
413 | /** | |
414 | * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message | |
415 | * @mci: A pointer to the EDAC memory controller instance associated | |
416 | * with the byte lane message being generated. | |
417 | * @status: A pointer to the ECC status structure to generate the | |
418 | * message from. | |
419 | * @buffer: A pointer to the buffer in which to generate the | |
420 | * message. | |
421 | * @size: The size, in bytes, of space available in buffer. | |
422 | * | |
423 | * This routine generates to the provided buffer the portion of the | |
424 | * driver-unique report message associated with the ECCESS[BNCE] | |
425 | * field of the specified ECC status. | |
426 | * | |
427 | * Returns the number of characters generated on success; otherwise, < | |
428 | * 0 on error. | |
429 | */ | |
430 | static int | |
431 | ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci, | |
432 | const struct ppc4xx_ecc_status *status, | |
433 | char *buffer, | |
434 | size_t size) | |
435 | { | |
436 | int n, total = 0; | |
437 | unsigned int lane, lanes; | |
438 | const unsigned int first_lane = 0; | |
439 | const unsigned int lane_count = 16; | |
440 | ||
441 | n = snprintf(buffer, size, "; Byte Lane Errors: "); | |
442 | ||
443 | if (n < 0 || n >= size) | |
444 | goto fail; | |
445 | ||
446 | buffer += n; | |
447 | size -= n; | |
448 | total += n; | |
449 | ||
450 | for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { | |
451 | if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { | |
452 | n = snprintf(buffer, size, | |
453 | "%s%u", | |
454 | (lanes++ ? ", " : ""), lane); | |
455 | ||
456 | if (n < 0 || n >= size) | |
457 | goto fail; | |
458 | ||
459 | buffer += n; | |
460 | size -= n; | |
461 | total += n; | |
462 | } | |
463 | } | |
464 | ||
465 | n = snprintf(buffer, size, "%s; ", lanes ? "" : "None"); | |
466 | ||
467 | if (n < 0 || n >= size) | |
468 | goto fail; | |
469 | ||
470 | buffer += n; | |
471 | size -= n; | |
472 | total += n; | |
473 | ||
474 | fail: | |
475 | return total; | |
476 | } | |
477 | ||
478 | /** | |
479 | * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message | |
480 | * @mci: A pointer to the EDAC memory controller instance associated | |
481 | * with the ECCES message being generated. | |
482 | * @status: A pointer to the ECC status structure to generate the | |
483 | * message from. | |
484 | * @buffer: A pointer to the buffer in which to generate the | |
485 | * message. | |
486 | * @size: The size, in bytes, of space available in buffer. | |
487 | * | |
488 | * This routine generates to the provided buffer the portion of the | |
489 | * driver-unique report message associated with the ECCESS register of | |
490 | * the specified ECC status. | |
491 | * | |
492 | * Returns the number of characters generated on success; otherwise, < | |
493 | * 0 on error. | |
494 | */ | |
495 | static int | |
496 | ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci, | |
497 | const struct ppc4xx_ecc_status *status, | |
498 | char *buffer, | |
499 | size_t size) | |
500 | { | |
501 | int n, total = 0; | |
502 | ||
503 | n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size); | |
504 | ||
505 | if (n < 0 || n >= size) | |
506 | goto fail; | |
507 | ||
508 | buffer += n; | |
509 | size -= n; | |
510 | total += n; | |
511 | ||
512 | n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size); | |
513 | ||
514 | if (n < 0 || n >= size) | |
515 | goto fail; | |
516 | ||
517 | buffer += n; | |
518 | size -= n; | |
519 | total += n; | |
520 | ||
521 | n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size); | |
522 | ||
523 | if (n < 0 || n >= size) | |
524 | goto fail; | |
525 | ||
526 | buffer += n; | |
527 | size -= n; | |
528 | total += n; | |
529 | ||
530 | fail: | |
531 | return total; | |
532 | } | |
533 | ||
534 | /** | |
535 | * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message | |
536 | * @mci: A pointer to the EDAC memory controller instance associated | |
537 | * with the PLB message being generated. | |
538 | * @status: A pointer to the ECC status structure to generate the | |
539 | * message from. | |
540 | * @buffer: A pointer to the buffer in which to generate the | |
541 | * message. | |
542 | * @size: The size, in bytes, of space available in buffer. | |
543 | * | |
544 | * This routine generates to the provided buffer the portion of the | |
545 | * driver-unique report message associated with the PLB-related BESR | |
546 | * and/or WMIRQ registers of the specified ECC status. | |
547 | * | |
548 | * Returns the number of characters generated on success; otherwise, < | |
549 | * 0 on error. | |
550 | */ | |
551 | static int | |
552 | ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci, | |
553 | const struct ppc4xx_ecc_status *status, | |
554 | char *buffer, | |
555 | size_t size) | |
556 | { | |
557 | unsigned int master; | |
558 | bool read; | |
559 | ||
560 | if ((status->besr & SDRAM_BESR_MASK) == 0) | |
561 | return 0; | |
562 | ||
563 | if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE) | |
564 | return 0; | |
565 | ||
566 | read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ); | |
567 | ||
568 | master = SDRAM_BESR_M0ID_DECODE(status->besr); | |
569 | ||
570 | return snprintf(buffer, size, | |
571 | "%s error w/ PLB master %u \"%s\"; ", | |
572 | (read ? "Read" : "Write"), | |
573 | master, | |
574 | (((master >= SDRAM_PLB_M0ID_FIRST) && | |
575 | (master <= SDRAM_PLB_M0ID_LAST)) ? | |
576 | ppc4xx_plb_masters[master] : "UNKNOWN")); | |
577 | } | |
578 | ||
579 | /** | |
580 | * ppc4xx_edac_generate_message - generate interpretted status message | |
581 | * @mci: A pointer to the EDAC memory controller instance associated | |
582 | * with the driver-unique message being generated. | |
583 | * @status: A pointer to the ECC status structure to generate the | |
584 | * message from. | |
585 | * @buffer: A pointer to the buffer in which to generate the | |
586 | * message. | |
587 | * @size: The size, in bytes, of space available in buffer. | |
588 | * | |
589 | * This routine generates to the provided buffer the driver-unique | |
590 | * EDAC report message from the specified ECC status. | |
591 | */ | |
592 | static void | |
593 | ppc4xx_edac_generate_message(const struct mem_ctl_info *mci, | |
594 | const struct ppc4xx_ecc_status *status, | |
595 | char *buffer, | |
596 | size_t size) | |
597 | { | |
598 | int n; | |
599 | ||
600 | if (buffer == NULL || size == 0) | |
601 | return; | |
602 | ||
603 | n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size); | |
604 | ||
605 | if (n < 0 || n >= size) | |
606 | return; | |
607 | ||
608 | buffer += n; | |
609 | size -= n; | |
610 | ||
611 | ppc4xx_edac_generate_plb_message(mci, status, buffer, size); | |
612 | } | |
613 | ||
614 | #ifdef DEBUG | |
615 | /** | |
616 | * ppc4xx_ecc_dump_status - dump controller ECC status registers | |
617 | * @mci: A pointer to the EDAC memory controller instance | |
618 | * associated with the status being dumped. | |
619 | * @status: A pointer to the ECC status structure to generate the | |
620 | * dump from. | |
621 | * | |
622 | * This routine dumps to the kernel log buffer the raw and | |
623 | * interpretted specified ECC status. | |
624 | */ | |
625 | static void | |
626 | ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci, | |
627 | const struct ppc4xx_ecc_status *status) | |
628 | { | |
629 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; | |
630 | ||
631 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); | |
632 | ||
633 | ppc4xx_edac_mc_printk(KERN_INFO, mci, | |
634 | "\n" | |
635 | "\tECCES: 0x%08x\n" | |
636 | "\tWMIRQ: 0x%08x\n" | |
637 | "\tBESR: 0x%08x\n" | |
638 | "\tBEAR: 0x%08x%08x\n" | |
639 | "\t%s\n", | |
640 | status->ecces, | |
641 | status->wmirq, | |
642 | status->besr, | |
643 | status->bearh, | |
644 | status->bearl, | |
645 | message); | |
646 | } | |
647 | #endif /* DEBUG */ | |
648 | ||
649 | /** | |
650 | * ppc4xx_ecc_get_status - get controller ECC status | |
651 | * @mci: A pointer to the EDAC memory controller instance | |
652 | * associated with the status being retrieved. | |
653 | * @status: A pointer to the ECC status structure to populate the | |
654 | * ECC status with. | |
655 | * | |
656 | * This routine reads and masks, as appropriate, all the relevant | |
657 | * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors. | |
658 | * While we read all of them, for correctable errors, we only expect | |
659 | * to deal with ECCES. For uncorrectable errors, we expect to deal | |
660 | * with all of them. | |
661 | */ | |
662 | static void | |
663 | ppc4xx_ecc_get_status(const struct mem_ctl_info *mci, | |
664 | struct ppc4xx_ecc_status *status) | |
665 | { | |
666 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
667 | const dcr_host_t *dcr_host = &pdata->dcr_host; | |
668 | ||
669 | status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK; | |
670 | status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK; | |
671 | status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK; | |
672 | status->bearl = mfsdram(dcr_host, SDRAM_BEARL); | |
673 | status->bearh = mfsdram(dcr_host, SDRAM_BEARH); | |
674 | } | |
675 | ||
676 | /** | |
677 | * ppc4xx_ecc_clear_status - clear controller ECC status | |
678 | * @mci: A pointer to the EDAC memory controller instance | |
679 | * associated with the status being cleared. | |
680 | * @status: A pointer to the ECC status structure containing the | |
681 | * values to write to clear the ECC status. | |
682 | * | |
683 | * This routine clears--by writing the masked (as appropriate) status | |
684 | * values back to--the status registers that deal with | |
685 | * ibm,sdram-4xx-ddr2 ECC errors. | |
686 | */ | |
687 | static void | |
688 | ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci, | |
689 | const struct ppc4xx_ecc_status *status) | |
690 | { | |
691 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
692 | const dcr_host_t *dcr_host = &pdata->dcr_host; | |
693 | ||
694 | mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK); | |
695 | mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK); | |
696 | mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK); | |
697 | mtsdram(dcr_host, SDRAM_BEARL, 0); | |
698 | mtsdram(dcr_host, SDRAM_BEARH, 0); | |
699 | } | |
700 | ||
701 | /** | |
702 | * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE) | |
703 | * @mci: A pointer to the EDAC memory controller instance | |
704 | * associated with the correctable error being handled and reported. | |
705 | * @status: A pointer to the ECC status structure associated with | |
706 | * the correctable error being handled and reported. | |
707 | * | |
708 | * This routine handles an ibm,sdram-4xx-ddr2 controller ECC | |
709 | * correctable error. Per the aforementioned discussion, there's not | |
710 | * enough status available to use the full EDAC correctable error | |
711 | * interface, so we just pass driver-unique message to the "no info" | |
712 | * interface. | |
713 | */ | |
714 | static void | |
715 | ppc4xx_edac_handle_ce(struct mem_ctl_info *mci, | |
716 | const struct ppc4xx_ecc_status *status) | |
717 | { | |
718 | int row; | |
719 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; | |
720 | ||
721 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); | |
722 | ||
723 | for (row = 0; row < mci->nr_csrows; row++) | |
724 | if (ppc4xx_edac_check_bank_error(status, row)) | |
9eb07a7f | 725 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
94d93374 MCC |
726 | 0, 0, 0, |
727 | row, 0, -1, | |
03f7eae8 | 728 | message, ""); |
dba7a77c GE |
729 | } |
730 | ||
731 | /** | |
732 | * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE) | |
733 | * @mci: A pointer to the EDAC memory controller instance | |
734 | * associated with the uncorrectable error being handled and | |
735 | * reported. | |
736 | * @status: A pointer to the ECC status structure associated with | |
737 | * the uncorrectable error being handled and reported. | |
738 | * | |
739 | * This routine handles an ibm,sdram-4xx-ddr2 controller ECC | |
740 | * uncorrectable error. | |
741 | */ | |
742 | static void | |
743 | ppc4xx_edac_handle_ue(struct mem_ctl_info *mci, | |
744 | const struct ppc4xx_ecc_status *status) | |
745 | { | |
746 | const u64 bear = ((u64)status->bearh << 32 | status->bearl); | |
747 | const unsigned long page = bear >> PAGE_SHIFT; | |
748 | const unsigned long offset = bear & ~PAGE_MASK; | |
749 | int row; | |
750 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; | |
751 | ||
752 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); | |
753 | ||
754 | for (row = 0; row < mci->nr_csrows; row++) | |
755 | if (ppc4xx_edac_check_bank_error(status, row)) | |
9eb07a7f | 756 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
94d93374 MCC |
757 | page, offset, 0, |
758 | row, 0, -1, | |
03f7eae8 | 759 | message, ""); |
dba7a77c GE |
760 | } |
761 | ||
762 | /** | |
763 | * ppc4xx_edac_check - check controller for ECC errors | |
764 | * @mci: A pointer to the EDAC memory controller instance | |
765 | * associated with the ibm,sdram-4xx-ddr2 controller being | |
766 | * checked. | |
767 | * | |
768 | * This routine is used to check and post ECC errors and is called by | |
769 | * both the EDAC polling thread and this driver's CE and UE interrupt | |
770 | * handler. | |
771 | */ | |
772 | static void | |
773 | ppc4xx_edac_check(struct mem_ctl_info *mci) | |
774 | { | |
775 | #ifdef DEBUG | |
776 | static unsigned int count; | |
777 | #endif | |
778 | struct ppc4xx_ecc_status status; | |
779 | ||
780 | ppc4xx_ecc_get_status(mci, &status); | |
781 | ||
782 | #ifdef DEBUG | |
783 | if (count++ % 30 == 0) | |
784 | ppc4xx_ecc_dump_status(mci, &status); | |
785 | #endif | |
786 | ||
787 | if (status.ecces & SDRAM_ECCES_UE) | |
788 | ppc4xx_edac_handle_ue(mci, &status); | |
789 | ||
790 | if (status.ecces & SDRAM_ECCES_CE) | |
791 | ppc4xx_edac_handle_ce(mci, &status); | |
792 | ||
793 | ppc4xx_ecc_clear_status(mci, &status); | |
794 | } | |
795 | ||
796 | /** | |
797 | * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine | |
798 | * @irq: The virtual interrupt number being serviced. | |
799 | * @dev_id: A pointer to the EDAC memory controller instance | |
800 | * associated with the interrupt being handled. | |
801 | * | |
802 | * This routine implements the interrupt handler for both correctable | |
803 | * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2 | |
804 | * controller. It simply calls through to the same routine used during | |
805 | * polling to check, report and clear the ECC status. | |
806 | * | |
807 | * Unconditionally returns IRQ_HANDLED. | |
808 | */ | |
809 | static irqreturn_t | |
810 | ppc4xx_edac_isr(int irq, void *dev_id) | |
811 | { | |
812 | struct mem_ctl_info *mci = dev_id; | |
813 | ||
814 | ppc4xx_edac_check(mci); | |
815 | ||
816 | return IRQ_HANDLED; | |
817 | } | |
818 | ||
819 | /** | |
820 | * ppc4xx_edac_get_dtype - return the controller memory width | |
821 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
822 | * currently set for the controller, from which the width | |
823 | * is derived. | |
824 | * | |
825 | * This routine returns the EDAC device type width appropriate for the | |
826 | * current controller configuration. | |
827 | * | |
828 | * TODO: This needs to be conditioned dynamically through feature | |
829 | * flags or some such when other controller variants are supported as | |
830 | * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the | |
831 | * 16- and 64-bit field definition/value/enumeration (b1) overloaded | |
832 | * among them. | |
833 | * | |
834 | * Returns a device type width enumeration. | |
835 | */ | |
9b3c6e85 | 836 | static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1) |
dba7a77c GE |
837 | { |
838 | switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) { | |
839 | case SDRAM_MCOPT1_WDTH_16: | |
840 | return DEV_X2; | |
841 | case SDRAM_MCOPT1_WDTH_32: | |
842 | return DEV_X4; | |
843 | default: | |
844 | return DEV_UNKNOWN; | |
845 | } | |
846 | } | |
847 | ||
848 | /** | |
849 | * ppc4xx_edac_get_mtype - return controller memory type | |
850 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
851 | * currently set for the controller, from which the memory type | |
852 | * is derived. | |
853 | * | |
854 | * This routine returns the EDAC memory type appropriate for the | |
855 | * current controller configuration. | |
856 | * | |
857 | * Returns a memory type enumeration. | |
858 | */ | |
9b3c6e85 | 859 | static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1) |
dba7a77c GE |
860 | { |
861 | bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN); | |
862 | ||
863 | switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) { | |
864 | case SDRAM_MCOPT1_DDR2_TYPE: | |
865 | return rden ? MEM_RDDR2 : MEM_DDR2; | |
866 | case SDRAM_MCOPT1_DDR1_TYPE: | |
867 | return rden ? MEM_RDDR : MEM_DDR; | |
868 | default: | |
869 | return MEM_UNKNOWN; | |
870 | } | |
871 | } | |
872 | ||
873 | /** | |
b595076a | 874 | * ppc4xx_edac_init_csrows - initialize driver instance rows |
dba7a77c GE |
875 | * @mci: A pointer to the EDAC memory controller instance |
876 | * associated with the ibm,sdram-4xx-ddr2 controller for which | |
877 | * the csrows (i.e. banks/ranks) are being initialized. | |
878 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
879 | * currently set for the controller, from which bank width | |
880 | * and memory typ information is derived. | |
881 | * | |
b595076a | 882 | * This routine initializes the virtual "chip select rows" associated |
dba7a77c GE |
883 | * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2 |
884 | * controller bank/rank is mapped to a row. | |
885 | * | |
886 | * Returns 0 if OK; otherwise, -EINVAL if the memory bank size | |
887 | * configuration cannot be determined. | |
888 | */ | |
9b3c6e85 | 889 | static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1) |
dba7a77c GE |
890 | { |
891 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
892 | int status = 0; | |
893 | enum mem_type mtype; | |
894 | enum dev_type dtype; | |
895 | enum edac_type edac_mode; | |
084a4fcc | 896 | int row, j; |
a895bf8b | 897 | u32 mbxcf, size, nr_pages; |
dba7a77c GE |
898 | |
899 | /* Establish the memory type and width */ | |
900 | ||
901 | mtype = ppc4xx_edac_get_mtype(mcopt1); | |
902 | dtype = ppc4xx_edac_get_dtype(mcopt1); | |
903 | ||
904 | /* Establish EDAC mode */ | |
905 | ||
906 | if (mci->edac_cap & EDAC_FLAG_SECDED) | |
907 | edac_mode = EDAC_SECDED; | |
908 | else if (mci->edac_cap & EDAC_FLAG_EC) | |
909 | edac_mode = EDAC_EC; | |
910 | else | |
911 | edac_mode = EDAC_NONE; | |
912 | ||
913 | /* | |
914 | * Initialize each chip select row structure which correspond | |
915 | * 1:1 with a controller bank/rank. | |
916 | */ | |
917 | ||
918 | for (row = 0; row < mci->nr_csrows; row++) { | |
5c16179b | 919 | struct csrow_info *csi = mci->csrows[row]; |
dba7a77c GE |
920 | |
921 | /* | |
922 | * Get the configuration settings for this | |
923 | * row/bank/rank and skip disabled banks. | |
924 | */ | |
925 | ||
926 | mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row)); | |
927 | ||
928 | if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE) | |
929 | continue; | |
930 | ||
931 | /* Map the bank configuration size setting to pages. */ | |
932 | ||
933 | size = mbxcf & SDRAM_MBCF_SZ_MASK; | |
934 | ||
935 | switch (size) { | |
936 | case SDRAM_MBCF_SZ_4MB: | |
937 | case SDRAM_MBCF_SZ_8MB: | |
938 | case SDRAM_MBCF_SZ_16MB: | |
939 | case SDRAM_MBCF_SZ_32MB: | |
940 | case SDRAM_MBCF_SZ_64MB: | |
941 | case SDRAM_MBCF_SZ_128MB: | |
942 | case SDRAM_MBCF_SZ_256MB: | |
943 | case SDRAM_MBCF_SZ_512MB: | |
944 | case SDRAM_MBCF_SZ_1GB: | |
945 | case SDRAM_MBCF_SZ_2GB: | |
946 | case SDRAM_MBCF_SZ_4GB: | |
947 | case SDRAM_MBCF_SZ_8GB: | |
a895bf8b | 948 | nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size); |
dba7a77c GE |
949 | break; |
950 | default: | |
951 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
952 | "Unrecognized memory bank %d " | |
953 | "size 0x%08x\n", | |
954 | row, SDRAM_MBCF_SZ_DECODE(size)); | |
955 | status = -EINVAL; | |
956 | goto done; | |
957 | } | |
958 | ||
dba7a77c GE |
959 | /* |
960 | * It's unclear exactly what grain should be set to | |
961 | * here. The SDRAM_ECCES register allows resolution of | |
962 | * an error down to a nibble which would potentially | |
963 | * argue for a grain of '1' byte, even though we only | |
964 | * know the associated address for uncorrectable | |
965 | * errors. This value is not used at present for | |
966 | * anything other than error reporting so getting it | |
967 | * wrong should be of little consequence. Other | |
968 | * possible values would be the PLB width (16), the | |
969 | * page size (PAGE_SIZE) or the memory width (2 or 4). | |
970 | */ | |
084a4fcc | 971 | for (j = 0; j < csi->nr_channels; j++) { |
2d34056d | 972 | struct dimm_info *dimm = csi->channels[j]->dimm; |
dba7a77c | 973 | |
a895bf8b | 974 | dimm->nr_pages = nr_pages / csi->nr_channels; |
084a4fcc | 975 | dimm->grain = 1; |
dba7a77c | 976 | |
084a4fcc MCC |
977 | dimm->mtype = mtype; |
978 | dimm->dtype = dtype; | |
dba7a77c | 979 | |
084a4fcc | 980 | dimm->edac_mode = edac_mode; |
084a4fcc | 981 | } |
dba7a77c GE |
982 | } |
983 | ||
984 | done: | |
985 | return status; | |
986 | } | |
987 | ||
988 | /** | |
b595076a | 989 | * ppc4xx_edac_mc_init - initialize driver instance |
dba7a77c GE |
990 | * @mci: A pointer to the EDAC memory controller instance being |
991 | * initialized. | |
992 | * @op: A pointer to the OpenFirmware device tree node associated | |
993 | * with the controller this EDAC instance is bound to. | |
dba7a77c GE |
994 | * @dcr_host: A pointer to the DCR data containing the DCR mapping |
995 | * for this controller instance. | |
996 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
997 | * currently set for the controller, from which ECC capabilities | |
998 | * and scrub mode are derived. | |
999 | * | |
1000 | * This routine performs initialization of the EDAC memory controller | |
1001 | * instance and related driver-private data associated with the | |
1002 | * ibm,sdram-4xx-ddr2 memory controller the instance is bound to. | |
1003 | * | |
1004 | * Returns 0 if OK; otherwise, < 0 on error. | |
1005 | */ | |
9b3c6e85 GKH |
1006 | static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci, |
1007 | struct platform_device *op, | |
1008 | const dcr_host_t *dcr_host, u32 mcopt1) | |
dba7a77c GE |
1009 | { |
1010 | int status = 0; | |
1011 | const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); | |
1012 | struct ppc4xx_edac_pdata *pdata = NULL; | |
a26f95fe | 1013 | const struct device_node *np = op->dev.of_node; |
dba7a77c | 1014 | |
b1608d69 | 1015 | if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL) |
dba7a77c GE |
1016 | return -EINVAL; |
1017 | ||
1018 | /* Initial driver pointers and private data */ | |
1019 | ||
fd687502 | 1020 | mci->pdev = &op->dev; |
dba7a77c | 1021 | |
fd687502 | 1022 | dev_set_drvdata(mci->pdev, mci); |
dba7a77c GE |
1023 | |
1024 | pdata = mci->pvt_info; | |
1025 | ||
1026 | pdata->dcr_host = *dcr_host; | |
dba7a77c GE |
1027 | |
1028 | /* Initialize controller capabilities and configuration */ | |
1029 | ||
1030 | mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR | | |
1031 | MEM_FLAG_DDR2 | MEM_FLAG_RDDR2); | |
1032 | ||
1033 | mci->edac_ctl_cap = (EDAC_FLAG_NONE | | |
1034 | EDAC_FLAG_EC | | |
1035 | EDAC_FLAG_SECDED); | |
1036 | ||
1037 | mci->scrub_cap = SCRUB_NONE; | |
1038 | mci->scrub_mode = SCRUB_NONE; | |
1039 | ||
1040 | /* | |
1041 | * Update the actual capabilites based on the MCOPT1[MCHK] | |
1042 | * settings. Scrubbing is only useful if reporting is enabled. | |
1043 | */ | |
1044 | ||
1045 | switch (memcheck) { | |
1046 | case SDRAM_MCOPT1_MCHK_CHK: | |
1047 | mci->edac_cap = EDAC_FLAG_EC; | |
1048 | break; | |
1049 | case SDRAM_MCOPT1_MCHK_CHK_REP: | |
1050 | mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED); | |
1051 | mci->scrub_mode = SCRUB_SW_SRC; | |
1052 | break; | |
1053 | default: | |
1054 | mci->edac_cap = EDAC_FLAG_NONE; | |
1055 | break; | |
1056 | } | |
1057 | ||
1058 | /* Initialize strings */ | |
1059 | ||
1060 | mci->mod_name = PPC4XX_EDAC_MODULE_NAME; | |
b877763e | 1061 | mci->ctl_name = ppc4xx_edac_match->compatible, |
dba7a77c GE |
1062 | mci->dev_name = np->full_name; |
1063 | ||
1064 | /* Initialize callbacks */ | |
1065 | ||
1066 | mci->edac_check = ppc4xx_edac_check; | |
1067 | mci->ctl_page_to_phys = NULL; | |
1068 | ||
1069 | /* Initialize chip select rows */ | |
1070 | ||
1071 | status = ppc4xx_edac_init_csrows(mci, mcopt1); | |
1072 | ||
1073 | if (status) | |
1074 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1075 | "Failed to initialize rows!\n"); | |
1076 | ||
1077 | return status; | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * ppc4xx_edac_register_irq - setup and register controller interrupts | |
1082 | * @op: A pointer to the OpenFirmware device tree node associated | |
1083 | * with the controller this EDAC instance is bound to. | |
1084 | * @mci: A pointer to the EDAC memory controller instance | |
1085 | * associated with the ibm,sdram-4xx-ddr2 controller for which | |
1086 | * interrupts are being registered. | |
1087 | * | |
1088 | * This routine parses the correctable (CE) and uncorrectable error (UE) | |
1089 | * interrupts from the device tree node and maps and assigns them to | |
1090 | * the associated EDAC memory controller instance. | |
1091 | * | |
1092 | * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be | |
1093 | * mapped and assigned. | |
1094 | */ | |
9b3c6e85 GKH |
1095 | static int ppc4xx_edac_register_irq(struct platform_device *op, |
1096 | struct mem_ctl_info *mci) | |
dba7a77c GE |
1097 | { |
1098 | int status = 0; | |
1099 | int ded_irq, sec_irq; | |
1100 | struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
a26f95fe | 1101 | struct device_node *np = op->dev.of_node; |
dba7a77c GE |
1102 | |
1103 | ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX); | |
1104 | sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX); | |
1105 | ||
37209572 | 1106 | if (!ded_irq || !sec_irq) { |
dba7a77c GE |
1107 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1108 | "Unable to map interrupts.\n"); | |
1109 | status = -ENODEV; | |
1110 | goto fail; | |
1111 | } | |
1112 | ||
1113 | status = request_irq(ded_irq, | |
1114 | ppc4xx_edac_isr, | |
5c43cbdf | 1115 | 0, |
dba7a77c GE |
1116 | "[EDAC] MC ECCDED", |
1117 | mci); | |
1118 | ||
1119 | if (status < 0) { | |
1120 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1121 | "Unable to request irq %d for ECC DED", | |
1122 | ded_irq); | |
1123 | status = -ENODEV; | |
1124 | goto fail1; | |
1125 | } | |
1126 | ||
1127 | status = request_irq(sec_irq, | |
1128 | ppc4xx_edac_isr, | |
5c43cbdf | 1129 | 0, |
dba7a77c GE |
1130 | "[EDAC] MC ECCSEC", |
1131 | mci); | |
1132 | ||
1133 | if (status < 0) { | |
1134 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1135 | "Unable to request irq %d for ECC SEC", | |
1136 | sec_irq); | |
1137 | status = -ENODEV; | |
1138 | goto fail2; | |
1139 | } | |
1140 | ||
1141 | ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq); | |
1142 | ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq); | |
1143 | ||
1144 | pdata->irqs.ded = ded_irq; | |
1145 | pdata->irqs.sec = sec_irq; | |
1146 | ||
1147 | return 0; | |
1148 | ||
1149 | fail2: | |
1150 | free_irq(sec_irq, mci); | |
1151 | ||
1152 | fail1: | |
1153 | free_irq(ded_irq, mci); | |
1154 | ||
1155 | fail: | |
1156 | return status; | |
1157 | } | |
1158 | ||
1159 | /** | |
1160 | * ppc4xx_edac_map_dcrs - locate and map controller registers | |
1161 | * @np: A pointer to the device tree node containing the DCR | |
1162 | * resources to map. | |
1163 | * @dcr_host: A pointer to the DCR data to populate with the | |
1164 | * DCR mapping. | |
1165 | * | |
1166 | * This routine attempts to locate in the device tree and map the DCR | |
1167 | * register resources associated with the controller's indirect DCR | |
1168 | * address and data windows. | |
1169 | * | |
1170 | * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on | |
1171 | * error. | |
1172 | */ | |
9b3c6e85 GKH |
1173 | static int ppc4xx_edac_map_dcrs(const struct device_node *np, |
1174 | dcr_host_t *dcr_host) | |
dba7a77c GE |
1175 | { |
1176 | unsigned int dcr_base, dcr_len; | |
1177 | ||
1178 | if (np == NULL || dcr_host == NULL) | |
1179 | return -EINVAL; | |
1180 | ||
1181 | /* Get the DCR resource extent and sanity check the values. */ | |
1182 | ||
1183 | dcr_base = dcr_resource_start(np, 0); | |
1184 | dcr_len = dcr_resource_len(np, 0); | |
1185 | ||
1186 | if (dcr_base == 0 || dcr_len == 0) { | |
1187 | ppc4xx_edac_printk(KERN_ERR, | |
1188 | "Failed to obtain DCR property.\n"); | |
1189 | return -ENODEV; | |
1190 | } | |
1191 | ||
1192 | if (dcr_len != SDRAM_DCR_RESOURCE_LEN) { | |
1193 | ppc4xx_edac_printk(KERN_ERR, | |
1194 | "Unexpected DCR length %d, expected %d.\n", | |
1195 | dcr_len, SDRAM_DCR_RESOURCE_LEN); | |
1196 | return -ENODEV; | |
1197 | } | |
1198 | ||
1199 | /* Attempt to map the DCR extent. */ | |
1200 | ||
1201 | *dcr_host = dcr_map(np, dcr_base, dcr_len); | |
1202 | ||
1203 | if (!DCR_MAP_OK(*dcr_host)) { | |
1204 | ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n"); | |
1205 | return -ENODEV; | |
1206 | } | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * ppc4xx_edac_probe - check controller and bind driver | |
1213 | * @op: A pointer to the OpenFirmware device tree node associated | |
1214 | * with the controller being probed for driver binding. | |
dba7a77c GE |
1215 | * |
1216 | * This routine probes a specific ibm,sdram-4xx-ddr2 controller | |
1217 | * instance for binding with the driver. | |
1218 | * | |
1219 | * Returns 0 if the controller instance was successfully bound to the | |
1220 | * driver; otherwise, < 0 on error. | |
1221 | */ | |
9b3c6e85 | 1222 | static int ppc4xx_edac_probe(struct platform_device *op) |
dba7a77c GE |
1223 | { |
1224 | int status = 0; | |
1225 | u32 mcopt1, memcheck; | |
1226 | dcr_host_t dcr_host; | |
a26f95fe | 1227 | const struct device_node *np = op->dev.of_node; |
dba7a77c | 1228 | struct mem_ctl_info *mci = NULL; |
94d93374 | 1229 | struct edac_mc_layer layers[2]; |
dba7a77c GE |
1230 | static int ppc4xx_edac_instance; |
1231 | ||
1232 | /* | |
1233 | * At this point, we only support the controller realized on | |
1234 | * the AMCC PPC 405EX[r]. Reject anything else. | |
1235 | */ | |
1236 | ||
1237 | if (!of_device_is_compatible(np, "ibm,sdram-405ex") && | |
1238 | !of_device_is_compatible(np, "ibm,sdram-405exr")) { | |
1239 | ppc4xx_edac_printk(KERN_NOTICE, | |
1240 | "Only the PPC405EX[r] is supported.\n"); | |
1241 | return -ENODEV; | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * Next, get the DCR property and attempt to map it so that we | |
1246 | * can probe the controller. | |
1247 | */ | |
1248 | ||
1249 | status = ppc4xx_edac_map_dcrs(np, &dcr_host); | |
1250 | ||
1251 | if (status) | |
1252 | return status; | |
1253 | ||
1254 | /* | |
1255 | * First determine whether ECC is enabled at all. If not, | |
1256 | * there is no useful checking or monitoring that can be done | |
1257 | * for this controller. | |
1258 | */ | |
1259 | ||
1260 | mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1); | |
1261 | memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); | |
1262 | ||
1263 | if (memcheck == SDRAM_MCOPT1_MCHK_NON) { | |
2efdda4a RH |
1264 | ppc4xx_edac_printk(KERN_INFO, "%pOF: No ECC memory detected or " |
1265 | "ECC is disabled.\n", np); | |
dba7a77c GE |
1266 | status = -ENODEV; |
1267 | goto done; | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * At this point, we know ECC is enabled, allocate an EDAC | |
1272 | * controller instance and perform the appropriate | |
1273 | * initialization. | |
1274 | */ | |
94d93374 MCC |
1275 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
1276 | layers[0].size = ppc4xx_edac_nr_csrows; | |
1277 | layers[0].is_virt_csrow = true; | |
1278 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
1279 | layers[1].size = ppc4xx_edac_nr_chans; | |
1280 | layers[1].is_virt_csrow = false; | |
ca0907b9 | 1281 | mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers, |
94d93374 | 1282 | sizeof(struct ppc4xx_edac_pdata)); |
dba7a77c | 1283 | if (mci == NULL) { |
2efdda4a | 1284 | ppc4xx_edac_printk(KERN_ERR, "%pOF: " |
dba7a77c | 1285 | "Failed to allocate EDAC MC instance!\n", |
2efdda4a | 1286 | np); |
dba7a77c GE |
1287 | status = -ENOMEM; |
1288 | goto done; | |
1289 | } | |
1290 | ||
00006124 | 1291 | status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1); |
dba7a77c GE |
1292 | |
1293 | if (status) { | |
1294 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1295 | "Failed to initialize instance!\n"); | |
1296 | goto fail; | |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * We have a valid, initialized EDAC instance bound to the | |
1301 | * controller. Attempt to register it with the EDAC subsystem | |
1302 | * and, if necessary, register interrupts. | |
1303 | */ | |
1304 | ||
1305 | if (edac_mc_add_mc(mci)) { | |
1306 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1307 | "Failed to add instance!\n"); | |
1308 | status = -ENODEV; | |
1309 | goto fail; | |
1310 | } | |
1311 | ||
1312 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1313 | status = ppc4xx_edac_register_irq(op, mci); | |
1314 | ||
1315 | if (status) | |
1316 | goto fail1; | |
1317 | } | |
1318 | ||
1319 | ppc4xx_edac_instance++; | |
1320 | ||
1321 | return 0; | |
1322 | ||
1323 | fail1: | |
fd687502 | 1324 | edac_mc_del_mc(mci->pdev); |
dba7a77c GE |
1325 | |
1326 | fail: | |
1327 | edac_mc_free(mci); | |
1328 | ||
1329 | done: | |
1330 | return status; | |
1331 | } | |
1332 | ||
1333 | /** | |
1334 | * ppc4xx_edac_remove - unbind driver from controller | |
1335 | * @op: A pointer to the OpenFirmware device tree node associated | |
1336 | * with the controller this EDAC instance is to be unbound/removed | |
1337 | * from. | |
1338 | * | |
1339 | * This routine unbinds the EDAC memory controller instance associated | |
1340 | * with the specified ibm,sdram-4xx-ddr2 controller described by the | |
1341 | * OpenFirmware device tree node passed as a parameter. | |
1342 | * | |
1343 | * Unconditionally returns 0. | |
1344 | */ | |
1345 | static int | |
2dc11581 | 1346 | ppc4xx_edac_remove(struct platform_device *op) |
dba7a77c GE |
1347 | { |
1348 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
1349 | struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
1350 | ||
1351 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1352 | free_irq(pdata->irqs.sec, mci); | |
1353 | free_irq(pdata->irqs.ded, mci); | |
1354 | } | |
1355 | ||
1356 | dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN); | |
1357 | ||
fd687502 | 1358 | edac_mc_del_mc(mci->pdev); |
dba7a77c GE |
1359 | edac_mc_free(mci); |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | /** | |
1365 | * ppc4xx_edac_opstate_init - initialize EDAC reporting method | |
1366 | * | |
1367 | * This routine ensures that the EDAC memory controller reporting | |
1368 | * method is mapped to a sane value as the EDAC core defines the value | |
1369 | * to EDAC_OPSTATE_INVAL by default. We don't call the global | |
1370 | * opstate_init as that defaults to polling and we want interrupt as | |
1371 | * the default. | |
1372 | */ | |
1373 | static inline void __init | |
1374 | ppc4xx_edac_opstate_init(void) | |
1375 | { | |
1376 | switch (edac_op_state) { | |
1377 | case EDAC_OPSTATE_POLL: | |
1378 | case EDAC_OPSTATE_INT: | |
1379 | break; | |
1380 | default: | |
1381 | edac_op_state = EDAC_OPSTATE_INT; | |
1382 | break; | |
1383 | } | |
1384 | ||
1385 | ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n", | |
1386 | ((edac_op_state == EDAC_OPSTATE_POLL) ? | |
1387 | EDAC_OPSTATE_POLL_STR : | |
1388 | ((edac_op_state == EDAC_OPSTATE_INT) ? | |
1389 | EDAC_OPSTATE_INT_STR : | |
1390 | EDAC_OPSTATE_UNKNOWN_STR))); | |
1391 | } | |
1392 | ||
1393 | /** | |
1394 | * ppc4xx_edac_init - driver/module insertion entry point | |
1395 | * | |
1396 | * This routine is the driver/module insertion entry point. It | |
1397 | * initializes the EDAC memory controller reporting state and | |
1398 | * registers the driver as an OpenFirmware device tree platform | |
1399 | * driver. | |
1400 | */ | |
1401 | static int __init | |
1402 | ppc4xx_edac_init(void) | |
1403 | { | |
1404 | ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n"); | |
1405 | ||
1406 | ppc4xx_edac_opstate_init(); | |
1407 | ||
00006124 | 1408 | return platform_driver_register(&ppc4xx_edac_driver); |
dba7a77c GE |
1409 | } |
1410 | ||
1411 | /** | |
1412 | * ppc4xx_edac_exit - driver/module removal entry point | |
1413 | * | |
1414 | * This routine is the driver/module removal entry point. It | |
1415 | * unregisters the driver as an OpenFirmware device tree platform | |
1416 | * driver. | |
1417 | */ | |
1418 | static void __exit | |
1419 | ppc4xx_edac_exit(void) | |
1420 | { | |
00006124 | 1421 | platform_driver_unregister(&ppc4xx_edac_driver); |
dba7a77c GE |
1422 | } |
1423 | ||
1424 | module_init(ppc4xx_edac_init); | |
1425 | module_exit(ppc4xx_edac_exit); | |
1426 | ||
1427 | MODULE_LICENSE("GPL v2"); | |
1428 | MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>"); | |
1429 | MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller"); | |
1430 | module_param(edac_op_state, int, 0444); | |
1431 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: " | |
1432 | "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR); |