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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
dba7a77c GE |
2 | /* |
3 | * Copyright (c) 2008 Nuovation System Designs, LLC | |
4 | * Grant Erickson <gerickson@nuovations.com> | |
dba7a77c GE |
5 | */ |
6 | ||
7 | #include <linux/edac.h> | |
8 | #include <linux/interrupt.h> | |
9 | #include <linux/irq.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of_device.h> | |
bce02f71 | 14 | #include <linux/of_irq.h> |
dba7a77c GE |
15 | #include <linux/of_platform.h> |
16 | #include <linux/types.h> | |
17 | ||
18 | #include <asm/dcr.h> | |
19 | ||
78d88e8a | 20 | #include "edac_module.h" |
dba7a77c GE |
21 | #include "ppc4xx_edac.h" |
22 | ||
23 | /* | |
24 | * This file implements a driver for monitoring and handling events | |
25 | * associated with the IMB DDR2 ECC controller found in the AMCC/IBM | |
26 | * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX. | |
27 | * | |
28 | * As realized in the 405EX[r], this controller features: | |
29 | * | |
30 | * - Support for registered- and non-registered DDR1 and DDR2 memory. | |
31 | * - 32-bit or 16-bit memory interface with optional ECC. | |
32 | * | |
33 | * o ECC support includes: | |
34 | * | |
35 | * - 4-bit SEC/DED | |
36 | * - Aligned-nibble error detect | |
37 | * - Bypass mode | |
38 | * | |
39 | * - Two (2) memory banks/ranks. | |
40 | * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per | |
41 | * bank/rank in 16-bit mode. | |
42 | * | |
43 | * As realized in the 440SP and 440SPe, this controller changes/adds: | |
44 | * | |
45 | * - 64-bit or 32-bit memory interface with optional ECC. | |
46 | * | |
47 | * o ECC support includes: | |
48 | * | |
49 | * - 8-bit SEC/DED | |
50 | * - Aligned-nibble error detect | |
51 | * - Bypass mode | |
52 | * | |
53 | * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB | |
54 | * per bank/rank in 32-bit mode. | |
55 | * | |
56 | * As realized in the 460EX and 460GT, this controller changes/adds: | |
57 | * | |
58 | * - 64-bit or 32-bit memory interface with optional ECC. | |
59 | * | |
60 | * o ECC support includes: | |
61 | * | |
62 | * - 8-bit SEC/DED | |
63 | * - Aligned-nibble error detect | |
64 | * - Bypass mode | |
65 | * | |
66 | * - Four (4) memory banks/ranks. | |
67 | * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB | |
68 | * per bank/rank in 32-bit mode. | |
69 | * | |
70 | * At present, this driver has ONLY been tested against the controller | |
71 | * realization in the 405EX[r] on the AMCC Kilauea and Haleakala | |
72 | * boards (256 MiB w/o ECC memory soldered onto the board) and a | |
73 | * proprietary board based on those designs (128 MiB ECC memory, also | |
74 | * soldered onto the board). | |
75 | * | |
76 | * Dynamic feature detection and handling needs to be added for the | |
77 | * other realizations of this controller listed above. | |
78 | * | |
79 | * Eventually, this driver will likely be adapted to the above variant | |
80 | * realizations of this controller as well as broken apart to handle | |
81 | * the other known ECC-capable controllers prevalent in other 4xx | |
82 | * processors: | |
83 | * | |
84 | * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx" | |
85 | * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr" | |
86 | * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2" | |
87 | * | |
88 | * For this controller, unfortunately, correctable errors report | |
89 | * nothing more than the beat/cycle and byte/lane the correction | |
90 | * occurred on and the check bit group that covered the error. | |
91 | * | |
92 | * In contrast, uncorrectable errors also report the failing address, | |
93 | * the bus master and the transaction direction (i.e. read or write) | |
94 | * | |
95 | * Regardless of whether the error is a CE or a UE, we report the | |
96 | * following pieces of information in the driver-unique message to the | |
97 | * EDAC subsystem: | |
98 | * | |
99 | * - Device tree path | |
100 | * - Bank(s) | |
101 | * - Check bit error group | |
102 | * - Beat(s)/lane(s) | |
103 | */ | |
104 | ||
105 | /* Preprocessor Definitions */ | |
106 | ||
107 | #define EDAC_OPSTATE_INT_STR "interrupt" | |
108 | #define EDAC_OPSTATE_POLL_STR "polled" | |
109 | #define EDAC_OPSTATE_UNKNOWN_STR "unknown" | |
110 | ||
111 | #define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac" | |
152ba394 | 112 | #define PPC4XX_EDAC_MODULE_REVISION "v1.0.0" |
dba7a77c GE |
113 | |
114 | #define PPC4XX_EDAC_MESSAGE_SIZE 256 | |
115 | ||
116 | /* | |
117 | * Kernel logging without an EDAC instance | |
118 | */ | |
119 | #define ppc4xx_edac_printk(level, fmt, arg...) \ | |
120 | edac_printk(level, "PPC4xx MC", fmt, ##arg) | |
121 | ||
122 | /* | |
123 | * Kernel logging with an EDAC instance | |
124 | */ | |
125 | #define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \ | |
126 | edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg) | |
127 | ||
128 | /* | |
129 | * Macros to convert bank configuration size enumerations into MiB and | |
130 | * page values. | |
131 | */ | |
132 | #define SDRAM_MBCF_SZ_MiB_MIN 4 | |
133 | #define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \ | |
134 | << (SDRAM_MBCF_SZ_DECODE(n))) | |
135 | #define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \ | |
136 | << (20 - PAGE_SHIFT + \ | |
137 | SDRAM_MBCF_SZ_DECODE(n))) | |
138 | ||
139 | /* | |
140 | * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are | |
42b2aa86 | 141 | * indirectly accessed and have a base and length defined by the |
dba7a77c GE |
142 | * device tree. The base can be anything; however, we expect the |
143 | * length to be precisely two registers, the first for the address | |
144 | * window and the second for the data window. | |
145 | */ | |
146 | #define SDRAM_DCR_RESOURCE_LEN 2 | |
147 | #define SDRAM_DCR_ADDR_OFFSET 0 | |
148 | #define SDRAM_DCR_DATA_OFFSET 1 | |
149 | ||
150 | /* | |
151 | * Device tree interrupt indices | |
152 | */ | |
153 | #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */ | |
154 | #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */ | |
155 | ||
156 | /* Type Definitions */ | |
157 | ||
158 | /* | |
159 | * PPC4xx SDRAM memory controller private instance data | |
160 | */ | |
161 | struct ppc4xx_edac_pdata { | |
162 | dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */ | |
163 | struct { | |
164 | int sec; /* Single-bit correctable error IRQ assigned */ | |
165 | int ded; /* Double-bit detectable error IRQ assigned */ | |
166 | } irqs; | |
167 | }; | |
168 | ||
169 | /* | |
170 | * Various status data gathered and manipulated when checking and | |
171 | * reporting ECC status. | |
172 | */ | |
173 | struct ppc4xx_ecc_status { | |
174 | u32 ecces; | |
175 | u32 besr; | |
176 | u32 bearh; | |
177 | u32 bearl; | |
178 | u32 wmirq; | |
179 | }; | |
180 | ||
181 | /* Function Prototypes */ | |
182 | ||
b877763e | 183 | static int ppc4xx_edac_probe(struct platform_device *device); |
2dc11581 | 184 | static int ppc4xx_edac_remove(struct platform_device *device); |
dba7a77c GE |
185 | |
186 | /* Global Variables */ | |
187 | ||
188 | /* | |
189 | * Device tree node type and compatible tuples this driver can match | |
190 | * on. | |
191 | */ | |
1afaa055 | 192 | static const struct of_device_id ppc4xx_edac_match[] = { |
dba7a77c GE |
193 | { |
194 | .compatible = "ibm,sdram-4xx-ddr2" | |
195 | }, | |
196 | { } | |
197 | }; | |
90b3b373 | 198 | MODULE_DEVICE_TABLE(of, ppc4xx_edac_match); |
dba7a77c | 199 | |
00006124 | 200 | static struct platform_driver ppc4xx_edac_driver = { |
dba7a77c GE |
201 | .probe = ppc4xx_edac_probe, |
202 | .remove = ppc4xx_edac_remove, | |
4018294b | 203 | .driver = { |
e57b708b | 204 | .name = PPC4XX_EDAC_MODULE_NAME, |
4018294b GL |
205 | .of_match_table = ppc4xx_edac_match, |
206 | }, | |
dba7a77c GE |
207 | }; |
208 | ||
209 | /* | |
210 | * TODO: The row and channel parameters likely need to be dynamically | |
211 | * set based on the aforementioned variant controller realizations. | |
212 | */ | |
213 | static const unsigned ppc4xx_edac_nr_csrows = 2; | |
214 | static const unsigned ppc4xx_edac_nr_chans = 1; | |
215 | ||
216 | /* | |
217 | * Strings associated with PLB master IDs capable of being posted in | |
218 | * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors. | |
219 | */ | |
220 | static const char * const ppc4xx_plb_masters[9] = { | |
221 | [SDRAM_PLB_M0ID_ICU] = "ICU", | |
222 | [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0", | |
223 | [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1", | |
224 | [SDRAM_PLB_M0ID_DMA] = "DMA", | |
225 | [SDRAM_PLB_M0ID_DCU] = "DCU", | |
226 | [SDRAM_PLB_M0ID_OPB] = "OPB", | |
227 | [SDRAM_PLB_M0ID_MAL] = "MAL", | |
228 | [SDRAM_PLB_M0ID_SEC] = "SEC", | |
229 | [SDRAM_PLB_M0ID_AHB] = "AHB" | |
230 | }; | |
231 | ||
232 | /** | |
233 | * mfsdram - read and return controller register data | |
234 | * @dcr_host: A pointer to the DCR mapping. | |
235 | * @idcr_n: The indirect DCR register to read. | |
236 | * | |
237 | * This routine reads and returns the data associated with the | |
238 | * controller's specified indirect DCR register. | |
239 | * | |
240 | * Returns the read data. | |
241 | */ | |
242 | static inline u32 | |
243 | mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n) | |
244 | { | |
245 | return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, | |
246 | dcr_host->base + SDRAM_DCR_DATA_OFFSET, | |
247 | idcr_n); | |
248 | } | |
249 | ||
250 | /** | |
251 | * mtsdram - write controller register data | |
252 | * @dcr_host: A pointer to the DCR mapping. | |
253 | * @idcr_n: The indirect DCR register to write. | |
254 | * @value: The data to write. | |
255 | * | |
256 | * This routine writes the provided data to the controller's specified | |
257 | * indirect DCR register. | |
258 | */ | |
259 | static inline void | |
260 | mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value) | |
261 | { | |
262 | return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, | |
263 | dcr_host->base + SDRAM_DCR_DATA_OFFSET, | |
264 | idcr_n, | |
265 | value); | |
266 | } | |
267 | ||
268 | /** | |
269 | * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error | |
270 | * @status: A pointer to the ECC status structure to check for an | |
271 | * ECC bank error. | |
272 | * @bank: The bank to check for an ECC error. | |
273 | * | |
274 | * This routine determines whether the specified bank has an ECC | |
275 | * error. | |
276 | * | |
277 | * Returns true if the specified bank has an ECC error; otherwise, | |
278 | * false. | |
279 | */ | |
280 | static bool | |
281 | ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status, | |
282 | unsigned int bank) | |
283 | { | |
284 | switch (bank) { | |
285 | case 0: | |
286 | return status->ecces & SDRAM_ECCES_BK0ER; | |
287 | case 1: | |
288 | return status->ecces & SDRAM_ECCES_BK1ER; | |
289 | default: | |
290 | return false; | |
291 | } | |
292 | } | |
293 | ||
294 | /** | |
295 | * ppc4xx_edac_generate_bank_message - generate interpretted bank status message | |
296 | * @mci: A pointer to the EDAC memory controller instance associated | |
297 | * with the bank message being generated. | |
298 | * @status: A pointer to the ECC status structure to generate the | |
299 | * message from. | |
300 | * @buffer: A pointer to the buffer in which to generate the | |
301 | * message. | |
302 | * @size: The size, in bytes, of space available in buffer. | |
303 | * | |
304 | * This routine generates to the provided buffer the portion of the | |
305 | * driver-unique report message associated with the ECCESS[BKNER] | |
306 | * field of the specified ECC status. | |
307 | * | |
308 | * Returns the number of characters generated on success; otherwise, < | |
309 | * 0 on error. | |
310 | */ | |
311 | static int | |
312 | ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci, | |
313 | const struct ppc4xx_ecc_status *status, | |
314 | char *buffer, | |
315 | size_t size) | |
316 | { | |
317 | int n, total = 0; | |
318 | unsigned int row, rows; | |
319 | ||
320 | n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name); | |
321 | ||
322 | if (n < 0 || n >= size) | |
323 | goto fail; | |
324 | ||
325 | buffer += n; | |
326 | size -= n; | |
327 | total += n; | |
328 | ||
329 | for (rows = 0, row = 0; row < mci->nr_csrows; row++) { | |
330 | if (ppc4xx_edac_check_bank_error(status, row)) { | |
331 | n = snprintf(buffer, size, "%s%u", | |
332 | (rows++ ? ", " : ""), row); | |
333 | ||
334 | if (n < 0 || n >= size) | |
335 | goto fail; | |
336 | ||
337 | buffer += n; | |
338 | size -= n; | |
339 | total += n; | |
340 | } | |
341 | } | |
342 | ||
343 | n = snprintf(buffer, size, "%s; ", rows ? "" : "None"); | |
344 | ||
345 | if (n < 0 || n >= size) | |
346 | goto fail; | |
347 | ||
348 | buffer += n; | |
349 | size -= n; | |
350 | total += n; | |
351 | ||
352 | fail: | |
353 | return total; | |
354 | } | |
355 | ||
356 | /** | |
357 | * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message | |
358 | * @mci: A pointer to the EDAC memory controller instance associated | |
359 | * with the checkbit message being generated. | |
360 | * @status: A pointer to the ECC status structure to generate the | |
361 | * message from. | |
362 | * @buffer: A pointer to the buffer in which to generate the | |
363 | * message. | |
364 | * @size: The size, in bytes, of space available in buffer. | |
365 | * | |
366 | * This routine generates to the provided buffer the portion of the | |
367 | * driver-unique report message associated with the ECCESS[CKBER] | |
368 | * field of the specified ECC status. | |
369 | * | |
370 | * Returns the number of characters generated on success; otherwise, < | |
371 | * 0 on error. | |
372 | */ | |
373 | static int | |
374 | ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci, | |
375 | const struct ppc4xx_ecc_status *status, | |
376 | char *buffer, | |
377 | size_t size) | |
378 | { | |
379 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
380 | const char *ckber = NULL; | |
381 | ||
382 | switch (status->ecces & SDRAM_ECCES_CKBER_MASK) { | |
383 | case SDRAM_ECCES_CKBER_NONE: | |
384 | ckber = "None"; | |
385 | break; | |
386 | case SDRAM_ECCES_CKBER_32_ECC_0_3: | |
387 | ckber = "ECC0:3"; | |
388 | break; | |
389 | case SDRAM_ECCES_CKBER_32_ECC_4_8: | |
390 | switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) & | |
391 | SDRAM_MCOPT1_WDTH_MASK) { | |
392 | case SDRAM_MCOPT1_WDTH_16: | |
393 | ckber = "ECC0:3"; | |
394 | break; | |
395 | case SDRAM_MCOPT1_WDTH_32: | |
396 | ckber = "ECC4:8"; | |
397 | break; | |
398 | default: | |
399 | ckber = "Unknown"; | |
400 | break; | |
401 | } | |
402 | break; | |
403 | case SDRAM_ECCES_CKBER_32_ECC_0_8: | |
404 | ckber = "ECC0:8"; | |
405 | break; | |
406 | default: | |
407 | ckber = "Unknown"; | |
408 | break; | |
409 | } | |
410 | ||
411 | return snprintf(buffer, size, "Checkbit Error: %s", ckber); | |
412 | } | |
413 | ||
414 | /** | |
415 | * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message | |
416 | * @mci: A pointer to the EDAC memory controller instance associated | |
417 | * with the byte lane message being generated. | |
418 | * @status: A pointer to the ECC status structure to generate the | |
419 | * message from. | |
420 | * @buffer: A pointer to the buffer in which to generate the | |
421 | * message. | |
422 | * @size: The size, in bytes, of space available in buffer. | |
423 | * | |
424 | * This routine generates to the provided buffer the portion of the | |
425 | * driver-unique report message associated with the ECCESS[BNCE] | |
426 | * field of the specified ECC status. | |
427 | * | |
428 | * Returns the number of characters generated on success; otherwise, < | |
429 | * 0 on error. | |
430 | */ | |
431 | static int | |
432 | ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci, | |
433 | const struct ppc4xx_ecc_status *status, | |
434 | char *buffer, | |
435 | size_t size) | |
436 | { | |
437 | int n, total = 0; | |
438 | unsigned int lane, lanes; | |
439 | const unsigned int first_lane = 0; | |
440 | const unsigned int lane_count = 16; | |
441 | ||
442 | n = snprintf(buffer, size, "; Byte Lane Errors: "); | |
443 | ||
444 | if (n < 0 || n >= size) | |
445 | goto fail; | |
446 | ||
447 | buffer += n; | |
448 | size -= n; | |
449 | total += n; | |
450 | ||
451 | for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { | |
452 | if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { | |
453 | n = snprintf(buffer, size, | |
454 | "%s%u", | |
455 | (lanes++ ? ", " : ""), lane); | |
456 | ||
457 | if (n < 0 || n >= size) | |
458 | goto fail; | |
459 | ||
460 | buffer += n; | |
461 | size -= n; | |
462 | total += n; | |
463 | } | |
464 | } | |
465 | ||
466 | n = snprintf(buffer, size, "%s; ", lanes ? "" : "None"); | |
467 | ||
468 | if (n < 0 || n >= size) | |
469 | goto fail; | |
470 | ||
471 | buffer += n; | |
472 | size -= n; | |
473 | total += n; | |
474 | ||
475 | fail: | |
476 | return total; | |
477 | } | |
478 | ||
479 | /** | |
480 | * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message | |
481 | * @mci: A pointer to the EDAC memory controller instance associated | |
482 | * with the ECCES message being generated. | |
483 | * @status: A pointer to the ECC status structure to generate the | |
484 | * message from. | |
485 | * @buffer: A pointer to the buffer in which to generate the | |
486 | * message. | |
487 | * @size: The size, in bytes, of space available in buffer. | |
488 | * | |
489 | * This routine generates to the provided buffer the portion of the | |
490 | * driver-unique report message associated with the ECCESS register of | |
491 | * the specified ECC status. | |
492 | * | |
493 | * Returns the number of characters generated on success; otherwise, < | |
494 | * 0 on error. | |
495 | */ | |
496 | static int | |
497 | ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci, | |
498 | const struct ppc4xx_ecc_status *status, | |
499 | char *buffer, | |
500 | size_t size) | |
501 | { | |
502 | int n, total = 0; | |
503 | ||
504 | n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size); | |
505 | ||
506 | if (n < 0 || n >= size) | |
507 | goto fail; | |
508 | ||
509 | buffer += n; | |
510 | size -= n; | |
511 | total += n; | |
512 | ||
513 | n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size); | |
514 | ||
515 | if (n < 0 || n >= size) | |
516 | goto fail; | |
517 | ||
518 | buffer += n; | |
519 | size -= n; | |
520 | total += n; | |
521 | ||
522 | n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size); | |
523 | ||
524 | if (n < 0 || n >= size) | |
525 | goto fail; | |
526 | ||
527 | buffer += n; | |
528 | size -= n; | |
529 | total += n; | |
530 | ||
531 | fail: | |
532 | return total; | |
533 | } | |
534 | ||
535 | /** | |
536 | * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message | |
537 | * @mci: A pointer to the EDAC memory controller instance associated | |
538 | * with the PLB message being generated. | |
539 | * @status: A pointer to the ECC status structure to generate the | |
540 | * message from. | |
541 | * @buffer: A pointer to the buffer in which to generate the | |
542 | * message. | |
543 | * @size: The size, in bytes, of space available in buffer. | |
544 | * | |
545 | * This routine generates to the provided buffer the portion of the | |
546 | * driver-unique report message associated with the PLB-related BESR | |
547 | * and/or WMIRQ registers of the specified ECC status. | |
548 | * | |
549 | * Returns the number of characters generated on success; otherwise, < | |
550 | * 0 on error. | |
551 | */ | |
552 | static int | |
553 | ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci, | |
554 | const struct ppc4xx_ecc_status *status, | |
555 | char *buffer, | |
556 | size_t size) | |
557 | { | |
558 | unsigned int master; | |
559 | bool read; | |
560 | ||
561 | if ((status->besr & SDRAM_BESR_MASK) == 0) | |
562 | return 0; | |
563 | ||
564 | if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE) | |
565 | return 0; | |
566 | ||
567 | read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ); | |
568 | ||
569 | master = SDRAM_BESR_M0ID_DECODE(status->besr); | |
570 | ||
571 | return snprintf(buffer, size, | |
572 | "%s error w/ PLB master %u \"%s\"; ", | |
573 | (read ? "Read" : "Write"), | |
574 | master, | |
575 | (((master >= SDRAM_PLB_M0ID_FIRST) && | |
576 | (master <= SDRAM_PLB_M0ID_LAST)) ? | |
577 | ppc4xx_plb_masters[master] : "UNKNOWN")); | |
578 | } | |
579 | ||
580 | /** | |
581 | * ppc4xx_edac_generate_message - generate interpretted status message | |
582 | * @mci: A pointer to the EDAC memory controller instance associated | |
583 | * with the driver-unique message being generated. | |
584 | * @status: A pointer to the ECC status structure to generate the | |
585 | * message from. | |
586 | * @buffer: A pointer to the buffer in which to generate the | |
587 | * message. | |
588 | * @size: The size, in bytes, of space available in buffer. | |
589 | * | |
590 | * This routine generates to the provided buffer the driver-unique | |
591 | * EDAC report message from the specified ECC status. | |
592 | */ | |
593 | static void | |
594 | ppc4xx_edac_generate_message(const struct mem_ctl_info *mci, | |
595 | const struct ppc4xx_ecc_status *status, | |
596 | char *buffer, | |
597 | size_t size) | |
598 | { | |
599 | int n; | |
600 | ||
601 | if (buffer == NULL || size == 0) | |
602 | return; | |
603 | ||
604 | n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size); | |
605 | ||
606 | if (n < 0 || n >= size) | |
607 | return; | |
608 | ||
609 | buffer += n; | |
610 | size -= n; | |
611 | ||
612 | ppc4xx_edac_generate_plb_message(mci, status, buffer, size); | |
613 | } | |
614 | ||
615 | #ifdef DEBUG | |
616 | /** | |
617 | * ppc4xx_ecc_dump_status - dump controller ECC status registers | |
618 | * @mci: A pointer to the EDAC memory controller instance | |
619 | * associated with the status being dumped. | |
620 | * @status: A pointer to the ECC status structure to generate the | |
621 | * dump from. | |
622 | * | |
623 | * This routine dumps to the kernel log buffer the raw and | |
624 | * interpretted specified ECC status. | |
625 | */ | |
626 | static void | |
627 | ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci, | |
628 | const struct ppc4xx_ecc_status *status) | |
629 | { | |
630 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; | |
631 | ||
632 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); | |
633 | ||
634 | ppc4xx_edac_mc_printk(KERN_INFO, mci, | |
635 | "\n" | |
636 | "\tECCES: 0x%08x\n" | |
637 | "\tWMIRQ: 0x%08x\n" | |
638 | "\tBESR: 0x%08x\n" | |
639 | "\tBEAR: 0x%08x%08x\n" | |
640 | "\t%s\n", | |
641 | status->ecces, | |
642 | status->wmirq, | |
643 | status->besr, | |
644 | status->bearh, | |
645 | status->bearl, | |
646 | message); | |
647 | } | |
648 | #endif /* DEBUG */ | |
649 | ||
650 | /** | |
651 | * ppc4xx_ecc_get_status - get controller ECC status | |
652 | * @mci: A pointer to the EDAC memory controller instance | |
653 | * associated with the status being retrieved. | |
654 | * @status: A pointer to the ECC status structure to populate the | |
655 | * ECC status with. | |
656 | * | |
657 | * This routine reads and masks, as appropriate, all the relevant | |
658 | * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors. | |
659 | * While we read all of them, for correctable errors, we only expect | |
660 | * to deal with ECCES. For uncorrectable errors, we expect to deal | |
661 | * with all of them. | |
662 | */ | |
663 | static void | |
664 | ppc4xx_ecc_get_status(const struct mem_ctl_info *mci, | |
665 | struct ppc4xx_ecc_status *status) | |
666 | { | |
667 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
668 | const dcr_host_t *dcr_host = &pdata->dcr_host; | |
669 | ||
670 | status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK; | |
671 | status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK; | |
672 | status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK; | |
673 | status->bearl = mfsdram(dcr_host, SDRAM_BEARL); | |
674 | status->bearh = mfsdram(dcr_host, SDRAM_BEARH); | |
675 | } | |
676 | ||
677 | /** | |
678 | * ppc4xx_ecc_clear_status - clear controller ECC status | |
679 | * @mci: A pointer to the EDAC memory controller instance | |
680 | * associated with the status being cleared. | |
681 | * @status: A pointer to the ECC status structure containing the | |
682 | * values to write to clear the ECC status. | |
683 | * | |
684 | * This routine clears--by writing the masked (as appropriate) status | |
685 | * values back to--the status registers that deal with | |
686 | * ibm,sdram-4xx-ddr2 ECC errors. | |
687 | */ | |
688 | static void | |
689 | ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci, | |
690 | const struct ppc4xx_ecc_status *status) | |
691 | { | |
692 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
693 | const dcr_host_t *dcr_host = &pdata->dcr_host; | |
694 | ||
695 | mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK); | |
696 | mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK); | |
697 | mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK); | |
698 | mtsdram(dcr_host, SDRAM_BEARL, 0); | |
699 | mtsdram(dcr_host, SDRAM_BEARH, 0); | |
700 | } | |
701 | ||
702 | /** | |
703 | * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE) | |
704 | * @mci: A pointer to the EDAC memory controller instance | |
705 | * associated with the correctable error being handled and reported. | |
706 | * @status: A pointer to the ECC status structure associated with | |
707 | * the correctable error being handled and reported. | |
708 | * | |
709 | * This routine handles an ibm,sdram-4xx-ddr2 controller ECC | |
710 | * correctable error. Per the aforementioned discussion, there's not | |
711 | * enough status available to use the full EDAC correctable error | |
712 | * interface, so we just pass driver-unique message to the "no info" | |
713 | * interface. | |
714 | */ | |
715 | static void | |
716 | ppc4xx_edac_handle_ce(struct mem_ctl_info *mci, | |
717 | const struct ppc4xx_ecc_status *status) | |
718 | { | |
719 | int row; | |
720 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; | |
721 | ||
722 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); | |
723 | ||
724 | for (row = 0; row < mci->nr_csrows; row++) | |
725 | if (ppc4xx_edac_check_bank_error(status, row)) | |
9eb07a7f | 726 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
94d93374 MCC |
727 | 0, 0, 0, |
728 | row, 0, -1, | |
03f7eae8 | 729 | message, ""); |
dba7a77c GE |
730 | } |
731 | ||
732 | /** | |
733 | * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE) | |
734 | * @mci: A pointer to the EDAC memory controller instance | |
735 | * associated with the uncorrectable error being handled and | |
736 | * reported. | |
737 | * @status: A pointer to the ECC status structure associated with | |
738 | * the uncorrectable error being handled and reported. | |
739 | * | |
740 | * This routine handles an ibm,sdram-4xx-ddr2 controller ECC | |
741 | * uncorrectable error. | |
742 | */ | |
743 | static void | |
744 | ppc4xx_edac_handle_ue(struct mem_ctl_info *mci, | |
745 | const struct ppc4xx_ecc_status *status) | |
746 | { | |
747 | const u64 bear = ((u64)status->bearh << 32 | status->bearl); | |
748 | const unsigned long page = bear >> PAGE_SHIFT; | |
749 | const unsigned long offset = bear & ~PAGE_MASK; | |
750 | int row; | |
751 | char message[PPC4XX_EDAC_MESSAGE_SIZE]; | |
752 | ||
753 | ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); | |
754 | ||
755 | for (row = 0; row < mci->nr_csrows; row++) | |
756 | if (ppc4xx_edac_check_bank_error(status, row)) | |
9eb07a7f | 757 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
94d93374 MCC |
758 | page, offset, 0, |
759 | row, 0, -1, | |
03f7eae8 | 760 | message, ""); |
dba7a77c GE |
761 | } |
762 | ||
763 | /** | |
764 | * ppc4xx_edac_check - check controller for ECC errors | |
765 | * @mci: A pointer to the EDAC memory controller instance | |
766 | * associated with the ibm,sdram-4xx-ddr2 controller being | |
767 | * checked. | |
768 | * | |
769 | * This routine is used to check and post ECC errors and is called by | |
770 | * both the EDAC polling thread and this driver's CE and UE interrupt | |
771 | * handler. | |
772 | */ | |
773 | static void | |
774 | ppc4xx_edac_check(struct mem_ctl_info *mci) | |
775 | { | |
776 | #ifdef DEBUG | |
777 | static unsigned int count; | |
778 | #endif | |
779 | struct ppc4xx_ecc_status status; | |
780 | ||
781 | ppc4xx_ecc_get_status(mci, &status); | |
782 | ||
783 | #ifdef DEBUG | |
784 | if (count++ % 30 == 0) | |
785 | ppc4xx_ecc_dump_status(mci, &status); | |
786 | #endif | |
787 | ||
788 | if (status.ecces & SDRAM_ECCES_UE) | |
789 | ppc4xx_edac_handle_ue(mci, &status); | |
790 | ||
791 | if (status.ecces & SDRAM_ECCES_CE) | |
792 | ppc4xx_edac_handle_ce(mci, &status); | |
793 | ||
794 | ppc4xx_ecc_clear_status(mci, &status); | |
795 | } | |
796 | ||
797 | /** | |
798 | * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine | |
799 | * @irq: The virtual interrupt number being serviced. | |
800 | * @dev_id: A pointer to the EDAC memory controller instance | |
801 | * associated with the interrupt being handled. | |
802 | * | |
803 | * This routine implements the interrupt handler for both correctable | |
804 | * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2 | |
805 | * controller. It simply calls through to the same routine used during | |
806 | * polling to check, report and clear the ECC status. | |
807 | * | |
808 | * Unconditionally returns IRQ_HANDLED. | |
809 | */ | |
810 | static irqreturn_t | |
811 | ppc4xx_edac_isr(int irq, void *dev_id) | |
812 | { | |
813 | struct mem_ctl_info *mci = dev_id; | |
814 | ||
815 | ppc4xx_edac_check(mci); | |
816 | ||
817 | return IRQ_HANDLED; | |
818 | } | |
819 | ||
820 | /** | |
821 | * ppc4xx_edac_get_dtype - return the controller memory width | |
822 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
823 | * currently set for the controller, from which the width | |
824 | * is derived. | |
825 | * | |
826 | * This routine returns the EDAC device type width appropriate for the | |
827 | * current controller configuration. | |
828 | * | |
829 | * TODO: This needs to be conditioned dynamically through feature | |
830 | * flags or some such when other controller variants are supported as | |
831 | * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the | |
832 | * 16- and 64-bit field definition/value/enumeration (b1) overloaded | |
833 | * among them. | |
834 | * | |
835 | * Returns a device type width enumeration. | |
836 | */ | |
9b3c6e85 | 837 | static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1) |
dba7a77c GE |
838 | { |
839 | switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) { | |
840 | case SDRAM_MCOPT1_WDTH_16: | |
841 | return DEV_X2; | |
842 | case SDRAM_MCOPT1_WDTH_32: | |
843 | return DEV_X4; | |
844 | default: | |
845 | return DEV_UNKNOWN; | |
846 | } | |
847 | } | |
848 | ||
849 | /** | |
850 | * ppc4xx_edac_get_mtype - return controller memory type | |
851 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
852 | * currently set for the controller, from which the memory type | |
853 | * is derived. | |
854 | * | |
855 | * This routine returns the EDAC memory type appropriate for the | |
856 | * current controller configuration. | |
857 | * | |
858 | * Returns a memory type enumeration. | |
859 | */ | |
9b3c6e85 | 860 | static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1) |
dba7a77c GE |
861 | { |
862 | bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN); | |
863 | ||
864 | switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) { | |
865 | case SDRAM_MCOPT1_DDR2_TYPE: | |
866 | return rden ? MEM_RDDR2 : MEM_DDR2; | |
867 | case SDRAM_MCOPT1_DDR1_TYPE: | |
868 | return rden ? MEM_RDDR : MEM_DDR; | |
869 | default: | |
870 | return MEM_UNKNOWN; | |
871 | } | |
872 | } | |
873 | ||
874 | /** | |
b595076a | 875 | * ppc4xx_edac_init_csrows - initialize driver instance rows |
dba7a77c GE |
876 | * @mci: A pointer to the EDAC memory controller instance |
877 | * associated with the ibm,sdram-4xx-ddr2 controller for which | |
878 | * the csrows (i.e. banks/ranks) are being initialized. | |
879 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
880 | * currently set for the controller, from which bank width | |
881 | * and memory typ information is derived. | |
882 | * | |
b595076a | 883 | * This routine initializes the virtual "chip select rows" associated |
dba7a77c GE |
884 | * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2 |
885 | * controller bank/rank is mapped to a row. | |
886 | * | |
887 | * Returns 0 if OK; otherwise, -EINVAL if the memory bank size | |
888 | * configuration cannot be determined. | |
889 | */ | |
9b3c6e85 | 890 | static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1) |
dba7a77c GE |
891 | { |
892 | const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
893 | int status = 0; | |
894 | enum mem_type mtype; | |
895 | enum dev_type dtype; | |
896 | enum edac_type edac_mode; | |
084a4fcc | 897 | int row, j; |
a895bf8b | 898 | u32 mbxcf, size, nr_pages; |
dba7a77c GE |
899 | |
900 | /* Establish the memory type and width */ | |
901 | ||
902 | mtype = ppc4xx_edac_get_mtype(mcopt1); | |
903 | dtype = ppc4xx_edac_get_dtype(mcopt1); | |
904 | ||
905 | /* Establish EDAC mode */ | |
906 | ||
907 | if (mci->edac_cap & EDAC_FLAG_SECDED) | |
908 | edac_mode = EDAC_SECDED; | |
909 | else if (mci->edac_cap & EDAC_FLAG_EC) | |
910 | edac_mode = EDAC_EC; | |
911 | else | |
912 | edac_mode = EDAC_NONE; | |
913 | ||
914 | /* | |
915 | * Initialize each chip select row structure which correspond | |
916 | * 1:1 with a controller bank/rank. | |
917 | */ | |
918 | ||
919 | for (row = 0; row < mci->nr_csrows; row++) { | |
5c16179b | 920 | struct csrow_info *csi = mci->csrows[row]; |
dba7a77c GE |
921 | |
922 | /* | |
923 | * Get the configuration settings for this | |
924 | * row/bank/rank and skip disabled banks. | |
925 | */ | |
926 | ||
927 | mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row)); | |
928 | ||
929 | if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE) | |
930 | continue; | |
931 | ||
932 | /* Map the bank configuration size setting to pages. */ | |
933 | ||
934 | size = mbxcf & SDRAM_MBCF_SZ_MASK; | |
935 | ||
936 | switch (size) { | |
937 | case SDRAM_MBCF_SZ_4MB: | |
938 | case SDRAM_MBCF_SZ_8MB: | |
939 | case SDRAM_MBCF_SZ_16MB: | |
940 | case SDRAM_MBCF_SZ_32MB: | |
941 | case SDRAM_MBCF_SZ_64MB: | |
942 | case SDRAM_MBCF_SZ_128MB: | |
943 | case SDRAM_MBCF_SZ_256MB: | |
944 | case SDRAM_MBCF_SZ_512MB: | |
945 | case SDRAM_MBCF_SZ_1GB: | |
946 | case SDRAM_MBCF_SZ_2GB: | |
947 | case SDRAM_MBCF_SZ_4GB: | |
948 | case SDRAM_MBCF_SZ_8GB: | |
a895bf8b | 949 | nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size); |
dba7a77c GE |
950 | break; |
951 | default: | |
952 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
953 | "Unrecognized memory bank %d " | |
954 | "size 0x%08x\n", | |
955 | row, SDRAM_MBCF_SZ_DECODE(size)); | |
956 | status = -EINVAL; | |
957 | goto done; | |
958 | } | |
959 | ||
dba7a77c GE |
960 | /* |
961 | * It's unclear exactly what grain should be set to | |
962 | * here. The SDRAM_ECCES register allows resolution of | |
963 | * an error down to a nibble which would potentially | |
964 | * argue for a grain of '1' byte, even though we only | |
965 | * know the associated address for uncorrectable | |
966 | * errors. This value is not used at present for | |
967 | * anything other than error reporting so getting it | |
968 | * wrong should be of little consequence. Other | |
969 | * possible values would be the PLB width (16), the | |
970 | * page size (PAGE_SIZE) or the memory width (2 or 4). | |
971 | */ | |
084a4fcc | 972 | for (j = 0; j < csi->nr_channels; j++) { |
2d34056d | 973 | struct dimm_info *dimm = csi->channels[j]->dimm; |
dba7a77c | 974 | |
a895bf8b | 975 | dimm->nr_pages = nr_pages / csi->nr_channels; |
084a4fcc | 976 | dimm->grain = 1; |
dba7a77c | 977 | |
084a4fcc MCC |
978 | dimm->mtype = mtype; |
979 | dimm->dtype = dtype; | |
dba7a77c | 980 | |
084a4fcc | 981 | dimm->edac_mode = edac_mode; |
084a4fcc | 982 | } |
dba7a77c GE |
983 | } |
984 | ||
985 | done: | |
986 | return status; | |
987 | } | |
988 | ||
989 | /** | |
b595076a | 990 | * ppc4xx_edac_mc_init - initialize driver instance |
dba7a77c GE |
991 | * @mci: A pointer to the EDAC memory controller instance being |
992 | * initialized. | |
993 | * @op: A pointer to the OpenFirmware device tree node associated | |
994 | * with the controller this EDAC instance is bound to. | |
dba7a77c GE |
995 | * @dcr_host: A pointer to the DCR data containing the DCR mapping |
996 | * for this controller instance. | |
997 | * @mcopt1: The 32-bit Memory Controller Option 1 register value | |
998 | * currently set for the controller, from which ECC capabilities | |
999 | * and scrub mode are derived. | |
1000 | * | |
1001 | * This routine performs initialization of the EDAC memory controller | |
1002 | * instance and related driver-private data associated with the | |
1003 | * ibm,sdram-4xx-ddr2 memory controller the instance is bound to. | |
1004 | * | |
1005 | * Returns 0 if OK; otherwise, < 0 on error. | |
1006 | */ | |
9b3c6e85 GKH |
1007 | static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci, |
1008 | struct platform_device *op, | |
1009 | const dcr_host_t *dcr_host, u32 mcopt1) | |
dba7a77c GE |
1010 | { |
1011 | int status = 0; | |
1012 | const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); | |
1013 | struct ppc4xx_edac_pdata *pdata = NULL; | |
a26f95fe | 1014 | const struct device_node *np = op->dev.of_node; |
dba7a77c | 1015 | |
b1608d69 | 1016 | if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL) |
dba7a77c GE |
1017 | return -EINVAL; |
1018 | ||
1019 | /* Initial driver pointers and private data */ | |
1020 | ||
fd687502 | 1021 | mci->pdev = &op->dev; |
dba7a77c | 1022 | |
fd687502 | 1023 | dev_set_drvdata(mci->pdev, mci); |
dba7a77c GE |
1024 | |
1025 | pdata = mci->pvt_info; | |
1026 | ||
1027 | pdata->dcr_host = *dcr_host; | |
dba7a77c GE |
1028 | |
1029 | /* Initialize controller capabilities and configuration */ | |
1030 | ||
1031 | mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR | | |
1032 | MEM_FLAG_DDR2 | MEM_FLAG_RDDR2); | |
1033 | ||
1034 | mci->edac_ctl_cap = (EDAC_FLAG_NONE | | |
1035 | EDAC_FLAG_EC | | |
1036 | EDAC_FLAG_SECDED); | |
1037 | ||
1038 | mci->scrub_cap = SCRUB_NONE; | |
1039 | mci->scrub_mode = SCRUB_NONE; | |
1040 | ||
1041 | /* | |
1042 | * Update the actual capabilites based on the MCOPT1[MCHK] | |
1043 | * settings. Scrubbing is only useful if reporting is enabled. | |
1044 | */ | |
1045 | ||
1046 | switch (memcheck) { | |
1047 | case SDRAM_MCOPT1_MCHK_CHK: | |
1048 | mci->edac_cap = EDAC_FLAG_EC; | |
1049 | break; | |
1050 | case SDRAM_MCOPT1_MCHK_CHK_REP: | |
1051 | mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED); | |
1052 | mci->scrub_mode = SCRUB_SW_SRC; | |
1053 | break; | |
1054 | default: | |
1055 | mci->edac_cap = EDAC_FLAG_NONE; | |
1056 | break; | |
1057 | } | |
1058 | ||
1059 | /* Initialize strings */ | |
1060 | ||
1061 | mci->mod_name = PPC4XX_EDAC_MODULE_NAME; | |
e0e04274 | 1062 | mci->ctl_name = ppc4xx_edac_match->compatible; |
dba7a77c GE |
1063 | mci->dev_name = np->full_name; |
1064 | ||
1065 | /* Initialize callbacks */ | |
1066 | ||
1067 | mci->edac_check = ppc4xx_edac_check; | |
1068 | mci->ctl_page_to_phys = NULL; | |
1069 | ||
1070 | /* Initialize chip select rows */ | |
1071 | ||
1072 | status = ppc4xx_edac_init_csrows(mci, mcopt1); | |
1073 | ||
1074 | if (status) | |
1075 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1076 | "Failed to initialize rows!\n"); | |
1077 | ||
1078 | return status; | |
1079 | } | |
1080 | ||
1081 | /** | |
1082 | * ppc4xx_edac_register_irq - setup and register controller interrupts | |
1083 | * @op: A pointer to the OpenFirmware device tree node associated | |
1084 | * with the controller this EDAC instance is bound to. | |
1085 | * @mci: A pointer to the EDAC memory controller instance | |
1086 | * associated with the ibm,sdram-4xx-ddr2 controller for which | |
1087 | * interrupts are being registered. | |
1088 | * | |
1089 | * This routine parses the correctable (CE) and uncorrectable error (UE) | |
1090 | * interrupts from the device tree node and maps and assigns them to | |
1091 | * the associated EDAC memory controller instance. | |
1092 | * | |
1093 | * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be | |
1094 | * mapped and assigned. | |
1095 | */ | |
9b3c6e85 GKH |
1096 | static int ppc4xx_edac_register_irq(struct platform_device *op, |
1097 | struct mem_ctl_info *mci) | |
dba7a77c GE |
1098 | { |
1099 | int status = 0; | |
1100 | int ded_irq, sec_irq; | |
1101 | struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
a26f95fe | 1102 | struct device_node *np = op->dev.of_node; |
dba7a77c GE |
1103 | |
1104 | ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX); | |
1105 | sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX); | |
1106 | ||
37209572 | 1107 | if (!ded_irq || !sec_irq) { |
dba7a77c GE |
1108 | ppc4xx_edac_mc_printk(KERN_ERR, mci, |
1109 | "Unable to map interrupts.\n"); | |
1110 | status = -ENODEV; | |
1111 | goto fail; | |
1112 | } | |
1113 | ||
1114 | status = request_irq(ded_irq, | |
1115 | ppc4xx_edac_isr, | |
5c43cbdf | 1116 | 0, |
dba7a77c GE |
1117 | "[EDAC] MC ECCDED", |
1118 | mci); | |
1119 | ||
1120 | if (status < 0) { | |
1121 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1122 | "Unable to request irq %d for ECC DED", | |
1123 | ded_irq); | |
1124 | status = -ENODEV; | |
1125 | goto fail1; | |
1126 | } | |
1127 | ||
1128 | status = request_irq(sec_irq, | |
1129 | ppc4xx_edac_isr, | |
5c43cbdf | 1130 | 0, |
dba7a77c GE |
1131 | "[EDAC] MC ECCSEC", |
1132 | mci); | |
1133 | ||
1134 | if (status < 0) { | |
1135 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1136 | "Unable to request irq %d for ECC SEC", | |
1137 | sec_irq); | |
1138 | status = -ENODEV; | |
1139 | goto fail2; | |
1140 | } | |
1141 | ||
1142 | ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq); | |
1143 | ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq); | |
1144 | ||
1145 | pdata->irqs.ded = ded_irq; | |
1146 | pdata->irqs.sec = sec_irq; | |
1147 | ||
1148 | return 0; | |
1149 | ||
1150 | fail2: | |
1151 | free_irq(sec_irq, mci); | |
1152 | ||
1153 | fail1: | |
1154 | free_irq(ded_irq, mci); | |
1155 | ||
1156 | fail: | |
1157 | return status; | |
1158 | } | |
1159 | ||
1160 | /** | |
1161 | * ppc4xx_edac_map_dcrs - locate and map controller registers | |
1162 | * @np: A pointer to the device tree node containing the DCR | |
1163 | * resources to map. | |
1164 | * @dcr_host: A pointer to the DCR data to populate with the | |
1165 | * DCR mapping. | |
1166 | * | |
1167 | * This routine attempts to locate in the device tree and map the DCR | |
1168 | * register resources associated with the controller's indirect DCR | |
1169 | * address and data windows. | |
1170 | * | |
1171 | * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on | |
1172 | * error. | |
1173 | */ | |
9b3c6e85 GKH |
1174 | static int ppc4xx_edac_map_dcrs(const struct device_node *np, |
1175 | dcr_host_t *dcr_host) | |
dba7a77c GE |
1176 | { |
1177 | unsigned int dcr_base, dcr_len; | |
1178 | ||
1179 | if (np == NULL || dcr_host == NULL) | |
1180 | return -EINVAL; | |
1181 | ||
1182 | /* Get the DCR resource extent and sanity check the values. */ | |
1183 | ||
1184 | dcr_base = dcr_resource_start(np, 0); | |
1185 | dcr_len = dcr_resource_len(np, 0); | |
1186 | ||
1187 | if (dcr_base == 0 || dcr_len == 0) { | |
1188 | ppc4xx_edac_printk(KERN_ERR, | |
1189 | "Failed to obtain DCR property.\n"); | |
1190 | return -ENODEV; | |
1191 | } | |
1192 | ||
1193 | if (dcr_len != SDRAM_DCR_RESOURCE_LEN) { | |
1194 | ppc4xx_edac_printk(KERN_ERR, | |
1195 | "Unexpected DCR length %d, expected %d.\n", | |
1196 | dcr_len, SDRAM_DCR_RESOURCE_LEN); | |
1197 | return -ENODEV; | |
1198 | } | |
1199 | ||
1200 | /* Attempt to map the DCR extent. */ | |
1201 | ||
1202 | *dcr_host = dcr_map(np, dcr_base, dcr_len); | |
1203 | ||
1204 | if (!DCR_MAP_OK(*dcr_host)) { | |
1205 | ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n"); | |
1206 | return -ENODEV; | |
1207 | } | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | /** | |
1213 | * ppc4xx_edac_probe - check controller and bind driver | |
1214 | * @op: A pointer to the OpenFirmware device tree node associated | |
1215 | * with the controller being probed for driver binding. | |
dba7a77c GE |
1216 | * |
1217 | * This routine probes a specific ibm,sdram-4xx-ddr2 controller | |
1218 | * instance for binding with the driver. | |
1219 | * | |
1220 | * Returns 0 if the controller instance was successfully bound to the | |
1221 | * driver; otherwise, < 0 on error. | |
1222 | */ | |
9b3c6e85 | 1223 | static int ppc4xx_edac_probe(struct platform_device *op) |
dba7a77c GE |
1224 | { |
1225 | int status = 0; | |
1226 | u32 mcopt1, memcheck; | |
1227 | dcr_host_t dcr_host; | |
a26f95fe | 1228 | const struct device_node *np = op->dev.of_node; |
dba7a77c | 1229 | struct mem_ctl_info *mci = NULL; |
94d93374 | 1230 | struct edac_mc_layer layers[2]; |
dba7a77c GE |
1231 | static int ppc4xx_edac_instance; |
1232 | ||
1233 | /* | |
1234 | * At this point, we only support the controller realized on | |
1235 | * the AMCC PPC 405EX[r]. Reject anything else. | |
1236 | */ | |
1237 | ||
1238 | if (!of_device_is_compatible(np, "ibm,sdram-405ex") && | |
1239 | !of_device_is_compatible(np, "ibm,sdram-405exr")) { | |
1240 | ppc4xx_edac_printk(KERN_NOTICE, | |
1241 | "Only the PPC405EX[r] is supported.\n"); | |
1242 | return -ENODEV; | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * Next, get the DCR property and attempt to map it so that we | |
1247 | * can probe the controller. | |
1248 | */ | |
1249 | ||
1250 | status = ppc4xx_edac_map_dcrs(np, &dcr_host); | |
1251 | ||
1252 | if (status) | |
1253 | return status; | |
1254 | ||
1255 | /* | |
1256 | * First determine whether ECC is enabled at all. If not, | |
1257 | * there is no useful checking or monitoring that can be done | |
1258 | * for this controller. | |
1259 | */ | |
1260 | ||
1261 | mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1); | |
1262 | memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); | |
1263 | ||
1264 | if (memcheck == SDRAM_MCOPT1_MCHK_NON) { | |
2efdda4a RH |
1265 | ppc4xx_edac_printk(KERN_INFO, "%pOF: No ECC memory detected or " |
1266 | "ECC is disabled.\n", np); | |
dba7a77c GE |
1267 | status = -ENODEV; |
1268 | goto done; | |
1269 | } | |
1270 | ||
1271 | /* | |
1272 | * At this point, we know ECC is enabled, allocate an EDAC | |
1273 | * controller instance and perform the appropriate | |
1274 | * initialization. | |
1275 | */ | |
94d93374 MCC |
1276 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
1277 | layers[0].size = ppc4xx_edac_nr_csrows; | |
1278 | layers[0].is_virt_csrow = true; | |
1279 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
1280 | layers[1].size = ppc4xx_edac_nr_chans; | |
1281 | layers[1].is_virt_csrow = false; | |
ca0907b9 | 1282 | mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers, |
94d93374 | 1283 | sizeof(struct ppc4xx_edac_pdata)); |
dba7a77c | 1284 | if (mci == NULL) { |
2efdda4a | 1285 | ppc4xx_edac_printk(KERN_ERR, "%pOF: " |
dba7a77c | 1286 | "Failed to allocate EDAC MC instance!\n", |
2efdda4a | 1287 | np); |
dba7a77c GE |
1288 | status = -ENOMEM; |
1289 | goto done; | |
1290 | } | |
1291 | ||
00006124 | 1292 | status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1); |
dba7a77c GE |
1293 | |
1294 | if (status) { | |
1295 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1296 | "Failed to initialize instance!\n"); | |
1297 | goto fail; | |
1298 | } | |
1299 | ||
1300 | /* | |
1301 | * We have a valid, initialized EDAC instance bound to the | |
1302 | * controller. Attempt to register it with the EDAC subsystem | |
1303 | * and, if necessary, register interrupts. | |
1304 | */ | |
1305 | ||
1306 | if (edac_mc_add_mc(mci)) { | |
1307 | ppc4xx_edac_mc_printk(KERN_ERR, mci, | |
1308 | "Failed to add instance!\n"); | |
1309 | status = -ENODEV; | |
1310 | goto fail; | |
1311 | } | |
1312 | ||
1313 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1314 | status = ppc4xx_edac_register_irq(op, mci); | |
1315 | ||
1316 | if (status) | |
1317 | goto fail1; | |
1318 | } | |
1319 | ||
1320 | ppc4xx_edac_instance++; | |
1321 | ||
1322 | return 0; | |
1323 | ||
1324 | fail1: | |
fd687502 | 1325 | edac_mc_del_mc(mci->pdev); |
dba7a77c GE |
1326 | |
1327 | fail: | |
1328 | edac_mc_free(mci); | |
1329 | ||
1330 | done: | |
1331 | return status; | |
1332 | } | |
1333 | ||
1334 | /** | |
1335 | * ppc4xx_edac_remove - unbind driver from controller | |
1336 | * @op: A pointer to the OpenFirmware device tree node associated | |
1337 | * with the controller this EDAC instance is to be unbound/removed | |
1338 | * from. | |
1339 | * | |
1340 | * This routine unbinds the EDAC memory controller instance associated | |
1341 | * with the specified ibm,sdram-4xx-ddr2 controller described by the | |
1342 | * OpenFirmware device tree node passed as a parameter. | |
1343 | * | |
1344 | * Unconditionally returns 0. | |
1345 | */ | |
1346 | static int | |
2dc11581 | 1347 | ppc4xx_edac_remove(struct platform_device *op) |
dba7a77c GE |
1348 | { |
1349 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
1350 | struct ppc4xx_edac_pdata *pdata = mci->pvt_info; | |
1351 | ||
1352 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1353 | free_irq(pdata->irqs.sec, mci); | |
1354 | free_irq(pdata->irqs.ded, mci); | |
1355 | } | |
1356 | ||
1357 | dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN); | |
1358 | ||
fd687502 | 1359 | edac_mc_del_mc(mci->pdev); |
dba7a77c GE |
1360 | edac_mc_free(mci); |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | /** | |
1366 | * ppc4xx_edac_opstate_init - initialize EDAC reporting method | |
1367 | * | |
1368 | * This routine ensures that the EDAC memory controller reporting | |
1369 | * method is mapped to a sane value as the EDAC core defines the value | |
1370 | * to EDAC_OPSTATE_INVAL by default. We don't call the global | |
1371 | * opstate_init as that defaults to polling and we want interrupt as | |
1372 | * the default. | |
1373 | */ | |
1374 | static inline void __init | |
1375 | ppc4xx_edac_opstate_init(void) | |
1376 | { | |
1377 | switch (edac_op_state) { | |
1378 | case EDAC_OPSTATE_POLL: | |
1379 | case EDAC_OPSTATE_INT: | |
1380 | break; | |
1381 | default: | |
1382 | edac_op_state = EDAC_OPSTATE_INT; | |
1383 | break; | |
1384 | } | |
1385 | ||
1386 | ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n", | |
1387 | ((edac_op_state == EDAC_OPSTATE_POLL) ? | |
1388 | EDAC_OPSTATE_POLL_STR : | |
1389 | ((edac_op_state == EDAC_OPSTATE_INT) ? | |
1390 | EDAC_OPSTATE_INT_STR : | |
1391 | EDAC_OPSTATE_UNKNOWN_STR))); | |
1392 | } | |
1393 | ||
1394 | /** | |
1395 | * ppc4xx_edac_init - driver/module insertion entry point | |
1396 | * | |
1397 | * This routine is the driver/module insertion entry point. It | |
1398 | * initializes the EDAC memory controller reporting state and | |
1399 | * registers the driver as an OpenFirmware device tree platform | |
1400 | * driver. | |
1401 | */ | |
1402 | static int __init | |
1403 | ppc4xx_edac_init(void) | |
1404 | { | |
1405 | ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n"); | |
1406 | ||
1407 | ppc4xx_edac_opstate_init(); | |
1408 | ||
00006124 | 1409 | return platform_driver_register(&ppc4xx_edac_driver); |
dba7a77c GE |
1410 | } |
1411 | ||
1412 | /** | |
1413 | * ppc4xx_edac_exit - driver/module removal entry point | |
1414 | * | |
1415 | * This routine is the driver/module removal entry point. It | |
1416 | * unregisters the driver as an OpenFirmware device tree platform | |
1417 | * driver. | |
1418 | */ | |
1419 | static void __exit | |
1420 | ppc4xx_edac_exit(void) | |
1421 | { | |
00006124 | 1422 | platform_driver_unregister(&ppc4xx_edac_driver); |
dba7a77c GE |
1423 | } |
1424 | ||
1425 | module_init(ppc4xx_edac_init); | |
1426 | module_exit(ppc4xx_edac_exit); | |
1427 | ||
1428 | MODULE_LICENSE("GPL v2"); | |
1429 | MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>"); | |
1430 | MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller"); | |
1431 | module_param(edac_op_state, int, 0444); | |
1432 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: " | |
1433 | "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR); |