Commit | Line | Data |
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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b70ef010 | 2 | #include <linux/module.h> |
888ab8e6 BP |
3 | #include <linux/slab.h> |
4 | ||
f3c0891c BP |
5 | #include <asm/cpu.h> |
6 | ||
47ca08a4 | 7 | #include "mce_amd.h" |
b52401ce | 8 | |
86e9f9d6 | 9 | static struct amd_decoder_ops fam_ops; |
888ab8e6 | 10 | |
2be64bfa | 11 | static u8 xec_mask = 0xf; |
5ce88f6e | 12 | |
5c332202 | 13 | static void (*decode_dram_ecc)(int node_id, struct mce *m); |
549d042d | 14 | |
b0b07a2b | 15 | void amd_register_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d | 16 | { |
5c332202 | 17 | decode_dram_ecc = f; |
549d042d BP |
18 | } |
19 | EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); | |
20 | ||
b0b07a2b | 21 | void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d | 22 | { |
5c332202 YG |
23 | if (decode_dram_ecc) { |
24 | WARN_ON(decode_dram_ecc != f); | |
549d042d | 25 | |
5c332202 | 26 | decode_dram_ecc = NULL; |
549d042d BP |
27 | } |
28 | } | |
29 | EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); | |
30 | ||
b52401ce DT |
31 | /* |
32 | * string representation for the different MCA reported error types, see F3x48 | |
33 | * or MSR0000_0411. | |
34 | */ | |
6337583d BP |
35 | |
36 | /* transaction type */ | |
0f08669e | 37 | static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; |
b52401ce | 38 | |
6337583d | 39 | /* cache level */ |
0f08669e | 40 | static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; |
b52401ce | 41 | |
6337583d | 42 | /* memory transaction type */ |
0f08669e | 43 | static const char * const rrrr_msgs[] = { |
6337583d | 44 | "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" |
b52401ce DT |
45 | }; |
46 | ||
6337583d | 47 | /* participating processor */ |
ebe2aea8 | 48 | const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; |
b70ef010 | 49 | EXPORT_SYMBOL_GPL(pp_msgs); |
b52401ce | 50 | |
6337583d | 51 | /* request timeout */ |
0f08669e | 52 | static const char * const to_msgs[] = { "no timeout", "timed out" }; |
b52401ce | 53 | |
6337583d | 54 | /* memory or i/o */ |
0f08669e | 55 | static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; |
b52401ce | 56 | |
980eec8b | 57 | /* internal error type */ |
0f08669e | 58 | static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" }; |
980eec8b | 59 | |
f05c41a9 | 60 | static const char * const f15h_mc1_mce_desc[] = { |
86039cd4 BP |
61 | "UC during a demand linefill from L2", |
62 | "Parity error during data load from IC", | |
63 | "Parity error for IC valid bit", | |
64 | "Main tag parity error", | |
65 | "Parity error in prediction queue", | |
66 | "PFB data/address parity error", | |
67 | "Parity error in the branch status reg", | |
68 | "PFB promotion address error", | |
69 | "Tag error during probe/victimization", | |
70 | "Parity error for IC probe tag valid bit", | |
71 | "PFB non-cacheable bit parity error", | |
72 | "PFB valid bit parity error", /* xec = 0xd */ | |
6c1173a6 | 73 | "Microcode Patch Buffer", /* xec = 010 */ |
86039cd4 BP |
74 | "uop queue", |
75 | "insn buffer", | |
76 | "predecode buffer", | |
eba4bfb3 AG |
77 | "fetch address FIFO", |
78 | "dispatch uop queue" | |
86039cd4 BP |
79 | }; |
80 | ||
f05c41a9 | 81 | static const char * const f15h_mc2_mce_desc[] = { |
70fdb494 BP |
82 | "Fill ECC error on data fills", /* xec = 0x4 */ |
83 | "Fill parity error on insn fills", | |
84 | "Prefetcher request FIFO parity error", | |
85 | "PRQ address parity error", | |
86 | "PRQ data parity error", | |
87 | "WCC Tag ECC error", | |
88 | "WCC Data ECC error", | |
89 | "WCB Data parity error", | |
b64a99c1 | 90 | "VB Data ECC or parity error", |
70fdb494 BP |
91 | "L2 Tag ECC error", /* xec = 0x10 */ |
92 | "Hard L2 Tag ECC error", | |
93 | "Multiple hits on L2 tag", | |
94 | "XAB parity error", | |
95 | "PRB address parity error" | |
96 | }; | |
97 | ||
f05c41a9 | 98 | static const char * const mc4_mce_desc[] = { |
68782673 BP |
99 | "DRAM ECC error detected on the NB", |
100 | "CRC error detected on HT link", | |
101 | "Link-defined sync error packets detected on HT link", | |
102 | "HT Master abort", | |
103 | "HT Target abort", | |
104 | "Invalid GART PTE entry during GART table walk", | |
105 | "Unsupported atomic RMW received from an IO link", | |
106 | "Watchdog timeout due to lack of progress", | |
107 | "DRAM ECC error detected on the NB", | |
108 | "SVM DMA Exclusion Vector error", | |
109 | "HT data error detected on link", | |
110 | "Protocol error (link, L3, probe filter)", | |
111 | "NB internal arrays parity error", | |
112 | "DRAM addr/ctl signals parity error", | |
113 | "IO link transmission error", | |
114 | "L3 data cache ECC error", /* xec = 0x1c */ | |
115 | "L3 cache tag error", | |
116 | "L3 LRU parity bits error", | |
117 | "ECC Error in the Probe Filter directory" | |
118 | }; | |
119 | ||
f05c41a9 | 120 | static const char * const mc5_mce_desc[] = { |
8259a7e5 BP |
121 | "CPU Watchdog timer expire", |
122 | "Wakeup array dest tag", | |
123 | "AG payload array", | |
124 | "EX payload array", | |
125 | "IDRF array", | |
126 | "Retire dispatch queue", | |
127 | "Mapper checkpoint array", | |
128 | "Physical register file EX0 port", | |
129 | "Physical register file EX1 port", | |
130 | "Physical register file AG0 port", | |
131 | "Physical register file AG1 port", | |
132 | "Flag register file", | |
aad19e51 AG |
133 | "DE error occurred", |
134 | "Retire status queue" | |
8259a7e5 BP |
135 | }; |
136 | ||
bc4febe9 AG |
137 | static const char * const mc6_mce_desc[] = { |
138 | "Hardware Assertion", | |
139 | "Free List", | |
140 | "Physical Register File", | |
141 | "Retire Queue", | |
142 | "Scheduler table", | |
143 | "Status Register File", | |
144 | }; | |
145 | ||
be0aec23 | 146 | /* Scalable MCA error strings */ |
856095b1 | 147 | static const char * const smca_ls_mce_desc[] = { |
e03447ee YG |
148 | "Load queue parity error", |
149 | "Store queue parity error", | |
150 | "Miss address buffer payload parity error", | |
151 | "Level 1 TLB parity error", | |
8a5dd2cd | 152 | "DC Tag error type 5", |
e03447ee YG |
153 | "DC Tag error type 6", |
154 | "DC Tag error type 1", | |
be0aec23 AG |
155 | "Internal error type 1", |
156 | "Internal error type 2", | |
e03447ee YG |
157 | "System Read Data Error Thread 0", |
158 | "System Read Data Error Thread 1", | |
159 | "DC Tag error type 2", | |
160 | "DC Data error type 1 and poison consumption", | |
161 | "DC Data error type 2", | |
162 | "DC Data error type 3", | |
163 | "DC Tag error type 4", | |
164 | "Level 2 TLB parity error", | |
be0aec23 | 165 | "PDC parity error", |
e03447ee YG |
166 | "DC Tag error type 3", |
167 | "DC Tag error type 5", | |
168 | "L2 Fill Data error", | |
be0aec23 AG |
169 | }; |
170 | ||
89a76171 YG |
171 | static const char * const smca_ls2_mce_desc[] = { |
172 | "An ECC error was detected on a data cache read by a probe or victimization", | |
173 | "An ECC error or L2 poison was detected on a data cache read by a load", | |
174 | "An ECC error was detected on a data cache read-modify-write by a store", | |
175 | "An ECC error or poison bit mismatch was detected on a tag read by a probe or victimization", | |
176 | "An ECC error or poison bit mismatch was detected on a tag read by a load", | |
177 | "An ECC error or poison bit mismatch was detected on a tag read by a store", | |
178 | "An ECC error was detected on an EMEM read by a load", | |
179 | "An ECC error was detected on an EMEM read-modify-write by a store", | |
180 | "A parity error was detected in an L1 TLB entry by any access", | |
181 | "A parity error was detected in an L2 TLB entry by any access", | |
182 | "A parity error was detected in a PWC entry by any access", | |
183 | "A parity error was detected in an STQ entry by any access", | |
184 | "A parity error was detected in an LDQ entry by any access", | |
185 | "A parity error was detected in a MAB entry by any access", | |
186 | "A parity error was detected in an SCB entry state field by any access", | |
187 | "A parity error was detected in an SCB entry address field by any access", | |
188 | "A parity error was detected in an SCB entry data field by any access", | |
189 | "A parity error was detected in a WCB entry by any access", | |
190 | "A poisoned line was detected in an SCB entry by any access", | |
191 | "A SystemReadDataError error was reported on read data returned from L2 for a load", | |
192 | "A SystemReadDataError error was reported on read data returned from L2 for an SCB store", | |
193 | "A SystemReadDataError error was reported on read data returned from L2 for a WCB store", | |
194 | "A hardware assertion error was reported", | |
195 | "A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access", | |
196 | }; | |
197 | ||
856095b1 | 198 | static const char * const smca_if_mce_desc[] = { |
e03447ee YG |
199 | "Op Cache Microtag Probe Port Parity Error", |
200 | "IC Microtag or Full Tag Multi-hit Error", | |
201 | "IC Full Tag Parity Error", | |
202 | "IC Data Array Parity Error", | |
203 | "Decoupling Queue PhysAddr Parity Error", | |
204 | "L0 ITLB Parity Error", | |
205 | "L1 ITLB Parity Error", | |
206 | "L2 ITLB Parity Error", | |
207 | "BPQ Thread 0 Snoop Parity Error", | |
208 | "BPQ Thread 1 Snoop Parity Error", | |
209 | "L1 BTB Multi-Match Error", | |
210 | "L2 BTB Multi-Match Error", | |
211 | "L2 Cache Response Poison Error", | |
212 | "System Read Data Error", | |
dc7a8476 YG |
213 | "Hardware Assertion Error", |
214 | "L1-TLB Multi-Hit", | |
215 | "L2-TLB Multi-Hit", | |
216 | "BSR Parity Error", | |
217 | "CT MCE", | |
be0aec23 AG |
218 | }; |
219 | ||
856095b1 | 220 | static const char * const smca_l2_mce_desc[] = { |
e03447ee YG |
221 | "L2M Tag Multiple-Way-Hit error", |
222 | "L2M Tag or State Array ECC Error", | |
223 | "L2M Data Array ECC Error", | |
224 | "Hardware Assert Error", | |
be0aec23 AG |
225 | }; |
226 | ||
856095b1 | 227 | static const char * const smca_de_mce_desc[] = { |
e03447ee YG |
228 | "Micro-op cache tag parity error", |
229 | "Micro-op cache data parity error", | |
230 | "Instruction buffer parity error", | |
231 | "Micro-op queue parity error", | |
232 | "Instruction dispatch queue parity error", | |
233 | "Fetch address FIFO parity error", | |
234 | "Patch RAM data parity error", | |
235 | "Patch RAM sequencer parity error", | |
dc7a8476 YG |
236 | "Micro-op buffer parity error", |
237 | "Hardware Assertion MCA Error", | |
be0aec23 AG |
238 | }; |
239 | ||
856095b1 | 240 | static const char * const smca_ex_mce_desc[] = { |
e03447ee YG |
241 | "Watchdog Timeout error", |
242 | "Physical register file parity error", | |
243 | "Flag register file parity error", | |
244 | "Immediate displacement register file parity error", | |
245 | "Address generator payload parity error", | |
246 | "EX payload parity error", | |
247 | "Checkpoint queue parity error", | |
248 | "Retire dispatch queue parity error", | |
c019b951 YG |
249 | "Retire status queue parity error", |
250 | "Scheduling queue parity error", | |
251 | "Branch buffer queue parity error", | |
8a5dd2cd | 252 | "Hardware Assertion error", |
dc7a8476 YG |
253 | "Spec Map parity error", |
254 | "Retire Map parity error", | |
be0aec23 AG |
255 | }; |
256 | ||
856095b1 | 257 | static const char * const smca_fp_mce_desc[] = { |
e03447ee YG |
258 | "Physical register file (PRF) parity error", |
259 | "Freelist (FL) parity error", | |
260 | "Schedule queue parity error", | |
be0aec23 | 261 | "NSQ parity error", |
e03447ee YG |
262 | "Retire queue (RQ) parity error", |
263 | "Status register file (SRF) parity error", | |
c019b951 | 264 | "Hardware assertion", |
be0aec23 AG |
265 | }; |
266 | ||
856095b1 | 267 | static const char * const smca_l3_mce_desc[] = { |
e03447ee YG |
268 | "Shadow Tag Macro ECC Error", |
269 | "Shadow Tag Macro Multi-way-hit Error", | |
270 | "L3M Tag ECC Error", | |
271 | "L3M Tag Multi-way-hit Error", | |
272 | "L3M Data ECC Error", | |
273 | "SDP Parity Error or SystemReadDataError from XI", | |
274 | "L3 Victim Queue Parity Error", | |
275 | "L3 Hardware Assertion", | |
be0aec23 AG |
276 | }; |
277 | ||
856095b1 | 278 | static const char * const smca_cs_mce_desc[] = { |
e03447ee YG |
279 | "Illegal Request", |
280 | "Address Violation", | |
281 | "Security Violation", | |
282 | "Illegal Response", | |
283 | "Unexpected Response", | |
284 | "Request or Probe Parity Error", | |
285 | "Read Response Parity Error", | |
286 | "Atomic Request Parity Error", | |
287 | "Probe Filter ECC Error", | |
be0aec23 AG |
288 | }; |
289 | ||
3ad7e748 YG |
290 | static const char * const smca_cs2_mce_desc[] = { |
291 | "Illegal Request", | |
292 | "Address Violation", | |
293 | "Security Violation", | |
294 | "Illegal Response", | |
295 | "Unexpected Response", | |
296 | "Request or Probe Parity Error", | |
297 | "Read Response Parity Error", | |
298 | "Atomic Request Parity Error", | |
299 | "SDP read response had no match in the CS queue", | |
300 | "Probe Filter Protocol Error", | |
301 | "Probe Filter ECC Error", | |
302 | "SDP read response had an unexpected RETRY error", | |
303 | "Counter overflow error", | |
304 | "Counter underflow error", | |
305 | }; | |
306 | ||
856095b1 | 307 | static const char * const smca_pie_mce_desc[] = { |
e03447ee YG |
308 | "Hardware Assert", |
309 | "Register security violation", | |
310 | "Link Error", | |
311 | "Poison data consumption", | |
8a5dd2cd | 312 | "A deferred error was detected in the DF" |
be0aec23 AG |
313 | }; |
314 | ||
856095b1 | 315 | static const char * const smca_umc_mce_desc[] = { |
be0aec23 | 316 | "DRAM ECC error", |
e03447ee | 317 | "Data poison error", |
be0aec23 AG |
318 | "SDP parity error", |
319 | "Advanced peripheral bus error", | |
e03447ee | 320 | "Address/Command parity error", |
be0aec23 | 321 | "Write data CRC error", |
8a5dd2cd YG |
322 | "DCQ SRAM ECC error", |
323 | "AES SRAM ECC error", | |
be0aec23 AG |
324 | }; |
325 | ||
94a311ce M |
326 | static const char * const smca_umc2_mce_desc[] = { |
327 | "DRAM ECC error", | |
328 | "Data poison error", | |
329 | "SDP parity error", | |
330 | "Reserved", | |
331 | "Address/Command parity error", | |
332 | "Write data parity error", | |
333 | "DCQ SRAM ECC error", | |
334 | "Reserved", | |
335 | "Read data parity error", | |
336 | "Rdb SRAM ECC error", | |
337 | "RdRsp SRAM ECC error", | |
338 | "LM32 MP errors", | |
339 | }; | |
340 | ||
856095b1 | 341 | static const char * const smca_pb_mce_desc[] = { |
e03447ee | 342 | "An ECC error in the Parameter Block RAM array", |
be0aec23 AG |
343 | }; |
344 | ||
856095b1 | 345 | static const char * const smca_psp_mce_desc[] = { |
e03447ee | 346 | "An ECC or parity error in a PSP RAM instance", |
be0aec23 AG |
347 | }; |
348 | ||
3ad7e748 YG |
349 | static const char * const smca_psp2_mce_desc[] = { |
350 | "High SRAM ECC or parity error", | |
351 | "Low SRAM ECC or parity error", | |
352 | "Instruction Cache Bank 0 ECC or parity error", | |
353 | "Instruction Cache Bank 1 ECC or parity error", | |
354 | "Instruction Tag Ram 0 parity error", | |
355 | "Instruction Tag Ram 1 parity error", | |
356 | "Data Cache Bank 0 ECC or parity error", | |
357 | "Data Cache Bank 1 ECC or parity error", | |
358 | "Data Cache Bank 2 ECC or parity error", | |
359 | "Data Cache Bank 3 ECC or parity error", | |
360 | "Data Tag Bank 0 parity error", | |
361 | "Data Tag Bank 1 parity error", | |
362 | "Data Tag Bank 2 parity error", | |
363 | "Data Tag Bank 3 parity error", | |
364 | "Dirty Data Ram parity error", | |
365 | "TLB Bank 0 parity error", | |
366 | "TLB Bank 1 parity error", | |
367 | "System Hub Read Buffer ECC or parity error", | |
368 | }; | |
369 | ||
856095b1 | 370 | static const char * const smca_smu_mce_desc[] = { |
e03447ee | 371 | "An ECC or parity error in an SMU RAM instance", |
be0aec23 AG |
372 | }; |
373 | ||
3ad7e748 YG |
374 | static const char * const smca_smu2_mce_desc[] = { |
375 | "High SRAM ECC or parity error", | |
376 | "Low SRAM ECC or parity error", | |
377 | "Data Cache Bank A ECC or parity error", | |
378 | "Data Cache Bank B ECC or parity error", | |
379 | "Data Tag Cache Bank A ECC or parity error", | |
380 | "Data Tag Cache Bank B ECC or parity error", | |
381 | "Instruction Cache Bank A ECC or parity error", | |
382 | "Instruction Cache Bank B ECC or parity error", | |
383 | "Instruction Tag Cache Bank A ECC or parity error", | |
384 | "Instruction Tag Cache Bank B ECC or parity error", | |
385 | "System Hub Read Buffer ECC or parity error", | |
dc7a8476 | 386 | "PHY RAM ECC error", |
3ad7e748 YG |
387 | }; |
388 | ||
cbfa447e YG |
389 | static const char * const smca_mp5_mce_desc[] = { |
390 | "High SRAM ECC or parity error", | |
391 | "Low SRAM ECC or parity error", | |
392 | "Data Cache Bank A ECC or parity error", | |
393 | "Data Cache Bank B ECC or parity error", | |
394 | "Data Tag Cache Bank A ECC or parity error", | |
395 | "Data Tag Cache Bank B ECC or parity error", | |
396 | "Instruction Cache Bank A ECC or parity error", | |
397 | "Instruction Cache Bank B ECC or parity error", | |
398 | "Instruction Tag Cache Bank A ECC or parity error", | |
399 | "Instruction Tag Cache Bank B ECC or parity error", | |
400 | }; | |
401 | ||
5176a93a YG |
402 | static const char * const smca_mpdma_mce_desc[] = { |
403 | "Main SRAM [31:0] bank ECC or parity error", | |
404 | "Main SRAM [63:32] bank ECC or parity error", | |
405 | "Main SRAM [95:64] bank ECC or parity error", | |
406 | "Main SRAM [127:96] bank ECC or parity error", | |
407 | "Data Cache Bank A ECC or parity error", | |
408 | "Data Cache Bank B ECC or parity error", | |
409 | "Data Tag Cache Bank A ECC or parity error", | |
410 | "Data Tag Cache Bank B ECC or parity error", | |
411 | "Instruction Cache Bank A ECC or parity error", | |
412 | "Instruction Cache Bank B ECC or parity error", | |
413 | "Instruction Tag Cache Bank A ECC or parity error", | |
414 | "Instruction Tag Cache Bank B ECC or parity error", | |
415 | "Data Cache Bank A ECC or parity error", | |
416 | "Data Cache Bank B ECC or parity error", | |
417 | "Data Tag Cache Bank A ECC or parity error", | |
418 | "Data Tag Cache Bank B ECC or parity error", | |
419 | "Instruction Cache Bank A ECC or parity error", | |
420 | "Instruction Cache Bank B ECC or parity error", | |
421 | "Instruction Tag Cache Bank A ECC or parity error", | |
422 | "Instruction Tag Cache Bank B ECC or parity error", | |
423 | "Data Cache Bank A ECC or parity error", | |
424 | "Data Cache Bank B ECC or parity error", | |
425 | "Data Tag Cache Bank A ECC or parity error", | |
426 | "Data Tag Cache Bank B ECC or parity error", | |
427 | "Instruction Cache Bank A ECC or parity error", | |
428 | "Instruction Cache Bank B ECC or parity error", | |
429 | "Instruction Tag Cache Bank A ECC or parity error", | |
430 | "Instruction Tag Cache Bank B ECC or parity error", | |
431 | "System Hub Read Buffer ECC or parity error", | |
432 | "MPDMA TVF DVSEC Memory ECC or parity error", | |
433 | "MPDMA TVF MMIO Mailbox0 ECC or parity error", | |
434 | "MPDMA TVF MMIO Mailbox1 ECC or parity error", | |
435 | "MPDMA TVF Doorbell Memory ECC or parity error", | |
436 | "MPDMA TVF SDP Slave Memory 0 ECC or parity error", | |
437 | "MPDMA TVF SDP Slave Memory 1 ECC or parity error", | |
438 | "MPDMA TVF SDP Slave Memory 2 ECC or parity error", | |
439 | "MPDMA TVF SDP Master Memory 0 ECC or parity error", | |
440 | "MPDMA TVF SDP Master Memory 1 ECC or parity error", | |
441 | "MPDMA TVF SDP Master Memory 2 ECC or parity error", | |
442 | "MPDMA TVF SDP Master Memory 3 ECC or parity error", | |
443 | "MPDMA TVF SDP Master Memory 4 ECC or parity error", | |
444 | "MPDMA TVF SDP Master Memory 5 ECC or parity error", | |
445 | "MPDMA TVF SDP Master Memory 6 ECC or parity error", | |
446 | "MPDMA PTE Command FIFO ECC or parity error", | |
447 | "MPDMA PTE Hub Data FIFO ECC or parity error", | |
448 | "MPDMA PTE Internal Data FIFO ECC or parity error", | |
449 | "MPDMA PTE Command Memory DMA ECC or parity error", | |
450 | "MPDMA PTE Command Memory Internal ECC or parity error", | |
451 | "MPDMA PTE DMA Completion FIFO ECC or parity error", | |
452 | "MPDMA PTE Tablewalk Completion FIFO ECC or parity error", | |
453 | "MPDMA PTE Descriptor Completion FIFO ECC or parity error", | |
454 | "MPDMA PTE ReadOnly Completion FIFO ECC or parity error", | |
455 | "MPDMA PTE DirectWrite Completion FIFO ECC or parity error", | |
456 | "SDP Watchdog Timer expired", | |
457 | }; | |
458 | ||
cbfa447e YG |
459 | static const char * const smca_nbio_mce_desc[] = { |
460 | "ECC or Parity error", | |
461 | "PCIE error", | |
462 | "SDP ErrEvent error", | |
463 | "SDP Egress Poison Error", | |
464 | "IOHC Internal Poison Error", | |
465 | }; | |
466 | ||
467 | static const char * const smca_pcie_mce_desc[] = { | |
468 | "CCIX PER Message logging", | |
469 | "CCIX Read Response with Status: Non-Data Error", | |
470 | "CCIX Write Response with Status: Non-Data Error", | |
471 | "CCIX Read Response with Status: Data Error", | |
472 | "CCIX Non-okay write response with data error", | |
473 | }; | |
474 | ||
94a311ce M |
475 | static const char * const smca_pcie2_mce_desc[] = { |
476 | "SDP Parity Error logging", | |
477 | }; | |
478 | ||
479 | static const char * const smca_xgmipcs_mce_desc[] = { | |
480 | "Data Loss Error", | |
481 | "Training Error", | |
482 | "Flow Control Acknowledge Error", | |
483 | "Rx Fifo Underflow Error", | |
484 | "Rx Fifo Overflow Error", | |
485 | "CRC Error", | |
486 | "BER Exceeded Error", | |
487 | "Tx Vcid Data Error", | |
488 | "Replay Buffer Parity Error", | |
489 | "Data Parity Error", | |
490 | "Replay Fifo Overflow Error", | |
429b2ba7 | 491 | "Replay Fifo Underflow Error", |
94a311ce M |
492 | "Elastic Fifo Overflow Error", |
493 | "Deskew Error", | |
494 | "Flow Control CRC Error", | |
495 | "Data Startup Limit Error", | |
496 | "FC Init Timeout Error", | |
497 | "Recovery Timeout Error", | |
498 | "Ready Serial Timeout Error", | |
499 | "Ready Serial Attempt Error", | |
500 | "Recovery Attempt Error", | |
501 | "Recovery Relock Attempt Error", | |
502 | "Replay Attempt Error", | |
503 | "Sync Header Error", | |
504 | "Tx Replay Timeout Error", | |
505 | "Rx Replay Timeout Error", | |
506 | "LinkSub Tx Timeout Error", | |
507 | "LinkSub Rx Timeout Error", | |
5176a93a | 508 | "Rx CMD Packet Error", |
94a311ce M |
509 | }; |
510 | ||
511 | static const char * const smca_xgmiphy_mce_desc[] = { | |
512 | "RAM ECC Error", | |
513 | "ARC instruction buffer parity error", | |
514 | "ARC data buffer parity error", | |
515 | "PHY APB error", | |
516 | }; | |
517 | ||
5176a93a YG |
518 | static const char * const smca_nbif_mce_desc[] = { |
519 | "Timeout error from GMI", | |
520 | "SRAM ECC error", | |
521 | "NTB Error Event", | |
522 | "SDP Parity error", | |
523 | }; | |
524 | ||
525 | static const char * const smca_sata_mce_desc[] = { | |
526 | "Parity error for port 0", | |
527 | "Parity error for port 1", | |
528 | "Parity error for port 2", | |
529 | "Parity error for port 3", | |
530 | "Parity error for port 4", | |
531 | "Parity error for port 5", | |
532 | "Parity error for port 6", | |
533 | "Parity error for port 7", | |
534 | }; | |
535 | ||
536 | static const char * const smca_usb_mce_desc[] = { | |
537 | "Parity error or ECC error for S0 RAM0", | |
538 | "Parity error or ECC error for S0 RAM1", | |
539 | "Parity error or ECC error for S0 RAM2", | |
540 | "Parity error for PHY RAM0", | |
541 | "Parity error for PHY RAM1", | |
542 | "AXI Slave Response error", | |
543 | }; | |
544 | ||
545 | static const char * const smca_gmipcs_mce_desc[] = { | |
546 | "Data Loss Error", | |
547 | "Training Error", | |
548 | "Replay Parity Error", | |
549 | "Rx Fifo Underflow Error", | |
550 | "Rx Fifo Overflow Error", | |
551 | "CRC Error", | |
552 | "BER Exceeded Error", | |
553 | "Tx Fifo Underflow Error", | |
554 | "Replay Buffer Parity Error", | |
555 | "Tx Overflow Error", | |
556 | "Replay Fifo Overflow Error", | |
557 | "Replay Fifo Underflow Error", | |
558 | "Elastic Fifo Overflow Error", | |
559 | "Deskew Error", | |
560 | "Offline Error", | |
561 | "Data Startup Limit Error", | |
562 | "FC Init Timeout Error", | |
563 | "Recovery Timeout Error", | |
564 | "Ready Serial Timeout Error", | |
565 | "Ready Serial Attempt Error", | |
566 | "Recovery Attempt Error", | |
567 | "Recovery Relock Attempt Error", | |
568 | "Deskew Abort Error", | |
569 | "Rx Buffer Error", | |
570 | "Rx LFDS Fifo Overflow Error", | |
571 | "Rx LFDS Fifo Underflow Error", | |
572 | "LinkSub Tx Timeout Error", | |
573 | "LinkSub Rx Timeout Error", | |
574 | "Rx CMD Packet Error", | |
575 | "LFDS Training Timeout Error", | |
576 | "LFDS FC Init Timeout Error", | |
577 | "Data Loss Error", | |
94a311ce M |
578 | }; |
579 | ||
5896820e YG |
580 | struct smca_mce_desc { |
581 | const char * const *descs; | |
582 | unsigned int num_descs; | |
583 | }; | |
584 | ||
585 | static struct smca_mce_desc smca_mce_descs[] = { | |
586 | [SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) }, | |
89a76171 | 587 | [SMCA_LS_V2] = { smca_ls2_mce_desc, ARRAY_SIZE(smca_ls2_mce_desc) }, |
5896820e YG |
588 | [SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) }, |
589 | [SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) }, | |
590 | [SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) }, | |
591 | [SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) }, | |
592 | [SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) }, | |
593 | [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) }, | |
594 | [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) }, | |
3ad7e748 | 595 | [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) }, |
5896820e YG |
596 | [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) }, |
597 | [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) }, | |
94a311ce | 598 | [SMCA_UMC_V2] = { smca_umc2_mce_desc, ARRAY_SIZE(smca_umc2_mce_desc) }, |
5896820e YG |
599 | [SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) }, |
600 | [SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) }, | |
3ad7e748 | 601 | [SMCA_PSP_V2] = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc) }, |
5896820e | 602 | [SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) }, |
3ad7e748 | 603 | [SMCA_SMU_V2] = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc) }, |
cbfa447e | 604 | [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) }, |
5176a93a | 605 | [SMCA_MPDMA] = { smca_mpdma_mce_desc, ARRAY_SIZE(smca_mpdma_mce_desc) }, |
cbfa447e YG |
606 | [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) }, |
607 | [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) }, | |
94a311ce M |
608 | [SMCA_PCIE_V2] = { smca_pcie2_mce_desc, ARRAY_SIZE(smca_pcie2_mce_desc) }, |
609 | [SMCA_XGMI_PCS] = { smca_xgmipcs_mce_desc, ARRAY_SIZE(smca_xgmipcs_mce_desc) }, | |
5176a93a YG |
610 | /* NBIF and SHUB have the same error descriptions, for now. */ |
611 | [SMCA_NBIF] = { smca_nbif_mce_desc, ARRAY_SIZE(smca_nbif_mce_desc) }, | |
612 | [SMCA_SHUB] = { smca_nbif_mce_desc, ARRAY_SIZE(smca_nbif_mce_desc) }, | |
613 | [SMCA_SATA] = { smca_sata_mce_desc, ARRAY_SIZE(smca_sata_mce_desc) }, | |
614 | [SMCA_USB] = { smca_usb_mce_desc, ARRAY_SIZE(smca_usb_mce_desc) }, | |
615 | [SMCA_GMI_PCS] = { smca_gmipcs_mce_desc, ARRAY_SIZE(smca_gmipcs_mce_desc) }, | |
616 | /* All the PHY bank types have the same error descriptions, for now. */ | |
94a311ce | 617 | [SMCA_XGMI_PHY] = { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc) }, |
5176a93a YG |
618 | [SMCA_WAFL_PHY] = { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc) }, |
619 | [SMCA_GMI_PHY] = { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc) }, | |
5896820e YG |
620 | }; |
621 | ||
f05c41a9 | 622 | static bool f12h_mc0_mce(u16 ec, u8 xec) |
51966241 | 623 | { |
888ab8e6 | 624 | bool ret = false; |
51966241 | 625 | |
888ab8e6 | 626 | if (MEM_ERROR(ec)) { |
62452882 | 627 | u8 ll = LL(ec); |
888ab8e6 | 628 | ret = true; |
51966241 | 629 | |
888ab8e6 BP |
630 | if (ll == LL_L2) |
631 | pr_cont("during L1 linefill from L2.\n"); | |
632 | else if (ll == LL_L1) | |
62452882 | 633 | pr_cont("Data/Tag %s error.\n", R4_MSG(ec)); |
888ab8e6 BP |
634 | else |
635 | ret = false; | |
636 | } | |
637 | return ret; | |
638 | } | |
51966241 | 639 | |
f05c41a9 | 640 | static bool f10h_mc0_mce(u16 ec, u8 xec) |
9be0bb10 | 641 | { |
62452882 | 642 | if (R4(ec) == R4_GEN && LL(ec) == LL_L1) { |
9be0bb10 BP |
643 | pr_cont("during data scrub.\n"); |
644 | return true; | |
645 | } | |
f05c41a9 | 646 | return f12h_mc0_mce(ec, xec); |
9be0bb10 BP |
647 | } |
648 | ||
f05c41a9 | 649 | static bool k8_mc0_mce(u16 ec, u8 xec) |
888ab8e6 BP |
650 | { |
651 | if (BUS_ERROR(ec)) { | |
652 | pr_cont("during system linefill.\n"); | |
653 | return true; | |
654 | } | |
51966241 | 655 | |
f05c41a9 | 656 | return f10h_mc0_mce(ec, xec); |
888ab8e6 BP |
657 | } |
658 | ||
980eec8b | 659 | static bool cat_mc0_mce(u16 ec, u8 xec) |
888ab8e6 | 660 | { |
62452882 | 661 | u8 r4 = R4(ec); |
888ab8e6 BP |
662 | bool ret = true; |
663 | ||
664 | if (MEM_ERROR(ec)) { | |
665 | ||
62452882 | 666 | if (TT(ec) != TT_DATA || LL(ec) != LL_L1) |
888ab8e6 BP |
667 | return false; |
668 | ||
669 | switch (r4) { | |
670 | case R4_DRD: | |
671 | case R4_DWR: | |
672 | pr_cont("Data/Tag parity error due to %s.\n", | |
673 | (r4 == R4_DRD ? "load/hw prf" : "store")); | |
674 | break; | |
675 | case R4_EVICT: | |
676 | pr_cont("Copyback parity error on a tag miss.\n"); | |
677 | break; | |
678 | case R4_SNOOP: | |
679 | pr_cont("Tag parity error during snoop.\n"); | |
680 | break; | |
681 | default: | |
682 | ret = false; | |
683 | } | |
684 | } else if (BUS_ERROR(ec)) { | |
685 | ||
62452882 | 686 | if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) |
888ab8e6 BP |
687 | return false; |
688 | ||
689 | pr_cont("System read data error on a "); | |
690 | ||
691 | switch (r4) { | |
692 | case R4_RD: | |
693 | pr_cont("TLB reload.\n"); | |
694 | break; | |
695 | case R4_DWR: | |
696 | pr_cont("store.\n"); | |
697 | break; | |
698 | case R4_DRD: | |
699 | pr_cont("load.\n"); | |
700 | break; | |
701 | default: | |
702 | ret = false; | |
703 | } | |
704 | } else { | |
705 | ret = false; | |
706 | } | |
707 | ||
708 | return ret; | |
709 | } | |
710 | ||
f05c41a9 | 711 | static bool f15h_mc0_mce(u16 ec, u8 xec) |
25a4f8b0 BP |
712 | { |
713 | bool ret = true; | |
714 | ||
715 | if (MEM_ERROR(ec)) { | |
716 | ||
717 | switch (xec) { | |
718 | case 0x0: | |
719 | pr_cont("Data Array access error.\n"); | |
720 | break; | |
721 | ||
722 | case 0x1: | |
723 | pr_cont("UC error during a linefill from L2/NB.\n"); | |
724 | break; | |
725 | ||
726 | case 0x2: | |
727 | case 0x11: | |
728 | pr_cont("STQ access error.\n"); | |
729 | break; | |
730 | ||
731 | case 0x3: | |
732 | pr_cont("SCB access error.\n"); | |
733 | break; | |
734 | ||
735 | case 0x10: | |
736 | pr_cont("Tag error.\n"); | |
737 | break; | |
738 | ||
739 | case 0x12: | |
740 | pr_cont("LDQ access error.\n"); | |
741 | break; | |
742 | ||
743 | default: | |
744 | ret = false; | |
745 | } | |
746 | } else if (BUS_ERROR(ec)) { | |
747 | ||
748 | if (!xec) | |
344f0a06 | 749 | pr_cont("System Read Data Error.\n"); |
25a4f8b0 | 750 | else |
344f0a06 | 751 | pr_cont(" Internal error condition type %d.\n", xec); |
eba4bfb3 AG |
752 | } else if (INT_ERROR(ec)) { |
753 | if (xec <= 0x1f) | |
754 | pr_cont("Hardware Assert.\n"); | |
755 | else | |
756 | ret = false; | |
757 | ||
25a4f8b0 BP |
758 | } else |
759 | ret = false; | |
760 | ||
761 | return ret; | |
762 | } | |
763 | ||
f05c41a9 | 764 | static void decode_mc0_mce(struct mce *m) |
888ab8e6 | 765 | { |
62452882 BP |
766 | u16 ec = EC(m->status); |
767 | u8 xec = XEC(m->status, xec_mask); | |
888ab8e6 | 768 | |
f05c41a9 | 769 | pr_emerg(HW_ERR "MC0 Error: "); |
888ab8e6 BP |
770 | |
771 | /* TLB error signatures are the same across families */ | |
772 | if (TLB_ERROR(ec)) { | |
62452882 | 773 | if (TT(ec) == TT_DATA) { |
888ab8e6 | 774 | pr_cont("%s TLB %s.\n", LL_MSG(ec), |
25a4f8b0 BP |
775 | ((xec == 2) ? "locked miss" |
776 | : (xec ? "multimatch" : "parity"))); | |
888ab8e6 BP |
777 | return; |
778 | } | |
86e9f9d6 | 779 | } else if (fam_ops.mc0_mce(ec, xec)) |
25a4f8b0 BP |
780 | ; |
781 | else | |
f05c41a9 | 782 | pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n"); |
51966241 BP |
783 | } |
784 | ||
f05c41a9 | 785 | static bool k8_mc1_mce(u16 ec, u8 xec) |
ab5535e7 | 786 | { |
62452882 | 787 | u8 ll = LL(ec); |
dd53bce4 | 788 | bool ret = true; |
ab5535e7 | 789 | |
dd53bce4 BP |
790 | if (!MEM_ERROR(ec)) |
791 | return false; | |
ab5535e7 | 792 | |
dd53bce4 BP |
793 | if (ll == 0x2) |
794 | pr_cont("during a linefill from L2.\n"); | |
795 | else if (ll == 0x1) { | |
62452882 | 796 | switch (R4(ec)) { |
dd53bce4 BP |
797 | case R4_IRD: |
798 | pr_cont("Parity error during data load.\n"); | |
799 | break; | |
ab5535e7 | 800 | |
dd53bce4 BP |
801 | case R4_EVICT: |
802 | pr_cont("Copyback Parity/Victim error.\n"); | |
803 | break; | |
804 | ||
805 | case R4_SNOOP: | |
806 | pr_cont("Tag Snoop error.\n"); | |
807 | break; | |
808 | ||
809 | default: | |
810 | ret = false; | |
811 | break; | |
812 | } | |
ab5535e7 | 813 | } else |
dd53bce4 | 814 | ret = false; |
ab5535e7 | 815 | |
dd53bce4 BP |
816 | return ret; |
817 | } | |
818 | ||
980eec8b | 819 | static bool cat_mc1_mce(u16 ec, u8 xec) |
dd53bce4 | 820 | { |
62452882 | 821 | u8 r4 = R4(ec); |
dd53bce4 | 822 | bool ret = true; |
ab5535e7 | 823 | |
980eec8b JS |
824 | if (!MEM_ERROR(ec)) |
825 | return false; | |
826 | ||
827 | if (TT(ec) != TT_INSTR) | |
828 | return false; | |
829 | ||
830 | if (r4 == R4_IRD) | |
831 | pr_cont("Data/tag array parity error for a tag hit.\n"); | |
832 | else if (r4 == R4_SNOOP) | |
833 | pr_cont("Tag error during snoop/victimization.\n"); | |
834 | else if (xec == 0x0) | |
835 | pr_cont("Tag parity error from victim castout.\n"); | |
836 | else if (xec == 0x2) | |
837 | pr_cont("Microcode patch RAM parity error.\n"); | |
838 | else | |
839 | ret = false; | |
dd53bce4 | 840 | |
dd53bce4 BP |
841 | return ret; |
842 | } | |
843 | ||
f05c41a9 | 844 | static bool f15h_mc1_mce(u16 ec, u8 xec) |
86039cd4 BP |
845 | { |
846 | bool ret = true; | |
847 | ||
848 | if (!MEM_ERROR(ec)) | |
849 | return false; | |
850 | ||
851 | switch (xec) { | |
852 | case 0x0 ... 0xa: | |
f05c41a9 | 853 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec]); |
86039cd4 BP |
854 | break; |
855 | ||
856 | case 0xd: | |
f05c41a9 | 857 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]); |
86039cd4 BP |
858 | break; |
859 | ||
6c1173a6 | 860 | case 0x10: |
f05c41a9 | 861 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); |
6c1173a6 BP |
862 | break; |
863 | ||
eba4bfb3 | 864 | case 0x11 ... 0x15: |
f05c41a9 | 865 | pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); |
86039cd4 BP |
866 | break; |
867 | ||
868 | default: | |
869 | ret = false; | |
870 | } | |
871 | return ret; | |
872 | } | |
873 | ||
f05c41a9 | 874 | static void decode_mc1_mce(struct mce *m) |
dd53bce4 | 875 | { |
62452882 BP |
876 | u16 ec = EC(m->status); |
877 | u8 xec = XEC(m->status, xec_mask); | |
dd53bce4 | 878 | |
f05c41a9 | 879 | pr_emerg(HW_ERR "MC1 Error: "); |
dd53bce4 BP |
880 | |
881 | if (TLB_ERROR(ec)) | |
882 | pr_cont("%s TLB %s.\n", LL_MSG(ec), | |
883 | (xec ? "multimatch" : "parity error")); | |
884 | else if (BUS_ERROR(ec)) { | |
525906bc | 885 | bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); |
dd53bce4 BP |
886 | |
887 | pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); | |
eba4bfb3 AG |
888 | } else if (INT_ERROR(ec)) { |
889 | if (xec <= 0x3f) | |
890 | pr_cont("Hardware Assert.\n"); | |
891 | else | |
892 | goto wrong_mc1_mce; | |
86e9f9d6 | 893 | } else if (fam_ops.mc1_mce(ec, xec)) |
dd53bce4 BP |
894 | ; |
895 | else | |
eba4bfb3 AG |
896 | goto wrong_mc1_mce; |
897 | ||
898 | return; | |
899 | ||
900 | wrong_mc1_mce: | |
901 | pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); | |
ab5535e7 BP |
902 | } |
903 | ||
4a73d3de | 904 | static bool k8_mc2_mce(u16 ec, u8 xec) |
56cad2d6 | 905 | { |
4a73d3de | 906 | bool ret = true; |
56cad2d6 BP |
907 | |
908 | if (xec == 0x1) | |
909 | pr_cont(" in the write data buffers.\n"); | |
910 | else if (xec == 0x3) | |
911 | pr_cont(" in the victim data buffers.\n"); | |
912 | else if (xec == 0x2 && MEM_ERROR(ec)) | |
62452882 | 913 | pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); |
56cad2d6 BP |
914 | else if (xec == 0x0) { |
915 | if (TLB_ERROR(ec)) | |
50872ccd BP |
916 | pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n", |
917 | TT_MSG(ec)); | |
56cad2d6 BP |
918 | else if (BUS_ERROR(ec)) |
919 | pr_cont(": %s/ECC error in data read from NB: %s.\n", | |
62452882 | 920 | R4_MSG(ec), PP_MSG(ec)); |
56cad2d6 | 921 | else if (MEM_ERROR(ec)) { |
62452882 | 922 | u8 r4 = R4(ec); |
56cad2d6 | 923 | |
62452882 | 924 | if (r4 >= 0x7) |
56cad2d6 | 925 | pr_cont(": %s error during data copyback.\n", |
62452882 BP |
926 | R4_MSG(ec)); |
927 | else if (r4 <= 0x1) | |
56cad2d6 | 928 | pr_cont(": %s parity/ECC error during data " |
62452882 | 929 | "access from L2.\n", R4_MSG(ec)); |
56cad2d6 | 930 | else |
4a73d3de | 931 | ret = false; |
56cad2d6 | 932 | } else |
4a73d3de | 933 | ret = false; |
56cad2d6 | 934 | } else |
4a73d3de | 935 | ret = false; |
56cad2d6 | 936 | |
4a73d3de | 937 | return ret; |
56cad2d6 BP |
938 | } |
939 | ||
4a73d3de | 940 | static bool f15h_mc2_mce(u16 ec, u8 xec) |
70fdb494 | 941 | { |
4a73d3de | 942 | bool ret = true; |
70fdb494 BP |
943 | |
944 | if (TLB_ERROR(ec)) { | |
945 | if (xec == 0x0) | |
946 | pr_cont("Data parity TLB read error.\n"); | |
947 | else if (xec == 0x1) | |
948 | pr_cont("Poison data provided for TLB fill.\n"); | |
949 | else | |
4a73d3de | 950 | ret = false; |
70fdb494 BP |
951 | } else if (BUS_ERROR(ec)) { |
952 | if (xec > 2) | |
4a73d3de | 953 | ret = false; |
70fdb494 BP |
954 | |
955 | pr_cont("Error during attempted NB data read.\n"); | |
956 | } else if (MEM_ERROR(ec)) { | |
957 | switch (xec) { | |
958 | case 0x4 ... 0xc: | |
f05c41a9 | 959 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); |
70fdb494 BP |
960 | break; |
961 | ||
962 | case 0x10 ... 0x14: | |
f05c41a9 | 963 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); |
70fdb494 BP |
964 | break; |
965 | ||
966 | default: | |
4a73d3de | 967 | ret = false; |
70fdb494 | 968 | } |
eba4bfb3 AG |
969 | } else if (INT_ERROR(ec)) { |
970 | if (xec <= 0x3f) | |
971 | pr_cont("Hardware Assert.\n"); | |
972 | else | |
973 | ret = false; | |
70fdb494 BP |
974 | } |
975 | ||
4a73d3de JS |
976 | return ret; |
977 | } | |
978 | ||
980eec8b JS |
979 | static bool f16h_mc2_mce(u16 ec, u8 xec) |
980 | { | |
981 | u8 r4 = R4(ec); | |
982 | ||
983 | if (!MEM_ERROR(ec)) | |
984 | return false; | |
985 | ||
986 | switch (xec) { | |
987 | case 0x04 ... 0x05: | |
988 | pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); | |
989 | break; | |
990 | ||
991 | case 0x09 ... 0x0b: | |
992 | case 0x0d ... 0x0f: | |
993 | pr_cont("ECC error in L2 tag (%s).\n", | |
994 | ((r4 == R4_GEN) ? "BankReq" : | |
995 | ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); | |
996 | break; | |
997 | ||
998 | case 0x10 ... 0x19: | |
999 | case 0x1b: | |
1000 | pr_cont("ECC error in L2 data array (%s).\n", | |
1001 | (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : | |
1002 | ((r4 == R4_GEN) ? "Attr" : | |
1003 | ((r4 == R4_EVICT) ? "Vict" : "Fill")))); | |
1004 | break; | |
1005 | ||
1006 | case 0x1c ... 0x1d: | |
1007 | case 0x1f: | |
1008 | pr_cont("Parity error in L2 attribute bits (%s).\n", | |
1009 | ((r4 == R4_RD) ? "Hit" : | |
1010 | ((r4 == R4_GEN) ? "Attr" : "Fill"))); | |
1011 | break; | |
1012 | ||
1013 | default: | |
1014 | return false; | |
1015 | } | |
1016 | ||
1017 | return true; | |
1018 | } | |
1019 | ||
4a73d3de JS |
1020 | static void decode_mc2_mce(struct mce *m) |
1021 | { | |
1022 | u16 ec = EC(m->status); | |
1023 | u8 xec = XEC(m->status, xec_mask); | |
70fdb494 | 1024 | |
4a73d3de JS |
1025 | pr_emerg(HW_ERR "MC2 Error: "); |
1026 | ||
86e9f9d6 | 1027 | if (!fam_ops.mc2_mce(ec, xec)) |
4a73d3de | 1028 | pr_cont(HW_ERR "Corrupted MC2 MCE info?\n"); |
70fdb494 BP |
1029 | } |
1030 | ||
f05c41a9 | 1031 | static void decode_mc3_mce(struct mce *m) |
f9350efd | 1032 | { |
62452882 BP |
1033 | u16 ec = EC(m->status); |
1034 | u8 xec = XEC(m->status, xec_mask); | |
ded50623 | 1035 | |
b18434ca | 1036 | if (boot_cpu_data.x86 >= 0x14) { |
f05c41a9 | 1037 | pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family," |
ded50623 BP |
1038 | " please report on LKML.\n"); |
1039 | return; | |
1040 | } | |
f9350efd | 1041 | |
f05c41a9 | 1042 | pr_emerg(HW_ERR "MC3 Error"); |
f9350efd BP |
1043 | |
1044 | if (xec == 0x0) { | |
62452882 | 1045 | u8 r4 = R4(ec); |
f9350efd | 1046 | |
ded50623 | 1047 | if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR)) |
f05c41a9 | 1048 | goto wrong_mc3_mce; |
f9350efd | 1049 | |
62452882 | 1050 | pr_cont(" during %s.\n", R4_MSG(ec)); |
ded50623 | 1051 | } else |
f05c41a9 | 1052 | goto wrong_mc3_mce; |
ded50623 | 1053 | |
f9350efd BP |
1054 | return; |
1055 | ||
f05c41a9 BP |
1056 | wrong_mc3_mce: |
1057 | pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n"); | |
f9350efd BP |
1058 | } |
1059 | ||
f05c41a9 | 1060 | static void decode_mc4_mce(struct mce *m) |
5ce88f6e | 1061 | { |
f3c0891c | 1062 | unsigned int fam = x86_family(m->cpuid); |
db970bd2 | 1063 | int node_id = topology_die_id(m->extcpu); |
68782673 BP |
1064 | u16 ec = EC(m->status); |
1065 | u8 xec = XEC(m->status, 0x1f); | |
1066 | u8 offset = 0; | |
5ce88f6e | 1067 | |
f05c41a9 | 1068 | pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); |
5ce88f6e | 1069 | |
68782673 BP |
1070 | switch (xec) { |
1071 | case 0x0 ... 0xe: | |
5ce88f6e | 1072 | |
68782673 BP |
1073 | /* special handling for DRAM ECCs */ |
1074 | if (xec == 0x0 || xec == 0x8) { | |
1075 | /* no ECCs on F11h */ | |
f3c0891c | 1076 | if (fam == 0x11) |
f05c41a9 | 1077 | goto wrong_mc4_mce; |
5ce88f6e | 1078 | |
f05c41a9 | 1079 | pr_cont("%s.\n", mc4_mce_desc[xec]); |
5ce88f6e | 1080 | |
5c332202 YG |
1081 | if (decode_dram_ecc) |
1082 | decode_dram_ecc(node_id, m); | |
68782673 BP |
1083 | return; |
1084 | } | |
5ce88f6e BP |
1085 | break; |
1086 | ||
1087 | case 0xf: | |
1088 | if (TLB_ERROR(ec)) | |
1089 | pr_cont("GART Table Walk data error.\n"); | |
1090 | else if (BUS_ERROR(ec)) | |
1091 | pr_cont("DMA Exclusion Vector Table Walk error.\n"); | |
1092 | else | |
f05c41a9 | 1093 | goto wrong_mc4_mce; |
68782673 | 1094 | return; |
5ce88f6e | 1095 | |
05cd667d | 1096 | case 0x19: |
f3c0891c | 1097 | if (fam == 0x15 || fam == 0x16) |
05cd667d BP |
1098 | pr_cont("Compute Unit Data Error.\n"); |
1099 | else | |
f05c41a9 | 1100 | goto wrong_mc4_mce; |
68782673 | 1101 | return; |
05cd667d | 1102 | |
5ce88f6e | 1103 | case 0x1c ... 0x1f: |
68782673 | 1104 | offset = 13; |
5ce88f6e BP |
1105 | break; |
1106 | ||
1107 | default: | |
f05c41a9 | 1108 | goto wrong_mc4_mce; |
68782673 | 1109 | } |
5ce88f6e | 1110 | |
f05c41a9 | 1111 | pr_cont("%s.\n", mc4_mce_desc[xec - offset]); |
5ce88f6e BP |
1112 | return; |
1113 | ||
f05c41a9 BP |
1114 | wrong_mc4_mce: |
1115 | pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); | |
d93cc222 | 1116 | } |
d93cc222 | 1117 | |
f05c41a9 | 1118 | static void decode_mc5_mce(struct mce *m) |
53bd5fed | 1119 | { |
f3c0891c | 1120 | unsigned int fam = x86_family(m->cpuid); |
eba4bfb3 | 1121 | u16 ec = EC(m->status); |
62452882 | 1122 | u8 xec = XEC(m->status, xec_mask); |
8259a7e5 | 1123 | |
f3c0891c | 1124 | if (fam == 0xf || fam == 0x11) |
f05c41a9 | 1125 | goto wrong_mc5_mce; |
fe4ea262 | 1126 | |
f05c41a9 | 1127 | pr_emerg(HW_ERR "MC5 Error: "); |
8259a7e5 | 1128 | |
eba4bfb3 AG |
1129 | if (INT_ERROR(ec)) { |
1130 | if (xec <= 0x1f) { | |
1131 | pr_cont("Hardware Assert.\n"); | |
1132 | return; | |
1133 | } else | |
1134 | goto wrong_mc5_mce; | |
1135 | } | |
1136 | ||
8259a7e5 | 1137 | if (xec == 0x0 || xec == 0xc) |
f05c41a9 | 1138 | pr_cont("%s.\n", mc5_mce_desc[xec]); |
aad19e51 | 1139 | else if (xec <= 0xd) |
f05c41a9 | 1140 | pr_cont("%s parity error.\n", mc5_mce_desc[xec]); |
8259a7e5 | 1141 | else |
f05c41a9 | 1142 | goto wrong_mc5_mce; |
8259a7e5 BP |
1143 | |
1144 | return; | |
fe4ea262 | 1145 | |
f05c41a9 BP |
1146 | wrong_mc5_mce: |
1147 | pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n"); | |
53bd5fed BP |
1148 | } |
1149 | ||
f05c41a9 | 1150 | static void decode_mc6_mce(struct mce *m) |
b8f85c47 | 1151 | { |
62452882 | 1152 | u8 xec = XEC(m->status, xec_mask); |
b8f85c47 | 1153 | |
f05c41a9 | 1154 | pr_emerg(HW_ERR "MC6 Error: "); |
b8f85c47 | 1155 | |
bc4febe9 | 1156 | if (xec > 0x5) |
f05c41a9 | 1157 | goto wrong_mc6_mce; |
b8f85c47 | 1158 | |
bc4febe9 | 1159 | pr_cont("%s parity error.\n", mc6_mce_desc[xec]); |
b8f85c47 BP |
1160 | return; |
1161 | ||
f05c41a9 BP |
1162 | wrong_mc6_mce: |
1163 | pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); | |
b8f85c47 BP |
1164 | } |
1165 | ||
be0aec23 | 1166 | /* Decode errors according to Scalable MCA specification */ |
4ab1784b | 1167 | static void decode_smca_error(struct mce *m) |
be0aec23 | 1168 | { |
91f75eb4 | 1169 | enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); |
be0aec23 | 1170 | const char *ip_name; |
5896820e | 1171 | u8 xec = XEC(m->status, xec_mask); |
be0aec23 | 1172 | |
91f75eb4 | 1173 | if (bank_type >= N_SMCA_BANK_TYPES) |
be0aec23 | 1174 | return; |
be0aec23 | 1175 | |
68627a69 YG |
1176 | if (bank_type == SMCA_RESERVED) { |
1177 | pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); | |
1178 | return; | |
1179 | } | |
1180 | ||
c09a8c40 | 1181 | ip_name = smca_get_long_name(bank_type); |
be0aec23 | 1182 | |
1c1522d3 | 1183 | pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec); |
be0aec23 | 1184 | |
5896820e | 1185 | /* Only print the decode of valid error codes */ |
368d1887 | 1186 | if (xec < smca_mce_descs[bank_type].num_descs) |
1c1522d3 | 1187 | pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]); |
5c332202 | 1188 | |
5c332202 | 1189 | if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc) |
8de0c991 | 1190 | decode_dram_ecc(topology_die_id(m->extcpu), m); |
be0aec23 AG |
1191 | } |
1192 | ||
6337583d | 1193 | static inline void amd_decode_err_code(u16 ec) |
d93cc222 | 1194 | { |
980eec8b JS |
1195 | if (INT_ERROR(ec)) { |
1196 | pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec)); | |
1197 | return; | |
1198 | } | |
fa7ae8cc BP |
1199 | |
1200 | pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec)); | |
1201 | ||
1202 | if (BUS_ERROR(ec)) | |
1203 | pr_cont(", mem/io: %s", II_MSG(ec)); | |
1204 | else | |
1205 | pr_cont(", tx: %s", TT_MSG(ec)); | |
1206 | ||
1207 | if (MEM_ERROR(ec) || BUS_ERROR(ec)) { | |
1208 | pr_cont(", mem-tx: %s", R4_MSG(ec)); | |
1209 | ||
1210 | if (BUS_ERROR(ec)) | |
1211 | pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec)); | |
1212 | } | |
1213 | ||
1214 | pr_cont("\n"); | |
549d042d | 1215 | } |
549d042d | 1216 | |
d5c6770d BP |
1217 | static const char *decode_error_status(struct mce *m) |
1218 | { | |
1219 | if (m->status & MCI_STATUS_UC) { | |
1220 | if (m->status & MCI_STATUS_PCC) | |
1221 | return "System Fatal error."; | |
1222 | if (m->mcgstatus & MCG_STATUS_RIPV) | |
1223 | return "Uncorrected, software restartable error."; | |
1224 | return "Uncorrected, software containable error."; | |
1225 | } | |
1226 | ||
1227 | if (m->status & MCI_STATUS_DEFERRED) | |
67d7fd30 | 1228 | return "Deferred error, no action required."; |
d5c6770d BP |
1229 | |
1230 | return "Corrected error, no action required."; | |
1231 | } | |
1232 | ||
1fbcd909 BP |
1233 | static int |
1234 | amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) | |
549d042d | 1235 | { |
fb253195 | 1236 | struct mce *m = (struct mce *)data; |
f3c0891c | 1237 | unsigned int fam = x86_family(m->cpuid); |
b0b07a2b | 1238 | int ecc; |
549d042d | 1239 | |
23ba710a TL |
1240 | if (m->kflags & MCE_HANDLED_CEC) |
1241 | return NOTIFY_DONE; | |
1242 | ||
fd0f5fff BP |
1243 | pr_emerg(HW_ERR "%s\n", decode_error_status(m)); |
1244 | ||
1245 | pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", | |
1246 | m->extcpu, | |
f3c0891c | 1247 | fam, x86_model(m->cpuid), x86_stepping(m->cpuid), |
fd0f5fff BP |
1248 | m->bank, |
1249 | ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), | |
99e1dfb7 AG |
1250 | ((m->status & MCI_STATUS_UC) ? "UE" : |
1251 | (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), | |
fd0f5fff | 1252 | ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), |
a0bcd3c0 YG |
1253 | ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), |
1254 | ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); | |
fd0f5fff | 1255 | |
a348ed83 | 1256 | if (boot_cpu_has(X86_FEATURE_SMCA)) { |
be0aec23 AG |
1257 | u32 low, high; |
1258 | u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); | |
1259 | ||
1260 | if (!rdmsr_safe(addr, &low, &high) && | |
1261 | (low & MCI_CONFIG_MCAX)) | |
1262 | pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); | |
a0bcd3c0 YG |
1263 | |
1264 | pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); | |
be0aec23 AG |
1265 | } |
1266 | ||
fd0f5fff BP |
1267 | /* do the two bits[14:13] together */ |
1268 | ecc = (m->status >> 45) & 0x3; | |
1269 | if (ecc) | |
1270 | pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); | |
1271 | ||
a0bcd3c0 YG |
1272 | if (fam >= 0x15) { |
1273 | pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); | |
1274 | ||
1275 | /* F15h, bank4, bit 43 is part of McaStatSubCache. */ | |
1276 | if (fam != 0x15 || m->bank != 4) | |
1277 | pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); | |
1278 | } | |
1279 | ||
3f4da372 YG |
1280 | if (fam >= 0x17) |
1281 | pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); | |
1282 | ||
fd0f5fff BP |
1283 | pr_cont("]: 0x%016llx\n", m->status); |
1284 | ||
1285 | if (m->status & MCI_STATUS_ADDRV) | |
75bf2f64 | 1286 | pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr); |
fd0f5fff | 1287 | |
bb2de0ad SK |
1288 | if (m->ppin) |
1289 | pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin); | |
1290 | ||
a348ed83 | 1291 | if (boot_cpu_has(X86_FEATURE_SMCA)) { |
75bf2f64 YG |
1292 | pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); |
1293 | ||
b300e873 YG |
1294 | if (m->status & MCI_STATUS_SYNDV) |
1295 | pr_cont(", Syndrome: 0x%016llx", m->synd); | |
1296 | ||
1297 | pr_cont("\n"); | |
1298 | ||
4ab1784b | 1299 | decode_smca_error(m); |
be0aec23 | 1300 | goto err_code; |
75bf2f64 | 1301 | } |
be0aec23 | 1302 | |
0bceab67 BP |
1303 | if (m->tsc) |
1304 | pr_emerg(HW_ERR "TSC: %llu\n", m->tsc); | |
1305 | ||
86e9f9d6 BP |
1306 | /* Doesn't matter which member to test. */ |
1307 | if (!fam_ops.mc0_mce) | |
fd0f5fff BP |
1308 | goto err_code; |
1309 | ||
51966241 BP |
1310 | switch (m->bank) { |
1311 | case 0: | |
f05c41a9 | 1312 | decode_mc0_mce(m); |
51966241 | 1313 | break; |
d93cc222 | 1314 | |
ab5535e7 | 1315 | case 1: |
f05c41a9 | 1316 | decode_mc1_mce(m); |
ab5535e7 BP |
1317 | break; |
1318 | ||
56cad2d6 | 1319 | case 2: |
4a73d3de | 1320 | decode_mc2_mce(m); |
56cad2d6 BP |
1321 | break; |
1322 | ||
f9350efd | 1323 | case 3: |
f05c41a9 | 1324 | decode_mc3_mce(m); |
f9350efd BP |
1325 | break; |
1326 | ||
51966241 | 1327 | case 4: |
f05c41a9 | 1328 | decode_mc4_mce(m); |
51966241 BP |
1329 | break; |
1330 | ||
53bd5fed | 1331 | case 5: |
f05c41a9 | 1332 | decode_mc5_mce(m); |
53bd5fed BP |
1333 | break; |
1334 | ||
b8f85c47 | 1335 | case 6: |
f05c41a9 | 1336 | decode_mc6_mce(m); |
b8f85c47 BP |
1337 | break; |
1338 | ||
51966241 BP |
1339 | default: |
1340 | break; | |
b69b29de | 1341 | } |
51966241 | 1342 | |
fd0f5fff | 1343 | err_code: |
51966241 | 1344 | amd_decode_err_code(m->status & 0xffff); |
fb253195 | 1345 | |
23ba710a TL |
1346 | m->kflags |= MCE_HANDLED_EDAC; |
1347 | return NOTIFY_OK; | |
549d042d | 1348 | } |
f436f8bb | 1349 | |
fb253195 BP |
1350 | static struct notifier_block amd_mce_dec_nb = { |
1351 | .notifier_call = amd_decode_mce, | |
9026cc82 | 1352 | .priority = MCE_PRIO_EDAC, |
fb253195 BP |
1353 | }; |
1354 | ||
f436f8bb IM |
1355 | static int __init mce_amd_init(void) |
1356 | { | |
bad11e03 BP |
1357 | struct cpuinfo_x86 *c = &boot_cpu_data; |
1358 | ||
c4a3e946 PW |
1359 | if (c->x86_vendor != X86_VENDOR_AMD && |
1360 | c->x86_vendor != X86_VENDOR_HYGON) | |
fd0f5fff | 1361 | return -ENODEV; |
e045c291 | 1362 | |
767f4b62 SK |
1363 | if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) |
1364 | return -ENODEV; | |
1365 | ||
9f6aef86 YG |
1366 | if (boot_cpu_has(X86_FEATURE_SMCA)) { |
1367 | xec_mask = 0x3f; | |
1368 | goto out; | |
1369 | } | |
1370 | ||
bad11e03 | 1371 | switch (c->x86) { |
888ab8e6 | 1372 | case 0xf: |
86e9f9d6 BP |
1373 | fam_ops.mc0_mce = k8_mc0_mce; |
1374 | fam_ops.mc1_mce = k8_mc1_mce; | |
1375 | fam_ops.mc2_mce = k8_mc2_mce; | |
888ab8e6 BP |
1376 | break; |
1377 | ||
1378 | case 0x10: | |
86e9f9d6 BP |
1379 | fam_ops.mc0_mce = f10h_mc0_mce; |
1380 | fam_ops.mc1_mce = k8_mc1_mce; | |
1381 | fam_ops.mc2_mce = k8_mc2_mce; | |
888ab8e6 BP |
1382 | break; |
1383 | ||
f0157b3a | 1384 | case 0x11: |
86e9f9d6 BP |
1385 | fam_ops.mc0_mce = k8_mc0_mce; |
1386 | fam_ops.mc1_mce = k8_mc1_mce; | |
1387 | fam_ops.mc2_mce = k8_mc2_mce; | |
f0157b3a BP |
1388 | break; |
1389 | ||
9be0bb10 | 1390 | case 0x12: |
86e9f9d6 BP |
1391 | fam_ops.mc0_mce = f12h_mc0_mce; |
1392 | fam_ops.mc1_mce = k8_mc1_mce; | |
1393 | fam_ops.mc2_mce = k8_mc2_mce; | |
9be0bb10 BP |
1394 | break; |
1395 | ||
888ab8e6 | 1396 | case 0x14: |
86e9f9d6 BP |
1397 | fam_ops.mc0_mce = cat_mc0_mce; |
1398 | fam_ops.mc1_mce = cat_mc1_mce; | |
1399 | fam_ops.mc2_mce = k8_mc2_mce; | |
888ab8e6 BP |
1400 | break; |
1401 | ||
2be64bfa | 1402 | case 0x15: |
eba4bfb3 AG |
1403 | xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f; |
1404 | ||
86e9f9d6 BP |
1405 | fam_ops.mc0_mce = f15h_mc0_mce; |
1406 | fam_ops.mc1_mce = f15h_mc1_mce; | |
1407 | fam_ops.mc2_mce = f15h_mc2_mce; | |
2be64bfa BP |
1408 | break; |
1409 | ||
980eec8b JS |
1410 | case 0x16: |
1411 | xec_mask = 0x1f; | |
86e9f9d6 BP |
1412 | fam_ops.mc0_mce = cat_mc0_mce; |
1413 | fam_ops.mc1_mce = cat_mc1_mce; | |
1414 | fam_ops.mc2_mce = f16h_mc2_mce; | |
980eec8b JS |
1415 | break; |
1416 | ||
be0aec23 | 1417 | case 0x17: |
c4a3e946 | 1418 | case 0x18: |
52cff04a | 1419 | pr_warn_once("Decoding supported only on Scalable MCA processors.\n"); |
86e9f9d6 | 1420 | return -EINVAL; |
be0aec23 | 1421 | |
888ab8e6 | 1422 | default: |
ec3e82d6 | 1423 | printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86); |
86e9f9d6 | 1424 | return -EINVAL; |
888ab8e6 BP |
1425 | } |
1426 | ||
9f6aef86 | 1427 | out: |
9530d608 BP |
1428 | pr_info("MCE: In-kernel MCE decoding enabled.\n"); |
1429 | ||
3653ada5 | 1430 | mce_register_decode_chain(&amd_mce_dec_nb); |
f436f8bb IM |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | early_initcall(mce_amd_init); | |
0d18b2e3 BP |
1435 | |
1436 | #ifdef MODULE | |
1437 | static void __exit mce_amd_exit(void) | |
1438 | { | |
3653ada5 | 1439 | mce_unregister_decode_chain(&amd_mce_dec_nb); |
0d18b2e3 BP |
1440 | } |
1441 | ||
1442 | MODULE_DESCRIPTION("AMD MCE decoder"); | |
1443 | MODULE_ALIAS("edac-mce-amd"); | |
1444 | MODULE_LICENSE("GPL"); | |
1445 | module_exit(mce_amd_exit); | |
1446 | #endif |