Commit | Line | Data |
---|---|---|
09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b70ef010 | 2 | #include <linux/module.h> |
888ab8e6 BP |
3 | #include <linux/slab.h> |
4 | ||
f3c0891c BP |
5 | #include <asm/cpu.h> |
6 | ||
47ca08a4 | 7 | #include "mce_amd.h" |
b52401ce | 8 | |
86e9f9d6 | 9 | static struct amd_decoder_ops fam_ops; |
888ab8e6 | 10 | |
2be64bfa | 11 | static u8 xec_mask = 0xf; |
5ce88f6e | 12 | |
5c332202 | 13 | static void (*decode_dram_ecc)(int node_id, struct mce *m); |
549d042d | 14 | |
b0b07a2b | 15 | void amd_register_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d | 16 | { |
5c332202 | 17 | decode_dram_ecc = f; |
549d042d BP |
18 | } |
19 | EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); | |
20 | ||
b0b07a2b | 21 | void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d | 22 | { |
5c332202 YG |
23 | if (decode_dram_ecc) { |
24 | WARN_ON(decode_dram_ecc != f); | |
549d042d | 25 | |
5c332202 | 26 | decode_dram_ecc = NULL; |
549d042d BP |
27 | } |
28 | } | |
29 | EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); | |
30 | ||
b52401ce DT |
31 | /* |
32 | * string representation for the different MCA reported error types, see F3x48 | |
33 | * or MSR0000_0411. | |
34 | */ | |
6337583d BP |
35 | |
36 | /* transaction type */ | |
0f08669e | 37 | static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; |
b52401ce | 38 | |
6337583d | 39 | /* cache level */ |
0f08669e | 40 | static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; |
b52401ce | 41 | |
6337583d | 42 | /* memory transaction type */ |
0f08669e | 43 | static const char * const rrrr_msgs[] = { |
6337583d | 44 | "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" |
b52401ce DT |
45 | }; |
46 | ||
6337583d | 47 | /* participating processor */ |
ebe2aea8 | 48 | const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; |
b70ef010 | 49 | EXPORT_SYMBOL_GPL(pp_msgs); |
b52401ce | 50 | |
6337583d | 51 | /* request timeout */ |
0f08669e | 52 | static const char * const to_msgs[] = { "no timeout", "timed out" }; |
b52401ce | 53 | |
6337583d | 54 | /* memory or i/o */ |
0f08669e | 55 | static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; |
b52401ce | 56 | |
980eec8b | 57 | /* internal error type */ |
0f08669e | 58 | static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" }; |
980eec8b | 59 | |
f05c41a9 | 60 | static const char * const f15h_mc1_mce_desc[] = { |
86039cd4 BP |
61 | "UC during a demand linefill from L2", |
62 | "Parity error during data load from IC", | |
63 | "Parity error for IC valid bit", | |
64 | "Main tag parity error", | |
65 | "Parity error in prediction queue", | |
66 | "PFB data/address parity error", | |
67 | "Parity error in the branch status reg", | |
68 | "PFB promotion address error", | |
69 | "Tag error during probe/victimization", | |
70 | "Parity error for IC probe tag valid bit", | |
71 | "PFB non-cacheable bit parity error", | |
72 | "PFB valid bit parity error", /* xec = 0xd */ | |
6c1173a6 | 73 | "Microcode Patch Buffer", /* xec = 010 */ |
86039cd4 BP |
74 | "uop queue", |
75 | "insn buffer", | |
76 | "predecode buffer", | |
eba4bfb3 AG |
77 | "fetch address FIFO", |
78 | "dispatch uop queue" | |
86039cd4 BP |
79 | }; |
80 | ||
f05c41a9 | 81 | static const char * const f15h_mc2_mce_desc[] = { |
70fdb494 BP |
82 | "Fill ECC error on data fills", /* xec = 0x4 */ |
83 | "Fill parity error on insn fills", | |
84 | "Prefetcher request FIFO parity error", | |
85 | "PRQ address parity error", | |
86 | "PRQ data parity error", | |
87 | "WCC Tag ECC error", | |
88 | "WCC Data ECC error", | |
89 | "WCB Data parity error", | |
b64a99c1 | 90 | "VB Data ECC or parity error", |
70fdb494 BP |
91 | "L2 Tag ECC error", /* xec = 0x10 */ |
92 | "Hard L2 Tag ECC error", | |
93 | "Multiple hits on L2 tag", | |
94 | "XAB parity error", | |
95 | "PRB address parity error" | |
96 | }; | |
97 | ||
f05c41a9 | 98 | static const char * const mc4_mce_desc[] = { |
68782673 BP |
99 | "DRAM ECC error detected on the NB", |
100 | "CRC error detected on HT link", | |
101 | "Link-defined sync error packets detected on HT link", | |
102 | "HT Master abort", | |
103 | "HT Target abort", | |
104 | "Invalid GART PTE entry during GART table walk", | |
105 | "Unsupported atomic RMW received from an IO link", | |
106 | "Watchdog timeout due to lack of progress", | |
107 | "DRAM ECC error detected on the NB", | |
108 | "SVM DMA Exclusion Vector error", | |
109 | "HT data error detected on link", | |
110 | "Protocol error (link, L3, probe filter)", | |
111 | "NB internal arrays parity error", | |
112 | "DRAM addr/ctl signals parity error", | |
113 | "IO link transmission error", | |
114 | "L3 data cache ECC error", /* xec = 0x1c */ | |
115 | "L3 cache tag error", | |
116 | "L3 LRU parity bits error", | |
117 | "ECC Error in the Probe Filter directory" | |
118 | }; | |
119 | ||
f05c41a9 | 120 | static const char * const mc5_mce_desc[] = { |
8259a7e5 BP |
121 | "CPU Watchdog timer expire", |
122 | "Wakeup array dest tag", | |
123 | "AG payload array", | |
124 | "EX payload array", | |
125 | "IDRF array", | |
126 | "Retire dispatch queue", | |
127 | "Mapper checkpoint array", | |
128 | "Physical register file EX0 port", | |
129 | "Physical register file EX1 port", | |
130 | "Physical register file AG0 port", | |
131 | "Physical register file AG1 port", | |
132 | "Flag register file", | |
aad19e51 AG |
133 | "DE error occurred", |
134 | "Retire status queue" | |
8259a7e5 BP |
135 | }; |
136 | ||
bc4febe9 AG |
137 | static const char * const mc6_mce_desc[] = { |
138 | "Hardware Assertion", | |
139 | "Free List", | |
140 | "Physical Register File", | |
141 | "Retire Queue", | |
142 | "Scheduler table", | |
143 | "Status Register File", | |
144 | }; | |
145 | ||
be0aec23 | 146 | /* Scalable MCA error strings */ |
856095b1 | 147 | static const char * const smca_ls_mce_desc[] = { |
e03447ee YG |
148 | "Load queue parity error", |
149 | "Store queue parity error", | |
150 | "Miss address buffer payload parity error", | |
151 | "Level 1 TLB parity error", | |
8a5dd2cd | 152 | "DC Tag error type 5", |
e03447ee YG |
153 | "DC Tag error type 6", |
154 | "DC Tag error type 1", | |
be0aec23 AG |
155 | "Internal error type 1", |
156 | "Internal error type 2", | |
e03447ee YG |
157 | "System Read Data Error Thread 0", |
158 | "System Read Data Error Thread 1", | |
159 | "DC Tag error type 2", | |
160 | "DC Data error type 1 and poison consumption", | |
161 | "DC Data error type 2", | |
162 | "DC Data error type 3", | |
163 | "DC Tag error type 4", | |
164 | "Level 2 TLB parity error", | |
be0aec23 | 165 | "PDC parity error", |
e03447ee YG |
166 | "DC Tag error type 3", |
167 | "DC Tag error type 5", | |
168 | "L2 Fill Data error", | |
be0aec23 AG |
169 | }; |
170 | ||
89a76171 YG |
171 | static const char * const smca_ls2_mce_desc[] = { |
172 | "An ECC error was detected on a data cache read by a probe or victimization", | |
173 | "An ECC error or L2 poison was detected on a data cache read by a load", | |
174 | "An ECC error was detected on a data cache read-modify-write by a store", | |
175 | "An ECC error or poison bit mismatch was detected on a tag read by a probe or victimization", | |
176 | "An ECC error or poison bit mismatch was detected on a tag read by a load", | |
177 | "An ECC error or poison bit mismatch was detected on a tag read by a store", | |
178 | "An ECC error was detected on an EMEM read by a load", | |
179 | "An ECC error was detected on an EMEM read-modify-write by a store", | |
180 | "A parity error was detected in an L1 TLB entry by any access", | |
181 | "A parity error was detected in an L2 TLB entry by any access", | |
182 | "A parity error was detected in a PWC entry by any access", | |
183 | "A parity error was detected in an STQ entry by any access", | |
184 | "A parity error was detected in an LDQ entry by any access", | |
185 | "A parity error was detected in a MAB entry by any access", | |
186 | "A parity error was detected in an SCB entry state field by any access", | |
187 | "A parity error was detected in an SCB entry address field by any access", | |
188 | "A parity error was detected in an SCB entry data field by any access", | |
189 | "A parity error was detected in a WCB entry by any access", | |
190 | "A poisoned line was detected in an SCB entry by any access", | |
191 | "A SystemReadDataError error was reported on read data returned from L2 for a load", | |
192 | "A SystemReadDataError error was reported on read data returned from L2 for an SCB store", | |
193 | "A SystemReadDataError error was reported on read data returned from L2 for a WCB store", | |
194 | "A hardware assertion error was reported", | |
195 | "A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access", | |
196 | }; | |
197 | ||
856095b1 | 198 | static const char * const smca_if_mce_desc[] = { |
e03447ee YG |
199 | "Op Cache Microtag Probe Port Parity Error", |
200 | "IC Microtag or Full Tag Multi-hit Error", | |
201 | "IC Full Tag Parity Error", | |
202 | "IC Data Array Parity Error", | |
203 | "Decoupling Queue PhysAddr Parity Error", | |
204 | "L0 ITLB Parity Error", | |
205 | "L1 ITLB Parity Error", | |
206 | "L2 ITLB Parity Error", | |
207 | "BPQ Thread 0 Snoop Parity Error", | |
208 | "BPQ Thread 1 Snoop Parity Error", | |
209 | "L1 BTB Multi-Match Error", | |
210 | "L2 BTB Multi-Match Error", | |
211 | "L2 Cache Response Poison Error", | |
212 | "System Read Data Error", | |
dc7a8476 YG |
213 | "Hardware Assertion Error", |
214 | "L1-TLB Multi-Hit", | |
215 | "L2-TLB Multi-Hit", | |
216 | "BSR Parity Error", | |
217 | "CT MCE", | |
be0aec23 AG |
218 | }; |
219 | ||
856095b1 | 220 | static const char * const smca_l2_mce_desc[] = { |
e03447ee YG |
221 | "L2M Tag Multiple-Way-Hit error", |
222 | "L2M Tag or State Array ECC Error", | |
223 | "L2M Data Array ECC Error", | |
224 | "Hardware Assert Error", | |
be0aec23 AG |
225 | }; |
226 | ||
856095b1 | 227 | static const char * const smca_de_mce_desc[] = { |
e03447ee YG |
228 | "Micro-op cache tag parity error", |
229 | "Micro-op cache data parity error", | |
230 | "Instruction buffer parity error", | |
231 | "Micro-op queue parity error", | |
232 | "Instruction dispatch queue parity error", | |
233 | "Fetch address FIFO parity error", | |
234 | "Patch RAM data parity error", | |
235 | "Patch RAM sequencer parity error", | |
dc7a8476 YG |
236 | "Micro-op buffer parity error", |
237 | "Hardware Assertion MCA Error", | |
be0aec23 AG |
238 | }; |
239 | ||
856095b1 | 240 | static const char * const smca_ex_mce_desc[] = { |
e03447ee YG |
241 | "Watchdog Timeout error", |
242 | "Physical register file parity error", | |
243 | "Flag register file parity error", | |
244 | "Immediate displacement register file parity error", | |
245 | "Address generator payload parity error", | |
246 | "EX payload parity error", | |
247 | "Checkpoint queue parity error", | |
248 | "Retire dispatch queue parity error", | |
c019b951 YG |
249 | "Retire status queue parity error", |
250 | "Scheduling queue parity error", | |
251 | "Branch buffer queue parity error", | |
8a5dd2cd | 252 | "Hardware Assertion error", |
dc7a8476 YG |
253 | "Spec Map parity error", |
254 | "Retire Map parity error", | |
be0aec23 AG |
255 | }; |
256 | ||
856095b1 | 257 | static const char * const smca_fp_mce_desc[] = { |
e03447ee YG |
258 | "Physical register file (PRF) parity error", |
259 | "Freelist (FL) parity error", | |
260 | "Schedule queue parity error", | |
be0aec23 | 261 | "NSQ parity error", |
e03447ee YG |
262 | "Retire queue (RQ) parity error", |
263 | "Status register file (SRF) parity error", | |
c019b951 | 264 | "Hardware assertion", |
be0aec23 AG |
265 | }; |
266 | ||
856095b1 | 267 | static const char * const smca_l3_mce_desc[] = { |
e03447ee YG |
268 | "Shadow Tag Macro ECC Error", |
269 | "Shadow Tag Macro Multi-way-hit Error", | |
270 | "L3M Tag ECC Error", | |
271 | "L3M Tag Multi-way-hit Error", | |
272 | "L3M Data ECC Error", | |
273 | "SDP Parity Error or SystemReadDataError from XI", | |
274 | "L3 Victim Queue Parity Error", | |
275 | "L3 Hardware Assertion", | |
be0aec23 AG |
276 | }; |
277 | ||
856095b1 | 278 | static const char * const smca_cs_mce_desc[] = { |
e03447ee YG |
279 | "Illegal Request", |
280 | "Address Violation", | |
281 | "Security Violation", | |
282 | "Illegal Response", | |
283 | "Unexpected Response", | |
284 | "Request or Probe Parity Error", | |
285 | "Read Response Parity Error", | |
286 | "Atomic Request Parity Error", | |
287 | "Probe Filter ECC Error", | |
be0aec23 AG |
288 | }; |
289 | ||
3ad7e748 YG |
290 | static const char * const smca_cs2_mce_desc[] = { |
291 | "Illegal Request", | |
292 | "Address Violation", | |
293 | "Security Violation", | |
294 | "Illegal Response", | |
295 | "Unexpected Response", | |
296 | "Request or Probe Parity Error", | |
297 | "Read Response Parity Error", | |
298 | "Atomic Request Parity Error", | |
299 | "SDP read response had no match in the CS queue", | |
300 | "Probe Filter Protocol Error", | |
301 | "Probe Filter ECC Error", | |
302 | "SDP read response had an unexpected RETRY error", | |
303 | "Counter overflow error", | |
304 | "Counter underflow error", | |
305 | }; | |
306 | ||
856095b1 | 307 | static const char * const smca_pie_mce_desc[] = { |
e03447ee YG |
308 | "Hardware Assert", |
309 | "Register security violation", | |
310 | "Link Error", | |
311 | "Poison data consumption", | |
8a5dd2cd | 312 | "A deferred error was detected in the DF" |
be0aec23 AG |
313 | }; |
314 | ||
856095b1 | 315 | static const char * const smca_umc_mce_desc[] = { |
be0aec23 | 316 | "DRAM ECC error", |
e03447ee | 317 | "Data poison error", |
be0aec23 AG |
318 | "SDP parity error", |
319 | "Advanced peripheral bus error", | |
e03447ee | 320 | "Address/Command parity error", |
be0aec23 | 321 | "Write data CRC error", |
8a5dd2cd YG |
322 | "DCQ SRAM ECC error", |
323 | "AES SRAM ECC error", | |
be0aec23 AG |
324 | }; |
325 | ||
856095b1 | 326 | static const char * const smca_pb_mce_desc[] = { |
e03447ee | 327 | "An ECC error in the Parameter Block RAM array", |
be0aec23 AG |
328 | }; |
329 | ||
856095b1 | 330 | static const char * const smca_psp_mce_desc[] = { |
e03447ee | 331 | "An ECC or parity error in a PSP RAM instance", |
be0aec23 AG |
332 | }; |
333 | ||
3ad7e748 YG |
334 | static const char * const smca_psp2_mce_desc[] = { |
335 | "High SRAM ECC or parity error", | |
336 | "Low SRAM ECC or parity error", | |
337 | "Instruction Cache Bank 0 ECC or parity error", | |
338 | "Instruction Cache Bank 1 ECC or parity error", | |
339 | "Instruction Tag Ram 0 parity error", | |
340 | "Instruction Tag Ram 1 parity error", | |
341 | "Data Cache Bank 0 ECC or parity error", | |
342 | "Data Cache Bank 1 ECC or parity error", | |
343 | "Data Cache Bank 2 ECC or parity error", | |
344 | "Data Cache Bank 3 ECC or parity error", | |
345 | "Data Tag Bank 0 parity error", | |
346 | "Data Tag Bank 1 parity error", | |
347 | "Data Tag Bank 2 parity error", | |
348 | "Data Tag Bank 3 parity error", | |
349 | "Dirty Data Ram parity error", | |
350 | "TLB Bank 0 parity error", | |
351 | "TLB Bank 1 parity error", | |
352 | "System Hub Read Buffer ECC or parity error", | |
353 | }; | |
354 | ||
856095b1 | 355 | static const char * const smca_smu_mce_desc[] = { |
e03447ee | 356 | "An ECC or parity error in an SMU RAM instance", |
be0aec23 AG |
357 | }; |
358 | ||
3ad7e748 YG |
359 | static const char * const smca_smu2_mce_desc[] = { |
360 | "High SRAM ECC or parity error", | |
361 | "Low SRAM ECC or parity error", | |
362 | "Data Cache Bank A ECC or parity error", | |
363 | "Data Cache Bank B ECC or parity error", | |
364 | "Data Tag Cache Bank A ECC or parity error", | |
365 | "Data Tag Cache Bank B ECC or parity error", | |
366 | "Instruction Cache Bank A ECC or parity error", | |
367 | "Instruction Cache Bank B ECC or parity error", | |
368 | "Instruction Tag Cache Bank A ECC or parity error", | |
369 | "Instruction Tag Cache Bank B ECC or parity error", | |
370 | "System Hub Read Buffer ECC or parity error", | |
dc7a8476 | 371 | "PHY RAM ECC error", |
3ad7e748 YG |
372 | }; |
373 | ||
cbfa447e YG |
374 | static const char * const smca_mp5_mce_desc[] = { |
375 | "High SRAM ECC or parity error", | |
376 | "Low SRAM ECC or parity error", | |
377 | "Data Cache Bank A ECC or parity error", | |
378 | "Data Cache Bank B ECC or parity error", | |
379 | "Data Tag Cache Bank A ECC or parity error", | |
380 | "Data Tag Cache Bank B ECC or parity error", | |
381 | "Instruction Cache Bank A ECC or parity error", | |
382 | "Instruction Cache Bank B ECC or parity error", | |
383 | "Instruction Tag Cache Bank A ECC or parity error", | |
384 | "Instruction Tag Cache Bank B ECC or parity error", | |
385 | }; | |
386 | ||
387 | static const char * const smca_nbio_mce_desc[] = { | |
388 | "ECC or Parity error", | |
389 | "PCIE error", | |
390 | "SDP ErrEvent error", | |
391 | "SDP Egress Poison Error", | |
392 | "IOHC Internal Poison Error", | |
393 | }; | |
394 | ||
395 | static const char * const smca_pcie_mce_desc[] = { | |
396 | "CCIX PER Message logging", | |
397 | "CCIX Read Response with Status: Non-Data Error", | |
398 | "CCIX Write Response with Status: Non-Data Error", | |
399 | "CCIX Read Response with Status: Data Error", | |
400 | "CCIX Non-okay write response with data error", | |
401 | }; | |
402 | ||
5896820e YG |
403 | struct smca_mce_desc { |
404 | const char * const *descs; | |
405 | unsigned int num_descs; | |
406 | }; | |
407 | ||
408 | static struct smca_mce_desc smca_mce_descs[] = { | |
409 | [SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) }, | |
89a76171 | 410 | [SMCA_LS_V2] = { smca_ls2_mce_desc, ARRAY_SIZE(smca_ls2_mce_desc) }, |
5896820e YG |
411 | [SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) }, |
412 | [SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) }, | |
413 | [SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) }, | |
414 | [SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) }, | |
415 | [SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) }, | |
416 | [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) }, | |
417 | [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) }, | |
3ad7e748 | 418 | [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) }, |
5896820e YG |
419 | [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) }, |
420 | [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) }, | |
421 | [SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) }, | |
422 | [SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) }, | |
3ad7e748 | 423 | [SMCA_PSP_V2] = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc) }, |
5896820e | 424 | [SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) }, |
3ad7e748 | 425 | [SMCA_SMU_V2] = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc) }, |
cbfa447e YG |
426 | [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) }, |
427 | [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) }, | |
428 | [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) }, | |
5896820e YG |
429 | }; |
430 | ||
f05c41a9 | 431 | static bool f12h_mc0_mce(u16 ec, u8 xec) |
51966241 | 432 | { |
888ab8e6 | 433 | bool ret = false; |
51966241 | 434 | |
888ab8e6 | 435 | if (MEM_ERROR(ec)) { |
62452882 | 436 | u8 ll = LL(ec); |
888ab8e6 | 437 | ret = true; |
51966241 | 438 | |
888ab8e6 BP |
439 | if (ll == LL_L2) |
440 | pr_cont("during L1 linefill from L2.\n"); | |
441 | else if (ll == LL_L1) | |
62452882 | 442 | pr_cont("Data/Tag %s error.\n", R4_MSG(ec)); |
888ab8e6 BP |
443 | else |
444 | ret = false; | |
445 | } | |
446 | return ret; | |
447 | } | |
51966241 | 448 | |
f05c41a9 | 449 | static bool f10h_mc0_mce(u16 ec, u8 xec) |
9be0bb10 | 450 | { |
62452882 | 451 | if (R4(ec) == R4_GEN && LL(ec) == LL_L1) { |
9be0bb10 BP |
452 | pr_cont("during data scrub.\n"); |
453 | return true; | |
454 | } | |
f05c41a9 | 455 | return f12h_mc0_mce(ec, xec); |
9be0bb10 BP |
456 | } |
457 | ||
f05c41a9 | 458 | static bool k8_mc0_mce(u16 ec, u8 xec) |
888ab8e6 BP |
459 | { |
460 | if (BUS_ERROR(ec)) { | |
461 | pr_cont("during system linefill.\n"); | |
462 | return true; | |
463 | } | |
51966241 | 464 | |
f05c41a9 | 465 | return f10h_mc0_mce(ec, xec); |
888ab8e6 BP |
466 | } |
467 | ||
980eec8b | 468 | static bool cat_mc0_mce(u16 ec, u8 xec) |
888ab8e6 | 469 | { |
62452882 | 470 | u8 r4 = R4(ec); |
888ab8e6 BP |
471 | bool ret = true; |
472 | ||
473 | if (MEM_ERROR(ec)) { | |
474 | ||
62452882 | 475 | if (TT(ec) != TT_DATA || LL(ec) != LL_L1) |
888ab8e6 BP |
476 | return false; |
477 | ||
478 | switch (r4) { | |
479 | case R4_DRD: | |
480 | case R4_DWR: | |
481 | pr_cont("Data/Tag parity error due to %s.\n", | |
482 | (r4 == R4_DRD ? "load/hw prf" : "store")); | |
483 | break; | |
484 | case R4_EVICT: | |
485 | pr_cont("Copyback parity error on a tag miss.\n"); | |
486 | break; | |
487 | case R4_SNOOP: | |
488 | pr_cont("Tag parity error during snoop.\n"); | |
489 | break; | |
490 | default: | |
491 | ret = false; | |
492 | } | |
493 | } else if (BUS_ERROR(ec)) { | |
494 | ||
62452882 | 495 | if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) |
888ab8e6 BP |
496 | return false; |
497 | ||
498 | pr_cont("System read data error on a "); | |
499 | ||
500 | switch (r4) { | |
501 | case R4_RD: | |
502 | pr_cont("TLB reload.\n"); | |
503 | break; | |
504 | case R4_DWR: | |
505 | pr_cont("store.\n"); | |
506 | break; | |
507 | case R4_DRD: | |
508 | pr_cont("load.\n"); | |
509 | break; | |
510 | default: | |
511 | ret = false; | |
512 | } | |
513 | } else { | |
514 | ret = false; | |
515 | } | |
516 | ||
517 | return ret; | |
518 | } | |
519 | ||
f05c41a9 | 520 | static bool f15h_mc0_mce(u16 ec, u8 xec) |
25a4f8b0 BP |
521 | { |
522 | bool ret = true; | |
523 | ||
524 | if (MEM_ERROR(ec)) { | |
525 | ||
526 | switch (xec) { | |
527 | case 0x0: | |
528 | pr_cont("Data Array access error.\n"); | |
529 | break; | |
530 | ||
531 | case 0x1: | |
532 | pr_cont("UC error during a linefill from L2/NB.\n"); | |
533 | break; | |
534 | ||
535 | case 0x2: | |
536 | case 0x11: | |
537 | pr_cont("STQ access error.\n"); | |
538 | break; | |
539 | ||
540 | case 0x3: | |
541 | pr_cont("SCB access error.\n"); | |
542 | break; | |
543 | ||
544 | case 0x10: | |
545 | pr_cont("Tag error.\n"); | |
546 | break; | |
547 | ||
548 | case 0x12: | |
549 | pr_cont("LDQ access error.\n"); | |
550 | break; | |
551 | ||
552 | default: | |
553 | ret = false; | |
554 | } | |
555 | } else if (BUS_ERROR(ec)) { | |
556 | ||
557 | if (!xec) | |
344f0a06 | 558 | pr_cont("System Read Data Error.\n"); |
25a4f8b0 | 559 | else |
344f0a06 | 560 | pr_cont(" Internal error condition type %d.\n", xec); |
eba4bfb3 AG |
561 | } else if (INT_ERROR(ec)) { |
562 | if (xec <= 0x1f) | |
563 | pr_cont("Hardware Assert.\n"); | |
564 | else | |
565 | ret = false; | |
566 | ||
25a4f8b0 BP |
567 | } else |
568 | ret = false; | |
569 | ||
570 | return ret; | |
571 | } | |
572 | ||
f05c41a9 | 573 | static void decode_mc0_mce(struct mce *m) |
888ab8e6 | 574 | { |
62452882 BP |
575 | u16 ec = EC(m->status); |
576 | u8 xec = XEC(m->status, xec_mask); | |
888ab8e6 | 577 | |
f05c41a9 | 578 | pr_emerg(HW_ERR "MC0 Error: "); |
888ab8e6 BP |
579 | |
580 | /* TLB error signatures are the same across families */ | |
581 | if (TLB_ERROR(ec)) { | |
62452882 | 582 | if (TT(ec) == TT_DATA) { |
888ab8e6 | 583 | pr_cont("%s TLB %s.\n", LL_MSG(ec), |
25a4f8b0 BP |
584 | ((xec == 2) ? "locked miss" |
585 | : (xec ? "multimatch" : "parity"))); | |
888ab8e6 BP |
586 | return; |
587 | } | |
86e9f9d6 | 588 | } else if (fam_ops.mc0_mce(ec, xec)) |
25a4f8b0 BP |
589 | ; |
590 | else | |
f05c41a9 | 591 | pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n"); |
51966241 BP |
592 | } |
593 | ||
f05c41a9 | 594 | static bool k8_mc1_mce(u16 ec, u8 xec) |
ab5535e7 | 595 | { |
62452882 | 596 | u8 ll = LL(ec); |
dd53bce4 | 597 | bool ret = true; |
ab5535e7 | 598 | |
dd53bce4 BP |
599 | if (!MEM_ERROR(ec)) |
600 | return false; | |
ab5535e7 | 601 | |
dd53bce4 BP |
602 | if (ll == 0x2) |
603 | pr_cont("during a linefill from L2.\n"); | |
604 | else if (ll == 0x1) { | |
62452882 | 605 | switch (R4(ec)) { |
dd53bce4 BP |
606 | case R4_IRD: |
607 | pr_cont("Parity error during data load.\n"); | |
608 | break; | |
ab5535e7 | 609 | |
dd53bce4 BP |
610 | case R4_EVICT: |
611 | pr_cont("Copyback Parity/Victim error.\n"); | |
612 | break; | |
613 | ||
614 | case R4_SNOOP: | |
615 | pr_cont("Tag Snoop error.\n"); | |
616 | break; | |
617 | ||
618 | default: | |
619 | ret = false; | |
620 | break; | |
621 | } | |
ab5535e7 | 622 | } else |
dd53bce4 | 623 | ret = false; |
ab5535e7 | 624 | |
dd53bce4 BP |
625 | return ret; |
626 | } | |
627 | ||
980eec8b | 628 | static bool cat_mc1_mce(u16 ec, u8 xec) |
dd53bce4 | 629 | { |
62452882 | 630 | u8 r4 = R4(ec); |
dd53bce4 | 631 | bool ret = true; |
ab5535e7 | 632 | |
980eec8b JS |
633 | if (!MEM_ERROR(ec)) |
634 | return false; | |
635 | ||
636 | if (TT(ec) != TT_INSTR) | |
637 | return false; | |
638 | ||
639 | if (r4 == R4_IRD) | |
640 | pr_cont("Data/tag array parity error for a tag hit.\n"); | |
641 | else if (r4 == R4_SNOOP) | |
642 | pr_cont("Tag error during snoop/victimization.\n"); | |
643 | else if (xec == 0x0) | |
644 | pr_cont("Tag parity error from victim castout.\n"); | |
645 | else if (xec == 0x2) | |
646 | pr_cont("Microcode patch RAM parity error.\n"); | |
647 | else | |
648 | ret = false; | |
dd53bce4 | 649 | |
dd53bce4 BP |
650 | return ret; |
651 | } | |
652 | ||
f05c41a9 | 653 | static bool f15h_mc1_mce(u16 ec, u8 xec) |
86039cd4 BP |
654 | { |
655 | bool ret = true; | |
656 | ||
657 | if (!MEM_ERROR(ec)) | |
658 | return false; | |
659 | ||
660 | switch (xec) { | |
661 | case 0x0 ... 0xa: | |
f05c41a9 | 662 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec]); |
86039cd4 BP |
663 | break; |
664 | ||
665 | case 0xd: | |
f05c41a9 | 666 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]); |
86039cd4 BP |
667 | break; |
668 | ||
6c1173a6 | 669 | case 0x10: |
f05c41a9 | 670 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); |
6c1173a6 BP |
671 | break; |
672 | ||
eba4bfb3 | 673 | case 0x11 ... 0x15: |
f05c41a9 | 674 | pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); |
86039cd4 BP |
675 | break; |
676 | ||
677 | default: | |
678 | ret = false; | |
679 | } | |
680 | return ret; | |
681 | } | |
682 | ||
f05c41a9 | 683 | static void decode_mc1_mce(struct mce *m) |
dd53bce4 | 684 | { |
62452882 BP |
685 | u16 ec = EC(m->status); |
686 | u8 xec = XEC(m->status, xec_mask); | |
dd53bce4 | 687 | |
f05c41a9 | 688 | pr_emerg(HW_ERR "MC1 Error: "); |
dd53bce4 BP |
689 | |
690 | if (TLB_ERROR(ec)) | |
691 | pr_cont("%s TLB %s.\n", LL_MSG(ec), | |
692 | (xec ? "multimatch" : "parity error")); | |
693 | else if (BUS_ERROR(ec)) { | |
525906bc | 694 | bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); |
dd53bce4 BP |
695 | |
696 | pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); | |
eba4bfb3 AG |
697 | } else if (INT_ERROR(ec)) { |
698 | if (xec <= 0x3f) | |
699 | pr_cont("Hardware Assert.\n"); | |
700 | else | |
701 | goto wrong_mc1_mce; | |
86e9f9d6 | 702 | } else if (fam_ops.mc1_mce(ec, xec)) |
dd53bce4 BP |
703 | ; |
704 | else | |
eba4bfb3 AG |
705 | goto wrong_mc1_mce; |
706 | ||
707 | return; | |
708 | ||
709 | wrong_mc1_mce: | |
710 | pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); | |
ab5535e7 BP |
711 | } |
712 | ||
4a73d3de | 713 | static bool k8_mc2_mce(u16 ec, u8 xec) |
56cad2d6 | 714 | { |
4a73d3de | 715 | bool ret = true; |
56cad2d6 BP |
716 | |
717 | if (xec == 0x1) | |
718 | pr_cont(" in the write data buffers.\n"); | |
719 | else if (xec == 0x3) | |
720 | pr_cont(" in the victim data buffers.\n"); | |
721 | else if (xec == 0x2 && MEM_ERROR(ec)) | |
62452882 | 722 | pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); |
56cad2d6 BP |
723 | else if (xec == 0x0) { |
724 | if (TLB_ERROR(ec)) | |
50872ccd BP |
725 | pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n", |
726 | TT_MSG(ec)); | |
56cad2d6 BP |
727 | else if (BUS_ERROR(ec)) |
728 | pr_cont(": %s/ECC error in data read from NB: %s.\n", | |
62452882 | 729 | R4_MSG(ec), PP_MSG(ec)); |
56cad2d6 | 730 | else if (MEM_ERROR(ec)) { |
62452882 | 731 | u8 r4 = R4(ec); |
56cad2d6 | 732 | |
62452882 | 733 | if (r4 >= 0x7) |
56cad2d6 | 734 | pr_cont(": %s error during data copyback.\n", |
62452882 BP |
735 | R4_MSG(ec)); |
736 | else if (r4 <= 0x1) | |
56cad2d6 | 737 | pr_cont(": %s parity/ECC error during data " |
62452882 | 738 | "access from L2.\n", R4_MSG(ec)); |
56cad2d6 | 739 | else |
4a73d3de | 740 | ret = false; |
56cad2d6 | 741 | } else |
4a73d3de | 742 | ret = false; |
56cad2d6 | 743 | } else |
4a73d3de | 744 | ret = false; |
56cad2d6 | 745 | |
4a73d3de | 746 | return ret; |
56cad2d6 BP |
747 | } |
748 | ||
4a73d3de | 749 | static bool f15h_mc2_mce(u16 ec, u8 xec) |
70fdb494 | 750 | { |
4a73d3de | 751 | bool ret = true; |
70fdb494 BP |
752 | |
753 | if (TLB_ERROR(ec)) { | |
754 | if (xec == 0x0) | |
755 | pr_cont("Data parity TLB read error.\n"); | |
756 | else if (xec == 0x1) | |
757 | pr_cont("Poison data provided for TLB fill.\n"); | |
758 | else | |
4a73d3de | 759 | ret = false; |
70fdb494 BP |
760 | } else if (BUS_ERROR(ec)) { |
761 | if (xec > 2) | |
4a73d3de | 762 | ret = false; |
70fdb494 BP |
763 | |
764 | pr_cont("Error during attempted NB data read.\n"); | |
765 | } else if (MEM_ERROR(ec)) { | |
766 | switch (xec) { | |
767 | case 0x4 ... 0xc: | |
f05c41a9 | 768 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); |
70fdb494 BP |
769 | break; |
770 | ||
771 | case 0x10 ... 0x14: | |
f05c41a9 | 772 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); |
70fdb494 BP |
773 | break; |
774 | ||
775 | default: | |
4a73d3de | 776 | ret = false; |
70fdb494 | 777 | } |
eba4bfb3 AG |
778 | } else if (INT_ERROR(ec)) { |
779 | if (xec <= 0x3f) | |
780 | pr_cont("Hardware Assert.\n"); | |
781 | else | |
782 | ret = false; | |
70fdb494 BP |
783 | } |
784 | ||
4a73d3de JS |
785 | return ret; |
786 | } | |
787 | ||
980eec8b JS |
788 | static bool f16h_mc2_mce(u16 ec, u8 xec) |
789 | { | |
790 | u8 r4 = R4(ec); | |
791 | ||
792 | if (!MEM_ERROR(ec)) | |
793 | return false; | |
794 | ||
795 | switch (xec) { | |
796 | case 0x04 ... 0x05: | |
797 | pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); | |
798 | break; | |
799 | ||
800 | case 0x09 ... 0x0b: | |
801 | case 0x0d ... 0x0f: | |
802 | pr_cont("ECC error in L2 tag (%s).\n", | |
803 | ((r4 == R4_GEN) ? "BankReq" : | |
804 | ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); | |
805 | break; | |
806 | ||
807 | case 0x10 ... 0x19: | |
808 | case 0x1b: | |
809 | pr_cont("ECC error in L2 data array (%s).\n", | |
810 | (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : | |
811 | ((r4 == R4_GEN) ? "Attr" : | |
812 | ((r4 == R4_EVICT) ? "Vict" : "Fill")))); | |
813 | break; | |
814 | ||
815 | case 0x1c ... 0x1d: | |
816 | case 0x1f: | |
817 | pr_cont("Parity error in L2 attribute bits (%s).\n", | |
818 | ((r4 == R4_RD) ? "Hit" : | |
819 | ((r4 == R4_GEN) ? "Attr" : "Fill"))); | |
820 | break; | |
821 | ||
822 | default: | |
823 | return false; | |
824 | } | |
825 | ||
826 | return true; | |
827 | } | |
828 | ||
4a73d3de JS |
829 | static void decode_mc2_mce(struct mce *m) |
830 | { | |
831 | u16 ec = EC(m->status); | |
832 | u8 xec = XEC(m->status, xec_mask); | |
70fdb494 | 833 | |
4a73d3de JS |
834 | pr_emerg(HW_ERR "MC2 Error: "); |
835 | ||
86e9f9d6 | 836 | if (!fam_ops.mc2_mce(ec, xec)) |
4a73d3de | 837 | pr_cont(HW_ERR "Corrupted MC2 MCE info?\n"); |
70fdb494 BP |
838 | } |
839 | ||
f05c41a9 | 840 | static void decode_mc3_mce(struct mce *m) |
f9350efd | 841 | { |
62452882 BP |
842 | u16 ec = EC(m->status); |
843 | u8 xec = XEC(m->status, xec_mask); | |
ded50623 | 844 | |
b18434ca | 845 | if (boot_cpu_data.x86 >= 0x14) { |
f05c41a9 | 846 | pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family," |
ded50623 BP |
847 | " please report on LKML.\n"); |
848 | return; | |
849 | } | |
f9350efd | 850 | |
f05c41a9 | 851 | pr_emerg(HW_ERR "MC3 Error"); |
f9350efd BP |
852 | |
853 | if (xec == 0x0) { | |
62452882 | 854 | u8 r4 = R4(ec); |
f9350efd | 855 | |
ded50623 | 856 | if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR)) |
f05c41a9 | 857 | goto wrong_mc3_mce; |
f9350efd | 858 | |
62452882 | 859 | pr_cont(" during %s.\n", R4_MSG(ec)); |
ded50623 | 860 | } else |
f05c41a9 | 861 | goto wrong_mc3_mce; |
ded50623 | 862 | |
f9350efd BP |
863 | return; |
864 | ||
f05c41a9 BP |
865 | wrong_mc3_mce: |
866 | pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n"); | |
f9350efd BP |
867 | } |
868 | ||
f05c41a9 | 869 | static void decode_mc4_mce(struct mce *m) |
5ce88f6e | 870 | { |
f3c0891c | 871 | unsigned int fam = x86_family(m->cpuid); |
db970bd2 | 872 | int node_id = topology_die_id(m->extcpu); |
68782673 BP |
873 | u16 ec = EC(m->status); |
874 | u8 xec = XEC(m->status, 0x1f); | |
875 | u8 offset = 0; | |
5ce88f6e | 876 | |
f05c41a9 | 877 | pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); |
5ce88f6e | 878 | |
68782673 BP |
879 | switch (xec) { |
880 | case 0x0 ... 0xe: | |
5ce88f6e | 881 | |
68782673 BP |
882 | /* special handling for DRAM ECCs */ |
883 | if (xec == 0x0 || xec == 0x8) { | |
884 | /* no ECCs on F11h */ | |
f3c0891c | 885 | if (fam == 0x11) |
f05c41a9 | 886 | goto wrong_mc4_mce; |
5ce88f6e | 887 | |
f05c41a9 | 888 | pr_cont("%s.\n", mc4_mce_desc[xec]); |
5ce88f6e | 889 | |
5c332202 YG |
890 | if (decode_dram_ecc) |
891 | decode_dram_ecc(node_id, m); | |
68782673 BP |
892 | return; |
893 | } | |
5ce88f6e BP |
894 | break; |
895 | ||
896 | case 0xf: | |
897 | if (TLB_ERROR(ec)) | |
898 | pr_cont("GART Table Walk data error.\n"); | |
899 | else if (BUS_ERROR(ec)) | |
900 | pr_cont("DMA Exclusion Vector Table Walk error.\n"); | |
901 | else | |
f05c41a9 | 902 | goto wrong_mc4_mce; |
68782673 | 903 | return; |
5ce88f6e | 904 | |
05cd667d | 905 | case 0x19: |
f3c0891c | 906 | if (fam == 0x15 || fam == 0x16) |
05cd667d BP |
907 | pr_cont("Compute Unit Data Error.\n"); |
908 | else | |
f05c41a9 | 909 | goto wrong_mc4_mce; |
68782673 | 910 | return; |
05cd667d | 911 | |
5ce88f6e | 912 | case 0x1c ... 0x1f: |
68782673 | 913 | offset = 13; |
5ce88f6e BP |
914 | break; |
915 | ||
916 | default: | |
f05c41a9 | 917 | goto wrong_mc4_mce; |
68782673 | 918 | } |
5ce88f6e | 919 | |
f05c41a9 | 920 | pr_cont("%s.\n", mc4_mce_desc[xec - offset]); |
5ce88f6e BP |
921 | return; |
922 | ||
f05c41a9 BP |
923 | wrong_mc4_mce: |
924 | pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); | |
d93cc222 | 925 | } |
d93cc222 | 926 | |
f05c41a9 | 927 | static void decode_mc5_mce(struct mce *m) |
53bd5fed | 928 | { |
f3c0891c | 929 | unsigned int fam = x86_family(m->cpuid); |
eba4bfb3 | 930 | u16 ec = EC(m->status); |
62452882 | 931 | u8 xec = XEC(m->status, xec_mask); |
8259a7e5 | 932 | |
f3c0891c | 933 | if (fam == 0xf || fam == 0x11) |
f05c41a9 | 934 | goto wrong_mc5_mce; |
fe4ea262 | 935 | |
f05c41a9 | 936 | pr_emerg(HW_ERR "MC5 Error: "); |
8259a7e5 | 937 | |
eba4bfb3 AG |
938 | if (INT_ERROR(ec)) { |
939 | if (xec <= 0x1f) { | |
940 | pr_cont("Hardware Assert.\n"); | |
941 | return; | |
942 | } else | |
943 | goto wrong_mc5_mce; | |
944 | } | |
945 | ||
8259a7e5 | 946 | if (xec == 0x0 || xec == 0xc) |
f05c41a9 | 947 | pr_cont("%s.\n", mc5_mce_desc[xec]); |
aad19e51 | 948 | else if (xec <= 0xd) |
f05c41a9 | 949 | pr_cont("%s parity error.\n", mc5_mce_desc[xec]); |
8259a7e5 | 950 | else |
f05c41a9 | 951 | goto wrong_mc5_mce; |
8259a7e5 BP |
952 | |
953 | return; | |
fe4ea262 | 954 | |
f05c41a9 BP |
955 | wrong_mc5_mce: |
956 | pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n"); | |
53bd5fed BP |
957 | } |
958 | ||
f05c41a9 | 959 | static void decode_mc6_mce(struct mce *m) |
b8f85c47 | 960 | { |
62452882 | 961 | u8 xec = XEC(m->status, xec_mask); |
b8f85c47 | 962 | |
f05c41a9 | 963 | pr_emerg(HW_ERR "MC6 Error: "); |
b8f85c47 | 964 | |
bc4febe9 | 965 | if (xec > 0x5) |
f05c41a9 | 966 | goto wrong_mc6_mce; |
b8f85c47 | 967 | |
bc4febe9 | 968 | pr_cont("%s parity error.\n", mc6_mce_desc[xec]); |
b8f85c47 BP |
969 | return; |
970 | ||
f05c41a9 BP |
971 | wrong_mc6_mce: |
972 | pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); | |
b8f85c47 BP |
973 | } |
974 | ||
be0aec23 | 975 | /* Decode errors according to Scalable MCA specification */ |
4ab1784b | 976 | static void decode_smca_error(struct mce *m) |
be0aec23 | 977 | { |
1ce9cd7f | 978 | struct smca_hwid *hwid; |
68627a69 | 979 | enum smca_bank_types bank_type; |
be0aec23 | 980 | const char *ip_name; |
5896820e | 981 | u8 xec = XEC(m->status, xec_mask); |
be0aec23 | 982 | |
5896820e | 983 | if (m->bank >= ARRAY_SIZE(smca_banks)) |
be0aec23 | 984 | return; |
be0aec23 | 985 | |
1ce9cd7f BP |
986 | hwid = smca_banks[m->bank].hwid; |
987 | if (!hwid) | |
be0aec23 | 988 | return; |
be0aec23 | 989 | |
1ce9cd7f | 990 | bank_type = hwid->bank_type; |
68627a69 YG |
991 | |
992 | if (bank_type == SMCA_RESERVED) { | |
993 | pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); | |
994 | return; | |
995 | } | |
996 | ||
c09a8c40 | 997 | ip_name = smca_get_long_name(bank_type); |
be0aec23 | 998 | |
1c1522d3 | 999 | pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec); |
be0aec23 | 1000 | |
5896820e | 1001 | /* Only print the decode of valid error codes */ |
368d1887 | 1002 | if (xec < smca_mce_descs[bank_type].num_descs) |
1c1522d3 | 1003 | pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]); |
5c332202 | 1004 | |
5c332202 | 1005 | if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc) |
8de0c991 | 1006 | decode_dram_ecc(topology_die_id(m->extcpu), m); |
be0aec23 AG |
1007 | } |
1008 | ||
6337583d | 1009 | static inline void amd_decode_err_code(u16 ec) |
d93cc222 | 1010 | { |
980eec8b JS |
1011 | if (INT_ERROR(ec)) { |
1012 | pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec)); | |
1013 | return; | |
1014 | } | |
fa7ae8cc BP |
1015 | |
1016 | pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec)); | |
1017 | ||
1018 | if (BUS_ERROR(ec)) | |
1019 | pr_cont(", mem/io: %s", II_MSG(ec)); | |
1020 | else | |
1021 | pr_cont(", tx: %s", TT_MSG(ec)); | |
1022 | ||
1023 | if (MEM_ERROR(ec) || BUS_ERROR(ec)) { | |
1024 | pr_cont(", mem-tx: %s", R4_MSG(ec)); | |
1025 | ||
1026 | if (BUS_ERROR(ec)) | |
1027 | pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec)); | |
1028 | } | |
1029 | ||
1030 | pr_cont("\n"); | |
549d042d | 1031 | } |
549d042d | 1032 | |
d5c6770d BP |
1033 | static const char *decode_error_status(struct mce *m) |
1034 | { | |
1035 | if (m->status & MCI_STATUS_UC) { | |
1036 | if (m->status & MCI_STATUS_PCC) | |
1037 | return "System Fatal error."; | |
1038 | if (m->mcgstatus & MCG_STATUS_RIPV) | |
1039 | return "Uncorrected, software restartable error."; | |
1040 | return "Uncorrected, software containable error."; | |
1041 | } | |
1042 | ||
1043 | if (m->status & MCI_STATUS_DEFERRED) | |
67d7fd30 | 1044 | return "Deferred error, no action required."; |
d5c6770d BP |
1045 | |
1046 | return "Corrected error, no action required."; | |
1047 | } | |
1048 | ||
1fbcd909 BP |
1049 | static int |
1050 | amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) | |
549d042d | 1051 | { |
fb253195 | 1052 | struct mce *m = (struct mce *)data; |
f3c0891c | 1053 | unsigned int fam = x86_family(m->cpuid); |
b0b07a2b | 1054 | int ecc; |
549d042d | 1055 | |
23ba710a TL |
1056 | if (m->kflags & MCE_HANDLED_CEC) |
1057 | return NOTIFY_DONE; | |
1058 | ||
fd0f5fff BP |
1059 | pr_emerg(HW_ERR "%s\n", decode_error_status(m)); |
1060 | ||
1061 | pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", | |
1062 | m->extcpu, | |
f3c0891c | 1063 | fam, x86_model(m->cpuid), x86_stepping(m->cpuid), |
fd0f5fff BP |
1064 | m->bank, |
1065 | ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), | |
99e1dfb7 AG |
1066 | ((m->status & MCI_STATUS_UC) ? "UE" : |
1067 | (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), | |
fd0f5fff | 1068 | ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), |
a0bcd3c0 YG |
1069 | ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), |
1070 | ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); | |
fd0f5fff | 1071 | |
a348ed83 | 1072 | if (boot_cpu_has(X86_FEATURE_SMCA)) { |
be0aec23 AG |
1073 | u32 low, high; |
1074 | u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); | |
1075 | ||
1076 | if (!rdmsr_safe(addr, &low, &high) && | |
1077 | (low & MCI_CONFIG_MCAX)) | |
1078 | pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); | |
a0bcd3c0 YG |
1079 | |
1080 | pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); | |
be0aec23 AG |
1081 | } |
1082 | ||
fd0f5fff BP |
1083 | /* do the two bits[14:13] together */ |
1084 | ecc = (m->status >> 45) & 0x3; | |
1085 | if (ecc) | |
1086 | pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); | |
1087 | ||
a0bcd3c0 YG |
1088 | if (fam >= 0x15) { |
1089 | pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); | |
1090 | ||
1091 | /* F15h, bank4, bit 43 is part of McaStatSubCache. */ | |
1092 | if (fam != 0x15 || m->bank != 4) | |
1093 | pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); | |
1094 | } | |
1095 | ||
3f4da372 YG |
1096 | if (fam >= 0x17) |
1097 | pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); | |
1098 | ||
fd0f5fff BP |
1099 | pr_cont("]: 0x%016llx\n", m->status); |
1100 | ||
1101 | if (m->status & MCI_STATUS_ADDRV) | |
75bf2f64 | 1102 | pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr); |
fd0f5fff | 1103 | |
bb2de0ad SK |
1104 | if (m->ppin) |
1105 | pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin); | |
1106 | ||
a348ed83 | 1107 | if (boot_cpu_has(X86_FEATURE_SMCA)) { |
75bf2f64 YG |
1108 | pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); |
1109 | ||
b300e873 YG |
1110 | if (m->status & MCI_STATUS_SYNDV) |
1111 | pr_cont(", Syndrome: 0x%016llx", m->synd); | |
1112 | ||
1113 | pr_cont("\n"); | |
1114 | ||
4ab1784b | 1115 | decode_smca_error(m); |
be0aec23 | 1116 | goto err_code; |
75bf2f64 | 1117 | } |
be0aec23 | 1118 | |
0bceab67 BP |
1119 | if (m->tsc) |
1120 | pr_emerg(HW_ERR "TSC: %llu\n", m->tsc); | |
1121 | ||
86e9f9d6 BP |
1122 | /* Doesn't matter which member to test. */ |
1123 | if (!fam_ops.mc0_mce) | |
fd0f5fff BP |
1124 | goto err_code; |
1125 | ||
51966241 BP |
1126 | switch (m->bank) { |
1127 | case 0: | |
f05c41a9 | 1128 | decode_mc0_mce(m); |
51966241 | 1129 | break; |
d93cc222 | 1130 | |
ab5535e7 | 1131 | case 1: |
f05c41a9 | 1132 | decode_mc1_mce(m); |
ab5535e7 BP |
1133 | break; |
1134 | ||
56cad2d6 | 1135 | case 2: |
4a73d3de | 1136 | decode_mc2_mce(m); |
56cad2d6 BP |
1137 | break; |
1138 | ||
f9350efd | 1139 | case 3: |
f05c41a9 | 1140 | decode_mc3_mce(m); |
f9350efd BP |
1141 | break; |
1142 | ||
51966241 | 1143 | case 4: |
f05c41a9 | 1144 | decode_mc4_mce(m); |
51966241 BP |
1145 | break; |
1146 | ||
53bd5fed | 1147 | case 5: |
f05c41a9 | 1148 | decode_mc5_mce(m); |
53bd5fed BP |
1149 | break; |
1150 | ||
b8f85c47 | 1151 | case 6: |
f05c41a9 | 1152 | decode_mc6_mce(m); |
b8f85c47 BP |
1153 | break; |
1154 | ||
51966241 BP |
1155 | default: |
1156 | break; | |
b69b29de | 1157 | } |
51966241 | 1158 | |
fd0f5fff | 1159 | err_code: |
51966241 | 1160 | amd_decode_err_code(m->status & 0xffff); |
fb253195 | 1161 | |
23ba710a TL |
1162 | m->kflags |= MCE_HANDLED_EDAC; |
1163 | return NOTIFY_OK; | |
549d042d | 1164 | } |
f436f8bb | 1165 | |
fb253195 BP |
1166 | static struct notifier_block amd_mce_dec_nb = { |
1167 | .notifier_call = amd_decode_mce, | |
9026cc82 | 1168 | .priority = MCE_PRIO_EDAC, |
fb253195 BP |
1169 | }; |
1170 | ||
f436f8bb IM |
1171 | static int __init mce_amd_init(void) |
1172 | { | |
bad11e03 BP |
1173 | struct cpuinfo_x86 *c = &boot_cpu_data; |
1174 | ||
c4a3e946 PW |
1175 | if (c->x86_vendor != X86_VENDOR_AMD && |
1176 | c->x86_vendor != X86_VENDOR_HYGON) | |
fd0f5fff | 1177 | return -ENODEV; |
e045c291 | 1178 | |
9f6aef86 YG |
1179 | if (boot_cpu_has(X86_FEATURE_SMCA)) { |
1180 | xec_mask = 0x3f; | |
1181 | goto out; | |
1182 | } | |
1183 | ||
bad11e03 | 1184 | switch (c->x86) { |
888ab8e6 | 1185 | case 0xf: |
86e9f9d6 BP |
1186 | fam_ops.mc0_mce = k8_mc0_mce; |
1187 | fam_ops.mc1_mce = k8_mc1_mce; | |
1188 | fam_ops.mc2_mce = k8_mc2_mce; | |
888ab8e6 BP |
1189 | break; |
1190 | ||
1191 | case 0x10: | |
86e9f9d6 BP |
1192 | fam_ops.mc0_mce = f10h_mc0_mce; |
1193 | fam_ops.mc1_mce = k8_mc1_mce; | |
1194 | fam_ops.mc2_mce = k8_mc2_mce; | |
888ab8e6 BP |
1195 | break; |
1196 | ||
f0157b3a | 1197 | case 0x11: |
86e9f9d6 BP |
1198 | fam_ops.mc0_mce = k8_mc0_mce; |
1199 | fam_ops.mc1_mce = k8_mc1_mce; | |
1200 | fam_ops.mc2_mce = k8_mc2_mce; | |
f0157b3a BP |
1201 | break; |
1202 | ||
9be0bb10 | 1203 | case 0x12: |
86e9f9d6 BP |
1204 | fam_ops.mc0_mce = f12h_mc0_mce; |
1205 | fam_ops.mc1_mce = k8_mc1_mce; | |
1206 | fam_ops.mc2_mce = k8_mc2_mce; | |
9be0bb10 BP |
1207 | break; |
1208 | ||
888ab8e6 | 1209 | case 0x14: |
86e9f9d6 BP |
1210 | fam_ops.mc0_mce = cat_mc0_mce; |
1211 | fam_ops.mc1_mce = cat_mc1_mce; | |
1212 | fam_ops.mc2_mce = k8_mc2_mce; | |
888ab8e6 BP |
1213 | break; |
1214 | ||
2be64bfa | 1215 | case 0x15: |
eba4bfb3 AG |
1216 | xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f; |
1217 | ||
86e9f9d6 BP |
1218 | fam_ops.mc0_mce = f15h_mc0_mce; |
1219 | fam_ops.mc1_mce = f15h_mc1_mce; | |
1220 | fam_ops.mc2_mce = f15h_mc2_mce; | |
2be64bfa BP |
1221 | break; |
1222 | ||
980eec8b JS |
1223 | case 0x16: |
1224 | xec_mask = 0x1f; | |
86e9f9d6 BP |
1225 | fam_ops.mc0_mce = cat_mc0_mce; |
1226 | fam_ops.mc1_mce = cat_mc1_mce; | |
1227 | fam_ops.mc2_mce = f16h_mc2_mce; | |
980eec8b JS |
1228 | break; |
1229 | ||
be0aec23 | 1230 | case 0x17: |
c4a3e946 | 1231 | case 0x18: |
52cff04a | 1232 | pr_warn_once("Decoding supported only on Scalable MCA processors.\n"); |
86e9f9d6 | 1233 | return -EINVAL; |
be0aec23 | 1234 | |
888ab8e6 | 1235 | default: |
ec3e82d6 | 1236 | printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86); |
86e9f9d6 | 1237 | return -EINVAL; |
888ab8e6 BP |
1238 | } |
1239 | ||
9f6aef86 | 1240 | out: |
9530d608 BP |
1241 | pr_info("MCE: In-kernel MCE decoding enabled.\n"); |
1242 | ||
3653ada5 | 1243 | mce_register_decode_chain(&amd_mce_dec_nb); |
f436f8bb IM |
1244 | |
1245 | return 0; | |
1246 | } | |
1247 | early_initcall(mce_amd_init); | |
0d18b2e3 BP |
1248 | |
1249 | #ifdef MODULE | |
1250 | static void __exit mce_amd_exit(void) | |
1251 | { | |
3653ada5 | 1252 | mce_unregister_decode_chain(&amd_mce_dec_nb); |
0d18b2e3 BP |
1253 | } |
1254 | ||
1255 | MODULE_DESCRIPTION("AMD MCE decoder"); | |
1256 | MODULE_ALIAS("edac-mce-amd"); | |
1257 | MODULE_LICENSE("GPL"); | |
1258 | module_exit(mce_amd_exit); | |
1259 | #endif |