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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7ee40b89 JB |
2 | /* |
3 | * Intel E3-1200 | |
4 | * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> | |
5 | * | |
6 | * Support for the E3-1200 processor family. Heavily based on previous | |
7 | * Intel EDAC drivers. | |
8 | * | |
9 | * Since the DRAM controller is on the cpu chip, we can use its PCI device | |
10 | * id to identify these processors. | |
11 | * | |
7d4c1ea2 | 12 | * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) |
7ee40b89 JB |
13 | * |
14 | * 0108: Xeon E3-1200 Processor Family DRAM Controller | |
15 | * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller | |
16 | * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller | |
17 | * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller | |
18 | * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller | |
19 | * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller | |
20 | * 0c08: Xeon E3-1200 v3 Processor DRAM Controller | |
953dee9b | 21 | * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers |
7103de0e | 22 | * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers |
c452a9d3 | 23 | * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers |
7ee40b89 JB |
24 | * |
25 | * Based on Intel specification: | |
7d4c1ea2 | 26 | * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf |
7ee40b89 | 27 | * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html |
7d4c1ea2 | 28 | * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html |
c452a9d3 | 29 | * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html |
7ee40b89 JB |
30 | * |
31 | * According to the above datasheet (p.16): | |
32 | * " | |
33 | * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with | |
34 | * requests that cross a DW boundary. | |
35 | * " | |
36 | * | |
37 | * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into | |
38 | * 2 readl() calls. This restriction may be lifted in subsequent chip releases, | |
39 | * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. | |
40 | */ | |
41 | ||
42 | #include <linux/module.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/pci.h> | |
45 | #include <linux/pci_ids.h> | |
46 | #include <linux/edac.h> | |
47 | ||
2f8e2c87 | 48 | #include <linux/io-64-nonatomic-lo-hi.h> |
78d88e8a | 49 | #include "edac_module.h" |
7ee40b89 | 50 | |
7ee40b89 JB |
51 | #define EDAC_MOD_STR "ie31200_edac" |
52 | ||
53 | #define ie31200_printk(level, fmt, arg...) \ | |
54 | edac_printk(level, "ie31200", fmt, ##arg) | |
55 | ||
56 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 | |
57 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c | |
58 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 | |
59 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 | |
60 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c | |
61 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 | |
62 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 | |
953dee9b | 63 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918 |
7103de0e | 64 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918 |
7ee40b89 | 65 | |
c452a9d3 ME |
66 | /* Coffee Lake-S */ |
67 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 | |
68 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f | |
69 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 | |
70 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f | |
71 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 | |
72 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 | |
73 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 | |
74 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 | |
75 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 | |
76 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 | |
77 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca | |
78 | ||
79 | /* Test if HB is for Skylake or later. */ | |
80 | #define DEVICE_ID_SKYLAKE_OR_LATER(did) \ | |
81 | (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \ | |
82 | ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \ | |
83 | (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \ | |
84 | PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK)) | |
85 | ||
7ee40b89 JB |
86 | #define IE31200_DIMMS 4 |
87 | #define IE31200_RANKS 8 | |
88 | #define IE31200_RANKS_PER_CHANNEL 4 | |
89 | #define IE31200_DIMMS_PER_CHANNEL 2 | |
90 | #define IE31200_CHANNELS 2 | |
91 | ||
92 | /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ | |
93 | #define IE31200_MCHBAR_LOW 0x48 | |
94 | #define IE31200_MCHBAR_HIGH 0x4c | |
95 | #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) | |
96 | #define IE31200_MMR_WINDOW_SIZE BIT(15) | |
97 | ||
98 | /* | |
99 | * Error Status Register (16b) | |
100 | * | |
101 | * 15 reserved | |
102 | * 14 Isochronous TBWRR Run Behind FIFO Full | |
103 | * (ITCV) | |
104 | * 13 Isochronous TBWRR Run Behind FIFO Put | |
105 | * (ITSTV) | |
106 | * 12 reserved | |
107 | * 11 MCH Thermal Sensor Event | |
108 | * for SMI/SCI/SERR (GTSE) | |
109 | * 10 reserved | |
110 | * 9 LOCK to non-DRAM Memory Flag (LCKF) | |
111 | * 8 reserved | |
112 | * 7 DRAM Throttle Flag (DTF) | |
113 | * 6:2 reserved | |
114 | * 1 Multi-bit DRAM ECC Error Flag (DMERR) | |
115 | * 0 Single-bit DRAM ECC Error Flag (DSERR) | |
116 | */ | |
117 | #define IE31200_ERRSTS 0xc8 | |
118 | #define IE31200_ERRSTS_UE BIT(1) | |
119 | #define IE31200_ERRSTS_CE BIT(0) | |
120 | #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) | |
121 | ||
122 | /* | |
123 | * Channel 0 ECC Error Log (64b) | |
124 | * | |
125 | * 63:48 Error Column Address (ERRCOL) | |
126 | * 47:32 Error Row Address (ERRROW) | |
127 | * 31:29 Error Bank Address (ERRBANK) | |
128 | * 28:27 Error Rank Address (ERRRANK) | |
129 | * 26:24 reserved | |
130 | * 23:16 Error Syndrome (ERRSYND) | |
131 | * 15: 2 reserved | |
132 | * 1 Multiple Bit Error Status (MERRSTS) | |
133 | * 0 Correctable Error Status (CERRSTS) | |
134 | */ | |
953dee9b | 135 | |
7ee40b89 JB |
136 | #define IE31200_C0ECCERRLOG 0x40c8 |
137 | #define IE31200_C1ECCERRLOG 0x44c8 | |
953dee9b JB |
138 | #define IE31200_C0ECCERRLOG_SKL 0x4048 |
139 | #define IE31200_C1ECCERRLOG_SKL 0x4448 | |
7ee40b89 JB |
140 | #define IE31200_ECCERRLOG_CE BIT(0) |
141 | #define IE31200_ECCERRLOG_UE BIT(1) | |
142 | #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) | |
143 | #define IE31200_ECCERRLOG_RANK_SHIFT 27 | |
144 | #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) | |
145 | #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16 | |
146 | ||
147 | #define IE31200_ECCERRLOG_SYNDROME(log) \ | |
148 | ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \ | |
149 | IE31200_ECCERRLOG_SYNDROME_SHIFT) | |
150 | ||
151 | #define IE31200_CAPID0 0xe4 | |
152 | #define IE31200_CAPID0_PDCD BIT(4) | |
153 | #define IE31200_CAPID0_DDPCD BIT(6) | |
154 | #define IE31200_CAPID0_ECC BIT(1) | |
155 | ||
953dee9b JB |
156 | #define IE31200_MAD_DIMM_0_OFFSET 0x5004 |
157 | #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C | |
158 | #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) | |
159 | #define IE31200_MAD_DIMM_A_RANK BIT(17) | |
160 | #define IE31200_MAD_DIMM_A_RANK_SHIFT 17 | |
161 | #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) | |
162 | #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10 | |
163 | #define IE31200_MAD_DIMM_A_WIDTH BIT(19) | |
164 | #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19 | |
165 | #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) | |
166 | #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8 | |
167 | ||
168 | /* Skylake reports 1GB increments, everything else is 256MB */ | |
169 | #define IE31200_PAGES(n, skl) \ | |
170 | (n << (28 + (2 * skl) - PAGE_SHIFT)) | |
7ee40b89 JB |
171 | |
172 | static int nr_channels; | |
709ed1bc JB |
173 | static struct pci_dev *mci_pdev; |
174 | static int ie31200_registered = 1; | |
7ee40b89 JB |
175 | |
176 | struct ie31200_priv { | |
177 | void __iomem *window; | |
953dee9b JB |
178 | void __iomem *c0errlog; |
179 | void __iomem *c1errlog; | |
7ee40b89 JB |
180 | }; |
181 | ||
182 | enum ie31200_chips { | |
183 | IE31200 = 0, | |
184 | }; | |
185 | ||
186 | struct ie31200_dev_info { | |
187 | const char *ctl_name; | |
188 | }; | |
189 | ||
190 | struct ie31200_error_info { | |
191 | u16 errsts; | |
192 | u16 errsts2; | |
193 | u64 eccerrlog[IE31200_CHANNELS]; | |
194 | }; | |
195 | ||
196 | static const struct ie31200_dev_info ie31200_devs[] = { | |
197 | [IE31200] = { | |
198 | .ctl_name = "IE31200" | |
199 | }, | |
200 | }; | |
201 | ||
202 | struct dimm_data { | |
953dee9b | 203 | u8 size; /* in multiples of 256MB, except Skylake is 1GB */ |
7ee40b89 | 204 | u8 dual_rank : 1, |
953dee9b | 205 | x16_width : 2; /* 0 means x8 width */ |
7ee40b89 JB |
206 | }; |
207 | ||
208 | static int how_many_channels(struct pci_dev *pdev) | |
209 | { | |
210 | int n_channels; | |
211 | unsigned char capid0_2b; /* 2nd byte of CAPID0 */ | |
212 | ||
213 | pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); | |
214 | ||
215 | /* check PDCD: Dual Channel Disable */ | |
216 | if (capid0_2b & IE31200_CAPID0_PDCD) { | |
217 | edac_dbg(0, "In single channel mode\n"); | |
218 | n_channels = 1; | |
219 | } else { | |
220 | edac_dbg(0, "In dual channel mode\n"); | |
221 | n_channels = 2; | |
222 | } | |
223 | ||
224 | /* check DDPCD - check if both channels are filled */ | |
225 | if (capid0_2b & IE31200_CAPID0_DDPCD) | |
226 | edac_dbg(0, "2 DIMMS per channel disabled\n"); | |
227 | else | |
228 | edac_dbg(0, "2 DIMMS per channel enabled\n"); | |
229 | ||
230 | return n_channels; | |
231 | } | |
232 | ||
233 | static bool ecc_capable(struct pci_dev *pdev) | |
234 | { | |
235 | unsigned char capid0_4b; /* 4th byte of CAPID0 */ | |
236 | ||
237 | pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); | |
238 | if (capid0_4b & IE31200_CAPID0_ECC) | |
239 | return false; | |
240 | return true; | |
241 | } | |
242 | ||
953dee9b | 243 | static int eccerrlog_row(u64 log) |
7ee40b89 | 244 | { |
953dee9b JB |
245 | return ((log & IE31200_ECCERRLOG_RANK_BITS) >> |
246 | IE31200_ECCERRLOG_RANK_SHIFT); | |
7ee40b89 JB |
247 | } |
248 | ||
249 | static void ie31200_clear_error_info(struct mem_ctl_info *mci) | |
250 | { | |
251 | /* | |
252 | * Clear any error bits. | |
253 | * (Yes, we really clear bits by writing 1 to them.) | |
254 | */ | |
255 | pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS, | |
256 | IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); | |
257 | } | |
258 | ||
259 | static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, | |
260 | struct ie31200_error_info *info) | |
261 | { | |
262 | struct pci_dev *pdev; | |
263 | struct ie31200_priv *priv = mci->pvt_info; | |
7ee40b89 JB |
264 | |
265 | pdev = to_pci_dev(mci->pdev); | |
266 | ||
267 | /* | |
268 | * This is a mess because there is no atomic way to read all the | |
269 | * registers at once and the registers can transition from CE being | |
270 | * overwritten by UE. | |
271 | */ | |
272 | pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); | |
273 | if (!(info->errsts & IE31200_ERRSTS_BITS)) | |
274 | return; | |
275 | ||
953dee9b | 276 | info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); |
7ee40b89 | 277 | if (nr_channels == 2) |
953dee9b | 278 | info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); |
7ee40b89 JB |
279 | |
280 | pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); | |
281 | ||
282 | /* | |
283 | * If the error is the same for both reads then the first set | |
284 | * of reads is valid. If there is a change then there is a CE | |
285 | * with no info and the second set of reads is valid and | |
286 | * should be UE info. | |
287 | */ | |
288 | if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { | |
953dee9b | 289 | info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); |
7ee40b89 JB |
290 | if (nr_channels == 2) |
291 | info->eccerrlog[1] = | |
953dee9b | 292 | lo_hi_readq(priv->c1errlog); |
7ee40b89 JB |
293 | } |
294 | ||
295 | ie31200_clear_error_info(mci); | |
296 | } | |
297 | ||
298 | static void ie31200_process_error_info(struct mem_ctl_info *mci, | |
299 | struct ie31200_error_info *info) | |
300 | { | |
301 | int channel; | |
302 | u64 log; | |
303 | ||
304 | if (!(info->errsts & IE31200_ERRSTS_BITS)) | |
305 | return; | |
306 | ||
307 | if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { | |
308 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, | |
309 | -1, -1, -1, "UE overwrote CE", ""); | |
310 | info->errsts = info->errsts2; | |
311 | } | |
312 | ||
313 | for (channel = 0; channel < nr_channels; channel++) { | |
314 | log = info->eccerrlog[channel]; | |
315 | if (log & IE31200_ECCERRLOG_UE) { | |
316 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, | |
317 | 0, 0, 0, | |
953dee9b | 318 | eccerrlog_row(log), |
7ee40b89 JB |
319 | channel, -1, |
320 | "ie31200 UE", ""); | |
321 | } else if (log & IE31200_ECCERRLOG_CE) { | |
322 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, | |
323 | 0, 0, | |
324 | IE31200_ECCERRLOG_SYNDROME(log), | |
953dee9b | 325 | eccerrlog_row(log), |
7ee40b89 JB |
326 | channel, -1, |
327 | "ie31200 CE", ""); | |
328 | } | |
329 | } | |
330 | } | |
331 | ||
332 | static void ie31200_check(struct mem_ctl_info *mci) | |
333 | { | |
334 | struct ie31200_error_info info; | |
335 | ||
7ee40b89 JB |
336 | ie31200_get_and_clear_error_info(mci, &info); |
337 | ie31200_process_error_info(mci, &info); | |
338 | } | |
339 | ||
340 | static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) | |
341 | { | |
342 | union { | |
343 | u64 mchbar; | |
344 | struct { | |
345 | u32 mchbar_low; | |
346 | u32 mchbar_high; | |
347 | }; | |
348 | } u; | |
349 | void __iomem *window; | |
350 | ||
351 | pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); | |
352 | pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); | |
353 | u.mchbar &= IE31200_MCHBAR_MASK; | |
354 | ||
355 | if (u.mchbar != (resource_size_t)u.mchbar) { | |
356 | ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", | |
357 | (unsigned long long)u.mchbar); | |
358 | return NULL; | |
359 | } | |
360 | ||
4bdc0d67 | 361 | window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE); |
7ee40b89 JB |
362 | if (!window) |
363 | ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", | |
364 | (unsigned long long)u.mchbar); | |
365 | ||
366 | return window; | |
367 | } | |
368 | ||
953dee9b JB |
369 | static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode, |
370 | int chan) | |
371 | { | |
372 | dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE; | |
373 | dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0; | |
374 | dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >> | |
375 | (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4))); | |
376 | } | |
377 | ||
378 | static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode, | |
379 | int chan) | |
380 | { | |
381 | dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE; | |
382 | dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0; | |
383 | dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0; | |
384 | } | |
385 | ||
386 | static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan, | |
387 | bool skl) | |
388 | { | |
389 | if (skl) | |
390 | __skl_populate_dimm_info(dd, addr_decode, chan); | |
391 | else | |
392 | __populate_dimm_info(dd, addr_decode, chan); | |
393 | } | |
394 | ||
395 | ||
7ee40b89 JB |
396 | static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) |
397 | { | |
78fd4d12 | 398 | int i, j, ret; |
7ee40b89 JB |
399 | struct mem_ctl_info *mci = NULL; |
400 | struct edac_mc_layer layers[2]; | |
401 | struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL]; | |
402 | void __iomem *window; | |
403 | struct ie31200_priv *priv; | |
953dee9b | 404 | u32 addr_decode, mad_offset; |
7103de0e JB |
405 | |
406 | /* | |
c452a9d3 ME |
407 | * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit |
408 | * this logic when adding new CPU support. | |
7103de0e | 409 | */ |
c452a9d3 | 410 | bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device); |
7ee40b89 JB |
411 | |
412 | edac_dbg(0, "MC:\n"); | |
413 | ||
414 | if (!ecc_capable(pdev)) { | |
415 | ie31200_printk(KERN_INFO, "No ECC support\n"); | |
416 | return -ENODEV; | |
417 | } | |
418 | ||
7ee40b89 | 419 | nr_channels = how_many_channels(pdev); |
7ee40b89 JB |
420 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
421 | layers[0].size = IE31200_DIMMS; | |
422 | layers[0].is_virt_csrow = true; | |
423 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
424 | layers[1].size = nr_channels; | |
425 | layers[1].is_virt_csrow = false; | |
426 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
427 | sizeof(struct ie31200_priv)); | |
7ee40b89 | 428 | if (!mci) |
78fd4d12 | 429 | return -ENOMEM; |
7ee40b89 | 430 | |
78fd4d12 JB |
431 | window = ie31200_map_mchbar(pdev); |
432 | if (!window) { | |
433 | ret = -ENODEV; | |
434 | goto fail_free; | |
435 | } | |
7ee40b89 | 436 | |
78fd4d12 | 437 | edac_dbg(3, "MC: init mci\n"); |
7ee40b89 | 438 | mci->pdev = &pdev->dev; |
953dee9b JB |
439 | if (skl) |
440 | mci->mtype_cap = MEM_FLAG_DDR4; | |
441 | else | |
442 | mci->mtype_cap = MEM_FLAG_DDR3; | |
7ee40b89 JB |
443 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
444 | mci->edac_cap = EDAC_FLAG_SECDED; | |
7ee40b89 | 445 | mci->mod_name = EDAC_MOD_STR; |
7ee40b89 JB |
446 | mci->ctl_name = ie31200_devs[dev_idx].ctl_name; |
447 | mci->dev_name = pci_name(pdev); | |
448 | mci->edac_check = ie31200_check; | |
449 | mci->ctl_page_to_phys = NULL; | |
450 | priv = mci->pvt_info; | |
451 | priv->window = window; | |
953dee9b JB |
452 | if (skl) { |
453 | priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL; | |
454 | priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL; | |
455 | mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL; | |
456 | } else { | |
457 | priv->c0errlog = window + IE31200_C0ECCERRLOG; | |
458 | priv->c1errlog = window + IE31200_C1ECCERRLOG; | |
459 | mad_offset = IE31200_MAD_DIMM_0_OFFSET; | |
460 | } | |
7ee40b89 | 461 | |
78fd4d12 JB |
462 | /* populate DIMM info */ |
463 | for (i = 0; i < IE31200_CHANNELS; i++) { | |
953dee9b | 464 | addr_decode = readl(window + mad_offset + |
78fd4d12 JB |
465 | (i * 4)); |
466 | edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); | |
467 | for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { | |
953dee9b JB |
468 | populate_dimm_info(&dimm_info[i][j], addr_decode, j, |
469 | skl); | |
78fd4d12 JB |
470 | edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n", |
471 | dimm_info[i][j].size, | |
472 | dimm_info[i][j].dual_rank, | |
473 | dimm_info[i][j].x16_width); | |
474 | } | |
475 | } | |
476 | ||
7ee40b89 JB |
477 | /* |
478 | * The dram rank boundary (DRB) reg values are boundary addresses | |
479 | * for each DRAM rank with a granularity of 64MB. DRB regs are | |
480 | * cumulative; the last one will contain the total memory | |
481 | * contained in all ranks. | |
482 | */ | |
483 | for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) { | |
484 | for (j = 0; j < IE31200_CHANNELS; j++) { | |
485 | struct dimm_info *dimm; | |
486 | unsigned long nr_pages; | |
487 | ||
953dee9b | 488 | nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); |
7ee40b89 JB |
489 | if (nr_pages == 0) |
490 | continue; | |
491 | ||
492 | if (dimm_info[j][i].dual_rank) { | |
493 | nr_pages = nr_pages / 2; | |
bc9ad9e4 | 494 | dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0); |
7ee40b89 JB |
495 | dimm->nr_pages = nr_pages; |
496 | edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); | |
497 | dimm->grain = 8; /* just a guess */ | |
953dee9b JB |
498 | if (skl) |
499 | dimm->mtype = MEM_DDR4; | |
500 | else | |
501 | dimm->mtype = MEM_DDR3; | |
7ee40b89 JB |
502 | dimm->dtype = DEV_UNKNOWN; |
503 | dimm->edac_mode = EDAC_UNKNOWN; | |
504 | } | |
bc9ad9e4 | 505 | dimm = edac_get_dimm(mci, i * 2, j, 0); |
7ee40b89 JB |
506 | dimm->nr_pages = nr_pages; |
507 | edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); | |
508 | dimm->grain = 8; /* same guess */ | |
953dee9b JB |
509 | if (skl) |
510 | dimm->mtype = MEM_DDR4; | |
511 | else | |
512 | dimm->mtype = MEM_DDR3; | |
7ee40b89 JB |
513 | dimm->dtype = DEV_UNKNOWN; |
514 | dimm->edac_mode = EDAC_UNKNOWN; | |
515 | } | |
516 | } | |
517 | ||
518 | ie31200_clear_error_info(mci); | |
519 | ||
7ee40b89 JB |
520 | if (edac_mc_add_mc(mci)) { |
521 | edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); | |
78fd4d12 JB |
522 | ret = -ENODEV; |
523 | goto fail_unmap; | |
7ee40b89 JB |
524 | } |
525 | ||
526 | /* get this far and it's successful */ | |
527 | edac_dbg(3, "MC: success\n"); | |
528 | return 0; | |
529 | ||
7ee40b89 JB |
530 | fail_unmap: |
531 | iounmap(window); | |
532 | ||
78fd4d12 JB |
533 | fail_free: |
534 | edac_mc_free(mci); | |
535 | ||
536 | return ret; | |
7ee40b89 JB |
537 | } |
538 | ||
539 | static int ie31200_init_one(struct pci_dev *pdev, | |
540 | const struct pci_device_id *ent) | |
541 | { | |
709ed1bc | 542 | int rc; |
7ee40b89 | 543 | |
709ed1bc | 544 | edac_dbg(0, "MC:\n"); |
7ee40b89 JB |
545 | if (pci_enable_device(pdev) < 0) |
546 | return -EIO; | |
709ed1bc JB |
547 | rc = ie31200_probe1(pdev, ent->driver_data); |
548 | if (rc == 0 && !mci_pdev) | |
549 | mci_pdev = pci_dev_get(pdev); | |
7ee40b89 | 550 | |
709ed1bc | 551 | return rc; |
7ee40b89 JB |
552 | } |
553 | ||
554 | static void ie31200_remove_one(struct pci_dev *pdev) | |
555 | { | |
556 | struct mem_ctl_info *mci; | |
557 | struct ie31200_priv *priv; | |
558 | ||
559 | edac_dbg(0, "\n"); | |
709ed1bc JB |
560 | pci_dev_put(mci_pdev); |
561 | mci_pdev = NULL; | |
7ee40b89 JB |
562 | mci = edac_mc_del_mc(&pdev->dev); |
563 | if (!mci) | |
564 | return; | |
565 | priv = mci->pvt_info; | |
566 | iounmap(priv->window); | |
567 | edac_mc_free(mci); | |
568 | } | |
569 | ||
570 | static const struct pci_device_id ie31200_pci_tbl[] = { | |
4d91fde8 ME |
571 | { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
572 | { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
573 | { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
574 | { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
575 | { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
576 | { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
577 | { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
578 | { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
579 | { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
580 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
581 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
582 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
583 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
584 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
585 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
586 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
587 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
588 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
589 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, | |
590 | { 0, } /* 0 terminated list. */ | |
7ee40b89 JB |
591 | }; |
592 | MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); | |
593 | ||
594 | static struct pci_driver ie31200_driver = { | |
595 | .name = EDAC_MOD_STR, | |
596 | .probe = ie31200_init_one, | |
597 | .remove = ie31200_remove_one, | |
598 | .id_table = ie31200_pci_tbl, | |
599 | }; | |
600 | ||
601 | static int __init ie31200_init(void) | |
602 | { | |
709ed1bc JB |
603 | int pci_rc, i; |
604 | ||
7ee40b89 JB |
605 | edac_dbg(3, "MC:\n"); |
606 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
607 | opstate_init(); | |
608 | ||
709ed1bc JB |
609 | pci_rc = pci_register_driver(&ie31200_driver); |
610 | if (pci_rc < 0) | |
611 | goto fail0; | |
612 | ||
613 | if (!mci_pdev) { | |
614 | ie31200_registered = 0; | |
615 | for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { | |
616 | mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor, | |
617 | ie31200_pci_tbl[i].device, | |
618 | NULL); | |
619 | if (mci_pdev) | |
620 | break; | |
621 | } | |
622 | if (!mci_pdev) { | |
623 | edac_dbg(0, "ie31200 pci_get_device fail\n"); | |
624 | pci_rc = -ENODEV; | |
625 | goto fail1; | |
626 | } | |
627 | pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]); | |
628 | if (pci_rc < 0) { | |
629 | edac_dbg(0, "ie31200 init fail\n"); | |
630 | pci_rc = -ENODEV; | |
631 | goto fail1; | |
632 | } | |
633 | } | |
634 | return 0; | |
635 | ||
636 | fail1: | |
637 | pci_unregister_driver(&ie31200_driver); | |
638 | fail0: | |
639 | pci_dev_put(mci_pdev); | |
640 | ||
641 | return pci_rc; | |
7ee40b89 JB |
642 | } |
643 | ||
644 | static void __exit ie31200_exit(void) | |
645 | { | |
646 | edac_dbg(3, "MC:\n"); | |
647 | pci_unregister_driver(&ie31200_driver); | |
709ed1bc JB |
648 | if (!ie31200_registered) |
649 | ie31200_remove_one(mci_pdev); | |
7ee40b89 JB |
650 | } |
651 | ||
652 | module_init(ie31200_init); | |
653 | module_exit(ie31200_exit); | |
654 | ||
655 | MODULE_LICENSE("GPL"); | |
656 | MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); | |
657 | MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); |