[linux-block.git] / drivers / edac / i82860_edac.c

/*
 * Intel 82860 Memory Controller kernel module
 * (C) 2005 Red Hat (http://www.redhat.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Ben Woodard <woodard@redhat.com>
 * shamelessly copied from and based upon the edac_i82875 driver
 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
 */


#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include "edac_mc.h"


#define i82860_printk(level, fmt, arg...) \
    edac_printk(level, "i82860", fmt, ##arg)


#define i82860_mc_printk(mci, level, fmt, arg...) \
    edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)


#ifndef PCI_DEVICE_ID_INTEL_82860_0
#define PCI_DEVICE_ID_INTEL_82860_0	0x2531
#endif				/* PCI_DEVICE_ID_INTEL_82860_0 */

#define I82860_MCHCFG 0x50
#define I82860_GBA 0x60
#define I82860_GBA_MASK 0x7FF
#define I82860_GBA_SHIFT 24
#define I82860_ERRSTS 0xC8
#define I82860_EAP 0xE4
#define I82860_DERRCTL_STS 0xE2

enum i82860_chips {
	I82860 = 0,
};

struct i82860_dev_info {
	const char *ctl_name;
};

struct i82860_error_info {
	u16 errsts;
	u32 eap;
	u16 derrsyn;
	u16 errsts2;
};

static const struct i82860_dev_info i82860_devs[] = {
	[I82860] = {
		    .ctl_name = "i82860"},
};

static struct pci_dev *mci_pdev = NULL;	/* init dev: in case that AGP code
					   has already registered driver */

static int i82860_registered = 1;

static void i82860_get_error_info (struct mem_ctl_info *mci,
		struct i82860_error_info *info)
{
	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts);
	pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
	pci_read_config_word(mci->pdev, I82860_DERRCTL_STS, &info->derrsyn);
	pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts2);

	pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);

	/*
	 * If the error is the same for both reads then the first set of reads
	 * is valid.  If there is a change then there is a CE no info and the
	 * second set of reads is valid and should be UE info.
	 */
	if (!(info->errsts2 & 0x0003))
		return;
	if ((info->errsts ^ info->errsts2) & 0x0003) {
		pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
		pci_read_config_word(mci->pdev, I82860_DERRCTL_STS,
		    &info->derrsyn);
	}
}

static int i82860_process_error_info (struct mem_ctl_info *mci,
		struct i82860_error_info *info, int handle_errors)
{
	int row;

	if (!(info->errsts2 & 0x0003))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0002)
		edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	else
		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
				       0, "i82860 UE");

	return 1;
}

static void i82860_check(struct mem_ctl_info *mci)
{
	struct i82860_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i82860_get_error_info(mci, &info);
	i82860_process_error_info(mci, &info, 1);
}

static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	int index;
	struct mem_ctl_info *mci = NULL;
	unsigned long last_cumul_size;

	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none,2=edac */

	/* RDRAM has channels but these don't map onto the abstractions that
	   edac uses.
	   The device groups from the GRA registers seem to map reasonably
	   well onto the notion of a chip select row.
	   There are 16 GRA registers and since the name is associated with
	   the channel and the GRA registers map to physical devices so we are
	   going to make 1 channel for group.
	 */
	mci = edac_mc_alloc(0, 16, 1);
	if (!mci)
		return -ENOMEM;

	debugf3("%s(): init mci\n", __func__);

	mci->pdev = pdev;
	mci->mtype_cap = MEM_FLAG_DDR;


	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	/* I"m not sure about this but I think that all RDRAM is SECDED */
	mci->edac_cap = EDAC_FLAG_SECDED;
	/* adjust FLAGS */

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = "$Revision: 1.1.2.6 $";
	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	mci->edac_check = i82860_check;
	mci->ctl_page_to_phys = NULL;

	pci_read_config_word(mci->pdev, I82860_MCHCFG, &mchcfg_ddim);
	mchcfg_ddim = mchcfg_ddim & 0x180;

	/*
	 * The group row boundary (GRA) reg values are boundary address
	 * for each DRAM row with a granularity of 16MB.  GRA regs are
	 * cumulative; therefore GRA15 will contain the total memory contained
	 * in all eight rows.
	 */
	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
		u16 value;
		u32 cumul_size;
		struct csrow_info *csrow = &mci->csrows[index];

		pci_read_config_word(mci->pdev, I82860_GBA + index * 2,
				     &value);

		cumul_size = (value & I82860_GBA_MASK) <<
		    (I82860_GBA_SHIFT - PAGE_SHIFT);
		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
			cumul_size);
		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		csrow->grain = 1 << 12;	/* I82860_EAP has 4KiB reolution */
		csrow->mtype = MEM_RMBS;
		csrow->dtype = DEV_UNKNOWN;
		csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	}

	/* clear counters */
	pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);

	if (edac_mc_add_mc(mci)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		edac_mc_free(mci);
	} else {
		/* get this far and it's successful */
		debugf3("%s(): success\n", __func__);
		rc = 0;
	}
	return rc;
}

/* returns count (>= 0), or negative on error */
static int __devinit i82860_init_one(struct pci_dev *pdev,
				     const struct pci_device_id *ent)
{
	int rc;

	debugf0("%s()\n", __func__);

	i82860_printk(KERN_INFO, "i82860 init one\n");
	if(pci_enable_device(pdev) < 0)
		return -EIO;
	rc = i82860_probe1(pdev, ent->driver_data);
	if(rc == 0)
		mci_pdev = pci_dev_get(pdev);
	return rc;
}

static void __devexit i82860_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	debugf0("%s()\n", __func__);

	mci = edac_mc_find_mci_by_pdev(pdev);
	if ((mci != NULL) && (edac_mc_del_mc(mci) == 0))
		edac_mc_free(mci);
}

static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
	{PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82860},
	{0,}			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);

static struct pci_driver i82860_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82860_init_one,
	.remove = __devexit_p(i82860_remove_one),
	.id_table = i82860_pci_tbl,
};

static int __init i82860_init(void)
{
	int pci_rc;

	debugf3("%s()\n", __func__);
	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
		return pci_rc;

	if (!mci_pdev) {
		i82860_registered = 0;
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					  PCI_DEVICE_ID_INTEL_82860_0, NULL);
		if (mci_pdev == NULL) {
			debugf0("860 pci_get_device fail\n");
			return -ENODEV;
		}
		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
		if (pci_rc < 0) {
			debugf0("860 init fail\n");
			pci_dev_put(mci_pdev);
			return -ENODEV;
		}
	}
	return 0;
}

static void __exit i82860_exit(void)
{
	debugf3("%s()\n", __func__);

	pci_unregister_driver(&i82860_driver);
	if (!i82860_registered) {
		i82860_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}

module_init(i82860_init);
module_exit(i82860_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR
    ("Red Hat Inc. (http://www.redhat.com.com) Ben Woodard <woodard@redhat.com>");
MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel 82860 Memory Controller kernel module
	3	* (C) 2005 Red Hat (http://www.redhat.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Ben Woodard <woodard@redhat.com>
	8	* shamelessly copied from and based upon the edac_i82875 driver
	9	* by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
	10	*/
	11
	12
	13	#include <linux/config.h>
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/pci.h>
	17	#include <linux/pci_ids.h>
	18	#include <linux/slab.h>
	19	#include "edac_mc.h"
	20
	21
537fba28 DP	22	#define i82860_printk(level, fmt, arg...) \
	23	edac_printk(level, "i82860", fmt, ##arg)
	24
	25
	26	#define i82860_mc_printk(mci, level, fmt, arg...) \
	27	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
	28
	29
0d88a10e AC	30	#ifndef PCI_DEVICE_ID_INTEL_82860_0
	31	#define PCI_DEVICE_ID_INTEL_82860_0 0x2531
	32	#endif /* PCI_DEVICE_ID_INTEL_82860_0 */
	33
	34	#define I82860_MCHCFG 0x50
	35	#define I82860_GBA 0x60
	36	#define I82860_GBA_MASK 0x7FF
	37	#define I82860_GBA_SHIFT 24
	38	#define I82860_ERRSTS 0xC8
	39	#define I82860_EAP 0xE4
	40	#define I82860_DERRCTL_STS 0xE2
	41
	42	enum i82860_chips {
	43	I82860 = 0,
	44	};
	45
	46	struct i82860_dev_info {
	47	const char *ctl_name;
	48	};
	49
	50	struct i82860_error_info {
	51	u16 errsts;
	52	u32 eap;
	53	u16 derrsyn;
	54	u16 errsts2;
	55	};
	56
	57	static const struct i82860_dev_info i82860_devs[] = {
	58	[I82860] = {
	59	.ctl_name = "i82860"},
	60	};
	61
	62	static struct pci_dev mci_pdev = NULL; / init dev: in case that AGP code
	63	has already registered driver */
	64
	65	static int i82860_registered = 1;
	66
	67	static void i82860_get_error_info (struct mem_ctl_info *mci,
	68	struct i82860_error_info *info)
	69	{
	70	/*
	71	* This is a mess because there is no atomic way to read all the
	72	* registers at once and the registers can transition from CE being
	73	* overwritten by UE.
	74	*/
	75	pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts);
	76	pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
	77	pci_read_config_word(mci->pdev, I82860_DERRCTL_STS, &info->derrsyn);
	78	pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts2);
	79
	80	pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
	81
	82	/*
	83	* If the error is the same for both reads then the first set of reads
	84	* is valid. If there is a change then there is a CE no info and the
	85	* second set of reads is valid and should be UE info.
	86	*/
	87	if (!(info->errsts2 & 0x0003))
	88	return;
	89	if ((info->errsts ^ info->errsts2) & 0x0003) {
	90	pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
	91	pci_read_config_word(mci->pdev, I82860_DERRCTL_STS,
	92	&info->derrsyn);
	93	}
94	}
95
96	static int i82860_process_error_info (struct mem_ctl_info *mci,
97	struct i82860_error_info *info, int handle_errors)
98	{
99	int row;
100
101	if (!(info->errsts2 & 0x0003))
102	return 0;
103
104	if (!handle_errors)
105	return 1;
106
107	if ((info->errsts ^ info->errsts2) & 0x0003) {
108	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
109	info->errsts = info->errsts2;
110	}
111
112	info->eap >>= PAGE_SHIFT;
113	row = edac_mc_find_csrow_by_page(mci, info->eap);
114
115	if (info->errsts & 0x0002)
116	edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
117	else
118	edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
119	0, "i82860 UE");
120
121	return 1;
122	}
123
124	static void i82860_check(struct mem_ctl_info *mci)
125	{
126	struct i82860_error_info info;
127
537fba28	128	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
0d88a10e AC	129	i82860_get_error_info(mci, &info);
	130	i82860_process_error_info(mci, &info, 1);
	131	}
	132
	133	static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
	134	{
	135	int rc = -ENODEV;
	136	int index;
	137	struct mem_ctl_info *mci = NULL;
	138	unsigned long last_cumul_size;
	139
	140	u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
	141
	142	/* RDRAM has channels but these don't map onto the abstractions that
	143	edac uses.
	144	The device groups from the GRA registers seem to map reasonably
	145	well onto the notion of a chip select row.
	146	There are 16 GRA registers and since the name is associated with
	147	the channel and the GRA registers map to physical devices so we are
	148	going to make 1 channel for group.
	149	*/
	150	mci = edac_mc_alloc(0, 16, 1);
	151	if (!mci)
	152	return -ENOMEM;
	153
537fba28	154	debugf3("%s(): init mci\n", __func__);
0d88a10e AC	155
	156	mci->pdev = pdev;
	157	mci->mtype_cap = MEM_FLAG_DDR;
	158
	159
	160	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	161	/* I"m not sure about this but I think that all RDRAM is SECDED */
	162	mci->edac_cap = EDAC_FLAG_SECDED;
	163	/* adjust FLAGS */
	164
680cbbbb	165	mci->mod_name = EDAC_MOD_STR;
0d88a10e AC	166	mci->mod_ver = "$Revision: 1.1.2.6 $";
	167	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	168	mci->edac_check = i82860_check;
	169	mci->ctl_page_to_phys = NULL;
	170
	171	pci_read_config_word(mci->pdev, I82860_MCHCFG, &mchcfg_ddim);
	172	mchcfg_ddim = mchcfg_ddim & 0x180;
	173
	174	/*
	175	* The group row boundary (GRA) reg values are boundary address
	176	* for each DRAM row with a granularity of 16MB. GRA regs are
	177	* cumulative; therefore GRA15 will contain the total memory contained
	178	* in all eight rows.
	179	*/
	180	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
	181	u16 value;
	182	u32 cumul_size;
	183	struct csrow_info *csrow = &mci->csrows[index];
	184
	185	pci_read_config_word(mci->pdev, I82860_GBA + index * 2,
	186	&value);
	187
	188	cumul_size = (value & I82860_GBA_MASK) <<
	189	(I82860_GBA_SHIFT - PAGE_SHIFT);
537fba28 DP	190	debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
537fba28 DP	191	cumul_size);
0d88a10e AC	192	if (cumul_size == last_cumul_size)
	193	continue; /* not populated */
	194
	195	csrow->first_page = last_cumul_size;
	196	csrow->last_page = cumul_size - 1;
	197	csrow->nr_pages = cumul_size - last_cumul_size;
	198	last_cumul_size = cumul_size;
	199	csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
	200	csrow->mtype = MEM_RMBS;
	201	csrow->dtype = DEV_UNKNOWN;
	202	csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	203	}
	204
	205	/* clear counters */
	206	pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
	207
	208	if (edac_mc_add_mc(mci)) {
537fba28	209	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
0d88a10e AC	210	edac_mc_free(mci);
	211	} else {
	212	/* get this far and it's successful */
537fba28	213	debugf3("%s(): success\n", __func__);
0d88a10e AC	214	rc = 0;
	215	}
	216	return rc;
	217	}
	218
	219	/* returns count (>= 0), or negative on error */
	220	static int __devinit i82860_init_one(struct pci_dev *pdev,
	221	const struct pci_device_id *ent)
	222	{
	223	int rc;
	224
537fba28	225	debugf0("%s()\n", __func__);
0d88a10e	226
537fba28	227	i82860_printk(KERN_INFO, "i82860 init one\n");
0d88a10e AC	228	if(pci_enable_device(pdev) < 0)
	229	return -EIO;
	230	rc = i82860_probe1(pdev, ent->driver_data);
	231	if(rc == 0)
	232	mci_pdev = pci_dev_get(pdev);
	233	return rc;
	234	}
	235
	236	static void __devexit i82860_remove_one(struct pci_dev *pdev)
	237	{
	238	struct mem_ctl_info *mci;
	239
537fba28	240	debugf0("%s()\n", __func__);
0d88a10e AC	241
	242	mci = edac_mc_find_mci_by_pdev(pdev);
	243	if ((mci != NULL) && (edac_mc_del_mc(mci) == 0))
	244	edac_mc_free(mci);
	245	}
	246
	247	static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
	248	{PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	249	I82860},
	250	{0,} /* 0 terminated list. */
	251	};
	252
	253	MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
	254
	255	static struct pci_driver i82860_driver = {
680cbbbb	256	.name = EDAC_MOD_STR,
0d88a10e AC	257	.probe = i82860_init_one,
	258	.remove = __devexit_p(i82860_remove_one),
	259	.id_table = i82860_pci_tbl,
	260	};
	261
da9bb1d2	262	static int __init i82860_init(void)
0d88a10e AC	263	{
	264	int pci_rc;
	265
537fba28	266	debugf3("%s()\n", __func__);
0d88a10e AC	267	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
	268	return pci_rc;
	269
	270	if (!mci_pdev) {
	271	i82860_registered = 0;
	272	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
	273	PCI_DEVICE_ID_INTEL_82860_0, NULL);
	274	if (mci_pdev == NULL) {
	275	debugf0("860 pci_get_device fail\n");
	276	return -ENODEV;
	277	}
	278	pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
	279	if (pci_rc < 0) {
	280	debugf0("860 init fail\n");
	281	pci_dev_put(mci_pdev);
	282	return -ENODEV;
	283	}
	284	}
	285	return 0;
	286	}
	287
	288	static void __exit i82860_exit(void)
	289	{
537fba28	290	debugf3("%s()\n", __func__);
0d88a10e AC	291
	292	pci_unregister_driver(&i82860_driver);
	293	if (!i82860_registered) {
	294	i82860_remove_one(mci_pdev);
	295	pci_dev_put(mci_pdev);
	296	}
	297	}
	298
	299	module_init(i82860_init);
	300	module_exit(i82860_exit);
	301
	302	MODULE_LICENSE("GPL");
	303	MODULE_AUTHOR
	304	("Red Hat Inc. (http://www.redhat.com.com) Ben Woodard <woodard@redhat.com>");
	305	MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");