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i7300_edac: Add a FIXME note about the error correction type
[linux-2.6-block.git] / drivers / edac / i7300_edac.c
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fcaf780b
MCC		 1/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 *
10 * Red Hat Inc. http://www.redhat.com
11 *
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
14 *
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
17 *
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/slab.h>
26#include <linux/edac.h>
27#include <linux/mmzone.h>
28
29#include "edac_core.h"
30
31/*
32 * Alter this version for the I7300 module when modifications are made
33 */
34#define I7300_REVISION " Ver: 1.0.0 " __DATE__
35
36#define EDAC_MOD_STR "i7300_edac"
37
38#define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
40
41#define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
43
44/*
45 * Memory topology is organized as:
46 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
47 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
48 * Each channel can have to 8 DIMM sets (called as SLOTS)
49 * Slots should generally be filled in pairs
50 * Except on Single Channel mode of operation
51 * just slot 0/channel0 filled on this mode
52 * On normal operation mode, the two channels on a branch should be
c3af2eaf 53 * filled together for the same SLOT#
fcaf780b
MCC		 54 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
55 * channels on both branches should be filled
56 */
57
58/* Limits for i7300 */
59#define MAX_SLOTS 8
60#define MAX_BRANCHES 2
61#define MAX_CH_PER_BRANCH 2
62#define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
63#define MAX_MIR 3
64
65#define to_channel(ch, branch) ((((branch)) << 1) | (ch))
66
67#define to_csrow(slot, ch, branch) \
68 (to_channel(ch, branch) | ((slot) << 2))
69
c3af2eaf
MCC		 70/*
71 * I7300 devices
fcaf780b
MCC		 72 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
73 * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
74 * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
75 * for device 21 (0,1).
c3af2eaf
MCC		 76 */
77
78/****************************************************
79 * i7300 Register definitions for memory enumberation
80 ****************************************************/
81
82/*
83 * Device 16,
84 * Function 0: System Address (not documented)
85 * Function 1: Memory Branch Map, Control, Errors Register
fcaf780b
MCC		 86 */
87
88 /* OFFSETS for Function 0 */
af3d8831
MCC		 89#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
90#define MAXCH 0x56 /* Max Channel Number */
91#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
fcaf780b
MCC		 92
93 /* OFFSETS for Function 1 */
af3d8831 94#define MC_SETTINGS 0x40
fcaf780b 95
af3d8831
MCC		 96#define TOLM 0x6C
97#define REDMEMB 0x7C
98
99#define MIR0 0x80
100#define MIR1 0x84
101#define MIR2 0x88
fcaf780b 102
fcaf780b
MCC		 103/*
104 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
105 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
106 * seems that we cannot use this information directly for the same usage.
107 * Each memory slot may have up to 2 AMB interfaces, one for income and another
108 * for outcome interface to the next slot.
109 * For now, the driver just stores the AMB present registers, but rely only at
110 * the MTR info to detect memory.
111 * Datasheet is also not clear about how to map each AMBPRESENT registers to
112 * one of the 4 available channels.
113 */
114#define AMBPRESENT_0 0x64
115#define AMBPRESENT_1 0x66
116
117const static u16 mtr_regs [MAX_SLOTS] = {
118 0x80, 0x84, 0x88, 0x8c,
119 0x82, 0x86, 0x8a, 0x8e
120};
121
122/* Defines to extract the vaious fields from the
123 * MTRx - Memory Technology Registers
124 */
125#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
126#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
127#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
128#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
129#define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
130#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
131#define MTR_DRAM_BANKS_ADDR_BITS 2
132#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
133#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
134#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
135
fcaf780b
MCC		 136#ifdef CONFIG_EDAC_DEBUG
137/* MTR NUMROW */
138static const char *numrow_toString[] = {
139 "8,192 - 13 rows",
140 "16,384 - 14 rows",
141 "32,768 - 15 rows",
142 "65,536 - 16 rows"
143};
144
145/* MTR NUMCOL */
146static const char *numcol_toString[] = {
147 "1,024 - 10 columns",
148 "2,048 - 11 columns",
149 "4,096 - 12 columns",
150 "reserved"
151};
152#endif
153
c3af2eaf
MCC		 154/************************************************
155 * i7300 Register definitions for error detection
156 ************************************************/
157/*
158 * Device 16.2: Global Error Registers
159 */
160
161#define FERR_GLOBAL_LO 0x40
162static const char *ferr_global_name[] = {
163 [31] = "Internal MCH Fatal Error",
164 [30] = "Intel QuickData Technology Device Fatal Error",
165 [29] = "FSB1 Fatal Error",
166 [28] = "FSB0 Fatal Error",
167 [27] = "FBD Channel 3 Fatal Error",
168 [26] = "FBD Channel 2 Fatal Error",
169 [25] = "FBD Channel 1 Fatal Error",
170 [24] = "FBD Channel 0 Fatal Error",
171 [23] = "PCI Express Device 7Fatal Error",
172 [22] = "PCI Express Device 6 Fatal Error",
173 [21] = "PCI Express Device 5 Fatal Error",
174 [20] = "PCI Express Device 4 Fatal Error",
175 [19] = "PCI Express Device 3 Fatal Error",
176 [18] = "PCI Express Device 2 Fatal Error",
177 [17] = "PCI Express Device 1 Fatal Error",
178 [16] = "ESI Fatal Error",
179 [15] = "Internal MCH Non-Fatal Error",
180 [14] = "Intel QuickData Technology Device Non Fatal Error",
181 [13] = "FSB1 Non-Fatal Error",
182 [12] = "FSB 0 Non-Fatal Error",
183 [11] = "FBD Channel 3 Non-Fatal Error",
184 [10] = "FBD Channel 2 Non-Fatal Error",
185 [9] = "FBD Channel 1 Non-Fatal Error",
186 [8] = "FBD Channel 0 Non-Fatal Error",
187 [7] = "PCI Express Device 7 Non-Fatal Error",
188 [6] = "PCI Express Device 6 Non-Fatal Error",
189 [5] = "PCI Express Device 5 Non-Fatal Error",
190 [4] = "PCI Express Device 4 Non-Fatal Error",
191 [3] = "PCI Express Device 3 Non-Fatal Error",
192 [2] = "PCI Express Device 2 Non-Fatal Error",
193 [1] = "PCI Express Device 1 Non-Fatal Error",
194 [0] = "ESI Non-Fatal Error",
195};
196
197#define NERR_GLOBAL 0x44
198static const char *nerr_global_name[] = {
199 [31] = "Internal MCH Fatal Error",
200 [30] = "Intel QuickData Technology Device Fatal Error",
201 [29] = "FSB1 Fatal Error",
202 [28] = "FSB0 Fatal Error",
203 [27] = "FSB2 Fatal Error",
204 [26] = "FSB3 Fatal Error",
205 [25] = "Reserved",
206 [24] = "FBD Channel 0,1,2 or 3 Fatal Error",
207 [23] = "PCI Express Device 7 Fatal Error",
208 [22] = "PCI Express Device 6 Fatal Error",
209 [21] = "PCI Express Device 5 Fatal Error",
210 [20] = "PCI Express Device 4 Fatal Error",
211 [19] = "PCI Express Device 3 Fatal Error",
212 [18] = "PCI Express Device 2 Fatal Error",
213 [17] = "PCI Express Device 1 Fatal Error",
214 [16] = "ESI Fatal Error",
215 [15] = "Internal MCH Non-Fatal Error",
216 [14] = "Intel QuickData Technology Device Non Fatal Error",
217 [13] = "FSB1 Non-Fatal Error",
218 [12] = "FSB0 Non-Fatal Error",
219 [11] = "FSB2 Non-Fatal Error",
220 [10] = "FSB3 Non-Fatal Error",
221 [9] = "Reserved",
222 [8] = "FBD Channel 0,1, 2 or 3 Non-Fatal Error",
223 [7] = "PCI Express Device 7 Non-Fatal Error",
224 [6] = "PCI Express Device 6 Non-Fatal Error",
225 [5] = "PCI Express Device 5 Non-Fatal Error",
226 [4] = "PCI Express Device 4 Non-Fatal Error",
227 [3] = "PCI Express Device 3 Non-Fatal Error",
228 [2] = "PCI Express Device 2 Non-Fatal Error",
229 [1] = "PCI Express Device 1 Non-Fatal Error",
230 [0] = "ESI Non-Fatal Error",
231};
232
fcaf780b
MCC		 233#if 0
234
235/*
236 * Error indicator bits and masks
237 * Error masks are according with Table 5-17 of i7300 datasheet
238 */
239
240enum error_mask {
241 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
242 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
243 EMASK_M3 = 1<<2, /* Reserved */
244 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
245 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
246 EMASK_M6 = 1<<5, /* Unsupported on i7300 */
247 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
248 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
249 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
250 EMASK_M10 = 1<<9, /* Unsupported on i7300 */
251 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
252 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
253 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
254 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
255 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
256 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
257 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
258 EMASK_M18 = 1<<17, /* Unsupported on i7300 */
259 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
260 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
261 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
262 EMASK_M22 = 1<<21, /* SPD protocol Error */
263 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
264 EMASK_M24 = 1<<23, /* Refresh error */
265 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
266 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
267 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
268 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
269 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
270};
271
272/*
273 * Names to translate bit error into something useful
274 */
275static const char *error_name[] = {
276 [0] = "Memory Write error on non-redundant retry",
277 [1] = "Memory or FB-DIMM configuration CRC read error",
278 /* Reserved */
279 [3] = "Uncorrectable Data ECC on Replay",
280 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
281 /* M6 Unsupported on i7300 */
282 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
283 [7] = "Aliased Uncorrectable Patrol Data ECC",
284 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
285 /* M10 Unsupported on i7300 */
286 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
287 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
288 [12] = "Memory Write error on first attempt",
289 [13] = "FB-DIMM Configuration Write error on first attempt",
290 [14] = "Memory or FB-DIMM configuration CRC read error",
291 [15] = "Channel Failed-Over Occurred",
292 [16] = "Correctable Non-Mirrored Demand Data ECC",
293 /* M18 Unsupported on i7300 */
294 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
295 [19] = "Correctable Patrol Data ECC",
296 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
297 [21] = "SPD protocol Error",
298 [22] = "Non-Redundant Fast Reset Timeout",
299 [23] = "Refresh error",
300 [24] = "Memory Write error on redundant retry",
301 [25] = "Redundant Fast Reset Timeout",
302 [26] = "Correctable Counter Threshold Exceeded",
303 [27] = "DIMM-Spare Copy Completed",
304 [28] = "DIMM-Isolation Completed",
305};
306
307/* Fatal errors */
308#define ERROR_FAT_MASK (EMASK_M1 | \
309 EMASK_M2 | \
310 EMASK_M23)
311
312/* Correctable errors */
313#define ERROR_NF_CORRECTABLE (EMASK_M27 | \
314 EMASK_M20 | \
315 EMASK_M19 | \
316 EMASK_M18 | \
317 EMASK_M17 | \
318 EMASK_M16)
319#define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
320 EMASK_M28)
321#define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
322#define ERROR_NF_NORTH_CRC (EMASK_M21)
323
324/* Recoverable errors */
325#define ERROR_NF_RECOVERABLE (EMASK_M26 | \
326 EMASK_M25 | \
327 EMASK_M24 | \
328 EMASK_M15 | \
329 EMASK_M14 | \
330 EMASK_M13 | \
331 EMASK_M12 | \
332 EMASK_M11 | \
333 EMASK_M9 | \
334 EMASK_M8 | \
335 EMASK_M7 | \
336 EMASK_M5)
337
338/* uncorrectable errors */
339#define ERROR_NF_UNCORRECTABLE (EMASK_M4)
340
341/* mask to all non-fatal errors */
342#define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
343 ERROR_NF_UNCORRECTABLE | \
344 ERROR_NF_RECOVERABLE | \
345 ERROR_NF_DIMM_SPARE | \
346 ERROR_NF_SPD_PROTOCOL | \
347 ERROR_NF_NORTH_CRC)
348
349/*
350 * Define error masks for the several registers
351 */
352
353/* Enable all fatal and non fatal errors */
354#define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
355
356/* mask for fatal error registers */
357#define FERR_FAT_MASK ERROR_FAT_MASK
358
359/* masks for non-fatal error register */
360static inline int to_nf_mask(unsigned int mask)
361{
362 return (mask & EMASK_M29) | (mask >> 3);
363};
364
365static inline int from_nf_ferr(unsigned int mask)
366{
367 return (mask & EMASK_M29) | /* Bit 28 */
368 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
369};
370
371#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
372#define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
373#define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
374#define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
375#define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
376#define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
377#define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
378
379#endif
380
381/* Device name and register DID (Device ID) */
382struct i7300_dev_info {
383 const char *ctl_name; /* name for this device */
384 u16 fsb_mapping_errors; /* DID for the branchmap,control */
385};
386
387/* Table of devices attributes supported by this driver */
388static const struct i7300_dev_info i7300_devs[] = {
389 {
390 .ctl_name = "I7300",
391 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
392 },
393};
394
395struct i7300_dimm_info {
396 int megabytes; /* size, 0 means not present */
397};
398
399/* driver private data structure */
400struct i7300_pvt {
401 struct pci_dev *system_address; /* 16.0 */
402 struct pci_dev *branchmap_werrors; /* 16.1 */
403 struct pci_dev *fsb_error_regs; /* 16.2 */
404 struct pci_dev *branch_pci[MAX_BRANCHES]; /* 21.0 and 22.0 */
405
406 u16 tolm; /* top of low memory */
407 u64 ambase; /* AMB BAR */
af3d8831 408 u32 mc_settings;
fcaf780b
MCC		 409
410 u16 mir[MAX_MIR];
411
412 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
413 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
414
415 /* DIMM information matrix, allocating architecture maximums */
416 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
417};
418
419#if 0
420/* I7300 MCH error information retrieved from Hardware */
421struct i7300_error_info {
422 /* These registers are always read from the MC */
423 u32 ferr_fat_fbd; /* First Errors Fatal */
424 u32 nerr_fat_fbd; /* Next Errors Fatal */
425 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
426 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
427
428 /* These registers are input ONLY if there was a Recoverable Error */
429 u32 redmemb; /* Recoverable Mem Data Error log B */
430 u16 recmema; /* Recoverable Mem Error log A */
431 u32 recmemb; /* Recoverable Mem Error log B */
432
433 /* These registers are input ONLY if there was a Non-Rec Error */
434 u16 nrecmema; /* Non-Recoverable Mem log A */
435 u16 nrecmemb; /* Non-Recoverable Mem log B */
436
437};
438#endif
439
440/* FIXME: Why do we need to have this static? */
441static struct edac_pci_ctl_info *i7300_pci;
442
443
444#if 0
445/* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
446 5400 better to use an inline function than a macro in this case */
447static inline int nrec_bank(struct i7300_error_info *info)
448{
449 return ((info->nrecmema) >> 12) & 0x7;
450}
451static inline int nrec_rank(struct i7300_error_info *info)
452{
453 return ((info->nrecmema) >> 8) & 0xf;
454}
455static inline int nrec_buf_id(struct i7300_error_info *info)
456{
457 return ((info->nrecmema)) & 0xff;
458}
459static inline int nrec_rdwr(struct i7300_error_info *info)
460{
461 return (info->nrecmemb) >> 31;
462}
463/* This applies to both NREC and REC string so it can be used with nrec_rdwr
464 and rec_rdwr */
465static inline const char *rdwr_str(int rdwr)
466{
467 return rdwr ? "Write" : "Read";
468}
469static inline int nrec_cas(struct i7300_error_info *info)
470{
471 return ((info->nrecmemb) >> 16) & 0x1fff;
472}
473static inline int nrec_ras(struct i7300_error_info *info)
474{
475 return (info->nrecmemb) & 0xffff;
476}
477static inline int rec_bank(struct i7300_error_info *info)
478{
479 return ((info->recmema) >> 12) & 0x7;
480}
481static inline int rec_rank(struct i7300_error_info *info)
482{
483 return ((info->recmema) >> 8) & 0xf;
484}
485static inline int rec_rdwr(struct i7300_error_info *info)
486{
487 return (info->recmemb) >> 31;
488}
489static inline int rec_cas(struct i7300_error_info *info)
490{
491 return ((info->recmemb) >> 16) & 0x1fff;
492}
493static inline int rec_ras(struct i7300_error_info *info)
494{
495 return (info->recmemb) & 0xffff;
496}
497
498/*
499 * i7300_get_error_info Retrieve the hardware error information from
500 * the hardware and cache it in the 'info'
501 * structure
502 */
503static void i7300_get_error_info(struct mem_ctl_info *mci,
504 struct i7300_error_info *info)
505{
506 struct i7300_pvt *pvt;
507 u32 value;
508
509 pvt = mci->pvt_info;
510
511 /* read in the 1st FATAL error register */
512 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
513
514 /* Mask only the bits that the doc says are valid
515 */
516 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
517
518 /* If there is an error, then read in the
519 NEXT FATAL error register and the Memory Error Log Register A
520 */
521 if (value & FERR_FAT_MASK) {
522 info->ferr_fat_fbd = value;
523
524 /* harvest the various error data we need */
525 pci_read_config_dword(pvt->branchmap_werrors,
526 NERR_FAT_FBD, &info->nerr_fat_fbd);
527 pci_read_config_word(pvt->branchmap_werrors,
528 NRECMEMA, &info->nrecmema);
529 pci_read_config_word(pvt->branchmap_werrors,
530 NRECMEMB, &info->nrecmemb);
531
532 /* Clear the error bits, by writing them back */
533 pci_write_config_dword(pvt->branchmap_werrors,
534 FERR_FAT_FBD, value);
535 } else {
536 info->ferr_fat_fbd = 0;
537 info->nerr_fat_fbd = 0;
538 info->nrecmema = 0;
539 info->nrecmemb = 0;
540 }
541
542 /* read in the 1st NON-FATAL error register */
543 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
544
545 /* If there is an error, then read in the 1st NON-FATAL error
546 * register as well */
547 if (value & FERR_NF_MASK) {
548 info->ferr_nf_fbd = value;
549
550 /* harvest the various error data we need */
551 pci_read_config_dword(pvt->branchmap_werrors,
552 NERR_NF_FBD, &info->nerr_nf_fbd);
553 pci_read_config_word(pvt->branchmap_werrors,
554 RECMEMA, &info->recmema);
555 pci_read_config_dword(pvt->branchmap_werrors,
556 RECMEMB, &info->recmemb);
557 pci_read_config_dword(pvt->branchmap_werrors,
558 REDMEMB, &info->redmemb);
559
560 /* Clear the error bits, by writing them back */
561 pci_write_config_dword(pvt->branchmap_werrors,
562 FERR_NF_FBD, value);
563 } else {
564 info->ferr_nf_fbd = 0;
565 info->nerr_nf_fbd = 0;
566 info->recmema = 0;
567 info->recmemb = 0;
568 info->redmemb = 0;
569 }
570}
571
572/*
573 * i7300_proccess_non_recoverable_info(struct mem_ctl_info *mci,
574 * struct i7300_error_info *info,
575 * int handle_errors);
576 *
577 * handle the Intel FATAL and unrecoverable errors, if any
578 */
579static void i7300_proccess_non_recoverable_info(struct mem_ctl_info *mci,
580 struct i7300_error_info *info,
581 unsigned long allErrors)
582{
583 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
584 int branch;
585 int channel;
586 int bank;
587 int buf_id;
588 int rank;
589 int rdwr;
590 int ras, cas;
591 int errnum;
592 char *type = NULL;
593
594 if (!allErrors)
595 return; /* if no error, return now */
596
597 if (allErrors & ERROR_FAT_MASK)
598 type = "FATAL";
599 else if (allErrors & FERR_NF_UNCORRECTABLE)
600 type = "NON-FATAL uncorrected";
601 else
602 type = "NON-FATAL recoverable";
603
604 /* ONLY ONE of the possible error bits will be set, as per the docs */
605
606 branch = extract_fbdchan_indx(info->ferr_fat_fbd);
607 channel = branch;
608
609 /* Use the NON-Recoverable macros to extract data */
610 bank = nrec_bank(info);
611 rank = nrec_rank(info);
612 buf_id = nrec_buf_id(info);
613 rdwr = nrec_rdwr(info);
614 ras = nrec_ras(info);
615 cas = nrec_cas(info);
616
617 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
618 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
619 rank, channel, channel + 1, branch >> 1, bank,
620 buf_id, rdwr_str(rdwr), ras, cas);
621
622 /* Only 1 bit will be on */
623 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
624
625 /* Form out message */
626 snprintf(msg, sizeof(msg),
627 "%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
628 "RAS=%d CAS=%d %s Err=0x%lx (%s))",
629 type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
630 type, allErrors, error_name[errnum]);
631
632 /* Call the helper to output message */
633 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
634}
635
636/*
637 * i7300_process_fatal_error_info(struct mem_ctl_info *mci,
638 * struct i7300_error_info *info,
639 * int handle_errors);
640 *
641 * handle the Intel NON-FATAL errors, if any
642 */
643static void i7300_process_nonfatal_error_info(struct mem_ctl_info *mci,
644 struct i7300_error_info *info)
645{
646 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
647 unsigned long allErrors;
648 int branch;
649 int channel;
650 int bank;
651 int rank;
652 int rdwr;
653 int ras, cas;
654 int errnum;
655
656 /* mask off the Error bits that are possible */
657 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
658 if (!allErrors)
659 return; /* if no error, return now */
660
661 /* ONLY ONE of the possible error bits will be set, as per the docs */
662
663 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
664 i7300_proccess_non_recoverable_info(mci, info, allErrors);
665 return;
666 }
667
668 /* Correctable errors */
669 if (allErrors & ERROR_NF_CORRECTABLE) {
670 debugf0("\tCorrected bits= 0x%lx\n", allErrors);
671
672 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
673
674 channel = 0;
675 if (REC_ECC_LOCATOR_ODD(info->redmemb))
676 channel = 1;
677
678 /* Convert channel to be based from zero, instead of
679 * from branch base of 0 */
680 channel += branch;
681
682 bank = rec_bank(info);
683 rank = rec_rank(info);
684 rdwr = rec_rdwr(info);
685 ras = rec_ras(info);
686 cas = rec_cas(info);
687
688 /* Only 1 bit will be on */
689 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
690
691 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
692 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
693 rank, channel, branch >> 1, bank,
694 rdwr_str(rdwr), ras, cas);
695
696 /* Form out message */
697 snprintf(msg, sizeof(msg),
698 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
699 "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
700 branch >> 1, bank, rdwr_str(rdwr), ras, cas,
701 allErrors, error_name[errnum]);
702
703 /* Call the helper to output message */
704 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
705
706 return;
707 }
708
709 /* Miscelaneous errors */
710 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
711
712 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
713
714 i7300_mc_printk(mci, KERN_EMERG,
715 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
716 branch >> 1, allErrors, error_name[errnum]);
717}
718
719/*
720 * i7300_process_error_info Process the error info that is
721 * in the 'info' structure, previously retrieved from hardware
722 */
723static void i7300_process_error_info(struct mem_ctl_info *mci,
724 struct i7300_error_info *info)
725{ u32 allErrors;
726
727 /* First handle any fatal errors that occurred */
728 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
729 i7300_proccess_non_recoverable_info(mci, info, allErrors);
730
731 /* now handle any non-fatal errors that occurred */
732 i7300_process_nonfatal_error_info(mci, info);
733}
734
735/*
736 * i7300_clear_error Retrieve any error from the hardware
737 * but do NOT process that error.
738 * Used for 'clearing' out of previous errors
739 * Called by the Core module.
740 */
741static void i7300_clear_error(struct mem_ctl_info *mci)
742{
743 struct i7300_error_info info;
744
745 i7300_get_error_info(mci, &info);
746}
747
748/*
749 * i7300_check_error Retrieve and process errors reported by the
750 * hardware. Called by the Core module.
751 */
752static void i7300_check_error(struct mem_ctl_info *mci)
753{
754 struct i7300_error_info info;
755 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
756 i7300_get_error_info(mci, &info);
757 i7300_process_error_info(mci, &info);
758}
759
760/*
761 * i7300_enable_error_reporting
762 * Turn on the memory reporting features of the hardware
763 */
764static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
765{
766 struct i7300_pvt *pvt;
767 u32 fbd_error_mask;
768
769 pvt = mci->pvt_info;
770
771 /* Read the FBD Error Mask Register */
772 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
773 &fbd_error_mask);
774
775 /* Enable with a '0' */
776 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
777
778 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
779 fbd_error_mask);
780}
781#endif
782
783/*
784 * determine_mtr(pvt, csrow, channel)
785 *
786 * return the proper MTR register as determine by the csrow and desired channel
787 */
788static int decode_mtr(struct i7300_pvt *pvt,
789 int slot, int ch, int branch,
790 struct i7300_dimm_info *dinfo,
791 struct csrow_info *p_csrow)
792{
793 int mtr, ans, addrBits, channel;
794
795 channel = to_channel(ch, branch);
796
797 mtr = pvt->mtr[slot][branch];
798 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
799
800 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
801 slot, channel,
802 ans ? "Present" : "NOT Present");
803
804 /* Determine if there is a DIMM present in this DIMM slot */
805
806#if 0
807 if (!amb_present || !ans)
808 return 0;
809#else
810 if (!ans)
811 return 0;
812#endif
813
814 /* Start with the number of bits for a Bank
815 * on the DRAM */
816 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
817 /* Add thenumber of ROW bits */
818 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
819 /* add the number of COLUMN bits */
820 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
821 /* add the number of RANK bits */
822 addrBits += MTR_DIMM_RANKS(mtr);
823
824 addrBits += 6; /* add 64 bits per DIMM */
825 addrBits -= 20; /* divide by 2^^20 */
826 addrBits -= 3; /* 8 bits per bytes */
827
828 dinfo->megabytes = 1 << addrBits;
829
830 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
831
832 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
833 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
834
835 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
836 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
837 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
838 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
839 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
840
841 p_csrow->grain = 8;
842 p_csrow->nr_pages = dinfo->megabytes << 8;
843 p_csrow->mtype = MEM_FB_DDR2;
116389ed
MCC		 844
845 /*
846 * FIXME: the type of error detection actually depends of the
847 * mode of operation. When it is just one single memory chip, at
848 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
849 * In normal or mirrored mode, it uses Single Device Data correction,
850 * with the possibility of using an extended algorithm for x8 memories
851 * See datasheet Sections 7.3.6 to 7.3.8
852 */
fcaf780b
MCC		 853 p_csrow->edac_mode = EDAC_S8ECD8ED;
854
855 /* ask what device type on this row */
856 if (MTR_DRAM_WIDTH(mtr))
857 p_csrow->dtype = DEV_X8;
858 else
859 p_csrow->dtype = DEV_X4;
860
861 return mtr;
862}
863
864/*
865 * print_dimm_size
866 *
867 * also will output a DIMM matrix map, if debug is enabled, for viewing
868 * how the DIMMs are populated
869 */
870static void print_dimm_size(struct i7300_pvt *pvt)
871{
872 struct i7300_dimm_info *dinfo;
873 char *p, *mem_buffer;
874 int space, n;
875 int channel, slot;
876
877 space = PAGE_SIZE;
878 mem_buffer = p = kmalloc(space, GFP_KERNEL);
879 if (p == NULL) {
880 i7300_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
881 __FILE__, __func__);
882 return;
883 }
884
885 n = snprintf(p, space, " ");
886 p += n;
887 space -= n;
888 for (channel = 0; channel < MAX_CHANNELS; channel++) {
889 n = snprintf(p, space, "channel %d | ", channel);
890 p += n;
891 space -= n;
892 }
893 debugf2("%s\n", mem_buffer);
894 p = mem_buffer;
895 space = PAGE_SIZE;
896 n = snprintf(p, space, "-------------------------------"
897 "------------------------------");
898 p += n;
899 space -= n;
900 debugf2("%s\n", mem_buffer);
901 p = mem_buffer;
902 space = PAGE_SIZE;
903
904 for (slot = 0; slot < MAX_SLOTS; slot++) {
905 n = snprintf(p, space, "csrow/SLOT %d ", slot);
906 p += n;
907 space -= n;
908
909 for (channel = 0; channel < MAX_CHANNELS; channel++) {
910 dinfo = &pvt->dimm_info[slot][channel];
911 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
912 p += n;
913 space -= n;
914 }
915
916 debugf2("%s\n", mem_buffer);
917 p = mem_buffer;
918 space = PAGE_SIZE;
919 }
920
921 n = snprintf(p, space, "-------------------------------"
922 "------------------------------");
923 p += n;
924 space -= n;
925 debugf2("%s\n", mem_buffer);
926 p = mem_buffer;
927 space = PAGE_SIZE;
928
929 kfree(mem_buffer);
930}
931
932/*
933 * i7300_init_csrows Initialize the 'csrows' table within
934 * the mci control structure with the
935 * addressing of memory.
936 *
937 * return:
938 * 0 success
939 * 1 no actual memory found on this MC
940 */
941static int i7300_init_csrows(struct mem_ctl_info *mci)
942{
943 struct i7300_pvt *pvt;
944 struct i7300_dimm_info *dinfo;
945 struct csrow_info *p_csrow;
946 int empty;
947 int mtr;
948 int ch, branch, slot, channel;
949
950 pvt = mci->pvt_info;
951
952 empty = 1; /* Assume NO memory */
953
954 debugf2("Memory Technology Registers:\n");
955
956 /* Get the AMB present registers for the four channels */
957 for (branch = 0; branch < MAX_BRANCHES; branch++) {
958 /* Read and dump branch 0's MTRs */
959 channel = to_channel(0, branch);
960 pci_read_config_word(pvt->branch_pci[branch], AMBPRESENT_0,
961 &pvt->ambpresent[channel]);
962 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
963 channel, pvt->ambpresent[channel]);
964
965 channel = to_channel(1, branch);
966 pci_read_config_word(pvt->branch_pci[branch], AMBPRESENT_1,
967 &pvt->ambpresent[channel]);
968 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
969 channel, pvt->ambpresent[channel]);
970 }
971
972 /* Get the set of MTR[0-7] regs by each branch */
973 for (slot = 0; slot < MAX_SLOTS; slot++) {
974 int where = mtr_regs[slot];
975 for (branch = 0; branch < MAX_BRANCHES; branch++) {
976 pci_read_config_word(pvt->branch_pci[branch],
977 where,
978 &pvt->mtr[slot][branch]);
979 for (ch = 0; ch < MAX_BRANCHES; ch++) {
980 int channel = to_channel(ch, branch);
981
982 dinfo = &pvt->dimm_info[slot][channel];
983 p_csrow = &mci->csrows[slot];
984
985 mtr = decode_mtr(pvt, slot, ch, branch,
986 dinfo, p_csrow);
987 /* if no DIMMS on this row, continue */
988 if (!MTR_DIMMS_PRESENT(mtr))
989 continue;
990
991 p_csrow->csrow_idx = slot;
992
993 /* FAKE OUT VALUES, FIXME */
994 p_csrow->first_page = 0 + slot * 20;
995 p_csrow->last_page = 9 + slot * 20;
996 p_csrow->page_mask = 0xfff;
997
998 empty = 0;
999 }
1000 }
1001 }
1002
1003 return empty;
1004}
1005
1006static void decode_mir(int mir_no, u16 mir[MAX_MIR])
1007{
1008 if (mir[mir_no] & 3)
1009 debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
1010 mir_no,
1011 (mir[mir_no] >> 4) & 0xfff,
1012 (mir[mir_no] & 1) ? "B0" : "",
1013 (mir[mir_no] & 2) ? "B1": "");
1014}
1015
1016/*
1017 * i7300_get_mc_regs read in the necessary registers and
1018 * cache locally
1019 *
1020 * Fills in the private data members
1021 */
1022static int i7300_get_mc_regs(struct mem_ctl_info *mci)
1023{
1024 struct i7300_pvt *pvt;
1025 u32 actual_tolm;
1026 int i, rc;
1027
1028 pvt = mci->pvt_info;
1029
1030 pci_read_config_dword(pvt->system_address, AMBASE,
1031 (u32 *) &pvt->ambase);
1032
1033 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
1034
1035 /* Get the Branch Map regs */
1036 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1037 pvt->tolm >>= 12;
1038 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1039 pvt->tolm);
1040
1041 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1042 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1043 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1044
af3d8831
MCC		 1045 /* Get memory controller settings */
1046 pci_read_config_dword(pvt->branchmap_werrors, MC_SETTINGS,
1047 &pvt->mc_settings);
1048 debugf0("Memory controller operating on %s mode\n",
1049 pvt->mc_settings & (1 << 16)? "mirrored" : "non-mirrored");
1050 debugf0("Error detection is %s\n",
1051 pvt->mc_settings & (1 << 5)? "enabled" : "disabled");
1052
1053 /* Get Memory Interleave Range registers */
fcaf780b
MCC		 1054 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir[0]);
1055 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir[1]);
1056 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir[2]);
1057
1058 /* Decode the MIR regs */
1059 for (i = 0; i < MAX_MIR; i++)
1060 decode_mir(i, pvt->mir);
1061
1062 rc = i7300_init_csrows(mci);
1063 if (rc < 0)
1064 return rc;
1065
1066 /* Go and determine the size of each DIMM and place in an
1067 * orderly matrix */
1068 print_dimm_size(pvt);
1069
1070 return 0;
1071}
1072
1073/*
1074 * i7300_put_devices 'put' all the devices that we have
1075 * reserved via 'get'
1076 */
1077static void i7300_put_devices(struct mem_ctl_info *mci)
1078{
1079 struct i7300_pvt *pvt;
1080 int branch;
1081
1082 pvt = mci->pvt_info;
1083
1084 /* Decrement usage count for devices */
1085 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
1086 pci_dev_put(pvt->branch_pci[branch]);
1087 pci_dev_put(pvt->fsb_error_regs);
1088 pci_dev_put(pvt->branchmap_werrors);
1089}
1090
1091/*
1092 * i7300_get_devices Find and perform 'get' operation on the MCH's
1093 * device/functions we want to reference for this driver
1094 *
1095 * Need to 'get' device 16 func 1 and func 2
1096 */
1097static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx)
1098{
1099 struct i7300_pvt *pvt;
1100 struct pci_dev *pdev;
1101
1102 pvt = mci->pvt_info;
1103
1104 /* Attempt to 'get' the MCH register we want */
1105 pdev = NULL;
1106 while (!pvt->branchmap_werrors || !pvt->fsb_error_regs) {
1107 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1108 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
1109 if (!pdev) {
1110 /* End of list, leave */
1111 i7300_printk(KERN_ERR,
1112 "'system address,Process Bus' "
1113 "device not found:"
1114 "vendor 0x%x device 0x%x ERR funcs "
1115 "(broken BIOS?)\n",
1116 PCI_VENDOR_ID_INTEL,
1117 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
1118 goto error;
1119 }
1120
1121 /* Store device 16 funcs 1 and 2 */
1122 switch (PCI_FUNC(pdev->devfn)) {
1123 case 1:
1124 pvt->branchmap_werrors = pdev;
1125 break;
1126 case 2:
1127 pvt->fsb_error_regs = pdev;
1128 break;
1129 }
1130 }
1131
1132 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
1133 pci_name(pvt->system_address),
1134 pvt->system_address->vendor, pvt->system_address->device);
1135 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
1136 pci_name(pvt->branchmap_werrors),
1137 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
1138 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
1139 pci_name(pvt->fsb_error_regs),
1140 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
1141
1142 pvt->branch_pci[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
1143 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
1144 NULL);
1145 if (!pvt->branch_pci[0]) {
1146 i7300_printk(KERN_ERR,
1147 "MC: 'BRANCH 0' device not found:"
1148 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
1149 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
1150 goto error;
1151 }
1152
1153 pvt->branch_pci[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
1154 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
1155 NULL);
1156 if (!pvt->branch_pci[1]) {
1157 i7300_printk(KERN_ERR,
1158 "MC: 'BRANCH 1' device not found:"
1159 "vendor 0x%x device 0x%x Func 0 "
1160 "(broken BIOS?)\n",
1161 PCI_VENDOR_ID_INTEL,
1162 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
1163 goto error;
1164 }
1165
1166 return 0;
1167
1168error:
1169 i7300_put_devices(mci);
1170 return -ENODEV;
1171}
1172
1173/*
1174 * i7300_probe1 Probe for ONE instance of device to see if it is
1175 * present.
1176 * return:
1177 * 0 for FOUND a device
1178 * < 0 for error code
1179 */
1180static int i7300_probe1(struct pci_dev *pdev, int dev_idx)
1181{
1182 struct mem_ctl_info *mci;
1183 struct i7300_pvt *pvt;
1184 int num_channels;
1185 int num_dimms_per_channel;
1186 int num_csrows;
1187
1188 if (dev_idx >= ARRAY_SIZE(i7300_devs))
1189 return -EINVAL;
1190
1191 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1192 __func__,
1193 pdev->bus->number,
1194 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1195
1196 /* We only are looking for func 0 of the set */
1197 if (PCI_FUNC(pdev->devfn) != 0)
1198 return -ENODEV;
1199
1200 /* As we don't have a motherboard identification routine to determine
1201 * actual number of slots/dimms per channel, we thus utilize the
1202 * resource as specified by the chipset. Thus, we might have
1203 * have more DIMMs per channel than actually on the mobo, but this
1204 * allows the driver to support upto the chipset max, without
1205 * some fancy mobo determination.
1206 */
1207 num_dimms_per_channel = MAX_SLOTS;
1208 num_channels = MAX_CHANNELS;
1209 num_csrows = MAX_SLOTS * MAX_CHANNELS;
1210
1211 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1212 __func__, num_channels, num_dimms_per_channel, num_csrows);
1213
1214 /* allocate a new MC control structure */
1215 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1216
1217 if (mci == NULL)
1218 return -ENOMEM;
1219
1220 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1221
1222 mci->dev = &pdev->dev; /* record ptr to the generic device */
1223
1224 pvt = mci->pvt_info;
1225 pvt->system_address = pdev; /* Record this device in our private */
1226
1227 /* 'get' the pci devices we want to reserve for our use */
1228 if (i7300_get_devices(mci, dev_idx))
1229 goto fail0;
1230
1231 mci->mc_idx = 0;
1232 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1233 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1234 mci->edac_cap = EDAC_FLAG_NONE;
1235 mci->mod_name = "i7300_edac.c";
1236 mci->mod_ver = I7300_REVISION;
1237 mci->ctl_name = i7300_devs[dev_idx].ctl_name;
1238 mci->dev_name = pci_name(pdev);
1239 mci->ctl_page_to_phys = NULL;
1240
1241#if 0
1242 /* Set the function pointer to an actual operation function */
1243 mci->edac_check = i7300_check_error;
1244#endif
1245
1246 /* initialize the MC control structure 'csrows' table
1247 * with the mapping and control information */
1248 if (i7300_get_mc_regs(mci)) {
1249 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1250 " because i7300_init_csrows() returned nonzero "
1251 "value\n");
1252 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1253 } else {
1254#if 0
1255 debugf1("MC: Enable error reporting now\n");
1256 i7300_enable_error_reporting(mci);
1257#endif
1258 }
1259
1260 /* add this new MC control structure to EDAC's list of MCs */
1261 if (edac_mc_add_mc(mci)) {
1262 debugf0("MC: " __FILE__
1263 ": %s(): failed edac_mc_add_mc()\n", __func__);
1264 /* FIXME: perhaps some code should go here that disables error
1265 * reporting if we just enabled it
1266 */
1267 goto fail1;
1268 }
1269
1270#if 0
1271 i7300_clear_error(mci);
1272#endif
1273
1274 /* allocating generic PCI control info */
1275 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1276 if (!i7300_pci) {
1277 printk(KERN_WARNING
1278 "%s(): Unable to create PCI control\n",
1279 __func__);
1280 printk(KERN_WARNING
1281 "%s(): PCI error report via EDAC not setup\n",
1282 __func__);
1283 }
1284
1285 return 0;
1286
1287 /* Error exit unwinding stack */
1288fail1:
1289
1290 i7300_put_devices(mci);
1291
1292fail0:
1293 edac_mc_free(mci);
1294 return -ENODEV;
1295}
1296
1297/*
1298 * i7300_init_one constructor for one instance of device
1299 *
1300 * returns:
1301 * negative on error
1302 * count (>= 0)
1303 */
1304static int __devinit i7300_init_one(struct pci_dev *pdev,
1305 const struct pci_device_id *id)
1306{
1307 int rc;
1308
1309 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1310
1311 /* wake up device */
1312 rc = pci_enable_device(pdev);
1313 if (rc == -EIO)
1314 return rc;
1315
1316 /* now probe and enable the device */
1317 return i7300_probe1(pdev, id->driver_data);
1318}
1319
1320/*
1321 * i7300_remove_one destructor for one instance of device
1322 *
1323 */
1324static void __devexit i7300_remove_one(struct pci_dev *pdev)
1325{
1326 struct mem_ctl_info *mci;
1327
1328 debugf0(__FILE__ ": %s()\n", __func__);
1329
1330 if (i7300_pci)
1331 edac_pci_release_generic_ctl(i7300_pci);
1332
1333 mci = edac_mc_del_mc(&pdev->dev);
1334 if (!mci)
1335 return;
1336
1337 /* retrieve references to resources, and free those resources */
1338 i7300_put_devices(mci);
1339
1340 edac_mc_free(mci);
1341}
1342
1343/*
1344 * pci_device_id table for which devices we are looking for
1345 *
1346 * The "E500P" device is the first device supported.
1347 */
1348static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
1349 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
1350 {0,} /* 0 terminated list. */
1351};
1352
1353MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
1354
1355/*
1356 * i7300_driver pci_driver structure for this module
1357 *
1358 */
1359static struct pci_driver i7300_driver = {
1360 .name = "i7300_edac",
1361 .probe = i7300_init_one,
1362 .remove = __devexit_p(i7300_remove_one),
1363 .id_table = i7300_pci_tbl,
1364};
1365
1366/*
1367 * i7300_init Module entry function
1368 * Try to initialize this module for its devices
1369 */
1370static int __init i7300_init(void)
1371{
1372 int pci_rc;
1373
1374 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1375
1376 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1377 opstate_init();
1378
1379 pci_rc = pci_register_driver(&i7300_driver);
1380
1381 return (pci_rc < 0) ? pci_rc : 0;
1382}
1383
1384/*
1385 * i7300_exit() Module exit function
1386 * Unregister the driver
1387 */
1388static void __exit i7300_exit(void)
1389{
1390 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1391 pci_unregister_driver(&i7300_driver);
1392}
1393
1394module_init(i7300_init);
1395module_exit(i7300_exit);
1396
1397MODULE_LICENSE("GPL");
1398MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1399MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1400MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1401 I7300_REVISION);
1402
1403module_param(edac_op_state, int, 0444);
1404MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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