[linux-2.6-block.git] / drivers / edac / i3200_edac.c

/*
 * Intel 3200/3210 Memory Controller kernel module
 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
 * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include <linux/io.h>
#include "edac_core.h"

#include <asm-generic/io-64-nonatomic-lo-hi.h>

#define I3200_REVISION        "1.1"

#define EDAC_MOD_STR        "i3200_edac"

#define PCI_DEVICE_ID_INTEL_3200_HB    0x29f0

#define I3200_DIMMS		4
#define I3200_RANKS		8
#define I3200_RANKS_PER_CHANNEL	4
#define I3200_CHANNELS		2

/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */

#define I3200_MCHBAR_LOW	0x48	/* MCH Memory Mapped Register BAR */
#define I3200_MCHBAR_HIGH	0x4c
#define I3200_MCHBAR_MASK	0xfffffc000ULL	/* bits 35:14 */
#define I3200_MMR_WINDOW_SIZE	16384

#define I3200_TOM		0xa0	/* Top of Memory (16b)
		 *
		 * 15:10 reserved
		 *  9:0  total populated physical memory
		 */
#define I3200_TOM_MASK		0x3ff	/* bits 9:0 */
#define I3200_TOM_SHIFT		26	/* 64MiB grain */

#define I3200_ERRSTS		0xc8	/* Error Status Register (16b)
		 *
		 * 15    reserved
		 * 14    Isochronous TBWRR Run Behind FIFO Full
		 *       (ITCV)
		 * 13    Isochronous TBWRR Run Behind FIFO Put
		 *       (ITSTV)
		 * 12    reserved
		 * 11    MCH Thermal Sensor Event
		 *       for SMI/SCI/SERR (GTSE)
		 * 10    reserved
		 *  9    LOCK to non-DRAM Memory Flag (LCKF)
		 *  8    reserved
		 *  7    DRAM Throttle Flag (DTF)
		 *  6:2  reserved
		 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
		 *  0    Single-bit DRAM ECC Error Flag (DSERR)
		 */
#define I3200_ERRSTS_UE		0x0002
#define I3200_ERRSTS_CE		0x0001
#define I3200_ERRSTS_BITS	(I3200_ERRSTS_UE | I3200_ERRSTS_CE)


/* Intel  MMIO register space - device 0 function 0 - MMR space */

#define I3200_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
		 *
		 * 15:10 reserved
		 *  9:0  Channel 0 DRAM Rank Boundary Address
		 */
#define I3200_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
#define I3200_DRB_MASK	0x3ff	/* bits 9:0 */
#define I3200_DRB_SHIFT	26	/* 64MiB grain */

#define I3200_C0ECCERRLOG	0x280	/* Channel 0 ECC Error Log (64b)
		 *
		 * 63:48 Error Column Address (ERRCOL)
		 * 47:32 Error Row Address (ERRROW)
		 * 31:29 Error Bank Address (ERRBANK)
		 * 28:27 Error Rank Address (ERRRANK)
		 * 26:24 reserved
		 * 23:16 Error Syndrome (ERRSYND)
		 * 15: 2 reserved
		 *    1  Multiple Bit Error Status (MERRSTS)
		 *    0  Correctable Error Status (CERRSTS)
		 */
#define I3200_C1ECCERRLOG		0x680	/* Chan 1 ECC Error Log (64b) */
#define I3200_ECCERRLOG_CE		0x1
#define I3200_ECCERRLOG_UE		0x2
#define I3200_ECCERRLOG_RANK_BITS	0x18000000
#define I3200_ECCERRLOG_RANK_SHIFT	27
#define I3200_ECCERRLOG_SYNDROME_BITS	0xff0000
#define I3200_ECCERRLOG_SYNDROME_SHIFT	16
#define I3200_CAPID0			0xe0	/* P.95 of spec for details */

struct i3200_priv {
	void __iomem *window;
};

static int nr_channels;

static int how_many_channels(struct pci_dev *pdev)
{
	int n_channels;

	unsigned char capid0_8b; /* 8th byte of CAPID0 */

	pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);

	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
		edac_dbg(0, "In single channel mode\n");
		n_channels = 1;
	} else {
		edac_dbg(0, "In dual channel mode\n");
		n_channels = 2;
	}

	if (capid0_8b & 0x10) /* check if both channels are filled */
		edac_dbg(0, "2 DIMMS per channel disabled\n");
	else
		edac_dbg(0, "2 DIMMS per channel enabled\n");

	return n_channels;
}

static unsigned long eccerrlog_syndrome(u64 log)
{
	return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
		I3200_ECCERRLOG_SYNDROME_SHIFT;
}

static int eccerrlog_row(int channel, u64 log)
{
	u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
		I3200_ECCERRLOG_RANK_SHIFT);
	return rank | (channel * I3200_RANKS_PER_CHANNEL);
}

enum i3200_chips {
	I3200 = 0,
};

struct i3200_dev_info {
	const char *ctl_name;
};

struct i3200_error_info {
	u16 errsts;
	u16 errsts2;
	u64 eccerrlog[I3200_CHANNELS];
};

static const struct i3200_dev_info i3200_devs[] = {
	[I3200] = {
		.ctl_name = "i3200"
	},
};

static struct pci_dev *mci_pdev;
static int i3200_registered = 1;


static void i3200_clear_error_info(struct mem_ctl_info *mci)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
		I3200_ERRSTS_BITS);
}

static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
		struct i3200_error_info *info)
{
	struct pci_dev *pdev;
	struct i3200_priv *priv = mci->pvt_info;
	void __iomem *window = priv->window;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
	if (!(info->errsts & I3200_ERRSTS_BITS))
		return;

	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
	if (nr_channels == 2)
		info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);

	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same for both reads then the first set
	 * of reads is valid.  If there is a change then there is a CE
	 * with no info and the second set of reads is valid and
	 * should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
		info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
		if (nr_channels == 2)
			info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
	}

	i3200_clear_error_info(mci);
}

static void i3200_process_error_info(struct mem_ctl_info *mci,
		struct i3200_error_info *info)
{
	int channel;
	u64 log;

	if (!(info->errsts & I3200_ERRSTS_BITS))
		return;

	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
				     -1, -1, -1, "UE overwrote CE", "");
		info->errsts = info->errsts2;
	}

	for (channel = 0; channel < nr_channels; channel++) {
		log = info->eccerrlog[channel];
		if (log & I3200_ECCERRLOG_UE) {
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     0, 0, 0,
					     eccerrlog_row(channel, log),
					     -1, -1,
					     "i3000 UE", "");
		} else if (log & I3200_ECCERRLOG_CE) {
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     0, 0, eccerrlog_syndrome(log),
					     eccerrlog_row(channel, log),
					     -1, -1,
					     "i3000 UE", "");
		}
	}
}

static void i3200_check(struct mem_ctl_info *mci)
{
	struct i3200_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i3200_get_and_clear_error_info(mci, &info);
	i3200_process_error_info(mci, &info);
}


void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
{
	union {
		u64 mchbar;
		struct {
			u32 mchbar_low;
			u32 mchbar_high;
		};
	} u;
	void __iomem *window;

	pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
	pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
	u.mchbar &= I3200_MCHBAR_MASK;

	if (u.mchbar != (resource_size_t)u.mchbar) {
		printk(KERN_ERR
			"i3200: mmio space beyond accessible range (0x%llx)\n",
			(unsigned long long)u.mchbar);
		return NULL;
	}

	window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
	if (!window)
		printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
			(unsigned long long)u.mchbar);

	return window;
}


static void i3200_get_drbs(void __iomem *window,
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
{
	int i;

	for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
		drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
		drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;

		edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
	}
}

static bool i3200_is_stacked(struct pci_dev *pdev,
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
{
	u16 tom;

	pci_read_config_word(pdev, I3200_TOM, &tom);
	tom &= I3200_TOM_MASK;

	return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
}

static unsigned long drb_to_nr_pages(
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
	int channel, int rank)
{
	int n;

	n = drbs[channel][rank];
	if (rank > 0)
		n -= drbs[channel][rank - 1];
	if (stacked && (channel == 1) &&
	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
		n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];

	n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
	return n;
}

static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc;
	int i, j;
	struct mem_ctl_info *mci = NULL;
	struct edac_mc_layer layers[2];
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
	bool stacked;
	void __iomem *window;
	struct i3200_priv *priv;

	edac_dbg(0, "MC:\n");

	window = i3200_map_mchbar(pdev);
	if (!window)
		return -ENODEV;

	i3200_get_drbs(window, drbs);
	nr_channels = how_many_channels(pdev);

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = I3200_DIMMS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = nr_channels;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
			    sizeof(struct i3200_priv));
	if (!mci)
		return -ENOMEM;

	edac_dbg(3, "MC: init mci\n");

	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR2;

	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I3200_REVISION;
	mci->ctl_name = i3200_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i3200_check;
	mci->ctl_page_to_phys = NULL;
	priv = mci->pvt_info;
	priv->window = window;

	stacked = i3200_is_stacked(pdev, drbs);

	/*
	 * The dram rank boundary (DRB) reg values are boundary addresses
	 * for each DRAM rank with a granularity of 64MB.  DRB regs are
	 * cumulative; the last one will contain the total memory
	 * contained in all ranks.
	 */
	for (i = 0; i < mci->nr_csrows; i++) {
		unsigned long nr_pages;
		struct csrow_info *csrow = mci->csrows[i];

		nr_pages = drb_to_nr_pages(drbs, stacked,
			i / I3200_RANKS_PER_CHANNEL,
			i % I3200_RANKS_PER_CHANNEL);

		if (nr_pages == 0)
			continue;

		for (j = 0; j < nr_channels; j++) {
			struct dimm_info *dimm = csrow->channels[j]->dimm;

			dimm->nr_pages = nr_pages;
			dimm->grain = nr_pages << PAGE_SHIFT;
			dimm->mtype = MEM_DDR2;
			dimm->dtype = DEV_UNKNOWN;
			dimm->edac_mode = EDAC_UNKNOWN;
		}
	}

	i3200_clear_error_info(mci);

	rc = -ENODEV;
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* get this far and it's successful */
	edac_dbg(3, "MC: success\n");
	return 0;

fail:
	iounmap(window);
	if (mci)
		edac_mc_free(mci);

	return rc;
}

static int i3200_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "MC:\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i3200_probe1(pdev, ent->driver_data);
	if (!mci_pdev)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i3200_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct i3200_priv *priv;

	edac_dbg(0, "\n");

	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

	priv = mci->pvt_info;
	iounmap(priv->window);

	edac_mc_free(mci);
}

static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
	{
		PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
		I3200},
	{
		0,
	}            /* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);

static struct pci_driver i3200_driver = {
	.name = EDAC_MOD_STR,
	.probe = i3200_init_one,
	.remove = i3200_remove_one,
	.id_table = i3200_pci_tbl,
};

static int __init i3200_init(void)
{
	int pci_rc;

	edac_dbg(3, "MC:\n");

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();

	pci_rc = pci_register_driver(&i3200_driver);
	if (pci_rc < 0)
		goto fail0;

	if (!mci_pdev) {
		i3200_registered = 0;
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				PCI_DEVICE_ID_INTEL_3200_HB, NULL);
		if (!mci_pdev) {
			edac_dbg(0, "i3200 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
		if (pci_rc < 0) {
			edac_dbg(0, "i3200 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i3200_driver);

fail0:
	if (mci_pdev)
		pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i3200_exit(void)
{
	edac_dbg(3, "MC:\n");

	pci_unregister_driver(&i3200_driver);
	if (!i3200_registered) {
		i3200_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}

module_init(i3200_init);
module_exit(i3200_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Akamai Technologies, Inc.");
MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
dd8ef1db JU	1	/*
	2	* Intel 3200/3210 Memory Controller kernel module
	3	* Copyright (C) 2008-2009 Akamai Technologies, Inc.
	4	* Portions by Hitoshi Mitake <h.mitake@gmail.com>.
	5	*
	6	* This file may be distributed under the terms of the
	7	* GNU General Public License.
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/init.h>
	12	#include <linux/pci.h>
	13	#include <linux/pci_ids.h>
dd8ef1db JU	14	#include <linux/edac.h>
	15	#include <linux/io.h>
	16	#include "edac_core.h"
	17
797a796a HM	18	#include <asm-generic/io-64-nonatomic-lo-hi.h>
797a796a HM	19
dd8ef1db JU	20	#define I3200_REVISION "1.1"
	21
	22	#define EDAC_MOD_STR "i3200_edac"
	23
	24	#define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0
	25
95b93287	26	#define I3200_DIMMS 4
dd8ef1db JU	27	#define I3200_RANKS 8
	28	#define I3200_RANKS_PER_CHANNEL 4
	29	#define I3200_CHANNELS 2
	30
	31	/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
	32
	33	#define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
	34	#define I3200_MCHBAR_HIGH 0x4c
	35	#define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
	36	#define I3200_MMR_WINDOW_SIZE 16384
	37
	38	#define I3200_TOM 0xa0 /* Top of Memory (16b)
	39	*
	40	* 15:10 reserved
	41	* 9:0 total populated physical memory
	42	*/
	43	#define I3200_TOM_MASK 0x3ff /* bits 9:0 */
	44	#define I3200_TOM_SHIFT 26 /* 64MiB grain */
	45
	46	#define I3200_ERRSTS 0xc8 /* Error Status Register (16b)
	47	*
	48	* 15 reserved
	49	* 14 Isochronous TBWRR Run Behind FIFO Full
	50	* (ITCV)
	51	* 13 Isochronous TBWRR Run Behind FIFO Put
	52	* (ITSTV)
	53	* 12 reserved
	54	* 11 MCH Thermal Sensor Event
	55	* for SMI/SCI/SERR (GTSE)
	56	* 10 reserved
	57	* 9 LOCK to non-DRAM Memory Flag (LCKF)
	58	* 8 reserved
	59	* 7 DRAM Throttle Flag (DTF)
	60	* 6:2 reserved
	61	* 1 Multi-bit DRAM ECC Error Flag (DMERR)
	62	* 0 Single-bit DRAM ECC Error Flag (DSERR)
	63	*/
	64	#define I3200_ERRSTS_UE 0x0002
	65	#define I3200_ERRSTS_CE 0x0001
	66	#define I3200_ERRSTS_BITS (I3200_ERRSTS_UE \| I3200_ERRSTS_CE)
	67
	68
	69	/* Intel MMIO register space - device 0 function 0 - MMR space */
	70
	71	#define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
	72	*
	73	* 15:10 reserved
	74	* 9:0 Channel 0 DRAM Rank Boundary Address
	75	*/
	76	#define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
	77	#define I3200_DRB_MASK 0x3ff /* bits 9:0 */
	78	#define I3200_DRB_SHIFT 26 /* 64MiB grain */
	79
	80	#define I3200_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
	81	*
	82	* 63:48 Error Column Address (ERRCOL)
	83	* 47:32 Error Row Address (ERRROW)
	84	* 31:29 Error Bank Address (ERRBANK)
	85	* 28:27 Error Rank Address (ERRRANK)
	86	* 26:24 reserved
	87	* 23:16 Error Syndrome (ERRSYND)
	88	* 15: 2 reserved
	89	* 1 Multiple Bit Error Status (MERRSTS)
	90	* 0 Correctable Error Status (CERRSTS)
91	*/
92	#define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */
93	#define I3200_ECCERRLOG_CE 0x1
94	#define I3200_ECCERRLOG_UE 0x2
95	#define I3200_ECCERRLOG_RANK_BITS 0x18000000
96	#define I3200_ECCERRLOG_RANK_SHIFT 27
97	#define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000
98	#define I3200_ECCERRLOG_SYNDROME_SHIFT 16
99	#define I3200_CAPID0 0xe0 /* P.95 of spec for details */
100
101	struct i3200_priv {
102	void __iomem *window;
103	};
104
105	static int nr_channels;
106
107	static int how_many_channels(struct pci_dev *pdev)
108	{
5f466cb0 MCC	109	int n_channels;
5f466cb0 MCC	110
dd8ef1db JU	111	unsigned char capid0_8b; /* 8th byte of CAPID0 */
	112
	113	pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
5f466cb0	114
dd8ef1db	115	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
956b9ba1	116	edac_dbg(0, "In single channel mode\n");
5f466cb0	117	n_channels = 1;
dd8ef1db	118	} else {
956b9ba1	119	edac_dbg(0, "In dual channel mode\n");
5f466cb0	120	n_channels = 2;
dd8ef1db	121	}
5f466cb0 MCC	122
	123	if (capid0_8b & 0x10) /* check if both channels are filled */
	124	edac_dbg(0, "2 DIMMS per channel disabled\n");
	125	else
	126	edac_dbg(0, "2 DIMMS per channel enabled\n");
	127
	128	return n_channels;
dd8ef1db JU	129	}
	130
	131	static unsigned long eccerrlog_syndrome(u64 log)
	132	{
	133	return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
	134	I3200_ECCERRLOG_SYNDROME_SHIFT;
	135	}
	136
	137	static int eccerrlog_row(int channel, u64 log)
	138	{
	139	u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
	140	I3200_ECCERRLOG_RANK_SHIFT);
	141	return rank \| (channel * I3200_RANKS_PER_CHANNEL);
	142	}
	143
	144	enum i3200_chips {
	145	I3200 = 0,
	146	};
	147
	148	struct i3200_dev_info {
	149	const char *ctl_name;
	150	};
	151
	152	struct i3200_error_info {
	153	u16 errsts;
	154	u16 errsts2;
	155	u64 eccerrlog[I3200_CHANNELS];
	156	};
	157
	158	static const struct i3200_dev_info i3200_devs[] = {
	159	[I3200] = {
	160	.ctl_name = "i3200"
	161	},
	162	};
	163
	164	static struct pci_dev *mci_pdev;
	165	static int i3200_registered = 1;
	166
	167
	168	static void i3200_clear_error_info(struct mem_ctl_info *mci)
	169	{
	170	struct pci_dev *pdev;
	171
fd687502	172	pdev = to_pci_dev(mci->pdev);
dd8ef1db JU	173
	174	/*
	175	* Clear any error bits.
	176	* (Yes, we really clear bits by writing 1 to them.)
	177	*/
	178	pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
	179	I3200_ERRSTS_BITS);
	180	}
	181
	182	static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
	183	struct i3200_error_info *info)
	184	{
	185	struct pci_dev *pdev;
	186	struct i3200_priv *priv = mci->pvt_info;
	187	void __iomem *window = priv->window;
	188
fd687502	189	pdev = to_pci_dev(mci->pdev);
dd8ef1db JU	190
	191	/*
	192	* This is a mess because there is no atomic way to read all the
	193	* registers at once and the registers can transition from CE being
	194	* overwritten by UE.
	195	*/
	196	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
	197	if (!(info->errsts & I3200_ERRSTS_BITS))
	198	return;
	199
	200	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
	201	if (nr_channels == 2)
	202	info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
	203
	204	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
	205
	206	/*
	207	* If the error is the same for both reads then the first set
	208	* of reads is valid. If there is a change then there is a CE
	209	* with no info and the second set of reads is valid and
	210	* should be UE info.
	211	*/
	212	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
	213	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
	214	if (nr_channels == 2)
	215	info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
	216	}
	217
	218	i3200_clear_error_info(mci);
	219	}
	220
	221	static void i3200_process_error_info(struct mem_ctl_info *mci,
	222	struct i3200_error_info *info)
	223	{
	224	int channel;
	225	u64 log;
	226
	227	if (!(info->errsts & I3200_ERRSTS_BITS))
	228	return;
	229
	230	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
9eb07a7f	231	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
03f7eae8	232	-1, -1, -1, "UE overwrote CE", "");
dd8ef1db JU	233	info->errsts = info->errsts2;
	234	}
	235
	236	for (channel = 0; channel < nr_channels; channel++) {
	237	log = info->eccerrlog[channel];
	238	if (log & I3200_ECCERRLOG_UE) {
9eb07a7f	239	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
95b93287 MCC	240	0, 0, 0,
	241	eccerrlog_row(channel, log),
	242	-1, -1,
03f7eae8	243	"i3000 UE", "");
dd8ef1db	244	} else if (log & I3200_ECCERRLOG_CE) {
9eb07a7f	245	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
95b93287 MCC	246	0, 0, eccerrlog_syndrome(log),
	247	eccerrlog_row(channel, log),
	248	-1, -1,
03f7eae8	249	"i3000 UE", "");
dd8ef1db JU	250	}
	251	}
	252	}
	253
	254	static void i3200_check(struct mem_ctl_info *mci)
	255	{
	256	struct i3200_error_info info;
	257
956b9ba1	258	edac_dbg(1, "MC%d\n", mci->mc_idx);
dd8ef1db JU	259	i3200_get_and_clear_error_info(mci, &info);
	260	i3200_process_error_info(mci, &info);
	261	}
	262
	263
	264	void __iomem i3200_map_mchbar(struct pci_dev pdev)
	265	{
	266	union {
	267	u64 mchbar;
	268	struct {
	269	u32 mchbar_low;
	270	u32 mchbar_high;
	271	};
	272	} u;
	273	void __iomem *window;
	274
	275	pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
	276	pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
	277	u.mchbar &= I3200_MCHBAR_MASK;
	278
	279	if (u.mchbar != (resource_size_t)u.mchbar) {
	280	printk(KERN_ERR
	281	"i3200: mmio space beyond accessible range (0x%llx)\n",
	282	(unsigned long long)u.mchbar);
	283	return NULL;
	284	}
	285
	286	window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
	287	if (!window)
	288	printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
	289	(unsigned long long)u.mchbar);
	290
	291	return window;
	292	}
	293
	294
	295	static void i3200_get_drbs(void __iomem *window,
	296	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
	297	{
	298	int i;
	299
	300	for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
	301	drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
	302	drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
5f466cb0 MCC	303
5f466cb0 MCC	304	edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
dd8ef1db JU	305	}
	306	}
	307
	308	static bool i3200_is_stacked(struct pci_dev *pdev,
	309	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
	310	{
	311	u16 tom;
	312
	313	pci_read_config_word(pdev, I3200_TOM, &tom);
	314	tom &= I3200_TOM_MASK;
	315
	316	return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
	317	}
	318
	319	static unsigned long drb_to_nr_pages(
	320	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
	321	int channel, int rank)
	322	{
	323	int n;
	324
	325	n = drbs[channel][rank];
	326	if (rank > 0)
	327	n -= drbs[channel][rank - 1];
	328	if (stacked && (channel == 1) &&
	329	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
	330	n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
	331
	332	n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
	333	return n;
	334	}
	335
	336	static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
	337	{
	338	int rc;
084a4fcc	339	int i, j;
dd8ef1db	340	struct mem_ctl_info *mci = NULL;
95b93287	341	struct edac_mc_layer layers[2];
dd8ef1db JU	342	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
	343	bool stacked;
	344	void __iomem *window;
	345	struct i3200_priv *priv;
	346
956b9ba1	347	edac_dbg(0, "MC:\n");
dd8ef1db JU	348
	349	window = i3200_map_mchbar(pdev);
	350	if (!window)
	351	return -ENODEV;
	352
	353	i3200_get_drbs(window, drbs);
	354	nr_channels = how_many_channels(pdev);
	355
95b93287 MCC	356	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	357	layers[0].size = I3200_DIMMS;
	358	layers[0].is_virt_csrow = true;
	359	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	360	layers[1].size = nr_channels;
	361	layers[1].is_virt_csrow = false;
ca0907b9	362	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
95b93287	363	sizeof(struct i3200_priv));
dd8ef1db JU	364	if (!mci)
	365	return -ENOMEM;
	366
956b9ba1	367	edac_dbg(3, "MC: init mci\n");
dd8ef1db	368
fd687502	369	mci->pdev = &pdev->dev;
dd8ef1db JU	370	mci->mtype_cap = MEM_FLAG_DDR2;
	371
	372	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	373	mci->edac_cap = EDAC_FLAG_SECDED;
	374
	375	mci->mod_name = EDAC_MOD_STR;
	376	mci->mod_ver = I3200_REVISION;
	377	mci->ctl_name = i3200_devs[dev_idx].ctl_name;
	378	mci->dev_name = pci_name(pdev);
	379	mci->edac_check = i3200_check;
	380	mci->ctl_page_to_phys = NULL;
	381	priv = mci->pvt_info;
	382	priv->window = window;
	383
	384	stacked = i3200_is_stacked(pdev, drbs);
	385
	386	/*
	387	* The dram rank boundary (DRB) reg values are boundary addresses
	388	* for each DRAM rank with a granularity of 64MB. DRB regs are
	389	* cumulative; the last one will contain the total memory
	390	* contained in all ranks.
	391	*/
dd8ef1db JU	392	for (i = 0; i < mci->nr_csrows; i++) {
dd8ef1db JU	393	unsigned long nr_pages;
de3910eb	394	struct csrow_info *csrow = mci->csrows[i];
dd8ef1db JU	395
	396	nr_pages = drb_to_nr_pages(drbs, stacked,
	397	i / I3200_RANKS_PER_CHANNEL,
	398	i % I3200_RANKS_PER_CHANNEL);
	399
084a4fcc	400	if (nr_pages == 0)
dd8ef1db	401	continue;
dd8ef1db	402
084a4fcc	403	for (j = 0; j < nr_channels; j++) {
de3910eb	404	struct dimm_info *dimm = csrow->channels[j]->dimm;
084a4fcc	405
582a8996	406	dimm->nr_pages = nr_pages;
084a4fcc MCC	407	dimm->grain = nr_pages << PAGE_SHIFT;
	408	dimm->mtype = MEM_DDR2;
	409	dimm->dtype = DEV_UNKNOWN;
	410	dimm->edac_mode = EDAC_UNKNOWN;
	411	}
dd8ef1db JU	412	}
	413
	414	i3200_clear_error_info(mci);
	415
	416	rc = -ENODEV;
	417	if (edac_mc_add_mc(mci)) {
956b9ba1	418	edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
dd8ef1db JU	419	goto fail;
	420	}
	421
	422	/* get this far and it's successful */
956b9ba1	423	edac_dbg(3, "MC: success\n");
dd8ef1db JU	424	return 0;
	425
	426	fail:
	427	iounmap(window);
	428	if (mci)
	429	edac_mc_free(mci);
	430
	431	return rc;
	432	}
	433
9b3c6e85	434	static int i3200_init_one(struct pci_dev pdev, const struct pci_device_id ent)
dd8ef1db JU	435	{
	436	int rc;
	437
956b9ba1	438	edac_dbg(0, "MC:\n");
dd8ef1db JU	439
	440	if (pci_enable_device(pdev) < 0)
	441	return -EIO;
	442
	443	rc = i3200_probe1(pdev, ent->driver_data);
	444	if (!mci_pdev)
	445	mci_pdev = pci_dev_get(pdev);
	446
	447	return rc;
	448	}
	449
9b3c6e85	450	static void i3200_remove_one(struct pci_dev *pdev)
dd8ef1db JU	451	{
	452	struct mem_ctl_info *mci;
	453	struct i3200_priv *priv;
	454
956b9ba1	455	edac_dbg(0, "\n");
dd8ef1db JU	456
	457	mci = edac_mc_del_mc(&pdev->dev);
	458	if (!mci)
	459	return;
	460
	461	priv = mci->pvt_info;
	462	iounmap(priv->window);
	463
	464	edac_mc_free(mci);
	465	}
	466
36c46f31	467	static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
dd8ef1db JU	468	{
	469	PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	470	I3200},
	471	{
	472	0,
	473	} /* 0 terminated list. */
	474	};
	475
	476	MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
	477
	478	static struct pci_driver i3200_driver = {
	479	.name = EDAC_MOD_STR,
	480	.probe = i3200_init_one,
9b3c6e85	481	.remove = i3200_remove_one,
dd8ef1db JU	482	.id_table = i3200_pci_tbl,
	483	};
	484
	485	static int __init i3200_init(void)
	486	{
	487	int pci_rc;
	488
956b9ba1	489	edac_dbg(3, "MC:\n");
dd8ef1db JU	490
	491	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	492	opstate_init();
	493
	494	pci_rc = pci_register_driver(&i3200_driver);
	495	if (pci_rc < 0)
	496	goto fail0;
	497
	498	if (!mci_pdev) {
	499	i3200_registered = 0;
	500	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
	501	PCI_DEVICE_ID_INTEL_3200_HB, NULL);
	502	if (!mci_pdev) {
956b9ba1	503	edac_dbg(0, "i3200 pci_get_device fail\n");
dd8ef1db JU	504	pci_rc = -ENODEV;
	505	goto fail1;
	506	}
	507
	508	pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
	509	if (pci_rc < 0) {
956b9ba1	510	edac_dbg(0, "i3200 init fail\n");
dd8ef1db JU	511	pci_rc = -ENODEV;
	512	goto fail1;
	513	}
	514	}
	515
	516	return 0;
	517
	518	fail1:
	519	pci_unregister_driver(&i3200_driver);
	520
	521	fail0:
	522	if (mci_pdev)
	523	pci_dev_put(mci_pdev);
	524
	525	return pci_rc;
	526	}
	527
	528	static void __exit i3200_exit(void)
	529	{
956b9ba1	530	edac_dbg(3, "MC:\n");
dd8ef1db JU	531
	532	pci_unregister_driver(&i3200_driver);
	533	if (!i3200_registered) {
	534	i3200_remove_one(mci_pdev);
	535	pci_dev_put(mci_pdev);
	536	}
	537	}
	538
	539	module_init(i3200_init);
	540	module_exit(i3200_exit);
	541
	542	MODULE_LICENSE("GPL");
	543	MODULE_AUTHOR("Akamai Technologies, Inc.");
	544	MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
	545
	546	module_param(edac_op_state, int, 0444);
	547	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");