[linux-2.6-block.git] / drivers / edac / i3000_edac.c

/*
 * Intel 3000/3010 Memory Controller kernel module
 * Copyright (C) 2007 Akamai Technologies, Inc.
 * Shamelessly copied from:
 * 	Intel D82875P Memory Controller kernel module
 * 	(C) 2003 Linux Networx (http://lnxi.com)
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define EDAC_MOD_STR		"i3000_edac"

#define I3000_RANKS		8
#define I3000_RANKS_PER_CHANNEL	4
#define I3000_CHANNELS		2

/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */

#define I3000_MCHBAR		0x44	/* MCH Memory Mapped Register BAR */
#define I3000_MCHBAR_MASK	0xffffc000
#define I3000_MMR_WINDOW_SIZE	16384

#define I3000_EDEAP	0x70	/* Extended DRAM Error Address Pointer (8b)
				 *
				 * 7:1   reserved
				 * 0     bit 32 of address
				 */
#define I3000_DEAP	0x58	/* DRAM Error Address Pointer (32b)
				 *
				 * 31:7  address
				 * 6:1   reserved
				 * 0     Error channel 0/1
				 */
#define I3000_DEAP_GRAIN 		(1 << 7)

/*
 * Helper functions to decode the DEAP/EDEAP hardware registers.
 *
 * The type promotion here is deliberate; we're deriving an
 * unsigned long pfn and offset from hardware regs which are u8/u32.
 */

static inline unsigned long deap_pfn(u8 edeap, u32 deap)
{
	deap >>= PAGE_SHIFT;
	deap |= (edeap & 1) << (32 - PAGE_SHIFT);
	return deap;
}

static inline unsigned long deap_offset(u32 deap)
{
	return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
}

static inline int deap_channel(u32 deap)
{
	return deap & 1;
}

#define I3000_DERRSYN	0x5c	/* DRAM Error Syndrome (8b)
				 *
				 *  7:0  DRAM ECC Syndrome
				 */

#define I3000_ERRSTS	0xc8	/* Error Status Register (16b)
				 *
				 * 15:12 reserved
				 * 11    MCH Thermal Sensor Event
				 *         for SMI/SCI/SERR
				 * 10    reserved
				 *  9    LOCK to non-DRAM Memory Flag (LCKF)
				 *  8    Received Refresh Timeout Flag (RRTOF)
				 *  7:2  reserved
				 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
				 *  0    Single-bit DRAM ECC Error Flag (DSERR)
				 */
#define I3000_ERRSTS_BITS	0x0b03	/* bits which indicate errors */
#define I3000_ERRSTS_UE		0x0002
#define I3000_ERRSTS_CE		0x0001

#define I3000_ERRCMD	0xca	/* Error Command (16b)
				 *
				 * 15:12 reserved
				 * 11    SERR on MCH Thermal Sensor Event
				 *         (TSESERR)
				 * 10    reserved
				 *  9    SERR on LOCK to non-DRAM Memory
				 *         (LCKERR)
				 *  8    SERR on DRAM Refresh Timeout
				 *         (DRTOERR)
				 *  7:2  reserved
				 *  1    SERR Multi-Bit DRAM ECC Error
				 *         (DMERR)
				 *  0    SERR on Single-Bit ECC Error
				 *         (DSERR)
				 */

/* Intel  MMIO register space - device 0 function 0 - MMR space */

#define I3000_DRB_SHIFT 25	/* 32MiB grain */

#define I3000_C0DRB	0x100	/* Channel 0 DRAM Rank Boundary (8b x 4)
				 *
				 * 7:0   Channel 0 DRAM Rank Boundary Address
				 */
#define I3000_C1DRB	0x180	/* Channel 1 DRAM Rank Boundary (8b x 4)
				 *
				 * 7:0   Channel 1 DRAM Rank Boundary Address
				 */

#define I3000_C0DRA	0x108	/* Channel 0 DRAM Rank Attribute (8b x 2)
				 *
				 * 7     reserved
				 * 6:4   DRAM odd Rank Attribute
				 * 3     reserved
				 * 2:0   DRAM even Rank Attribute
				 *
				 * Each attribute defines the page
				 * size of the corresponding rank:
				 *     000: unpopulated
				 *     001: reserved
				 *     010: 4 KB
				 *     011: 8 KB
				 *     100: 16 KB
				 *     Others: reserved
				 */
#define I3000_C1DRA	0x188	/* Channel 1 DRAM Rank Attribute (8b x 2) */

static inline unsigned char odd_rank_attrib(unsigned char dra)
{
	return (dra & 0x70) >> 4;
}

static inline unsigned char even_rank_attrib(unsigned char dra)
{
	return dra & 0x07;
}

#define I3000_C0DRC0	0x120	/* DRAM Controller Mode 0 (32b)
				 *
				 * 31:30 reserved
				 * 29    Initialization Complete (IC)
				 * 28:11 reserved
				 * 10:8  Refresh Mode Select (RMS)
				 * 7     reserved
				 * 6:4   Mode Select (SMS)
				 * 3:2   reserved
				 * 1:0   DRAM Type (DT)
				 */

#define I3000_C0DRC1	0x124	/* DRAM Controller Mode 1 (32b)
				 *
				 * 31    Enhanced Addressing Enable (ENHADE)
				 * 30:0  reserved
				 */

enum i3000p_chips {
	I3000 = 0,
};

struct i3000_dev_info {
	const char *ctl_name;
};

struct i3000_error_info {
	u16 errsts;
	u8 derrsyn;
	u8 edeap;
	u32 deap;
	u16 errsts2;
};

static const struct i3000_dev_info i3000_devs[] = {
	[I3000] = {
		.ctl_name = "i3000"},
};

static struct pci_dev *mci_pdev;
static int i3000_registered = 1;
static struct edac_pci_ctl_info *i3000_pci;

static void i3000_get_error_info(struct mem_ctl_info *mci,
				 struct i3000_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
	if (!(info->errsts & I3000_ERRSTS_BITS))
		return;
	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same for both reads then the first set
	 * of reads is valid.  If there is a change then there is a CE
	 * with no info and the second set of reads is valid and
	 * should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
		pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
		pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
		pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
	}

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
			 I3000_ERRSTS_BITS);
}

static int i3000_process_error_info(struct mem_ctl_info *mci,
				struct i3000_error_info *info,
				int handle_errors)
{
	int row, multi_chan, channel;
	unsigned long pfn, offset;

	multi_chan = mci->csrows[0]->nr_channels - 1;

	if (!(info->errsts & I3000_ERRSTS_BITS))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
				     -1, -1, -1,
				     "UE overwrote CE", "");
		info->errsts = info->errsts2;
	}

	pfn = deap_pfn(info->edeap, info->deap);
	offset = deap_offset(info->deap);
	channel = deap_channel(info->deap);

	row = edac_mc_find_csrow_by_page(mci, pfn);

	if (info->errsts & I3000_ERRSTS_UE)
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     pfn, offset, 0,
				     row, -1, -1,
				     "i3000 UE", "");
	else
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     pfn, offset, info->derrsyn,
				     row, multi_chan ? channel : 0, -1,
				     "i3000 CE", "");

	return 1;
}

static void i3000_check(struct mem_ctl_info *mci)
{
	struct i3000_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i3000_get_error_info(mci, &info);
	i3000_process_error_info(mci, &info, 1);
}

static int i3000_is_interleaved(const unsigned char *c0dra,
				const unsigned char *c1dra,
				const unsigned char *c0drb,
				const unsigned char *c1drb)
{
	int i;

	/*
	 * If the channels aren't populated identically then
	 * we're not interleaved.
	 */
	for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
		if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
			even_rank_attrib(c0dra[i]) !=
						even_rank_attrib(c1dra[i]))
			return 0;

	/*
	 * If the rank boundaries for the two channels are different
	 * then we're not interleaved.
	 */
	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
		if (c0drb[i] != c1drb[i])
			return 0;

	return 1;
}

static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc;
	int i, j;
	struct mem_ctl_info *mci = NULL;
	struct edac_mc_layer layers[2];
	unsigned long last_cumul_size, nr_pages;
	int interleaved, nr_channels;
	unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
	unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
	unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
	unsigned long mchbar;
	void __iomem *window;

	edac_dbg(0, "MC:\n");

	pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
	mchbar &= I3000_MCHBAR_MASK;
	window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
	if (!window) {
		printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
			mchbar);
		return -ENODEV;
	}

	c0dra[0] = readb(window + I3000_C0DRA + 0);	/* ranks 0,1 */
	c0dra[1] = readb(window + I3000_C0DRA + 1);	/* ranks 2,3 */
	c1dra[0] = readb(window + I3000_C1DRA + 0);	/* ranks 0,1 */
	c1dra[1] = readb(window + I3000_C1DRA + 1);	/* ranks 2,3 */

	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
		c0drb[i] = readb(window + I3000_C0DRB + i);
		c1drb[i] = readb(window + I3000_C1DRB + i);
	}

	iounmap(window);

	/*
	 * Figure out how many channels we have.
	 *
	 * If we have what the datasheet calls "asymmetric channels"
	 * (essentially the same as what was called "virtual single
	 * channel mode" in the i82875) then it's a single channel as
	 * far as EDAC is concerned.
	 */
	interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
	nr_channels = interleaved ? 2 : 1;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = I3000_RANKS / nr_channels;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = nr_channels;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (!mci)
		return -ENOMEM;

	edac_dbg(3, "MC: init mci\n");

	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR2;

	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;

	mci->mod_name = EDAC_MOD_STR;
	mci->ctl_name = i3000_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i3000_check;
	mci->ctl_page_to_phys = NULL;

	/*
	 * The dram rank boundary (DRB) reg values are boundary addresses
	 * for each DRAM rank with a granularity of 32MB.  DRB regs are
	 * cumulative; the last one will contain the total memory
	 * contained in all ranks.
	 *
	 * If we're in interleaved mode then we're only walking through
	 * the ranks of controller 0, so we double all the values we see.
	 */
	for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
		u8 value;
		u32 cumul_size;
		struct csrow_info *csrow = mci->csrows[i];

		value = drb[i];
		cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
		if (interleaved)
			cumul_size <<= 1;
		edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
		if (cumul_size == last_cumul_size)
			continue;

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;

		for (j = 0; j < nr_channels; j++) {
			struct dimm_info *dimm = csrow->channels[j]->dimm;

			dimm->nr_pages = nr_pages / nr_channels;
			dimm->grain = I3000_DEAP_GRAIN;
			dimm->mtype = MEM_DDR2;
			dimm->dtype = DEV_UNKNOWN;
			dimm->edac_mode = EDAC_UNKNOWN;
		}
	}

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
			 I3000_ERRSTS_BITS);

	rc = -ENODEV;
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i3000_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "MC: success\n");
	return 0;

fail:
	if (mci)
		edac_mc_free(mci);

	return rc;
}

/* returns count (>= 0), or negative on error */
static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "MC:\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i3000_probe1(pdev, ent->driver_data);
	if (!mci_pdev)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i3000_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (i3000_pci)
		edac_pci_release_generic_ctl(i3000_pci);

	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i3000_pci_tbl[] = {
	{
	 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I3000},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);

static struct pci_driver i3000_driver = {
	.name = EDAC_MOD_STR,
	.probe = i3000_init_one,
	.remove = i3000_remove_one,
	.id_table = i3000_pci_tbl,
};

static int __init i3000_init(void)
{
	int pci_rc;

	edac_dbg(3, "MC:\n");

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();

	pci_rc = pci_register_driver(&i3000_driver);
	if (pci_rc < 0)
		goto fail0;

	if (!mci_pdev) {
		i3000_registered = 0;
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_3000_HB, NULL);
		if (!mci_pdev) {
			edac_dbg(0, "i3000 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
		if (pci_rc < 0) {
			edac_dbg(0, "i3000 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i3000_driver);

fail0:
	pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i3000_exit(void)
{
	edac_dbg(3, "MC:\n");

	pci_unregister_driver(&i3000_driver);
	if (!i3000_registered) {
		i3000_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}

module_init(i3000_init);
module_exit(i3000_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
535c6a53 JU	1	/*
	2	* Intel 3000/3010 Memory Controller kernel module
	3	* Copyright (C) 2007 Akamai Technologies, Inc.
	4	* Shamelessly copied from:
	5	* Intel D82875P Memory Controller kernel module
	6	* (C) 2003 Linux Networx (http://lnxi.com)
	7	*
	8	* This file may be distributed under the terms of the
	9	* GNU General Public License.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
7ed31e0f	16	#include <linux/edac.h>
78d88e8a	17	#include "edac_module.h"
535c6a53	18
535c6a53 JU	19	#define EDAC_MOD_STR "i3000_edac"
	20
	21	#define I3000_RANKS 8
	22	#define I3000_RANKS_PER_CHANNEL 4
	23	#define I3000_CHANNELS 2
	24
	25	/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
	26
	27	#define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
	28	#define I3000_MCHBAR_MASK 0xffffc000
	29	#define I3000_MMR_WINDOW_SIZE 16384
	30
ce783d70 JU	31	#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
	32	*
	33	* 7:1 reserved
	34	* 0 bit 32 of address
	35	*/
	36	#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
	37	*
	38	* 31:7 address
	39	* 6:1 reserved
	40	* 0 Error channel 0/1
	41	*/
	42	#define I3000_DEAP_GRAIN (1 << 7)
4d2b165e	43
870897a5 JU	44	/*
	45	* Helper functions to decode the DEAP/EDEAP hardware registers.
	46	*
	47	* The type promotion here is deliberate; we're deriving an
	48	* unsigned long pfn and offset from hardware regs which are u8/u32.
	49	*/
	50
4d2b165e JU	51	static inline unsigned long deap_pfn(u8 edeap, u32 deap)
	52	{
	53	deap >>= PAGE_SHIFT;
	54	deap \|= (edeap & 1) << (32 - PAGE_SHIFT);
	55	return deap;
	56	}
	57
	58	static inline unsigned long deap_offset(u32 deap)
	59	{
	60	return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
	61	}
	62
	63	static inline int deap_channel(u32 deap)
	64	{
	65	return deap & 1;
	66	}
535c6a53	67
ce783d70 JU	68	#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
	69	*
	70	* 7:0 DRAM ECC Syndrome
	71	*/
	72
	73	#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
	74	*
	75	* 15:12 reserved
	76	* 11 MCH Thermal Sensor Event
	77	* for SMI/SCI/SERR
	78	* 10 reserved
	79	* 9 LOCK to non-DRAM Memory Flag (LCKF)
	80	* 8 Received Refresh Timeout Flag (RRTOF)
	81	* 7:2 reserved
	82	* 1 Multi-bit DRAM ECC Error Flag (DMERR)
	83	* 0 Single-bit DRAM ECC Error Flag (DSERR)
	84	*/
535c6a53 JU	85	#define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
	86	#define I3000_ERRSTS_UE 0x0002
	87	#define I3000_ERRSTS_CE 0x0001
	88
ce783d70 JU	89	#define I3000_ERRCMD 0xca /* Error Command (16b)
	90	*
	91	* 15:12 reserved
	92	* 11 SERR on MCH Thermal Sensor Event
	93	* (TSESERR)
	94	* 10 reserved
	95	* 9 SERR on LOCK to non-DRAM Memory
	96	* (LCKERR)
	97	* 8 SERR on DRAM Refresh Timeout
	98	* (DRTOERR)
	99	* 7:2 reserved
	100	* 1 SERR Multi-Bit DRAM ECC Error
	101	* (DMERR)
	102	* 0 SERR on Single-Bit ECC Error
	103	* (DSERR)
	104	*/
535c6a53 JU	105
	106	/* Intel MMIO register space - device 0 function 0 - MMR space */
	107
	108	#define I3000_DRB_SHIFT 25 /* 32MiB grain */
	109
ce783d70 JU	110	#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
	111	*
	112	* 7:0 Channel 0 DRAM Rank Boundary Address
	113	*/
	114	#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
	115	*
	116	* 7:0 Channel 1 DRAM Rank Boundary Address
	117	*/
	118
	119	#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
	120	*
	121	* 7 reserved
	122	* 6:4 DRAM odd Rank Attribute
	123	* 3 reserved
	124	* 2:0 DRAM even Rank Attribute
	125	*
	126	* Each attribute defines the page
	127	* size of the corresponding rank:
	128	* 000: unpopulated
	129	* 001: reserved
	130	* 010: 4 KB
	131	* 011: 8 KB
	132	* 100: 16 KB
	133	* Others: reserved
	134	*/
	135	#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
4d2b165e JU	136
	137	static inline unsigned char odd_rank_attrib(unsigned char dra)
	138	{
	139	return (dra & 0x70) >> 4;
	140	}
	141
	142	static inline unsigned char even_rank_attrib(unsigned char dra)
	143	{
	144	return dra & 0x07;
	145	}
ce783d70 JU	146
	147	#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
	148	*
	149	* 31:30 reserved
	150	* 29 Initialization Complete (IC)
	151	* 28:11 reserved
	152	* 10:8 Refresh Mode Select (RMS)
	153	* 7 reserved
	154	* 6:4 Mode Select (SMS)
	155	* 3:2 reserved
	156	* 1:0 DRAM Type (DT)
	157	*/
	158
	159	#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
	160	*
	161	* 31 Enhanced Addressing Enable (ENHADE)
	162	* 30:0 reserved
	163	*/
535c6a53	164
535c6a53 JU	165	enum i3000p_chips {
	166	I3000 = 0,
	167	};
	168
	169	struct i3000_dev_info {
	170	const char *ctl_name;
	171	};
	172
	173	struct i3000_error_info {
	174	u16 errsts;
	175	u8 derrsyn;
	176	u8 edeap;
	177	u32 deap;
	178	u16 errsts2;
	179	};
	180
	181	static const struct i3000_dev_info i3000_devs[] = {
	182	[I3000] = {
052dfb45	183	.ctl_name = "i3000"},
535c6a53 JU	184	};
535c6a53 JU	185
f044091c	186	static struct pci_dev *mci_pdev;
535c6a53	187	static int i3000_registered = 1;
456a2f95	188	static struct edac_pci_ctl_info *i3000_pci;
535c6a53 JU	189
535c6a53 JU	190	static void i3000_get_error_info(struct mem_ctl_info *mci,
36b8289e	191	struct i3000_error_info *info)
535c6a53 JU	192	{
	193	struct pci_dev *pdev;
	194
fd687502	195	pdev = to_pci_dev(mci->pdev);
535c6a53 JU	196
	197	/*
	198	* This is a mess because there is no atomic way to read all the
	199	* registers at once and the registers can transition from CE being
	200	* overwritten by UE.
	201	*/
	202	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
	203	if (!(info->errsts & I3000_ERRSTS_BITS))
	204	return;
	205	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
	206	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
	207	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
	208	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
	209
	210	/*
	211	* If the error is the same for both reads then the first set
	212	* of reads is valid. If there is a change then there is a CE
	213	* with no info and the second set of reads is valid and
	214	* should be UE info.
	215	*/
	216	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
36b8289e DJ	217	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
	218	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
	219	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
535c6a53 JU	220	}
535c6a53 JU	221
ce783d70 JU	222	/*
ce783d70 JU	223	* Clear any error bits.
535c6a53 JU	224	* (Yes, we really clear bits by writing 1 to them.)
535c6a53 JU	225	*/
36b8289e DJ	226	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
36b8289e DJ	227	I3000_ERRSTS_BITS);
535c6a53 JU	228	}
	229
	230	static int i3000_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	231	struct i3000_error_info *info,
052dfb45 DT	232	int handle_errors)
535c6a53	233	{
4d2b165e JU	234	int row, multi_chan, channel;
4d2b165e JU	235	unsigned long pfn, offset;
535c6a53	236
de3910eb	237	multi_chan = mci->csrows[0]->nr_channels - 1;
535c6a53 JU	238
	239	if (!(info->errsts & I3000_ERRSTS_BITS))
	240	return 0;
	241
	242	if (!handle_errors)
	243	return 1;
	244
	245	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
9eb07a7f	246	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
884906f1	247	-1, -1, -1,
03f7eae8	248	"UE overwrote CE", "");
535c6a53 JU	249	info->errsts = info->errsts2;
	250	}
	251
4d2b165e JU	252	pfn = deap_pfn(info->edeap, info->deap);
	253	offset = deap_offset(info->deap);
	254	channel = deap_channel(info->deap);
535c6a53 JU	255
	256	row = edac_mc_find_csrow_by_page(mci, pfn);
	257
	258	if (info->errsts & I3000_ERRSTS_UE)
9eb07a7f	259	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
884906f1 MCC	260	pfn, offset, 0,
884906f1 MCC	261	row, -1, -1,
03f7eae8	262	"i3000 UE", "");
535c6a53	263	else
9eb07a7f	264	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
884906f1 MCC	265	pfn, offset, info->derrsyn,
884906f1 MCC	266	row, multi_chan ? channel : 0, -1,
03f7eae8	267	"i3000 CE", "");
535c6a53 JU	268
	269	return 1;
	270	}
	271
	272	static void i3000_check(struct mem_ctl_info *mci)
	273	{
	274	struct i3000_error_info info;
	275
956b9ba1	276	edac_dbg(1, "MC%d\n", mci->mc_idx);
535c6a53 JU	277	i3000_get_error_info(mci, &info);
	278	i3000_process_error_info(mci, &info, 1);
	279	}
	280
	281	static int i3000_is_interleaved(const unsigned char *c0dra,
	282	const unsigned char *c1dra,
	283	const unsigned char *c0drb,
	284	const unsigned char *c1drb)
	285	{
	286	int i;
	287
ce783d70 JU	288	/*
ce783d70 JU	289	* If the channels aren't populated identically then
535c6a53 JU	290	* we're not interleaved.
	291	*/
	292	for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
4d2b165e JU	293	if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) \|\|
	294	even_rank_attrib(c0dra[i]) !=
	295	even_rank_attrib(c1dra[i]))
535c6a53 JU	296	return 0;
535c6a53 JU	297
ce783d70 JU	298	/*
ce783d70 JU	299	* If the rank boundaries for the two channels are different
535c6a53 JU	300	* then we're not interleaved.
	301	*/
	302	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
	303	if (c0drb[i] != c1drb[i])
	304	return 0;
	305
	306	return 1;
	307	}
	308
	309	static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
	310	{
	311	int rc;
084a4fcc	312	int i, j;
535c6a53	313	struct mem_ctl_info *mci = NULL;
884906f1	314	struct edac_mc_layer layers[2];
a895bf8b	315	unsigned long last_cumul_size, nr_pages;
535c6a53 JU	316	int interleaved, nr_channels;
	317	unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
	318	unsigned char c0dra = dra, c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
	319	unsigned char c0drb = drb, c1drb = &drb[I3000_RANKS_PER_CHANNEL];
	320	unsigned long mchbar;
0bd8496b	321	void __iomem *window;
535c6a53	322
956b9ba1	323	edac_dbg(0, "MC:\n");
535c6a53	324
36b8289e	325	pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
535c6a53 JU	326	mchbar &= I3000_MCHBAR_MASK;
	327	window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
	328	if (!window) {
36b8289e	329	printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
052dfb45	330	mchbar);
535c6a53 JU	331	return -ENODEV;
	332	}
	333
36b8289e DJ	334	c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
	335	c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
	336	c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
	337	c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
535c6a53 JU	338
	339	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
	340	c0drb[i] = readb(window + I3000_C0DRB + i);
	341	c1drb[i] = readb(window + I3000_C1DRB + i);
	342	}
	343
	344	iounmap(window);
	345
ce783d70 JU	346	/*
ce783d70 JU	347	* Figure out how many channels we have.
535c6a53 JU	348	*
	349	* If we have what the datasheet calls "asymmetric channels"
	350	* (essentially the same as what was called "virtual single
	351	* channel mode" in the i82875) then it's a single channel as
	352	* far as EDAC is concerned.
	353	*/
	354	interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
	355	nr_channels = interleaved ? 2 : 1;
884906f1 MCC	356
	357	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	358	layers[0].size = I3000_RANKS / nr_channels;
	359	layers[0].is_virt_csrow = true;
	360	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	361	layers[1].size = nr_channels;
	362	layers[1].is_virt_csrow = false;
ca0907b9	363	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
535c6a53 JU	364	if (!mci)
	365	return -ENOMEM;
	366
956b9ba1	367	edac_dbg(3, "MC: init mci\n");
535c6a53	368
fd687502	369	mci->pdev = &pdev->dev;
535c6a53 JU	370	mci->mtype_cap = MEM_FLAG_DDR2;
	371
	372	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	373	mci->edac_cap = EDAC_FLAG_SECDED;
	374
	375	mci->mod_name = EDAC_MOD_STR;
535c6a53 JU	376	mci->ctl_name = i3000_devs[dev_idx].ctl_name;
	377	mci->dev_name = pci_name(pdev);
	378	mci->edac_check = i3000_check;
	379	mci->ctl_page_to_phys = NULL;
	380
	381	/*
	382	* The dram rank boundary (DRB) reg values are boundary addresses
	383	* for each DRAM rank with a granularity of 32MB. DRB regs are
	384	* cumulative; the last one will contain the total memory
	385	* contained in all ranks.
	386	*
	387	* If we're in interleaved mode then we're only walking through
	388	* the ranks of controller 0, so we double all the values we see.
	389	*/
	390	for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
	391	u8 value;
	392	u32 cumul_size;
de3910eb	393	struct csrow_info *csrow = mci->csrows[i];
535c6a53 JU	394
	395	value = drb[i];
	396	cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
	397	if (interleaved)
	398	cumul_size <<= 1;
956b9ba1	399	edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
084a4fcc	400	if (cumul_size == last_cumul_size)
535c6a53	401	continue;
535c6a53 JU	402
	403	csrow->first_page = last_cumul_size;
	404	csrow->last_page = cumul_size - 1;
a895bf8b	405	nr_pages = cumul_size - last_cumul_size;
535c6a53	406	last_cumul_size = cumul_size;
084a4fcc MCC	407
084a4fcc MCC	408	for (j = 0; j < nr_channels; j++) {
de3910eb	409	struct dimm_info *dimm = csrow->channels[j]->dimm;
a895bf8b MCC	410
a895bf8b MCC	411	dimm->nr_pages = nr_pages / nr_channels;
084a4fcc MCC	412	dimm->grain = I3000_DEAP_GRAIN;
	413	dimm->mtype = MEM_DDR2;
	414	dimm->dtype = DEV_UNKNOWN;
	415	dimm->edac_mode = EDAC_UNKNOWN;
	416	}
535c6a53 JU	417	}
535c6a53 JU	418
ce783d70 JU	419	/*
ce783d70 JU	420	* Clear any error bits.
535c6a53 JU	421	* (Yes, we really clear bits by writing 1 to them.)
535c6a53 JU	422	*/
36b8289e DJ	423	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
36b8289e DJ	424	I3000_ERRSTS_BITS);
535c6a53 JU	425
535c6a53 JU	426	rc = -ENODEV;
b8f6f975	427	if (edac_mc_add_mc(mci)) {
956b9ba1	428	edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
535c6a53 JU	429	goto fail;
	430	}
	431
456a2f95 DJ	432	/* allocating generic PCI control info */
	433	i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	434	if (!i3000_pci) {
	435	printk(KERN_WARNING
	436	"%s(): Unable to create PCI control\n",
	437	__func__);
	438	printk(KERN_WARNING
	439	"%s(): PCI error report via EDAC not setup\n",
	440	__func__);
	441	}
	442
535c6a53	443	/* get this far and it's successful */
956b9ba1	444	edac_dbg(3, "MC: success\n");
535c6a53 JU	445	return 0;
535c6a53 JU	446
ce783d70	447	fail:
535c6a53 JU	448	if (mci)
	449	edac_mc_free(mci);
	450
	451	return rc;
	452	}
	453
	454	/* returns count (>= 0), or negative on error */
9b3c6e85	455	static int i3000_init_one(struct pci_dev pdev, const struct pci_device_id ent)
535c6a53 JU	456	{
	457	int rc;
	458
956b9ba1	459	edac_dbg(0, "MC:\n");
535c6a53 JU	460
	461	if (pci_enable_device(pdev) < 0)
	462	return -EIO;
	463
	464	rc = i3000_probe1(pdev, ent->driver_data);
ce783d70	465	if (!mci_pdev)
535c6a53 JU	466	mci_pdev = pci_dev_get(pdev);
	467
	468	return rc;
	469	}
	470
9b3c6e85	471	static void i3000_remove_one(struct pci_dev *pdev)
535c6a53 JU	472	{
	473	struct mem_ctl_info *mci;
	474
956b9ba1	475	edac_dbg(0, "\n");
535c6a53	476
456a2f95 DJ	477	if (i3000_pci)
	478	edac_pci_release_generic_ctl(i3000_pci);
	479
ce783d70 JU	480	mci = edac_mc_del_mc(&pdev->dev);
ce783d70 JU	481	if (!mci)
535c6a53 JU	482	return;
	483
	484	edac_mc_free(mci);
	485	}
	486
ba935f40	487	static const struct pci_device_id i3000_pci_tbl[] = {
535c6a53	488	{
36b8289e DJ	489	PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
36b8289e DJ	490	I3000},
535c6a53	491	{
36b8289e DJ	492	0,
36b8289e DJ	493	} /* 0 terminated list. */
535c6a53 JU	494	};
	495
	496	MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
	497
	498	static struct pci_driver i3000_driver = {
	499	.name = EDAC_MOD_STR,
	500	.probe = i3000_init_one,
9b3c6e85	501	.remove = i3000_remove_one,
535c6a53 JU	502	.id_table = i3000_pci_tbl,
	503	};
	504
	505	static int __init i3000_init(void)
	506	{
	507	int pci_rc;
	508
956b9ba1	509	edac_dbg(3, "MC:\n");
c3c52bce	510
1722bc0e CIK	511	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
1722bc0e CIK	512	opstate_init();
c3c52bce	513
535c6a53 JU	514	pci_rc = pci_register_driver(&i3000_driver);
	515	if (pci_rc < 0)
	516	goto fail0;
	517
ce783d70	518	if (!mci_pdev) {
535c6a53 JU	519	i3000_registered = 0;
535c6a53 JU	520	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	521	PCI_DEVICE_ID_INTEL_3000_HB, NULL);
535c6a53	522	if (!mci_pdev) {
956b9ba1	523	edac_dbg(0, "i3000 pci_get_device fail\n");
535c6a53 JU	524	pci_rc = -ENODEV;
	525	goto fail1;
	526	}
	527
	528	pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
	529	if (pci_rc < 0) {
956b9ba1	530	edac_dbg(0, "i3000 init fail\n");
535c6a53 JU	531	pci_rc = -ENODEV;
	532	goto fail1;
	533	}
	534	}
	535
	536	return 0;
	537
052dfb45	538	fail1:
535c6a53 JU	539	pci_unregister_driver(&i3000_driver);
535c6a53 JU	540
052dfb45	541	fail0:
0a98babd	542	pci_dev_put(mci_pdev);
535c6a53 JU	543
	544	return pci_rc;
	545	}
	546
	547	static void __exit i3000_exit(void)
	548	{
956b9ba1	549	edac_dbg(3, "MC:\n");
535c6a53 JU	550
	551	pci_unregister_driver(&i3000_driver);
	552	if (!i3000_registered) {
	553	i3000_remove_one(mci_pdev);
	554	pci_dev_put(mci_pdev);
	555	}
	556	}
	557
	558	module_init(i3000_init);
	559	module_exit(i3000_exit);
	560
	561	MODULE_LICENSE("GPL");
	562	MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
	563	MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
7ed31e0f HM	564
	565	module_param(edac_op_state, int, 0444);
	566	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");