[linux-block.git] / drivers / edac / i10nm_base.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for Intel(R) 10nm server memory controller.
 * Copyright (c) 2019, Intel Corporation.
 *
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/mce.h>
#include "edac_module.h"
#include "skx_common.h"

#define I10NM_REVISION	"v0.0.5"
#define EDAC_MOD_STR	"i10nm_edac"

/* Debug macros */
#define i10nm_printk(level, fmt, arg...)	\
	edac_printk(level, "i10nm", fmt, ##arg)

#define I10NM_GET_SCK_BAR(d, reg)	\
	pci_read_config_dword((d)->uracu, 0xd0, &(reg))
#define I10NM_GET_IMC_BAR(d, i, reg)	\
	pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
#define I10NM_GET_SAD(d, offset, i, reg)\
	pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg))
#define I10NM_GET_HBM_IMC_BAR(d, reg)	\
	pci_read_config_dword((d)->uracu, 0xd4, &(reg))
#define I10NM_GET_CAPID3_CFG(d, reg)	\
	pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg))
#define I10NM_GET_DIMMMTR(m, i, j)	\
	readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \
	(i) * (m)->chan_mmio_sz + (j) * 4)
#define I10NM_GET_MCDDRTCFG(m, i)	\
	readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
	(i) * (m)->chan_mmio_sz)
#define I10NM_GET_MCMTR(m, i)		\
	readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \
	(i) * (m)->chan_mmio_sz)
#define I10NM_GET_AMAP(m, i)		\
	readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \
	(i) * (m)->chan_mmio_sz)
#define I10NM_GET_REG32(m, i, offset)	\
	readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
#define I10NM_GET_REG64(m, i, offset)	\
	readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
#define I10NM_SET_REG32(m, i, offset, v)	\
	writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))

#define I10NM_GET_SCK_MMIO_BASE(reg)	(GET_BITFIELD(reg, 0, 28) << 23)
#define I10NM_GET_IMC_MMIO_OFFSET(reg)	(GET_BITFIELD(reg, 0, 10) << 12)
#define I10NM_GET_IMC_MMIO_SIZE(reg)	((GET_BITFIELD(reg, 13, 23) - \
					 GET_BITFIELD(reg, 0, 10) + 1) << 12)
#define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg)	\
	((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)

#define I10NM_HBM_IMC_MMIO_SIZE		0x9000
#define I10NM_IS_HBM_PRESENT(reg)	GET_BITFIELD(reg, 27, 30)
#define I10NM_IS_HBM_IMC(reg)		GET_BITFIELD(reg, 29, 29)

#define I10NM_MAX_SAD			16
#define I10NM_SAD_ENABLE(reg)		GET_BITFIELD(reg, 0, 0)
#define I10NM_SAD_NM_CACHEABLE(reg)	GET_BITFIELD(reg, 5, 5)

#define RETRY_RD_ERR_LOG_UC		BIT(1)
#define RETRY_RD_ERR_LOG_NOOVER		BIT(14)
#define RETRY_RD_ERR_LOG_EN		BIT(15)
#define RETRY_RD_ERR_LOG_NOOVER_UC	(BIT(14) | BIT(1))
#define RETRY_RD_ERR_LOG_OVER_UC_V	(BIT(2) | BIT(1) | BIT(0))

static struct list_head *i10nm_edac_list;

static struct res_config *res_cfg;
static int retry_rd_err_log;

static u32 offsets_scrub_icx[]  = {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8};
static u32 offsets_scrub_spr[]  = {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8};
static u32 offsets_demand_icx[] = {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0};
static u32 offsets_demand_spr[] = {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0};

static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable)
{
	u32 s, d;

	if (!imc->mbase)
		return;

	s = I10NM_GET_REG32(imc, chan, res_cfg->offsets_scrub[0]);
	d = I10NM_GET_REG32(imc, chan, res_cfg->offsets_demand[0]);

	if (enable) {
		/* Save default configurations */
		imc->chan[chan].retry_rd_err_log_s = s;
		imc->chan[chan].retry_rd_err_log_d = d;

		s &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
		s |=  RETRY_RD_ERR_LOG_EN;
		d &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
		d |=  RETRY_RD_ERR_LOG_EN;
	} else {
		/* Restore default configurations */
		if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_UC)
			s |=  RETRY_RD_ERR_LOG_UC;
		if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_NOOVER)
			s |=  RETRY_RD_ERR_LOG_NOOVER;
		if (!(imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_EN))
			s &= ~RETRY_RD_ERR_LOG_EN;
		if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_UC)
			d |=  RETRY_RD_ERR_LOG_UC;
		if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_NOOVER)
			d |=  RETRY_RD_ERR_LOG_NOOVER;
		if (!(imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_EN))
			d &= ~RETRY_RD_ERR_LOG_EN;
	}

	I10NM_SET_REG32(imc, chan, res_cfg->offsets_scrub[0], s);
	I10NM_SET_REG32(imc, chan, res_cfg->offsets_demand[0], d);
}

static void enable_retry_rd_err_log(bool enable)
{
	struct skx_dev *d;
	int i, j;

	edac_dbg(2, "\n");

	list_for_each_entry(d, i10nm_edac_list, list)
		for (i = 0; i < I10NM_NUM_IMC; i++)
			for (j = 0; j < I10NM_NUM_CHANNELS; j++)
				__enable_retry_rd_err_log(&d->imc[i], j, enable);
}

static void show_retry_rd_err_log(struct decoded_addr *res, char *msg,
				  int len, bool scrub_err)
{
	struct skx_imc *imc = &res->dev->imc[res->imc];
	u32 log0, log1, log2, log3, log4;
	u32 corr0, corr1, corr2, corr3;
	u64 log2a, log5;
	u32 *offsets;
	int n;

	if (!imc->mbase)
		return;

	offsets = scrub_err ? res_cfg->offsets_scrub : res_cfg->offsets_demand;

	log0 = I10NM_GET_REG32(imc, res->channel, offsets[0]);
	log1 = I10NM_GET_REG32(imc, res->channel, offsets[1]);
	log3 = I10NM_GET_REG32(imc, res->channel, offsets[3]);
	log4 = I10NM_GET_REG32(imc, res->channel, offsets[4]);
	log5 = I10NM_GET_REG64(imc, res->channel, offsets[5]);

	if (res_cfg->type == SPR) {
		log2a = I10NM_GET_REG64(imc, res->channel, offsets[2]);
		n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.16llx %.8x %.8x %.16llx]",
			     log0, log1, log2a, log3, log4, log5);
	} else {
		log2 = I10NM_GET_REG32(imc, res->channel, offsets[2]);
		n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x %.16llx]",
			     log0, log1, log2, log3, log4, log5);
	}

	corr0 = I10NM_GET_REG32(imc, res->channel, 0x22c18);
	corr1 = I10NM_GET_REG32(imc, res->channel, 0x22c1c);
	corr2 = I10NM_GET_REG32(imc, res->channel, 0x22c20);
	corr3 = I10NM_GET_REG32(imc, res->channel, 0x22c24);

	if (len - n > 0)
		snprintf(msg + n, len - n,
			 " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
			 corr0 & 0xffff, corr0 >> 16,
			 corr1 & 0xffff, corr1 >> 16,
			 corr2 & 0xffff, corr2 >> 16,
			 corr3 & 0xffff, corr3 >> 16);

	/* Clear status bits */
	if (retry_rd_err_log == 2 && (log0 & RETRY_RD_ERR_LOG_OVER_UC_V)) {
		log0 &= ~RETRY_RD_ERR_LOG_OVER_UC_V;
		I10NM_SET_REG32(imc, res->channel, offsets[0], log0);
	}
}

static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
					   unsigned int dev, unsigned int fun)
{
	struct pci_dev *pdev;

	pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
	if (!pdev) {
		edac_dbg(2, "No device %02x:%02x.%x\n",
			 bus, dev, fun);
		return NULL;
	}

	if (unlikely(pci_enable_device(pdev) < 0)) {
		edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
			 bus, dev, fun);
		return NULL;
	}

	pci_dev_get(pdev);

	return pdev;
}

static bool i10nm_check_2lm(struct res_config *cfg)
{
	struct skx_dev *d;
	u32 reg;
	int i;

	list_for_each_entry(d, i10nm_edac_list, list) {
		d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[1],
						 PCI_SLOT(cfg->sad_all_devfn),
						 PCI_FUNC(cfg->sad_all_devfn));
		if (!d->sad_all)
			continue;

		for (i = 0; i < I10NM_MAX_SAD; i++) {
			I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg);
			if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) {
				edac_dbg(2, "2-level memory configuration.\n");
				return true;
			}
		}
	}

	return false;
}

static int i10nm_get_ddr_munits(void)
{
	struct pci_dev *mdev;
	void __iomem *mbase;
	unsigned long size;
	struct skx_dev *d;
	int i, j = 0;
	u32 reg, off;
	u64 base;

	list_for_each_entry(d, i10nm_edac_list, list) {
		d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
		if (!d->util_all)
			return -ENODEV;

		d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
		if (!d->uracu)
			return -ENODEV;

		if (I10NM_GET_SCK_BAR(d, reg)) {
			i10nm_printk(KERN_ERR, "Failed to socket bar\n");
			return -ENODEV;
		}

		base = I10NM_GET_SCK_MMIO_BASE(reg);
		edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
			 j++, base, reg);

		for (i = 0; i < I10NM_NUM_DDR_IMC; i++) {
			mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
						   12 + i, 0);
			if (i == 0 && !mdev) {
				i10nm_printk(KERN_ERR, "No IMC found\n");
				return -ENODEV;
			}
			if (!mdev)
				continue;

			d->imc[i].mdev = mdev;

			if (I10NM_GET_IMC_BAR(d, i, reg)) {
				i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
				return -ENODEV;
			}

			off  = I10NM_GET_IMC_MMIO_OFFSET(reg);
			size = I10NM_GET_IMC_MMIO_SIZE(reg);
			edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
				 i, base + off, size, reg);

			mbase = ioremap(base + off, size);
			if (!mbase) {
				i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
					     base + off);
				return -ENODEV;
			}

			d->imc[i].mbase = mbase;
		}
	}

	return 0;
}

static bool i10nm_check_hbm_imc(struct skx_dev *d)
{
	u32 reg;

	if (I10NM_GET_CAPID3_CFG(d, reg)) {
		i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n");
		return false;
	}

	return I10NM_IS_HBM_PRESENT(reg) != 0;
}

static int i10nm_get_hbm_munits(void)
{
	struct pci_dev *mdev;
	void __iomem *mbase;
	u32 reg, off, mcmtr;
	struct skx_dev *d;
	int i, lmc;
	u64 base;

	list_for_each_entry(d, i10nm_edac_list, list) {
		d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3);
		if (!d->pcu_cr3)
			return -ENODEV;

		if (!i10nm_check_hbm_imc(d)) {
			i10nm_printk(KERN_DEBUG, "No hbm memory\n");
			return -ENODEV;
		}

		if (I10NM_GET_SCK_BAR(d, reg)) {
			i10nm_printk(KERN_ERR, "Failed to get socket bar\n");
			return -ENODEV;
		}
		base = I10NM_GET_SCK_MMIO_BASE(reg);

		if (I10NM_GET_HBM_IMC_BAR(d, reg)) {
			i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n");
			return -ENODEV;
		}
		base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg);

		lmc = I10NM_NUM_DDR_IMC;

		for (i = 0; i < I10NM_NUM_HBM_IMC; i++) {
			mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
						   12 + i / 4, 1 + i % 4);
			if (i == 0 && !mdev) {
				i10nm_printk(KERN_ERR, "No hbm mc found\n");
				return -ENODEV;
			}
			if (!mdev)
				continue;

			d->imc[lmc].mdev = mdev;
			off = i * I10NM_HBM_IMC_MMIO_SIZE;

			edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",
				 lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE);

			mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE);
			if (!mbase) {
				pci_dev_put(d->imc[lmc].mdev);
				d->imc[lmc].mdev = NULL;

				i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n",
					     base + off);
				return -ENOMEM;
			}

			d->imc[lmc].mbase = mbase;
			d->imc[lmc].hbm_mc = true;

			mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
			if (!I10NM_IS_HBM_IMC(mcmtr)) {
				iounmap(d->imc[lmc].mbase);
				d->imc[lmc].mbase = NULL;
				d->imc[lmc].hbm_mc = false;
				pci_dev_put(d->imc[lmc].mdev);
				d->imc[lmc].mdev = NULL;

				i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n");
				return -ENODEV;
			}

			lmc++;
		}
	}

	return 0;
}

static struct res_config i10nm_cfg0 = {
	.type			= I10NM,
	.decs_did		= 0x3452,
	.busno_cfg_offset	= 0xcc,
	.ddr_chan_mmio_sz	= 0x4000,
	.sad_all_devfn		= PCI_DEVFN(29, 0),
	.sad_all_offset		= 0x108,
	.offsets_scrub		= offsets_scrub_icx,
	.offsets_demand		= offsets_demand_icx,
};

static struct res_config i10nm_cfg1 = {
	.type			= I10NM,
	.decs_did		= 0x3452,
	.busno_cfg_offset	= 0xd0,
	.ddr_chan_mmio_sz	= 0x4000,
	.sad_all_devfn		= PCI_DEVFN(29, 0),
	.sad_all_offset		= 0x108,
	.offsets_scrub		= offsets_scrub_icx,
	.offsets_demand		= offsets_demand_icx,
};

static struct res_config spr_cfg = {
	.type			= SPR,
	.decs_did		= 0x3252,
	.busno_cfg_offset	= 0xd0,
	.ddr_chan_mmio_sz	= 0x8000,
	.hbm_chan_mmio_sz	= 0x4000,
	.support_ddr5		= true,
	.sad_all_devfn		= PCI_DEVFN(10, 0),
	.sad_all_offset		= 0x300,
	.offsets_scrub		= offsets_scrub_spr,
	.offsets_demand		= offsets_demand_spr,
};

static const struct x86_cpu_id i10nm_cpuids[] = {
	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,	X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,	X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,		X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,		X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D,		X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X,	X86_STEPPINGS(0x0, 0xf), &spr_cfg),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);

static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
{
	u32 mcmtr;

	mcmtr = I10NM_GET_MCMTR(imc, chan);
	edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);

	return !!GET_BITFIELD(mcmtr, 2, 2);
}

static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
				 struct res_config *cfg)
{
	struct skx_pvt *pvt = mci->pvt_info;
	struct skx_imc *imc = pvt->imc;
	u32 mtr, amap, mcddrtcfg;
	struct dimm_info *dimm;
	int i, j, ndimms;

	for (i = 0; i < imc->num_channels; i++) {
		if (!imc->mbase)
			continue;

		ndimms = 0;
		amap = I10NM_GET_AMAP(imc, i);
		mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
		for (j = 0; j < imc->num_dimms; j++) {
			dimm = edac_get_dimm(mci, i, j, 0);
			mtr = I10NM_GET_DIMMMTR(imc, i, j);
			edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
				 mtr, mcddrtcfg, imc->mc, i, j);

			if (IS_DIMM_PRESENT(mtr))
				ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
							    imc, i, j, cfg);
			else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
				ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
							      EDAC_MOD_STR);
		}
		if (ndimms && !i10nm_check_ecc(imc, i)) {
			i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
				     imc->mc, i);
			return -ENODEV;
		}
	}

	return 0;
}

static struct notifier_block i10nm_mce_dec = {
	.notifier_call	= skx_mce_check_error,
	.priority	= MCE_PRIO_EDAC,
};

#ifdef CONFIG_EDAC_DEBUG
/*
 * Debug feature.
 * Exercise the address decode logic by writing an address to
 * /sys/kernel/debug/edac/i10nm_test/addr.
 */
static struct dentry *i10nm_test;

static int debugfs_u64_set(void *data, u64 val)
{
	struct mce m;

	pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);

	memset(&m, 0, sizeof(m));
	/* ADDRV + MemRd + Unknown channel */
	m.status = MCI_STATUS_ADDRV + 0x90;
	/* One corrected error */
	m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
	m.addr = val;
	skx_mce_check_error(NULL, 0, &m);

	return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");

static void setup_i10nm_debug(void)
{
	i10nm_test = edac_debugfs_create_dir("i10nm_test");
	if (!i10nm_test)
		return;

	if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
				      NULL, &fops_u64_wo)) {
		debugfs_remove(i10nm_test);
		i10nm_test = NULL;
	}
}

static void teardown_i10nm_debug(void)
{
	debugfs_remove_recursive(i10nm_test);
}
#else
static inline void setup_i10nm_debug(void) {}
static inline void teardown_i10nm_debug(void) {}
#endif /*CONFIG_EDAC_DEBUG*/

static int __init i10nm_init(void)
{
	u8 mc = 0, src_id = 0, node_id = 0;
	const struct x86_cpu_id *id;
	struct res_config *cfg;
	const char *owner;
	struct skx_dev *d;
	int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
	u64 tolm, tohm;

	edac_dbg(2, "\n");

	owner = edac_get_owner();
	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
		return -EBUSY;

	if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
		return -ENODEV;

	id = x86_match_cpu(i10nm_cpuids);
	if (!id)
		return -ENODEV;

	cfg = (struct res_config *)id->driver_data;
	res_cfg = cfg;

	rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
	if (rc)
		return rc;

	rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
	if (rc < 0)
		goto fail;
	if (rc == 0) {
		i10nm_printk(KERN_ERR, "No memory controllers found\n");
		return -ENODEV;
	}

	skx_set_mem_cfg(i10nm_check_2lm(cfg));

	rc = i10nm_get_ddr_munits();

	if (i10nm_get_hbm_munits() && rc)
		goto fail;

	list_for_each_entry(d, i10nm_edac_list, list) {
		rc = skx_get_src_id(d, 0xf8, &src_id);
		if (rc < 0)
			goto fail;

		rc = skx_get_node_id(d, &node_id);
		if (rc < 0)
			goto fail;

		edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
		for (i = 0; i < I10NM_NUM_IMC; i++) {
			if (!d->imc[i].mdev)
				continue;

			d->imc[i].mc  = mc++;
			d->imc[i].lmc = i;
			d->imc[i].src_id  = src_id;
			d->imc[i].node_id = node_id;
			if (d->imc[i].hbm_mc) {
				d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
				d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS;
				d->imc[i].num_dimms    = I10NM_NUM_HBM_DIMMS;
			} else {
				d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
				d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS;
				d->imc[i].num_dimms    = I10NM_NUM_DDR_DIMMS;
			}

			rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
					      "Intel_10nm Socket", EDAC_MOD_STR,
					      i10nm_get_dimm_config, cfg);
			if (rc < 0)
				goto fail;
		}
	}

	rc = skx_adxl_get();
	if (rc)
		goto fail;

	opstate_init();
	mce_register_decode_chain(&i10nm_mce_dec);
	setup_i10nm_debug();

	if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
		skx_set_decode(NULL, show_retry_rd_err_log);
		if (retry_rd_err_log == 2)
			enable_retry_rd_err_log(true);
	}

	i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);

	return 0;
fail:
	skx_remove();
	return rc;
}

static void __exit i10nm_exit(void)
{
	edac_dbg(2, "\n");

	if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
		skx_set_decode(NULL, NULL);
		if (retry_rd_err_log == 2)
			enable_retry_rd_err_log(false);
	}

	teardown_i10nm_debug();
	mce_unregister_decode_chain(&i10nm_mce_dec);
	skx_adxl_put();
	skx_remove();
}

module_init(i10nm_init);
module_exit(i10nm_exit);

module_param(retry_rd_err_log, int, 0444);
MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)");

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");
Commit	Line	Data
d4dc89d0 QZ	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Driver for Intel(R) 10nm server memory controller.
	4	* Copyright (c) 2019, Intel Corporation.
	5	*
	6	*/
	7
	8	#include <linux/kernel.h>
83ff51c4	9	#include <linux/io.h>
d4dc89d0 QZ	10	#include <asm/cpu_device_id.h>
	11	#include <asm/intel-family.h>
	12	#include <asm/mce.h>
	13	#include "edac_module.h"
	14	#include "skx_common.h"
	15
c9450883	16	#define I10NM_REVISION "v0.0.5"
d4dc89d0 QZ	17	#define EDAC_MOD_STR "i10nm_edac"
	18
	19	/* Debug macros */
	20	#define i10nm_printk(level, fmt, arg...) \
	21	edac_printk(level, "i10nm", fmt, ##arg)
	22
83ff51c4	23	#define I10NM_GET_SCK_BAR(d, reg) \
d4dc89d0 QZ	24	pci_read_config_dword((d)->uracu, 0xd0, &(reg))
	25	#define I10NM_GET_IMC_BAR(d, i, reg) \
	26	pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
4bd4d32e QZ	27	#define I10NM_GET_SAD(d, offset, i, reg)\
4bd4d32e QZ	28	pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg))
c9450883 QZ	29	#define I10NM_GET_HBM_IMC_BAR(d, reg) \
	30	pci_read_config_dword((d)->uracu, 0xd4, &(reg))
	31	#define I10NM_GET_CAPID3_CFG(d, reg) \
	32	pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg))
d4dc89d0	33	#define I10NM_GET_DIMMMTR(m, i, j) \
c9450883 QZ	34	readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \
c9450883 QZ	35	(i) * (m)->chan_mmio_sz + (j) * 4)
2294a729	36	#define I10NM_GET_MCDDRTCFG(m, i) \
c9450883	37	readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
2294a729	38	(i) * (m)->chan_mmio_sz)
83ff51c4	39	#define I10NM_GET_MCMTR(m, i) \
c9450883 QZ	40	readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \
c9450883 QZ	41	(i) * (m)->chan_mmio_sz)
479f58dd	42	#define I10NM_GET_AMAP(m, i) \
c9450883 QZ	43	readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \
c9450883 QZ	44	(i) * (m)->chan_mmio_sz)
cf4e6d52 YS	45	#define I10NM_GET_REG32(m, i, offset) \
	46	readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
	47	#define I10NM_GET_REG64(m, i, offset) \
	48	readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
	49	#define I10NM_SET_REG32(m, i, offset, v) \
	50	writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
d4dc89d0 QZ	51
	52	#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
	53	#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
	54	#define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
	55	GET_BITFIELD(reg, 0, 10) + 1) << 12)
c9450883 QZ	56	#define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \
	57	((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
	58
	59	#define I10NM_HBM_IMC_MMIO_SIZE 0x9000
	60	#define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30)
	61	#define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29)
d4dc89d0	62
4bd4d32e QZ	63	#define I10NM_MAX_SAD 16
	64	#define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
	65	#define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5)
	66
cf4e6d52 YS	67	#define RETRY_RD_ERR_LOG_UC BIT(1)
	68	#define RETRY_RD_ERR_LOG_NOOVER BIT(14)
	69	#define RETRY_RD_ERR_LOG_EN BIT(15)
	70	#define RETRY_RD_ERR_LOG_NOOVER_UC (BIT(14) \| BIT(1))
	71	#define RETRY_RD_ERR_LOG_OVER_UC_V (BIT(2) \| BIT(1) \| BIT(0))
	72
d4dc89d0 QZ	73	static struct list_head *i10nm_edac_list;
d4dc89d0 QZ	74
cf4e6d52 YS	75	static struct res_config *res_cfg;
	76	static int retry_rd_err_log;
	77
	78	static u32 offsets_scrub_icx[] = {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8};
	79	static u32 offsets_scrub_spr[] = {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8};
	80	static u32 offsets_demand_icx[] = {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0};
	81	static u32 offsets_demand_spr[] = {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0};
	82
	83	static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable)
	84	{
	85	u32 s, d;
	86
	87	if (!imc->mbase)
	88	return;
	89
	90	s = I10NM_GET_REG32(imc, chan, res_cfg->offsets_scrub[0]);
	91	d = I10NM_GET_REG32(imc, chan, res_cfg->offsets_demand[0]);
	92
	93	if (enable) {
	94	/* Save default configurations */
	95	imc->chan[chan].retry_rd_err_log_s = s;
	96	imc->chan[chan].retry_rd_err_log_d = d;
	97
	98	s &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
	99	s \|= RETRY_RD_ERR_LOG_EN;
	100	d &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
	101	d \|= RETRY_RD_ERR_LOG_EN;
	102	} else {
	103	/* Restore default configurations */
	104	if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_UC)
	105	s \|= RETRY_RD_ERR_LOG_UC;
	106	if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_NOOVER)
	107	s \|= RETRY_RD_ERR_LOG_NOOVER;
	108	if (!(imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_EN))
	109	s &= ~RETRY_RD_ERR_LOG_EN;
	110	if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_UC)
	111	d \|= RETRY_RD_ERR_LOG_UC;
	112	if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_NOOVER)
	113	d \|= RETRY_RD_ERR_LOG_NOOVER;
	114	if (!(imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_EN))
	115	d &= ~RETRY_RD_ERR_LOG_EN;
	116	}
	117
	118	I10NM_SET_REG32(imc, chan, res_cfg->offsets_scrub[0], s);
	119	I10NM_SET_REG32(imc, chan, res_cfg->offsets_demand[0], d);
	120	}
	121
	122	static void enable_retry_rd_err_log(bool enable)
	123	{
	124	struct skx_dev *d;
	125	int i, j;
	126
	127	edac_dbg(2, "\n");
	128
	129	list_for_each_entry(d, i10nm_edac_list, list)
	130	for (i = 0; i < I10NM_NUM_IMC; i++)
	131	for (j = 0; j < I10NM_NUM_CHANNELS; j++)
	132	__enable_retry_rd_err_log(&d->imc[i], j, enable);
	133	}
	134
	135	static void show_retry_rd_err_log(struct decoded_addr res, char msg,
	136	int len, bool scrub_err)
	137	{
	138	struct skx_imc *imc = &res->dev->imc[res->imc];
139	u32 log0, log1, log2, log3, log4;
140	u32 corr0, corr1, corr2, corr3;
141	u64 log2a, log5;
142	u32 *offsets;
143	int n;
144
145	if (!imc->mbase)
146	return;
147
148	offsets = scrub_err ? res_cfg->offsets_scrub : res_cfg->offsets_demand;
149
150	log0 = I10NM_GET_REG32(imc, res->channel, offsets[0]);
151	log1 = I10NM_GET_REG32(imc, res->channel, offsets[1]);
152	log3 = I10NM_GET_REG32(imc, res->channel, offsets[3]);
153	log4 = I10NM_GET_REG32(imc, res->channel, offsets[4]);
154	log5 = I10NM_GET_REG64(imc, res->channel, offsets[5]);
155
156	if (res_cfg->type == SPR) {
157	log2a = I10NM_GET_REG64(imc, res->channel, offsets[2]);
158	n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.16llx %.8x %.8x %.16llx]",
159	log0, log1, log2a, log3, log4, log5);
160	} else {
161	log2 = I10NM_GET_REG32(imc, res->channel, offsets[2]);
162	n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x %.16llx]",
163	log0, log1, log2, log3, log4, log5);
164	}
165
166	corr0 = I10NM_GET_REG32(imc, res->channel, 0x22c18);
167	corr1 = I10NM_GET_REG32(imc, res->channel, 0x22c1c);
168	corr2 = I10NM_GET_REG32(imc, res->channel, 0x22c20);
169	corr3 = I10NM_GET_REG32(imc, res->channel, 0x22c24);
170
171	if (len - n > 0)
172	snprintf(msg + n, len - n,
173	" correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
174	corr0 & 0xffff, corr0 >> 16,
175	corr1 & 0xffff, corr1 >> 16,
176	corr2 & 0xffff, corr2 >> 16,
177	corr3 & 0xffff, corr3 >> 16);
178
179	/* Clear status bits */
180	if (retry_rd_err_log == 2 && (log0 & RETRY_RD_ERR_LOG_OVER_UC_V)) {
181	log0 &= ~RETRY_RD_ERR_LOG_OVER_UC_V;
182	I10NM_SET_REG32(imc, res->channel, offsets[0], log0);
183	}
184	}
185
d4dc89d0 QZ	186	static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
	187	unsigned int dev, unsigned int fun)
	188	{
	189	struct pci_dev *pdev;
	190
	191	pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
	192	if (!pdev) {
	193	edac_dbg(2, "No device %02x:%02x.%x\n",
	194	bus, dev, fun);
	195	return NULL;
	196	}
	197
	198	if (unlikely(pci_enable_device(pdev) < 0)) {
	199	edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
	200	bus, dev, fun);
	201	return NULL;
	202	}
	203
	204	pci_dev_get(pdev);
	205
	206	return pdev;
	207	}
	208
4bd4d32e QZ	209	static bool i10nm_check_2lm(struct res_config *cfg)
	210	{
	211	struct skx_dev *d;
	212	u32 reg;
	213	int i;
	214
	215	list_for_each_entry(d, i10nm_edac_list, list) {
	216	d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[1],
	217	PCI_SLOT(cfg->sad_all_devfn),
	218	PCI_FUNC(cfg->sad_all_devfn));
	219	if (!d->sad_all)
	220	continue;
	221
	222	for (i = 0; i < I10NM_MAX_SAD; i++) {
	223	I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg);
	224	if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) {
	225	edac_dbg(2, "2-level memory configuration.\n");
	226	return true;
	227	}
	228	}
	229	}
	230
	231	return false;
	232	}
	233
c9450883	234	static int i10nm_get_ddr_munits(void)
d4dc89d0 QZ	235	{
	236	struct pci_dev *mdev;
	237	void __iomem *mbase;
	238	unsigned long size;
	239	struct skx_dev *d;
	240	int i, j = 0;
	241	u32 reg, off;
	242	u64 base;
	243
	244	list_for_each_entry(d, i10nm_edac_list, list) {
	245	d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
	246	if (!d->util_all)
	247	return -ENODEV;
	248
	249	d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
	250	if (!d->uracu)
	251	return -ENODEV;
	252
	253	if (I10NM_GET_SCK_BAR(d, reg)) {
	254	i10nm_printk(KERN_ERR, "Failed to socket bar\n");
	255	return -ENODEV;
	256	}
	257
	258	base = I10NM_GET_SCK_MMIO_BASE(reg);
	259	edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
	260	j++, base, reg);
	261
c9450883	262	for (i = 0; i < I10NM_NUM_DDR_IMC; i++) {
d4dc89d0 QZ	263	mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
	264	12 + i, 0);
	265	if (i == 0 && !mdev) {
	266	i10nm_printk(KERN_ERR, "No IMC found\n");
	267	return -ENODEV;
	268	}
	269	if (!mdev)
	270	continue;
	271
	272	d->imc[i].mdev = mdev;
	273
	274	if (I10NM_GET_IMC_BAR(d, i, reg)) {
	275	i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
	276	return -ENODEV;
	277	}
	278
	279	off = I10NM_GET_IMC_MMIO_OFFSET(reg);
	280	size = I10NM_GET_IMC_MMIO_SIZE(reg);
	281	edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
	282	i, base + off, size, reg);
	283
	284	mbase = ioremap(base + off, size);
	285	if (!mbase) {
	286	i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
	287	base + off);
	288	return -ENODEV;
	289	}
	290
	291	d->imc[i].mbase = mbase;
	292	}
	293	}
	294
	295	return 0;
	296	}
	297
c9450883 QZ	298	static bool i10nm_check_hbm_imc(struct skx_dev *d)
	299	{
	300	u32 reg;
	301
	302	if (I10NM_GET_CAPID3_CFG(d, reg)) {
	303	i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n");
	304	return false;
	305	}
	306
	307	return I10NM_IS_HBM_PRESENT(reg) != 0;
	308	}
	309
	310	static int i10nm_get_hbm_munits(void)
	311	{
	312	struct pci_dev *mdev;
	313	void __iomem *mbase;
	314	u32 reg, off, mcmtr;
	315	struct skx_dev *d;
	316	int i, lmc;
	317	u64 base;
	318
	319	list_for_each_entry(d, i10nm_edac_list, list) {
	320	d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3);
	321	if (!d->pcu_cr3)
	322	return -ENODEV;
	323
	324	if (!i10nm_check_hbm_imc(d)) {
	325	i10nm_printk(KERN_DEBUG, "No hbm memory\n");
	326	return -ENODEV;
	327	}
	328
	329	if (I10NM_GET_SCK_BAR(d, reg)) {
	330	i10nm_printk(KERN_ERR, "Failed to get socket bar\n");
	331	return -ENODEV;
	332	}
	333	base = I10NM_GET_SCK_MMIO_BASE(reg);
	334
	335	if (I10NM_GET_HBM_IMC_BAR(d, reg)) {
	336	i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n");
	337	return -ENODEV;
	338	}
	339	base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg);
	340
	341	lmc = I10NM_NUM_DDR_IMC;
	342
	343	for (i = 0; i < I10NM_NUM_HBM_IMC; i++) {
	344	mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
	345	12 + i / 4, 1 + i % 4);
	346	if (i == 0 && !mdev) {
	347	i10nm_printk(KERN_ERR, "No hbm mc found\n");
	348	return -ENODEV;
	349	}
	350	if (!mdev)
	351	continue;
	352
	353	d->imc[lmc].mdev = mdev;
	354	off = i * I10NM_HBM_IMC_MMIO_SIZE;
	355
	356	edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",
	357	lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE);
	358
	359	mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE);
	360	if (!mbase) {
c370baa3 QZ	361	pci_dev_put(d->imc[lmc].mdev);
	362	d->imc[lmc].mdev = NULL;
	363
c9450883 QZ	364	i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n",
	365	base + off);
	366	return -ENOMEM;
	367	}
	368
	369	d->imc[lmc].mbase = mbase;
	370	d->imc[lmc].hbm_mc = true;
	371
	372	mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
	373	if (!I10NM_IS_HBM_IMC(mcmtr)) {
c370baa3 QZ	374	iounmap(d->imc[lmc].mbase);
	375	d->imc[lmc].mbase = NULL;
	376	d->imc[lmc].hbm_mc = false;
	377	pci_dev_put(d->imc[lmc].mdev);
	378	d->imc[lmc].mdev = NULL;
	379
c9450883 QZ	380	i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n");
	381	return -ENODEV;
	382	}
	383
	384	lmc++;
	385	}
	386	}
	387
	388	return 0;
	389	}
	390
ce206708	391	static struct res_config i10nm_cfg0 = {
ee5340ab QZ	392	.type = I10NM,
	393	.decs_did = 0x3452,
	394	.busno_cfg_offset = 0xcc,
479f58dd	395	.ddr_chan_mmio_sz = 0x4000,
4bd4d32e QZ	396	.sad_all_devfn = PCI_DEVFN(29, 0),
4bd4d32e QZ	397	.sad_all_offset = 0x108,
cf4e6d52 YS	398	.offsets_scrub = offsets_scrub_icx,
cf4e6d52 YS	399	.offsets_demand = offsets_demand_icx,
ee5340ab QZ	400	};
ee5340ab QZ	401
ce206708 QZ	402	static struct res_config i10nm_cfg1 = {
	403	.type = I10NM,
	404	.decs_did = 0x3452,
	405	.busno_cfg_offset = 0xd0,
479f58dd	406	.ddr_chan_mmio_sz = 0x4000,
4bd4d32e QZ	407	.sad_all_devfn = PCI_DEVFN(29, 0),
4bd4d32e QZ	408	.sad_all_offset = 0x108,
cf4e6d52 YS	409	.offsets_scrub = offsets_scrub_icx,
cf4e6d52 YS	410	.offsets_demand = offsets_demand_icx,
479f58dd QZ	411	};
	412
	413	static struct res_config spr_cfg = {
	414	.type = SPR,
	415	.decs_did = 0x3252,
	416	.busno_cfg_offset = 0xd0,
	417	.ddr_chan_mmio_sz = 0x8000,
c9450883	418	.hbm_chan_mmio_sz = 0x4000,
479f58dd	419	.support_ddr5 = true,
4bd4d32e QZ	420	.sad_all_devfn = PCI_DEVFN(10, 0),
4bd4d32e QZ	421	.sad_all_offset = 0x300,
cf4e6d52 YS	422	.offsets_scrub = offsets_scrub_spr,
cf4e6d52 YS	423	.offsets_demand = offsets_demand_spr,
ce206708 QZ	424	};
ce206708 QZ	425
d4dc89d0	426	static const struct x86_cpu_id i10nm_cpuids[] = {
8807e155 QZ	427	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
	428	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
	429	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
	430	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
	431	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
479f58dd	432	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
29842621	433	{}
d4dc89d0 QZ	434	};
	435	MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
	436
	437	static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
	438	{
	439	u32 mcmtr;
	440
83ff51c4	441	mcmtr = I10NM_GET_MCMTR(imc, chan);
d4dc89d0 QZ	442	edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
	443
	444	return !!GET_BITFIELD(mcmtr, 2, 2);
	445	}
	446
479f58dd QZ	447	static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
479f58dd QZ	448	struct res_config *cfg)
d4dc89d0 QZ	449	{
	450	struct skx_pvt *pvt = mci->pvt_info;
	451	struct skx_imc *imc = pvt->imc;
479f58dd	452	u32 mtr, amap, mcddrtcfg;
d4dc89d0	453	struct dimm_info *dimm;
d4dc89d0 QZ	454	int i, j, ndimms;
d4dc89d0 QZ	455
c9450883	456	for (i = 0; i < imc->num_channels; i++) {
d4dc89d0 QZ	457	if (!imc->mbase)
	458	continue;
	459
	460	ndimms = 0;
479f58dd	461	amap = I10NM_GET_AMAP(imc, i);
2294a729	462	mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
c9450883	463	for (j = 0; j < imc->num_dimms; j++) {
bc9ad9e4	464	dimm = edac_get_dimm(mci, i, j, 0);
d4dc89d0	465	mtr = I10NM_GET_DIMMMTR(imc, i, j);
d4dc89d0 QZ	466	edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
	467	mtr, mcddrtcfg, imc->mc, i, j);
	468
	469	if (IS_DIMM_PRESENT(mtr))
479f58dd QZ	470	ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
479f58dd QZ	471	imc, i, j, cfg);
d4dc89d0 QZ	472	else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
	473	ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
	474	EDAC_MOD_STR);
	475	}
c4a1dd9e QZ	476	if (ndimms && !i10nm_check_ecc(imc, i)) {
	477	i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
	478	imc->mc, i);
d4dc89d0 QZ	479	return -ENODEV;
	480	}
	481	}
	482
	483	return 0;
	484	}
	485
	486	static struct notifier_block i10nm_mce_dec = {
	487	.notifier_call = skx_mce_check_error,
	488	.priority = MCE_PRIO_EDAC,
	489	};
	490
fe783516 QZ	491	#ifdef CONFIG_EDAC_DEBUG
	492	/*
	493	* Debug feature.
	494	* Exercise the address decode logic by writing an address to
	495	* /sys/kernel/debug/edac/i10nm_test/addr.
	496	*/
	497	static struct dentry *i10nm_test;
	498
	499	static int debugfs_u64_set(void *data, u64 val)
	500	{
	501	struct mce m;
	502
	503	pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
	504
	505	memset(&m, 0, sizeof(m));
	506	/* ADDRV + MemRd + Unknown channel */
	507	m.status = MCI_STATUS_ADDRV + 0x90;
	508	/* One corrected error */
	509	m.status \|= BIT_ULL(MCI_STATUS_CEC_SHIFT);
	510	m.addr = val;
	511	skx_mce_check_error(NULL, 0, &m);
	512
	513	return 0;
	514	}
	515	DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
	516
	517	static void setup_i10nm_debug(void)
	518	{
	519	i10nm_test = edac_debugfs_create_dir("i10nm_test");
	520	if (!i10nm_test)
	521	return;
	522
	523	if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
	524	NULL, &fops_u64_wo)) {
	525	debugfs_remove(i10nm_test);
	526	i10nm_test = NULL;
	527	}
	528	}
	529
	530	static void teardown_i10nm_debug(void)
	531	{
	532	debugfs_remove_recursive(i10nm_test);
	533	}
	534	#else
	535	static inline void setup_i10nm_debug(void) {}
	536	static inline void teardown_i10nm_debug(void) {}
	537	#endif /CONFIG_EDAC_DEBUG/
	538
d4dc89d0 QZ	539	static int __init i10nm_init(void)
	540	{
	541	u8 mc = 0, src_id = 0, node_id = 0;
	542	const struct x86_cpu_id *id;
ee5340ab	543	struct res_config *cfg;
d4dc89d0 QZ	544	const char *owner;
	545	struct skx_dev *d;
	546	int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
	547	u64 tolm, tohm;
	548
	549	edac_dbg(2, "\n");
	550
	551	owner = edac_get_owner();
	552	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
	553	return -EBUSY;
	554
f0a029ff LT	555	if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
	556	return -ENODEV;
	557
d4dc89d0 QZ	558	id = x86_match_cpu(i10nm_cpuids);
	559	if (!id)
	560	return -ENODEV;
	561
ee5340ab	562	cfg = (struct res_config *)id->driver_data;
cf4e6d52	563	res_cfg = cfg;
ee5340ab	564
d4dc89d0 QZ	565	rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
	566	if (rc)
	567	return rc;
	568
ee5340ab	569	rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
d4dc89d0 QZ	570	if (rc < 0)
	571	goto fail;
	572	if (rc == 0) {
	573	i10nm_printk(KERN_ERR, "No memory controllers found\n");
	574	return -ENODEV;
	575	}
	576
4bd4d32e QZ	577	skx_set_mem_cfg(i10nm_check_2lm(cfg));
4bd4d32e QZ	578
c9450883 QZ	579	rc = i10nm_get_ddr_munits();
	580
	581	if (i10nm_get_hbm_munits() && rc)
d4dc89d0 QZ	582	goto fail;
	583
	584	list_for_each_entry(d, i10nm_edac_list, list) {
1dc78f1f	585	rc = skx_get_src_id(d, 0xf8, &src_id);
d4dc89d0 QZ	586	if (rc < 0)
	587	goto fail;
	588
	589	rc = skx_get_node_id(d, &node_id);
	590	if (rc < 0)
	591	goto fail;
	592
	593	edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
	594	for (i = 0; i < I10NM_NUM_IMC; i++) {
	595	if (!d->imc[i].mdev)
	596	continue;
	597
	598	d->imc[i].mc = mc++;
	599	d->imc[i].lmc = i;
	600	d->imc[i].src_id = src_id;
	601	d->imc[i].node_id = node_id;
c9450883 QZ	602	if (d->imc[i].hbm_mc) {
	603	d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
	604	d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS;
	605	d->imc[i].num_dimms = I10NM_NUM_HBM_DIMMS;
	606	} else {
	607	d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
	608	d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS;
	609	d->imc[i].num_dimms = I10NM_NUM_DDR_DIMMS;
	610	}
d4dc89d0 QZ	611
	612	rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
	613	"Intel_10nm Socket", EDAC_MOD_STR,
479f58dd	614	i10nm_get_dimm_config, cfg);
d4dc89d0 QZ	615	if (rc < 0)
	616	goto fail;
	617	}
	618	}
	619
	620	rc = skx_adxl_get();
	621	if (rc)
	622	goto fail;
	623
	624	opstate_init();
	625	mce_register_decode_chain(&i10nm_mce_dec);
fe783516	626	setup_i10nm_debug();
d4dc89d0	627
cf4e6d52 YS	628	if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
	629	skx_set_decode(NULL, show_retry_rd_err_log);
	630	if (retry_rd_err_log == 2)
	631	enable_retry_rd_err_log(true);
	632	}
	633
d4dc89d0 QZ	634	i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
	635
	636	return 0;
	637	fail:
	638	skx_remove();
	639	return rc;
	640	}
	641
	642	static void __exit i10nm_exit(void)
	643	{
	644	edac_dbg(2, "\n");
cf4e6d52 YS	645
	646	if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
	647	skx_set_decode(NULL, NULL);
	648	if (retry_rd_err_log == 2)
	649	enable_retry_rd_err_log(false);
	650	}
	651
fe783516	652	teardown_i10nm_debug();
d4dc89d0 QZ	653	mce_unregister_decode_chain(&i10nm_mce_dec);
	654	skx_adxl_put();
	655	skx_remove();
	656	}
	657
	658	module_init(i10nm_init);
	659	module_exit(i10nm_exit);
	660
cf4e6d52 YS	661	module_param(retry_rd_err_log, int, 0444);
	662	MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)");
	663
d4dc89d0 QZ	664	MODULE_LICENSE("GPL v2");
d4dc89d0 QZ	665	MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");