[linux-2.6-block.git] / drivers / edac / highbank_mc_edac.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2011-2012 Calxeda, Inc.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/edac.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/uaccess.h>

#include "edac_module.h"

/* DDR Ctrlr Error Registers */

#define HB_DDR_ECC_ERR_BASE		0x128
#define MW_DDR_ECC_ERR_BASE		0x1b4

#define HB_DDR_ECC_OPT			0x00
#define HB_DDR_ECC_U_ERR_ADDR		0x08
#define HB_DDR_ECC_U_ERR_STAT		0x0c
#define HB_DDR_ECC_U_ERR_DATAL		0x10
#define HB_DDR_ECC_U_ERR_DATAH		0x14
#define HB_DDR_ECC_C_ERR_ADDR		0x18
#define HB_DDR_ECC_C_ERR_STAT		0x1c
#define HB_DDR_ECC_C_ERR_DATAL		0x20
#define HB_DDR_ECC_C_ERR_DATAH		0x24

#define HB_DDR_ECC_OPT_MODE_MASK	0x3
#define HB_DDR_ECC_OPT_FWC		0x100
#define HB_DDR_ECC_OPT_XOR_SHIFT	16

/* DDR Ctrlr Interrupt Registers */

#define HB_DDR_ECC_INT_BASE		0x180
#define MW_DDR_ECC_INT_BASE		0x218

#define HB_DDR_ECC_INT_STATUS		0x00
#define HB_DDR_ECC_INT_ACK		0x04

#define HB_DDR_ECC_INT_STAT_CE		0x8
#define HB_DDR_ECC_INT_STAT_DOUBLE_CE	0x10
#define HB_DDR_ECC_INT_STAT_UE		0x20
#define HB_DDR_ECC_INT_STAT_DOUBLE_UE	0x40

struct hb_mc_drvdata {
	void __iomem *mc_err_base;
	void __iomem *mc_int_base;
};

static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
{
	struct mem_ctl_info *mci = dev_id;
	struct hb_mc_drvdata *drvdata = mci->pvt_info;
	u32 status, err_addr;

	/* Read the interrupt status register */
	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);

	if (status & HB_DDR_ECC_INT_STAT_UE) {
		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, 0,
				     0, 0, -1,
				     mci->ctl_name, "");
	}
	if (status & HB_DDR_ECC_INT_STAT_CE) {
		u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
		syndrome = (syndrome >> 8) & 0xff;
		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, syndrome,
				     0, 0, -1,
				     mci->ctl_name, "");
	}

	/* clear the error, clears the interrupt */
	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
	return IRQ_HANDLED;
}

static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
{
	struct hb_mc_drvdata *pdata = mci->pvt_info;
	u32 reg;

	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
	reg &= HB_DDR_ECC_OPT_MODE_MASK;
	reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
}

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

static ssize_t highbank_mc_inject_ctrl(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	struct mem_ctl_info *mci = to_mci(dev);
	u8 synd;

	if (kstrtou8(buf, 16, &synd))
		return -EINVAL;

	highbank_mc_err_inject(mci, synd);

	return count;
}

static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);

static struct attribute *highbank_dev_attrs[] = {
	&dev_attr_inject_ctrl.attr,
	NULL
};

ATTRIBUTE_GROUPS(highbank_dev);

struct hb_mc_settings {
	int	err_offset;
	int	int_offset;
};

static struct hb_mc_settings hb_settings = {
	.err_offset = HB_DDR_ECC_ERR_BASE,
	.int_offset = HB_DDR_ECC_INT_BASE,
};

static struct hb_mc_settings mw_settings = {
	.err_offset = MW_DDR_ECC_ERR_BASE,
	.int_offset = MW_DDR_ECC_INT_BASE,
};

static const struct of_device_id hb_ddr_ctrl_of_match[] = {
	{ .compatible = "calxeda,hb-ddr-ctrl",		.data = &hb_settings },
	{ .compatible = "calxeda,ecx-2000-ddr-ctrl",	.data = &mw_settings },
	{},
};
MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);

static int highbank_mc_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	const struct hb_mc_settings *settings;
	struct edac_mc_layer layers[2];
	struct mem_ctl_info *mci;
	struct hb_mc_drvdata *drvdata;
	struct dimm_info *dimm;
	struct resource *r;
	void __iomem *base;
	u32 control;
	int irq;
	int res = 0;

	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
	if (!id)
		return -ENODEV;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = 1;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
			    sizeof(struct hb_mc_drvdata));
	if (!mci)
		return -ENOMEM;

	mci->pdev = &pdev->dev;
	drvdata = mci->pvt_info;
	platform_set_drvdata(pdev, mci);

	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "Unable to get mem resource\n");
		res = -ENODEV;
		goto err;
	}

	if (!devm_request_mem_region(&pdev->dev, r->start,
				     resource_size(r), dev_name(&pdev->dev))) {
		dev_err(&pdev->dev, "Error while requesting mem region\n");
		res = -EBUSY;
		goto err;
	}

	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!base) {
		dev_err(&pdev->dev, "Unable to map regs\n");
		res = -ENOMEM;
		goto err;
	}

	settings = id->data;
	drvdata->mc_err_base = base + settings->err_offset;
	drvdata->mc_int_base = base + settings->int_offset;

	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
	if (!control || (control == 0x2)) {
		dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
		res = -ENODEV;
		goto err;
	}

	mci->mtype_cap = MEM_FLAG_DDR3;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = pdev->dev.driver->name;
	mci->ctl_name = id->compatible;
	mci->dev_name = dev_name(&pdev->dev);
	mci->scrub_mode = SCRUB_SW_SRC;

	/* Only a single 4GB DIMM is supported */
	dimm = *mci->dimms;
	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
	dimm->grain = 8;
	dimm->dtype = DEV_X8;
	dimm->mtype = MEM_DDR3;
	dimm->edac_mode = EDAC_SECDED;

	res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
	if (res < 0)
		goto err;

	irq = platform_get_irq(pdev, 0);
	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
			       0, dev_name(&pdev->dev), mci);
	if (res < 0) {
		dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
		goto err2;
	}

	devres_close_group(&pdev->dev, NULL);
	return 0;
err2:
	edac_mc_del_mc(&pdev->dev);
err:
	devres_release_group(&pdev->dev, NULL);
	edac_mc_free(mci);
	return res;
}

static int highbank_mc_remove(struct platform_device *pdev)
{
	struct mem_ctl_info *mci = platform_get_drvdata(pdev);

	edac_mc_del_mc(&pdev->dev);
	edac_mc_free(mci);
	return 0;
}

static struct platform_driver highbank_mc_edac_driver = {
	.probe = highbank_mc_probe,
	.remove = highbank_mc_remove,
	.driver = {
		.name = "hb_mc_edac",
		.of_match_table = hb_ddr_ctrl_of_match,
	},
};

module_platform_driver(highbank_mc_edac_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Calxeda, Inc.");
MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
a1b01edb RH	2	/*
a1b01edb RH	3	* Copyright 2011-2012 Calxeda, Inc.
a1b01edb RH	4	*/
	5	#include <linux/types.h>
	6	#include <linux/kernel.h>
	7	#include <linux/ctype.h>
	8	#include <linux/edac.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/of_platform.h>
	12	#include <linux/uaccess.h>
	13
a1b01edb RH	14	#include "edac_module.h"
	15
	16	/* DDR Ctrlr Error Registers */
a1b01edb	17
0ec8579e RR	18	#define HB_DDR_ECC_ERR_BASE 0x128
	19	#define MW_DDR_ECC_ERR_BASE 0x1b4
	20
	21	#define HB_DDR_ECC_OPT 0x00
	22	#define HB_DDR_ECC_U_ERR_ADDR 0x08
	23	#define HB_DDR_ECC_U_ERR_STAT 0x0c
	24	#define HB_DDR_ECC_U_ERR_DATAL 0x10
	25	#define HB_DDR_ECC_U_ERR_DATAH 0x14
	26	#define HB_DDR_ECC_C_ERR_ADDR 0x18
	27	#define HB_DDR_ECC_C_ERR_STAT 0x1c
	28	#define HB_DDR_ECC_C_ERR_DATAL 0x20
	29	#define HB_DDR_ECC_C_ERR_DATAH 0x24
a1b01edb RH	30
	31	#define HB_DDR_ECC_OPT_MODE_MASK 0x3
	32	#define HB_DDR_ECC_OPT_FWC 0x100
	33	#define HB_DDR_ECC_OPT_XOR_SHIFT 16
	34
0ec8579e RR	35	/* DDR Ctrlr Interrupt Registers */
	36
	37	#define HB_DDR_ECC_INT_BASE 0x180
	38	#define MW_DDR_ECC_INT_BASE 0x218
	39
	40	#define HB_DDR_ECC_INT_STATUS 0x00
	41	#define HB_DDR_ECC_INT_ACK 0x04
	42
	43	#define HB_DDR_ECC_INT_STAT_CE 0x8
	44	#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
	45	#define HB_DDR_ECC_INT_STAT_UE 0x20
	46	#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
	47
a1b01edb	48	struct hb_mc_drvdata {
0ec8579e RR	49	void __iomem *mc_err_base;
0ec8579e RR	50	void __iomem *mc_int_base;
a1b01edb RH	51	};
	52
	53	static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
	54	{
	55	struct mem_ctl_info *mci = dev_id;
	56	struct hb_mc_drvdata *drvdata = mci->pvt_info;
	57	u32 status, err_addr;
	58
	59	/* Read the interrupt status register */
0ec8579e	60	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
a1b01edb RH	61
a1b01edb RH	62	if (status & HB_DDR_ECC_INT_STAT_UE) {
0ec8579e	63	err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
a1b01edb RH	64	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
	65	err_addr >> PAGE_SHIFT,
	66	err_addr & ~PAGE_MASK, 0,
	67	0, 0, -1,
	68	mci->ctl_name, "");
	69	}
	70	if (status & HB_DDR_ECC_INT_STAT_CE) {
0ec8579e	71	u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
a1b01edb	72	syndrome = (syndrome >> 8) & 0xff;
0ec8579e	73	err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
a1b01edb RH	74	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
	75	err_addr >> PAGE_SHIFT,
	76	err_addr & ~PAGE_MASK, syndrome,
	77	0, 0, -1,
	78	mci->ctl_name, "");
	79	}
	80
	81	/* clear the error, clears the interrupt */
0ec8579e	82	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
a1b01edb RH	83	return IRQ_HANDLED;
	84	}
	85
78cfbf0b	86	static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
a1b01edb	87	{
a1b01edb	88	struct hb_mc_drvdata *pdata = mci->pvt_info;
a1b01edb	89	u32 reg;
78cfbf0b RR	90
	91	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
	92	reg &= HB_DDR_ECC_OPT_MODE_MASK;
	93	reg \|= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) \| HB_DDR_ECC_OPT_FWC;
	94	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
	95	}
	96
	97	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
	98
	99	static ssize_t highbank_mc_inject_ctrl(struct device *dev,
	100	struct device_attribute attr, const char buf, size_t count)
	101	{
	102	struct mem_ctl_info *mci = to_mci(dev);
a1b01edb RH	103	u8 synd;
a1b01edb RH	104
78cfbf0b RR	105	if (kstrtou8(buf, 16, &synd))
78cfbf0b RR	106	return -EINVAL;
a1b01edb	107
78cfbf0b	108	highbank_mc_err_inject(mci, synd);
a1b01edb RH	109
	110	return count;
	111	}
	112
78cfbf0b	113	static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
a1b01edb	114
fc7cc6b7 TI	115	static struct attribute *highbank_dev_attrs[] = {
	116	&dev_attr_inject_ctrl.attr,
	117	NULL
	118	};
	119
	120	ATTRIBUTE_GROUPS(highbank_dev);
	121
0ec8579e RR	122	struct hb_mc_settings {
	123	int err_offset;
	124	int int_offset;
	125	};
	126
	127	static struct hb_mc_settings hb_settings = {
	128	.err_offset = HB_DDR_ECC_ERR_BASE,
	129	.int_offset = HB_DDR_ECC_INT_BASE,
	130	};
	131
	132	static struct hb_mc_settings mw_settings = {
	133	.err_offset = MW_DDR_ECC_ERR_BASE,
	134	.int_offset = MW_DDR_ECC_INT_BASE,
	135	};
	136
1afaa055	137	static const struct of_device_id hb_ddr_ctrl_of_match[] = {
0ec8579e RR	138	{ .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
	139	{ .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
	140	{},
	141	};
	142	MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
	143
9b3c6e85	144	static int highbank_mc_probe(struct platform_device *pdev)
a1b01edb	145	{
0ec8579e RR	146	const struct of_device_id *id;
0ec8579e RR	147	const struct hb_mc_settings *settings;
a1b01edb RH	148	struct edac_mc_layer layers[2];
	149	struct mem_ctl_info *mci;
	150	struct hb_mc_drvdata *drvdata;
	151	struct dimm_info *dimm;
	152	struct resource *r;
0ec8579e	153	void __iomem *base;
a1b01edb RH	154	u32 control;
	155	int irq;
	156	int res = 0;
	157
0ec8579e RR	158	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
	159	if (!id)
	160	return -ENODEV;
	161
a1b01edb RH	162	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	163	layers[0].size = 1;
	164	layers[0].is_virt_csrow = true;
	165	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	166	layers[1].size = 1;
	167	layers[1].is_virt_csrow = false;
	168	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
	169	sizeof(struct hb_mc_drvdata));
	170	if (!mci)
	171	return -ENOMEM;
	172
	173	mci->pdev = &pdev->dev;
	174	drvdata = mci->pvt_info;
	175	platform_set_drvdata(pdev, mci);
	176
	177	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
	178	return -ENOMEM;
	179
	180	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	181	if (!r) {
	182	dev_err(&pdev->dev, "Unable to get mem resource\n");
	183	res = -ENODEV;
	184	goto err;
	185	}
	186
	187	if (!devm_request_mem_region(&pdev->dev, r->start,
	188	resource_size(r), dev_name(&pdev->dev))) {
	189	dev_err(&pdev->dev, "Error while requesting mem region\n");
	190	res = -EBUSY;
	191	goto err;
	192	}
	193
0ec8579e RR	194	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
0ec8579e RR	195	if (!base) {
a1b01edb RH	196	dev_err(&pdev->dev, "Unable to map regs\n");
	197	res = -ENOMEM;
	198	goto err;
	199	}
	200
0ec8579e RR	201	settings = id->data;
	202	drvdata->mc_err_base = base + settings->err_offset;
	203	drvdata->mc_int_base = base + settings->int_offset;
	204
	205	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
a1b01edb RH	206	if (!control \|\| (control == 0x2)) {
	207	dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
	208	res = -ENODEV;
	209	goto err;
	210	}
	211
a1b01edb RH	212	mci->mtype_cap = MEM_FLAG_DDR3;
	213	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	214	mci->edac_cap = EDAC_FLAG_SECDED;
41ec0e8d	215	mci->mod_name = pdev->dev.driver->name;
41ec0e8d RR	216	mci->ctl_name = id->compatible;
41ec0e8d RR	217	mci->dev_name = dev_name(&pdev->dev);
a1b01edb RH	218	mci->scrub_mode = SCRUB_SW_SRC;
	219
	220	/* Only a single 4GB DIMM is supported */
	221	dimm = *mci->dimms;
	222	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
	223	dimm->grain = 8;
	224	dimm->dtype = DEV_X8;
	225	dimm->mtype = MEM_DDR3;
	226	dimm->edac_mode = EDAC_SECDED;
	227
fc7cc6b7	228	res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
a1b01edb RH	229	if (res < 0)
	230	goto err;
	231
a72b8859 RR	232	irq = platform_get_irq(pdev, 0);
	233	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
	234	0, dev_name(&pdev->dev), mci);
	235	if (res < 0) {
	236	dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
	237	goto err2;
	238	}
	239
a1b01edb RH	240	devres_close_group(&pdev->dev, NULL);
a1b01edb RH	241	return 0;
a72b8859 RR	242	err2:
a72b8859 RR	243	edac_mc_del_mc(&pdev->dev);
a1b01edb RH	244	err:
	245	devres_release_group(&pdev->dev, NULL);
	246	edac_mc_free(mci);
	247	return res;
	248	}
	249
	250	static int highbank_mc_remove(struct platform_device *pdev)
	251	{
	252	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
	253
	254	edac_mc_del_mc(&pdev->dev);
	255	edac_mc_free(mci);
	256	return 0;
	257	}
	258
a1b01edb RH	259	static struct platform_driver highbank_mc_edac_driver = {
	260	.probe = highbank_mc_probe,
	261	.remove = highbank_mc_remove,
	262	.driver = {
	263	.name = "hb_mc_edac",
	264	.of_match_table = hb_ddr_ctrl_of_match,
	265	},
	266	};
	267
	268	module_platform_driver(highbank_mc_edac_driver);
	269
	270	MODULE_LICENSE("GPL v2");
	271	MODULE_AUTHOR("Calxeda, Inc.");
	272	MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");