[linux-block.git] / drivers / edac / ghes_edac.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GHES/EDAC Linux driver
 *
 * Copyright (c) 2013 by Mauro Carvalho Chehab
 *
 * Red Hat Inc. https://www.redhat.com
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <acpi/ghes.h>
#include <linux/edac.h>
#include <linux/dmi.h>
#include "edac_module.h"
#include <ras/ras_event.h>
#include <linux/notifier.h>

#define OTHER_DETAIL_LEN	400

struct ghes_pvt {
	struct mem_ctl_info *mci;

	/* Buffers for the error handling routine */
	char other_detail[OTHER_DETAIL_LEN];
	char msg[80];
};

static refcount_t ghes_refcount = REFCOUNT_INIT(0);

/*
 * Access to ghes_pvt must be protected by ghes_lock. The spinlock
 * also provides the necessary (implicit) memory barrier for the SMP
 * case to make the pointer visible on another CPU.
 */
static struct ghes_pvt *ghes_pvt;

/*
 * This driver's representation of the system hardware, as collected
 * from DMI.
 */
static struct ghes_hw_desc {
	int num_dimms;
	struct dimm_info *dimms;
} ghes_hw;

/* GHES registration mutex */
static DEFINE_MUTEX(ghes_reg_mutex);

/*
 * Sync with other, potentially concurrent callers of
 * ghes_edac_report_mem_error(). We don't know what the
 * "inventive" firmware would do.
 */
static DEFINE_SPINLOCK(ghes_lock);

static bool system_scanned;

static struct list_head *ghes_devs;

/* Memory Device - Type 17 of SMBIOS spec */
struct memdev_dmi_entry {
	u8 type;
	u8 length;
	u16 handle;
	u16 phys_mem_array_handle;
	u16 mem_err_info_handle;
	u16 total_width;
	u16 data_width;
	u16 size;
	u8 form_factor;
	u8 device_set;
	u8 device_locator;
	u8 bank_locator;
	u8 memory_type;
	u16 type_detail;
	u16 speed;
	u8 manufacturer;
	u8 serial_number;
	u8 asset_tag;
	u8 part_number;
	u8 attributes;
	u32 extended_size;
	u16 conf_mem_clk_speed;
} __attribute__((__packed__));

static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
{
	struct dimm_info *dimm;

	mci_for_each_dimm(mci, dimm) {
		if (dimm->smbios_handle == handle)
			return dimm;
	}

	return NULL;
}

static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
{
	const char *bank = NULL, *device = NULL;

	dmi_memdev_name(handle, &bank, &device);

	/*
	 * Set to a NULL string when both bank and device are zero. In this case,
	 * the label assigned by default will be preserved.
	 */
	snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
		 (bank && *bank) ? bank : "",
		 (bank && *bank && device && *device) ? " " : "",
		 (device && *device) ? device : "");
}

static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
{
	u16 rdr_mask = BIT(7) | BIT(13);

	if (entry->size == 0xffff) {
		pr_info("Can't get DIMM%i size\n", dimm->idx);
		dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
	} else if (entry->size == 0x7fff) {
		dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
	} else {
		if (entry->size & BIT(15))
			dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
		else
			dimm->nr_pages = MiB_TO_PAGES(entry->size);
	}

	switch (entry->memory_type) {
	case 0x12:
		if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR;
		else
			dimm->mtype = MEM_DDR;
		break;
	case 0x13:
		if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR2;
		else
			dimm->mtype = MEM_DDR2;
		break;
	case 0x14:
		dimm->mtype = MEM_FB_DDR2;
		break;
	case 0x18:
		if (entry->type_detail & BIT(12))
			dimm->mtype = MEM_NVDIMM;
		else if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR3;
		else
			dimm->mtype = MEM_DDR3;
		break;
	case 0x1a:
		if (entry->type_detail & BIT(12))
			dimm->mtype = MEM_NVDIMM;
		else if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR4;
		else
			dimm->mtype = MEM_DDR4;
		break;
	default:
		if (entry->type_detail & BIT(6))
			dimm->mtype = MEM_RMBS;
		else if ((entry->type_detail & rdr_mask) == rdr_mask)
			dimm->mtype = MEM_RDR;
		else if (entry->type_detail & BIT(7))
			dimm->mtype = MEM_SDR;
		else if (entry->type_detail & BIT(9))
			dimm->mtype = MEM_EDO;
		else
			dimm->mtype = MEM_UNKNOWN;
	}

	/*
	 * Actually, we can only detect if the memory has bits for
	 * checksum or not
	 */
	if (entry->total_width == entry->data_width)
		dimm->edac_mode = EDAC_NONE;
	else
		dimm->edac_mode = EDAC_SECDED;

	dimm->dtype = DEV_UNKNOWN;
	dimm->grain = 128;		/* Likely, worse case */

	dimm_setup_label(dimm, entry->handle);

	if (dimm->nr_pages) {
		edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
			dimm->idx, edac_mem_types[dimm->mtype],
			PAGES_TO_MiB(dimm->nr_pages),
			(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
		edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
			entry->memory_type, entry->type_detail,
			entry->total_width, entry->data_width);
	}

	dimm->smbios_handle = entry->handle;
}

static void enumerate_dimms(const struct dmi_header *dh, void *arg)
{
	struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
	struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
	struct dimm_info *d;

	if (dh->type != DMI_ENTRY_MEM_DEVICE)
		return;

	/* Enlarge the array with additional 16 */
	if (!hw->num_dimms || !(hw->num_dimms % 16)) {
		struct dimm_info *new;

		new = krealloc_array(hw->dimms, hw->num_dimms + 16,
				     sizeof(struct dimm_info), GFP_KERNEL);
		if (!new) {
			WARN_ON_ONCE(1);
			return;
		}

		hw->dimms = new;
	}

	d = &hw->dimms[hw->num_dimms];
	d->idx = hw->num_dimms;

	assign_dmi_dimm_info(d, entry);

	hw->num_dimms++;
}

static void ghes_scan_system(void)
{
	if (system_scanned)
		return;

	dmi_walk(enumerate_dimms, &ghes_hw);

	system_scanned = true;
}

static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
					const char *location, unsigned int len)
{
	u32 n;

	if (!msg)
		return 0;

	n = 0;
	len -= 1;

	n += scnprintf(msg + n, len - n, "APEI location: %s ", location);

	if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
		goto out;

	n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
	n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));

out:
	msg[n] = '\0';

	return n;
}

static int ghes_edac_report_mem_error(struct notifier_block *nb,
				      unsigned long val, void *data)
{
	struct cper_sec_mem_err *mem_err = (struct cper_sec_mem_err *)data;
	struct cper_mem_err_compact cmem;
	struct edac_raw_error_desc *e;
	struct mem_ctl_info *mci;
	unsigned long sev = val;
	struct ghes_pvt *pvt;
	unsigned long flags;
	char *p;

	/*
	 * We can do the locking below because GHES defers error processing
	 * from NMI to IRQ context. Whenever that changes, we'd at least
	 * know.
	 */
	if (WARN_ON_ONCE(in_nmi()))
		return NOTIFY_OK;

	spin_lock_irqsave(&ghes_lock, flags);

	pvt = ghes_pvt;
	if (!pvt)
		goto unlock;

	mci = pvt->mci;
	e = &mci->error_desc;

	/* Cleans the error report buffer */
	memset(e, 0, sizeof (*e));
	e->error_count = 1;
	e->grain = 1;
	e->msg = pvt->msg;
	e->other_detail = pvt->other_detail;
	e->top_layer = -1;
	e->mid_layer = -1;
	e->low_layer = -1;
	*pvt->other_detail = '\0';
	*pvt->msg = '\0';

	switch (sev) {
	case GHES_SEV_CORRECTED:
		e->type = HW_EVENT_ERR_CORRECTED;
		break;
	case GHES_SEV_RECOVERABLE:
		e->type = HW_EVENT_ERR_UNCORRECTED;
		break;
	case GHES_SEV_PANIC:
		e->type = HW_EVENT_ERR_FATAL;
		break;
	default:
	case GHES_SEV_NO:
		e->type = HW_EVENT_ERR_INFO;
	}

	edac_dbg(1, "error validation_bits: 0x%08llx\n",
		 (long long)mem_err->validation_bits);

	/* Error type, mapped on e->msg */
	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
		u8 etype = mem_err->error_type;

		p = pvt->msg;
		p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
	} else {
		strcpy(pvt->msg, "unknown error");
	}

	/* Error address */
	if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
		e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
		e->offset_in_page = offset_in_page(mem_err->physical_addr);
	}

	/* Error grain */
	if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
		e->grain = ~mem_err->physical_addr_mask + 1;

	/* Memory error location, mapped on e->location */
	p = e->location;
	cper_mem_err_pack(mem_err, &cmem);
	p += cper_mem_err_location(&cmem, p);

	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
		struct dimm_info *dimm;

		p += cper_dimm_err_location(&cmem, p);
		dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
		if (dimm) {
			e->top_layer = dimm->idx;
			strcpy(e->label, dimm->label);
		}
	}
	if (p > e->location)
		*(p - 1) = '\0';

	if (!*e->label)
		strcpy(e->label, "unknown memory");

	/* All other fields are mapped on e->other_detail */
	p = pvt->other_detail;
	p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
	if (p > pvt->other_detail)
		*(p - 1) = '\0';

	edac_raw_mc_handle_error(e);

unlock:
	spin_unlock_irqrestore(&ghes_lock, flags);

	return NOTIFY_OK;
}

static struct notifier_block ghes_edac_mem_err_nb = {
	.notifier_call	= ghes_edac_report_mem_error,
	.priority	= 0,
};

static int ghes_edac_register(struct device *dev)
{
	bool fake = false;
	struct mem_ctl_info *mci;
	struct ghes_pvt *pvt;
	struct edac_mc_layer layers[1];
	unsigned long flags;
	int rc = 0;

	/* finish another registration/unregistration instance first */
	mutex_lock(&ghes_reg_mutex);

	/*
	 * We have only one logical memory controller to which all DIMMs belong.
	 */
	if (refcount_inc_not_zero(&ghes_refcount))
		goto unlock;

	ghes_scan_system();

	/* Check if we've got a bogus BIOS */
	if (!ghes_hw.num_dimms) {
		fake = true;
		ghes_hw.num_dimms = 1;
	}

	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
	layers[0].size = ghes_hw.num_dimms;
	layers[0].is_virt_csrow = true;

	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
	if (!mci) {
		pr_info("Can't allocate memory for EDAC data\n");
		rc = -ENOMEM;
		goto unlock;
	}

	pvt		= mci->pvt_info;
	pvt->mci	= mci;

	mci->pdev = dev;
	mci->mtype_cap = MEM_FLAG_EMPTY;
	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	mci->edac_cap = EDAC_FLAG_NONE;
	mci->mod_name = "ghes_edac.c";
	mci->ctl_name = "ghes_edac";
	mci->dev_name = "ghes";

	if (fake) {
		pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
		pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
		pr_info("work on such system. Use this driver with caution\n");
	}

	pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);

	if (!fake) {
		struct dimm_info *src, *dst;
		int i = 0;

		mci_for_each_dimm(mci, dst) {
			src = &ghes_hw.dimms[i];

			dst->idx	   = src->idx;
			dst->smbios_handle = src->smbios_handle;
			dst->nr_pages	   = src->nr_pages;
			dst->mtype	   = src->mtype;
			dst->edac_mode	   = src->edac_mode;
			dst->dtype	   = src->dtype;
			dst->grain	   = src->grain;

			/*
			 * If no src->label, preserve default label assigned
			 * from EDAC core.
			 */
			if (strlen(src->label))
				memcpy(dst->label, src->label, sizeof(src->label));

			i++;
		}

	} else {
		struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);

		dimm->nr_pages = 1;
		dimm->grain = 128;
		dimm->mtype = MEM_UNKNOWN;
		dimm->dtype = DEV_UNKNOWN;
		dimm->edac_mode = EDAC_SECDED;
	}

	rc = edac_mc_add_mc(mci);
	if (rc < 0) {
		pr_info("Can't register with the EDAC core\n");
		edac_mc_free(mci);
		rc = -ENODEV;
		goto unlock;
	}

	spin_lock_irqsave(&ghes_lock, flags);
	ghes_pvt = pvt;
	spin_unlock_irqrestore(&ghes_lock, flags);

	ghes_register_report_chain(&ghes_edac_mem_err_nb);

	/* only set on success */
	refcount_set(&ghes_refcount, 1);

unlock:

	/* Not needed anymore */
	kfree(ghes_hw.dimms);
	ghes_hw.dimms = NULL;

	mutex_unlock(&ghes_reg_mutex);

	return rc;
}

static void ghes_edac_unregister(struct ghes *ghes)
{
	struct mem_ctl_info *mci;
	unsigned long flags;

	mutex_lock(&ghes_reg_mutex);

	system_scanned = false;
	memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));

	if (!refcount_dec_and_test(&ghes_refcount))
		goto unlock;

	/*
	 * Wait for the irq handler being finished.
	 */
	spin_lock_irqsave(&ghes_lock, flags);
	mci = ghes_pvt ? ghes_pvt->mci : NULL;
	ghes_pvt = NULL;
	spin_unlock_irqrestore(&ghes_lock, flags);

	if (!mci)
		goto unlock;

	mci = edac_mc_del_mc(mci->pdev);
	if (mci)
		edac_mc_free(mci);

	ghes_unregister_report_chain(&ghes_edac_mem_err_nb);

unlock:
	mutex_unlock(&ghes_reg_mutex);
}

static int __init ghes_edac_init(void)
{
	struct ghes *g, *g_tmp;

	ghes_devs = ghes_get_devices();
	if (!ghes_devs)
		return -ENODEV;

	if (list_empty(ghes_devs)) {
		pr_info("GHES probing device list is empty");
		return -ENODEV;
	}

	list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
		ghes_edac_register(g->dev);
	}

	return 0;
}
module_init(ghes_edac_init);

static void __exit ghes_edac_exit(void)
{
	struct ghes *g, *g_tmp;

	list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
		ghes_edac_unregister(g);
	}
}
module_exit(ghes_edac_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Output ACPI APEI/GHES BIOS detected errors via EDAC");
Commit	Line	Data
12237550	1	// SPDX-License-Identifier: GPL-2.0-only
77c5f5d2 MCC	2	/*
	3	* GHES/EDAC Linux driver
	4	*
37e59f87	5	* Copyright (c) 2013 by Mauro Carvalho Chehab
77c5f5d2	6	*
7d4c1ea2	7	* Red Hat Inc. https://www.redhat.com
77c5f5d2 MCC	8	*/
77c5f5d2 MCC	9
d2a68566 MCC	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
d2a68566 MCC	11
77c5f5d2 MCC	12	#include <acpi/ghes.h>
77c5f5d2 MCC	13	#include <linux/edac.h>
32fa1f53	14	#include <linux/dmi.h>
78d88e8a	15	#include "edac_module.h"
8ae8f50a	16	#include <ras/ras_event.h>
8e40612f	17	#include <linux/notifier.h>
77c5f5d2	18
ed27b5df SX	19	#define OTHER_DETAIL_LEN 400
ed27b5df SX	20
b001694d	21	struct ghes_pvt {
77c5f5d2	22	struct mem_ctl_info *mci;
689c9cd8 MCC	23
689c9cd8 MCC	24	/* Buffers for the error handling routine */
ed27b5df	25	char other_detail[OTHER_DETAIL_LEN];
689c9cd8	26	char msg[80];
77c5f5d2 MCC	27	};
77c5f5d2 MCC	28
23f61b9f RR	29	static refcount_t ghes_refcount = REFCOUNT_INIT(0);
	30
	31	/*
	32	* Access to ghes_pvt must be protected by ghes_lock. The spinlock
	33	* also provides the necessary (implicit) memory barrier for the SMP
	34	* case to make the pointer visible on another CPU.
	35	*/
b001694d	36	static struct ghes_pvt *ghes_pvt;
77c5f5d2	37
b9cae277 BP	38	/*
	39	* This driver's representation of the system hardware, as collected
	40	* from DMI.
	41	*/
815fad6e	42	static struct ghes_hw_desc {
b9cae277 BP	43	int num_dimms;
	44	struct dimm_info *dimms;
	45	} ghes_hw;
	46
23f61b9f RR	47	/* GHES registration mutex */
	48	static DEFINE_MUTEX(ghes_reg_mutex);
	49
0fe5f281 BP	50	/*
	51	* Sync with other, potentially concurrent callers of
	52	* ghes_edac_report_mem_error(). We don't know what the
	53	* "inventive" firmware would do.
	54	*/
	55	static DEFINE_SPINLOCK(ghes_lock);
d2a68566	56
b972fdba SJ	57	static bool system_scanned;
b972fdba SJ	58
802e7f1d JH	59	static struct list_head *ghes_devs;
802e7f1d JH	60
32fa1f53 MCC	61	/* Memory Device - Type 17 of SMBIOS spec */
	62	struct memdev_dmi_entry {
	63	u8 type;
	64	u8 length;
	65	u16 handle;
	66	u16 phys_mem_array_handle;
	67	u16 mem_err_info_handle;
	68	u16 total_width;
	69	u16 data_width;
	70	u16 size;
	71	u8 form_factor;
	72	u8 device_set;
	73	u8 device_locator;
	74	u8 bank_locator;
	75	u8 memory_type;
	76	u16 type_detail;
	77	u16 speed;
	78	u8 manufacturer;
	79	u8 serial_number;
	80	u8 asset_tag;
	81	u8 part_number;
	82	u8 attributes;
	83	u32 extended_size;
	84	u16 conf_mem_clk_speed;
	85	} __attribute__((__packed__));
	86
cb51a371	87	static struct dimm_info find_dimm_by_handle(struct mem_ctl_info mci, u16 handle)
c798c88f	88	{
c498afaf	89	struct dimm_info *dimm;
c798c88f	90
c498afaf RR	91	mci_for_each_dimm(mci, dimm) {
c498afaf RR	92	if (dimm->smbios_handle == handle)
cb51a371	93	return dimm;
c798c88f	94	}
c498afaf	95
cb51a371 RR	96	return NULL;
	97	}
	98
	99	static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
	100	{
	101	const char bank = NULL, device = NULL;
	102
	103	dmi_memdev_name(handle, &bank, &device);
	104
5e2805d5 TK	105	/*
	106	* Set to a NULL string when both bank and device are zero. In this case,
	107	* the label assigned by default will be preserved.
	108	*/
	109	snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
	110	(bank && *bank) ? bank : "",
	111	(bank && bank && device && device) ? " " : "",
	112	(device && *device) ? device : "");
c798c88f FW	113	}
c798c88f FW	114
b9cae277	115	static void assign_dmi_dimm_info(struct dimm_info dimm, struct memdev_dmi_entry entry)
32fa1f53	116	{
b9cae277	117	u16 rdr_mask = BIT(7) \| BIT(13);
32fa1f53	118
b9cae277 BP	119	if (entry->size == 0xffff) {
	120	pr_info("Can't get DIMM%i size\n", dimm->idx);
	121	dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
	122	} else if (entry->size == 0x7fff) {
	123	dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
	124	} else {
	125	if (entry->size & BIT(15))
	126	dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
	127	else
	128	dimm->nr_pages = MiB_TO_PAGES(entry->size);
	129	}
32fa1f53	130
b9cae277 BP	131	switch (entry->memory_type) {
	132	case 0x12:
	133	if (entry->type_detail & BIT(13))
	134	dimm->mtype = MEM_RDDR;
	135	else
	136	dimm->mtype = MEM_DDR;
	137	break;
	138	case 0x13:
	139	if (entry->type_detail & BIT(13))
	140	dimm->mtype = MEM_RDDR2;
32fa1f53	141	else
b9cae277 BP	142	dimm->mtype = MEM_DDR2;
	143	break;
	144	case 0x14:
	145	dimm->mtype = MEM_FB_DDR2;
	146	break;
	147	case 0x18:
	148	if (entry->type_detail & BIT(12))
	149	dimm->mtype = MEM_NVDIMM;
	150	else if (entry->type_detail & BIT(13))
	151	dimm->mtype = MEM_RDDR3;
	152	else
	153	dimm->mtype = MEM_DDR3;
	154	break;
	155	case 0x1a:
	156	if (entry->type_detail & BIT(12))
	157	dimm->mtype = MEM_NVDIMM;
	158	else if (entry->type_detail & BIT(13))
	159	dimm->mtype = MEM_RDDR4;
	160	else
	161	dimm->mtype = MEM_DDR4;
	162	break;
	163	default:
	164	if (entry->type_detail & BIT(6))
	165	dimm->mtype = MEM_RMBS;
	166	else if ((entry->type_detail & rdr_mask) == rdr_mask)
	167	dimm->mtype = MEM_RDR;
	168	else if (entry->type_detail & BIT(7))
	169	dimm->mtype = MEM_SDR;
	170	else if (entry->type_detail & BIT(9))
	171	dimm->mtype = MEM_EDO;
	172	else
	173	dimm->mtype = MEM_UNKNOWN;
	174	}
32fa1f53	175
b9cae277 BP	176	/*
	177	* Actually, we can only detect if the memory has bits for
	178	* checksum or not
	179	*/
	180	if (entry->total_width == entry->data_width)
	181	dimm->edac_mode = EDAC_NONE;
	182	else
	183	dimm->edac_mode = EDAC_SECDED;
	184
	185	dimm->dtype = DEV_UNKNOWN;
	186	dimm->grain = 128; /* Likely, worse case */
32fa1f53	187
b9cae277	188	dimm_setup_label(dimm, entry->handle);
c798c88f	189
b9cae277 BP	190	if (dimm->nr_pages) {
	191	edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
	192	dimm->idx, edac_mem_types[dimm->mtype],
	193	PAGES_TO_MiB(dimm->nr_pages),
	194	(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
	195	edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
	196	entry->memory_type, entry->type_detail,
	197	entry->total_width, entry->data_width);
32fa1f53	198	}
b9cae277 BP	199
	200	dimm->smbios_handle = entry->handle;
	201	}
	202
	203	static void enumerate_dimms(const struct dmi_header dh, void arg)
	204	{
	205	struct memdev_dmi_entry entry = (struct memdev_dmi_entry )dh;
	206	struct ghes_hw_desc hw = (struct ghes_hw_desc )arg;
	207	struct dimm_info *d;
	208
	209	if (dh->type != DMI_ENTRY_MEM_DEVICE)
	210	return;
	211
	212	/* Enlarge the array with additional 16 */
	213	if (!hw->num_dimms \|\| !(hw->num_dimms % 16)) {
	214	struct dimm_info *new;
	215
af11be05 BG	216	new = krealloc_array(hw->dimms, hw->num_dimms + 16,
af11be05 BG	217	sizeof(struct dimm_info), GFP_KERNEL);
b9cae277 BP	218	if (!new) {
	219	WARN_ON_ONCE(1);
	220	return;
	221	}
	222
	223	hw->dimms = new;
	224	}
	225
	226	d = &hw->dimms[hw->num_dimms];
	227	d->idx = hw->num_dimms;
	228
	229	assign_dmi_dimm_info(d, entry);
	230
	231	hw->num_dimms++;
	232	}
	233
	234	static void ghes_scan_system(void)
	235	{
b972fdba	236	if (system_scanned)
b9cae277 BP	237	return;
	238
	239	dmi_walk(enumerate_dimms, &ghes_hw);
	240
b972fdba	241	system_scanned = true;
32fa1f53 MCC	242	}
32fa1f53 MCC	243
ed27b5df SX	244	static int print_mem_error_other_detail(const struct cper_sec_mem_err mem, char msg,
	245	const char *location, unsigned int len)
	246	{
	247	u32 n;
	248
	249	if (!msg)
	250	return 0;
	251
	252	n = 0;
	253	len -= 1;
	254
	255	n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
	256
	257	if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
	258	goto out;
	259
	260	n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
	261	n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
	262
	263	out:
	264	msg[n] = '\0';
	265
	266	return n;
	267	}
	268
8e40612f JH	269	static int ghes_edac_report_mem_error(struct notifier_block *nb,
8e40612f JH	270	unsigned long val, void *data)
77c5f5d2	271	{
8e40612f	272	struct cper_sec_mem_err mem_err = (struct cper_sec_mem_err )data;
ed27b5df	273	struct cper_mem_err_compact cmem;
f04c62a7 MCC	274	struct edac_raw_error_desc *e;
f04c62a7 MCC	275	struct mem_ctl_info *mci;
8e40612f	276	unsigned long sev = val;
b001694d	277	struct ghes_pvt *pvt;
0fe5f281	278	unsigned long flags;
689c9cd8	279	char *p;
f04c62a7	280
0fe5f281 BP	281	/*
	282	* We can do the locking below because GHES defers error processing
	283	* from NMI to IRQ context. Whenever that changes, we'd at least
	284	* know.
	285	*/
	286	if (WARN_ON_ONCE(in_nmi()))
8e40612f	287	return NOTIFY_OK;
0fe5f281 BP	288
	289	spin_lock_irqsave(&ghes_lock, flags);
	290
23f61b9f RR	291	pvt = ghes_pvt;
	292	if (!pvt)
	293	goto unlock;
	294
f04c62a7 MCC	295	mci = pvt->mci;
	296	e = &mci->error_desc;
	297
	298	/* Cleans the error report buffer */
	299	memset(e, 0, sizeof (*e));
	300	e->error_count = 1;
7088e29e	301	e->grain = 1;
689c9cd8 MCC	302	e->msg = pvt->msg;
	303	e->other_detail = pvt->other_detail;
	304	e->top_layer = -1;
	305	e->mid_layer = -1;
	306	e->low_layer = -1;
	307	*pvt->other_detail = '\0';
	308	*pvt->msg = '\0';
f04c62a7 MCC	309
	310	switch (sev) {
	311	case GHES_SEV_CORRECTED:
672ef0e5	312	e->type = HW_EVENT_ERR_CORRECTED;
f04c62a7 MCC	313	break;
f04c62a7 MCC	314	case GHES_SEV_RECOVERABLE:
672ef0e5	315	e->type = HW_EVENT_ERR_UNCORRECTED;
f04c62a7 MCC	316	break;
f04c62a7 MCC	317	case GHES_SEV_PANIC:
672ef0e5	318	e->type = HW_EVENT_ERR_FATAL;
f04c62a7 MCC	319	break;
	320	default:
	321	case GHES_SEV_NO:
672ef0e5	322	e->type = HW_EVENT_ERR_INFO;
f04c62a7 MCC	323	}
f04c62a7 MCC	324
689c9cd8 MCC	325	edac_dbg(1, "error validation_bits: 0x%08llx\n",
	326	(long long)mem_err->validation_bits);
	327
	328	/* Error type, mapped on e->msg */
	329	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
ed27b5df SX	330	u8 etype = mem_err->error_type;
ed27b5df SX	331
689c9cd8	332	p = pvt->msg;
ed27b5df	333	p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
689c9cd8 MCC	334	} else {
	335	strcpy(pvt->msg, "unknown error");
	336	}
	337
	338	/* Error address */
147de147	339	if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
7c104931 RR	340	e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
7c104931 RR	341	e->offset_in_page = offset_in_page(mem_err->physical_addr);
689c9cd8 MCC	342	}
	343
	344	/* Error grain */
147de147	345	if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
7088e29e	346	e->grain = ~mem_err->physical_addr_mask + 1;
689c9cd8 MCC	347
	348	/* Memory error location, mapped on e->location */
	349	p = e->location;
ed27b5df SX	350	cper_mem_err_pack(mem_err, &cmem);
	351	p += cper_mem_err_location(&cmem, p);
	352
56507694	353	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
cb51a371	354	struct dimm_info *dimm;
c798c88f	355
ed27b5df	356	p += cper_dimm_err_location(&cmem, p);
cb51a371 RR	357	dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
	358	if (dimm) {
	359	e->top_layer = dimm->idx;
	360	strcpy(e->label, dimm->label);
	361	}
56507694	362	}
689c9cd8 MCC	363	if (p > e->location)
	364	*(p - 1) = '\0';
	365
cb51a371 RR	366	if (!*e->label)
	367	strcpy(e->label, "unknown memory");
	368
689c9cd8 MCC	369	/* All other fields are mapped on e->other_detail */
689c9cd8 MCC	370	p = pvt->other_detail;
ed27b5df	371	p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
689c9cd8 MCC	372	if (p > pvt->other_detail)
689c9cd8 MCC	373	*(p - 1) = '\0';
f04c62a7	374
91b327f6	375	edac_raw_mc_handle_error(e);
23f61b9f RR	376
23f61b9f RR	377	unlock:
0fe5f281	378	spin_unlock_irqrestore(&ghes_lock, flags);
8e40612f JH	379
8e40612f JH	380	return NOTIFY_OK;
77c5f5d2	381	}
77c5f5d2	382
8e40612f JH	383	static struct notifier_block ghes_edac_mem_err_nb = {
	384	.notifier_call = ghes_edac_report_mem_error,
	385	.priority = 0,
	386	};
	387
802e7f1d	388	static int ghes_edac_register(struct device *dev)
77c5f5d2	389	{
32fa1f53	390	bool fake = false;
77c5f5d2	391	struct mem_ctl_info *mci;
b001694d	392	struct ghes_pvt *pvt;
77c5f5d2	393	struct edac_mc_layer layers[1];
23f61b9f	394	unsigned long flags;
b9cae277	395	int rc = 0;
5deed6b6	396
23f61b9f RR	397	/* finish another registration/unregistration instance first */
	398	mutex_lock(&ghes_reg_mutex);
	399
0fe5f281 BP	400	/*
	401	* We have only one logical memory controller to which all DIMMs belong.
	402	*/
23f61b9f RR	403	if (refcount_inc_not_zero(&ghes_refcount))
23f61b9f RR	404	goto unlock;
0fe5f281	405
b9cae277	406	ghes_scan_system();
32fa1f53 MCC	407
32fa1f53 MCC	408	/* Check if we've got a bogus BIOS */
b9cae277	409	if (!ghes_hw.num_dimms) {
32fa1f53	410	fake = true;
b9cae277	411	ghes_hw.num_dimms = 1;
32fa1f53	412	}
77c5f5d2 MCC	413
77c5f5d2 MCC	414	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
b9cae277	415	layers[0].size = ghes_hw.num_dimms;
77c5f5d2 MCC	416	layers[0].is_virt_csrow = true;
77c5f5d2 MCC	417
b001694d	418	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
77c5f5d2	419	if (!mci) {
d2a68566	420	pr_info("Can't allocate memory for EDAC data\n");
23f61b9f RR	421	rc = -ENOMEM;
23f61b9f RR	422	goto unlock;
77c5f5d2 MCC	423	}
77c5f5d2 MCC	424
23f61b9f	425	pvt = mci->pvt_info;
23f61b9f	426	pvt->mci = mci;
77c5f5d2	427
0fe5f281	428	mci->pdev = dev;
77c5f5d2 MCC	429	mci->mtype_cap = MEM_FLAG_EMPTY;
	430	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	431	mci->edac_cap = EDAC_FLAG_NONE;
	432	mci->mod_name = "ghes_edac.c";
77c5f5d2 MCC	433	mci->ctl_name = "ghes_edac";
	434	mci->dev_name = "ghes";
	435
5deed6b6 TK	436	if (fake) {
	437	pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
	438	pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
	439	pr_info("work on such system. Use this driver with caution\n");
d2a68566 MCC	440	}
d2a68566 MCC	441
9057a3f7 JH	442	pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
9057a3f7 JH	443
32fa1f53	444	if (!fake) {
b9cae277 BP	445	struct dimm_info src, dst;
	446	int i = 0;
	447
	448	mci_for_each_dimm(mci, dst) {
	449	src = &ghes_hw.dimms[i];
	450
	451	dst->idx = src->idx;
	452	dst->smbios_handle = src->smbios_handle;
	453	dst->nr_pages = src->nr_pages;
	454	dst->mtype = src->mtype;
	455	dst->edac_mode = src->edac_mode;
	456	dst->dtype = src->dtype;
	457	dst->grain = src->grain;
	458
	459	/*
	460	* If no src->label, preserve default label assigned
	461	* from EDAC core.
	462	*/
	463	if (strlen(src->label))
	464	memcpy(dst->label, src->label, sizeof(src->label));
	465
	466	i++;
	467	}
	468
32fa1f53	469	} else {
bc9ad9e4	470	struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
77c5f5d2	471
d2a68566	472	dimm->nr_pages = 1;
32fa1f53 MCC	473	dimm->grain = 128;
	474	dimm->mtype = MEM_UNKNOWN;
	475	dimm->dtype = DEV_UNKNOWN;
	476	dimm->edac_mode = EDAC_SECDED;
	477	}
77c5f5d2 MCC	478
	479	rc = edac_mc_add_mc(mci);
	480	if (rc < 0) {
b9cae277	481	pr_info("Can't register with the EDAC core\n");
77c5f5d2	482	edac_mc_free(mci);
23f61b9f RR	483	rc = -ENODEV;
23f61b9f RR	484	goto unlock;
77c5f5d2	485	}
23f61b9f RR	486
	487	spin_lock_irqsave(&ghes_lock, flags);
	488	ghes_pvt = pvt;
	489	spin_unlock_irqrestore(&ghes_lock, flags);
	490
8e40612f JH	491	ghes_register_report_chain(&ghes_edac_mem_err_nb);
8e40612f JH	492
16214bd9 RR	493	/* only set on success */
16214bd9 RR	494	refcount_set(&ghes_refcount, 1);
23f61b9f RR	495
23f61b9f RR	496	unlock:
b9cae277 BP	497
	498	/* Not needed anymore */
	499	kfree(ghes_hw.dimms);
	500	ghes_hw.dimms = NULL;
	501
23f61b9f RR	502	mutex_unlock(&ghes_reg_mutex);
	503
	504	return rc;
77c5f5d2	505	}
77c5f5d2	506
802e7f1d	507	static void ghes_edac_unregister(struct ghes *ghes)
77c5f5d2 MCC	508	{
77c5f5d2 MCC	509	struct mem_ctl_info *mci;
23f61b9f	510	unsigned long flags;
0fe5f281	511
23f61b9f	512	mutex_lock(&ghes_reg_mutex);
a66bdf5d	513
b972fdba	514	system_scanned = false;
cd8100f1	515	memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
b972fdba	516
23f61b9f RR	517	if (!refcount_dec_and_test(&ghes_refcount))
23f61b9f RR	518	goto unlock;
1e72e673	519
23f61b9f RR	520	/*
	521	* Wait for the irq handler being finished.
	522	*/
	523	spin_lock_irqsave(&ghes_lock, flags);
	524	mci = ghes_pvt ? ghes_pvt->mci : NULL;
1e72e673	525	ghes_pvt = NULL;
23f61b9f RR	526	spin_unlock_irqrestore(&ghes_lock, flags);
	527
	528	if (!mci)
	529	goto unlock;
	530
	531	mci = edac_mc_del_mc(mci->pdev);
	532	if (mci)
	533	edac_mc_free(mci);
	534
8e40612f JH	535	ghes_unregister_report_chain(&ghes_edac_mem_err_nb);
8e40612f JH	536
23f61b9f RR	537	unlock:
23f61b9f RR	538	mutex_unlock(&ghes_reg_mutex);
77c5f5d2	539	}
802e7f1d JH	540
	541	static int __init ghes_edac_init(void)
	542	{
	543	struct ghes g, g_tmp;
	544
	545	ghes_devs = ghes_get_devices();
	546	if (!ghes_devs)
	547	return -ENODEV;
	548
	549	if (list_empty(ghes_devs)) {
	550	pr_info("GHES probing device list is empty");
	551	return -ENODEV;
	552	}
	553
	554	list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
	555	ghes_edac_register(g->dev);
	556	}
	557
	558	return 0;
	559	}
	560	module_init(ghes_edac_init);
	561
	562	static void __exit ghes_edac_exit(void)
	563	{
	564	struct ghes g, g_tmp;
	565
	566	list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
	567	ghes_edac_unregister(g);
	568	}
	569	}
	570	module_exit(ghes_edac_exit);
	571
	572	MODULE_LICENSE("GPL");
	573	MODULE_DESCRIPTION("Output ACPI APEI/GHES BIOS detected errors via EDAC");