[linux-2.6-block.git] / drivers / edac / ghes_edac.c

/*
 * GHES/EDAC Linux driver
 *
 * This file may be distributed under the terms of the GNU General Public
 * License version 2.
 *
 * Copyright (c) 2013 by Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <acpi/ghes.h>
#include <linux/edac.h>
#include <linux/dmi.h>
#include "edac_core.h"
#include <ras/ras_event.h>

#define GHES_EDAC_REVISION " Ver: 1.0.0"

struct ghes_edac_pvt {
	struct list_head list;
	struct ghes *ghes;
	struct mem_ctl_info *mci;

	/* Buffers for the error handling routine */
	char detail_location[240];
	char other_detail[160];
	char msg[80];
};

static LIST_HEAD(ghes_reglist);
static DEFINE_MUTEX(ghes_edac_lock);
static int ghes_edac_mc_num;


/* Memory Device - Type 17 of SMBIOS spec */
struct memdev_dmi_entry {
	u8 type;
	u8 length;
	u16 handle;
	u16 phys_mem_array_handle;
	u16 mem_err_info_handle;
	u16 total_width;
	u16 data_width;
	u16 size;
	u8 form_factor;
	u8 device_set;
	u8 device_locator;
	u8 bank_locator;
	u8 memory_type;
	u16 type_detail;
	u16 speed;
	u8 manufacturer;
	u8 serial_number;
	u8 asset_tag;
	u8 part_number;
	u8 attributes;
	u32 extended_size;
	u16 conf_mem_clk_speed;
} __attribute__((__packed__));

struct ghes_edac_dimm_fill {
	struct mem_ctl_info *mci;
	unsigned count;
};

char *memory_type[] = {
	[MEM_EMPTY] = "EMPTY",
	[MEM_RESERVED] = "RESERVED",
	[MEM_UNKNOWN] = "UNKNOWN",
	[MEM_FPM] = "FPM",
	[MEM_EDO] = "EDO",
	[MEM_BEDO] = "BEDO",
	[MEM_SDR] = "SDR",
	[MEM_RDR] = "RDR",
	[MEM_DDR] = "DDR",
	[MEM_RDDR] = "RDDR",
	[MEM_RMBS] = "RMBS",
	[MEM_DDR2] = "DDR2",
	[MEM_FB_DDR2] = "FB_DDR2",
	[MEM_RDDR2] = "RDDR2",
	[MEM_XDR] = "XDR",
	[MEM_DDR3] = "DDR3",
	[MEM_RDDR3] = "RDDR3",
};

static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
{
	int *num_dimm = arg;

	if (dh->type == DMI_ENTRY_MEM_DEVICE)
		(*num_dimm)++;
}

static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
{
	struct ghes_edac_dimm_fill *dimm_fill = arg;
	struct mem_ctl_info *mci = dimm_fill->mci;

	if (dh->type == DMI_ENTRY_MEM_DEVICE) {
		struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
		struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
						       mci->n_layers,
						       dimm_fill->count, 0, 0);

		if (entry->size == 0xffff) {
			pr_info("Can't get DIMM%i size\n",
				dimm_fill->count);
			dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
		} else if (entry->size == 0x7fff) {
			dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
		} else {
			if (entry->size & 1 << 15)
				dimm->nr_pages = MiB_TO_PAGES((entry->size &
							       0x7fff) << 10);
			else
				dimm->nr_pages = MiB_TO_PAGES(entry->size);
		}

		switch (entry->memory_type) {
		case 0x12:
			if (entry->type_detail & 1 << 13)
				dimm->mtype = MEM_RDDR;
			else
				dimm->mtype = MEM_DDR;
			break;
		case 0x13:
			if (entry->type_detail & 1 << 13)
				dimm->mtype = MEM_RDDR2;
			else
				dimm->mtype = MEM_DDR2;
			break;
		case 0x14:
			dimm->mtype = MEM_FB_DDR2;
			break;
		case 0x18:
			if (entry->type_detail & 1 << 13)
				dimm->mtype = MEM_RDDR3;
			else
				dimm->mtype = MEM_DDR3;
			break;
		default:
			if (entry->type_detail & 1 << 6)
				dimm->mtype = MEM_RMBS;
			else if ((entry->type_detail & ((1 << 7) | (1 << 13)))
				 == ((1 << 7) | (1 << 13)))
				dimm->mtype = MEM_RDR;
			else if (entry->type_detail & 1 << 7)
				dimm->mtype = MEM_SDR;
			else if (entry->type_detail & 1 << 9)
				dimm->mtype = MEM_EDO;
			else
				dimm->mtype = MEM_UNKNOWN;
		}

		/*
		 * Actually, we can only detect if the memory has bits for
		 * checksum or not
		 */
		if (entry->total_width == entry->data_width)
			dimm->edac_mode = EDAC_NONE;
		else
			dimm->edac_mode = EDAC_SECDED;

		dimm->dtype = DEV_UNKNOWN;
		dimm->grain = 128;		/* Likely, worse case */

		/*
		 * FIXME: It shouldn't be hard to also fill the DIMM labels
		 */

		if (dimm->nr_pages) {
			edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
				dimm_fill->count, memory_type[dimm->mtype],
				PAGES_TO_MiB(dimm->nr_pages),
				(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
			edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
				entry->memory_type, entry->type_detail,
				entry->total_width, entry->data_width);
		}

		dimm_fill->count++;
	}
}

void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
				struct cper_sec_mem_err *mem_err)
{
	enum hw_event_mc_err_type type;
	struct edac_raw_error_desc *e;
	struct mem_ctl_info *mci;
	struct ghes_edac_pvt *pvt = NULL;
	char *p;
	u8 grain_bits;

	list_for_each_entry(pvt, &ghes_reglist, list) {
		if (ghes == pvt->ghes)
			break;
	}
	if (!pvt) {
		pr_err("Internal error: Can't find EDAC structure\n");
		return;
	}
	mci = pvt->mci;
	e = &mci->error_desc;

	/* Cleans the error report buffer */
	memset(e, 0, sizeof (*e));
	e->error_count = 1;
	strcpy(e->label, "unknown label");
	e->msg = pvt->msg;
	e->other_detail = pvt->other_detail;
	e->top_layer = -1;
	e->mid_layer = -1;
	e->low_layer = -1;
	*pvt->other_detail = '\0';
	*pvt->msg = '\0';

	switch (sev) {
	case GHES_SEV_CORRECTED:
		type = HW_EVENT_ERR_CORRECTED;
		break;
	case GHES_SEV_RECOVERABLE:
		type = HW_EVENT_ERR_UNCORRECTED;
		break;
	case GHES_SEV_PANIC:
		type = HW_EVENT_ERR_FATAL;
		break;
	default:
	case GHES_SEV_NO:
		type = HW_EVENT_ERR_INFO;
	}

	edac_dbg(1, "error validation_bits: 0x%08llx\n",
		 (long long)mem_err->validation_bits);

	/* Error type, mapped on e->msg */
	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
		p = pvt->msg;
		switch (mem_err->error_type) {
		case 0:
			p += sprintf(p, "Unknown");
			break;
		case 1:
			p += sprintf(p, "No error");
			break;
		case 2:
			p += sprintf(p, "Single-bit ECC");
			break;
		case 3:
			p += sprintf(p, "Multi-bit ECC");
			break;
		case 4:
			p += sprintf(p, "Single-symbol ChipKill ECC");
			break;
		case 5:
			p += sprintf(p, "Multi-symbol ChipKill ECC");
			break;
		case 6:
			p += sprintf(p, "Master abort");
			break;
		case 7:
			p += sprintf(p, "Target abort");
			break;
		case 8:
			p += sprintf(p, "Parity Error");
			break;
		case 9:
			p += sprintf(p, "Watchdog timeout");
			break;
		case 10:
			p += sprintf(p, "Invalid address");
			break;
		case 11:
			p += sprintf(p, "Mirror Broken");
			break;
		case 12:
			p += sprintf(p, "Memory Sparing");
			break;
		case 13:
			p += sprintf(p, "Scrub corrected error");
			break;
		case 14:
			p += sprintf(p, "Scrub uncorrected error");
			break;
		case 15:
			p += sprintf(p, "Physical Memory Map-out event");
			break;
		default:
			p += sprintf(p, "reserved error (%d)",
				     mem_err->error_type);
		}
	} else {
		strcpy(pvt->msg, "unknown error");
	}

	/* Error address */
	if (mem_err->validation_bits & CPER_MEM_VALID_PHYSICAL_ADDRESS) {
		e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
		e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
	}

	/* Error grain */
	if (mem_err->validation_bits & CPER_MEM_VALID_PHYSICAL_ADDRESS_MASK) {
		e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
	}

	/* Memory error location, mapped on e->location */
	p = e->location;
	if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
		p += sprintf(p, "node:%d ", mem_err->node);
	if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
		p += sprintf(p, "card:%d ", mem_err->card);
	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
		p += sprintf(p, "module:%d ", mem_err->module);
	if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
		p += sprintf(p, "bank:%d ", mem_err->bank);
	if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
		p += sprintf(p, "row:%d ", mem_err->row);
	if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
		p += sprintf(p, "col:%d ", mem_err->column);
	if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
		p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
	if (p > e->location)
		*(p - 1) = '\0';

	/* All other fields are mapped on e->other_detail */
	p = pvt->other_detail;
	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
		u64 status = mem_err->error_status;

		p += sprintf(p, "status(0x%016llx): ", (long long)status);
		switch ((status >> 8) & 0xff) {
		case 1:
			p += sprintf(p, "Error detected internal to the component ");
			break;
		case 16:
			p += sprintf(p, "Error detected in the bus ");
			break;
		case 4:
			p += sprintf(p, "Storage error in DRAM memory ");
			break;
		case 5:
			p += sprintf(p, "Storage error in TLB ");
			break;
		case 6:
			p += sprintf(p, "Storage error in cache ");
			break;
		case 7:
			p += sprintf(p, "Error in one or more functional units ");
			break;
		case 8:
			p += sprintf(p, "component failed self test ");
			break;
		case 9:
			p += sprintf(p, "Overflow or undervalue of internal queue ");
			break;
		case 17:
			p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
			break;
		case 18:
			p += sprintf(p, "Improper access error ");
			break;
		case 19:
			p += sprintf(p, "Access to a memory address which is not mapped to any component ");
			break;
		case 20:
			p += sprintf(p, "Loss of Lockstep ");
			break;
		case 21:
			p += sprintf(p, "Response not associated with a request ");
			break;
		case 22:
			p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
			break;
		case 23:
			p += sprintf(p, "Detection of a PATH_ERROR ");
			break;
		case 25:
			p += sprintf(p, "Bus operation timeout ");
			break;
		case 26:
			p += sprintf(p, "A read was issued to data that has been poisoned ");
			break;
		default:
			p += sprintf(p, "reserved ");
			break;
		}
	}
	if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
		p += sprintf(p, "requestorID: 0x%016llx ",
			     (long long)mem_err->requestor_id);
	if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
		p += sprintf(p, "responderID: 0x%016llx ",
			     (long long)mem_err->responder_id);
	if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
		p += sprintf(p, "targetID: 0x%016llx ",
			     (long long)mem_err->responder_id);
	if (p > pvt->other_detail)
		*(p - 1) = '\0';

	/* Generate the trace event */
	grain_bits = fls_long(e->grain);
	sprintf(pvt->detail_location, "APEI location: %s %s",
		e->location, e->other_detail);
	trace_mc_event(type, e->msg, e->label, e->error_count,
		       mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
		       PAGES_TO_MiB(e->page_frame_number) | e->offset_in_page,
		       grain_bits, e->syndrome, pvt->detail_location);

	/* Report the error via EDAC API */
	edac_raw_mc_handle_error(type, mci, e);
}
EXPORT_SYMBOL_GPL(ghes_edac_report_mem_error);

int ghes_edac_register(struct ghes *ghes, struct device *dev)
{
	bool fake = false;
	int rc, num_dimm = 0;
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[1];
	struct ghes_edac_pvt *pvt;
	struct ghes_edac_dimm_fill dimm_fill;

	/* Get the number of DIMMs */
	dmi_walk(ghes_edac_count_dimms, &num_dimm);

	/* Check if we've got a bogus BIOS */
	if (num_dimm == 0) {
		fake = true;
		num_dimm = 1;
	}

	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
	layers[0].size = num_dimm;
	layers[0].is_virt_csrow = true;

	/*
	 * We need to serialize edac_mc_alloc() and edac_mc_add_mc(),
	 * to avoid duplicated memory controller numbers
	 */
	mutex_lock(&ghes_edac_lock);
	mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,
			    sizeof(*pvt));
	if (!mci) {
		pr_info("Can't allocate memory for EDAC data\n");
		mutex_unlock(&ghes_edac_lock);
		return -ENOMEM;
	}

	pvt = mci->pvt_info;
	memset(pvt, 0, sizeof(*pvt));
	list_add_tail(&pvt->list, &ghes_reglist);
	pvt->ghes = ghes;
	pvt->mci  = mci;
	mci->pdev = dev;

	mci->mtype_cap = MEM_FLAG_EMPTY;
	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	mci->edac_cap = EDAC_FLAG_NONE;
	mci->mod_name = "ghes_edac.c";
	mci->mod_ver = GHES_EDAC_REVISION;
	mci->ctl_name = "ghes_edac";
	mci->dev_name = "ghes";

	if (!ghes_edac_mc_num) {
		if (!fake) {
			pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
			pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
			pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
			pr_info("If you find incorrect reports, please contact your hardware vendor\n");
			pr_info("to correct its BIOS.\n");
			pr_info("This system has %d DIMM sockets.\n",
				num_dimm);
		} else {
			pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
			pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
			pr_info("work on such system. Use this driver with caution\n");
		}
	}

	if (!fake) {
		/*
		 * Fill DIMM info from DMI for the memory controller #0
		 *
		 * Keep it in blank for the other memory controllers, as
		 * there's no reliable way to properly credit each DIMM to
		 * the memory controller, as different BIOSes fill the
		 * DMI bank location fields on different ways
		 */
		if (!ghes_edac_mc_num) {
			dimm_fill.count = 0;
			dimm_fill.mci = mci;
			dmi_walk(ghes_edac_dmidecode, &dimm_fill);
		}
	} else {
		struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
						       mci->n_layers, 0, 0, 0);

		dimm->nr_pages = 1;
		dimm->grain = 128;
		dimm->mtype = MEM_UNKNOWN;
		dimm->dtype = DEV_UNKNOWN;
		dimm->edac_mode = EDAC_SECDED;
	}

	rc = edac_mc_add_mc(mci);
	if (rc < 0) {
		pr_info("Can't register at EDAC core\n");
		edac_mc_free(mci);
		mutex_unlock(&ghes_edac_lock);
		return -ENODEV;
	}

	ghes_edac_mc_num++;
	mutex_unlock(&ghes_edac_lock);
	return 0;
}
EXPORT_SYMBOL_GPL(ghes_edac_register);

void ghes_edac_unregister(struct ghes *ghes)
{
	struct mem_ctl_info *mci;
	struct ghes_edac_pvt *pvt, *tmp;

	list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) {
		if (ghes == pvt->ghes) {
			mci = pvt->mci;
			edac_mc_del_mc(mci->pdev);
			edac_mc_free(mci);
			list_del(&pvt->list);
		}
	}
}
EXPORT_SYMBOL_GPL(ghes_edac_unregister);
Commit	Line	Data
77c5f5d2 MCC	1	/*
	2	* GHES/EDAC Linux driver
	3	*
	4	* This file may be distributed under the terms of the GNU General Public
	5	* License version 2.
	6	*
	7	* Copyright (c) 2013 by Mauro Carvalho Chehab <mchehab@redhat.com>
	8	*
	9	* Red Hat Inc. http://www.redhat.com
	10	*/
	11
d2a68566 MCC	12	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
d2a68566 MCC	13
77c5f5d2 MCC	14	#include <acpi/ghes.h>
77c5f5d2 MCC	15	#include <linux/edac.h>
32fa1f53	16	#include <linux/dmi.h>
77c5f5d2	17	#include "edac_core.h"
8ae8f50a	18	#include <ras/ras_event.h>
77c5f5d2	19
77c5f5d2 MCC	20	#define GHES_EDAC_REVISION " Ver: 1.0.0"
	21
	22	struct ghes_edac_pvt {
	23	struct list_head list;
	24	struct ghes *ghes;
	25	struct mem_ctl_info *mci;
689c9cd8 MCC	26
689c9cd8 MCC	27	/* Buffers for the error handling routine */
8ae8f50a	28	char detail_location[240];
689c9cd8 MCC	29	char other_detail[160];
689c9cd8 MCC	30	char msg[80];
77c5f5d2 MCC	31	};
	32
	33	static LIST_HEAD(ghes_reglist);
	34	static DEFINE_MUTEX(ghes_edac_lock);
	35	static int ghes_edac_mc_num;
	36
d2a68566	37
32fa1f53 MCC	38	/* Memory Device - Type 17 of SMBIOS spec */
	39	struct memdev_dmi_entry {
	40	u8 type;
	41	u8 length;
	42	u16 handle;
	43	u16 phys_mem_array_handle;
	44	u16 mem_err_info_handle;
	45	u16 total_width;
	46	u16 data_width;
	47	u16 size;
	48	u8 form_factor;
	49	u8 device_set;
	50	u8 device_locator;
	51	u8 bank_locator;
	52	u8 memory_type;
	53	u16 type_detail;
	54	u16 speed;
	55	u8 manufacturer;
	56	u8 serial_number;
	57	u8 asset_tag;
	58	u8 part_number;
	59	u8 attributes;
	60	u32 extended_size;
	61	u16 conf_mem_clk_speed;
	62	} __attribute__((__packed__));
	63
	64	struct ghes_edac_dimm_fill {
	65	struct mem_ctl_info *mci;
	66	unsigned count;
	67	};
	68
	69	char *memory_type[] = {
	70	[MEM_EMPTY] = "EMPTY",
	71	[MEM_RESERVED] = "RESERVED",
	72	[MEM_UNKNOWN] = "UNKNOWN",
	73	[MEM_FPM] = "FPM",
	74	[MEM_EDO] = "EDO",
	75	[MEM_BEDO] = "BEDO",
	76	[MEM_SDR] = "SDR",
	77	[MEM_RDR] = "RDR",
	78	[MEM_DDR] = "DDR",
	79	[MEM_RDDR] = "RDDR",
	80	[MEM_RMBS] = "RMBS",
	81	[MEM_DDR2] = "DDR2",
	82	[MEM_FB_DDR2] = "FB_DDR2",
	83	[MEM_RDDR2] = "RDDR2",
	84	[MEM_XDR] = "XDR",
	85	[MEM_DDR3] = "DDR3",
	86	[MEM_RDDR3] = "RDDR3",
	87	};
	88
	89	static void ghes_edac_count_dimms(const struct dmi_header dh, void arg)
	90	{
	91	int *num_dimm = arg;
	92
	93	if (dh->type == DMI_ENTRY_MEM_DEVICE)
	94	(*num_dimm)++;
	95	}
	96
	97	static void ghes_edac_dmidecode(const struct dmi_header dh, void arg)
	98	{
	99	struct ghes_edac_dimm_fill *dimm_fill = arg;
	100	struct mem_ctl_info *mci = dimm_fill->mci;
	101
102	if (dh->type == DMI_ENTRY_MEM_DEVICE) {
103	struct memdev_dmi_entry entry = (struct memdev_dmi_entry )dh;
104	struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
105	mci->n_layers,
106	dimm_fill->count, 0, 0);
107
108	if (entry->size == 0xffff) {
d2a68566 MCC	109	pr_info("Can't get DIMM%i size\n",
d2a68566 MCC	110	dimm_fill->count);
32fa1f53 MCC	111	dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
	112	} else if (entry->size == 0x7fff) {
	113	dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
	114	} else {
	115	if (entry->size & 1 << 15)
	116	dimm->nr_pages = MiB_TO_PAGES((entry->size &
	117	0x7fff) << 10);
	118	else
	119	dimm->nr_pages = MiB_TO_PAGES(entry->size);
	120	}
	121
	122	switch (entry->memory_type) {
	123	case 0x12:
	124	if (entry->type_detail & 1 << 13)
	125	dimm->mtype = MEM_RDDR;
	126	else
	127	dimm->mtype = MEM_DDR;
	128	break;
	129	case 0x13:
	130	if (entry->type_detail & 1 << 13)
	131	dimm->mtype = MEM_RDDR2;
	132	else
	133	dimm->mtype = MEM_DDR2;
	134	break;
	135	case 0x14:
	136	dimm->mtype = MEM_FB_DDR2;
	137	break;
	138	case 0x18:
	139	if (entry->type_detail & 1 << 13)
	140	dimm->mtype = MEM_RDDR3;
	141	else
	142	dimm->mtype = MEM_DDR3;
	143	break;
	144	default:
	145	if (entry->type_detail & 1 << 6)
	146	dimm->mtype = MEM_RMBS;
	147	else if ((entry->type_detail & ((1 << 7) \| (1 << 13)))
	148	== ((1 << 7) \| (1 << 13)))
	149	dimm->mtype = MEM_RDR;
	150	else if (entry->type_detail & 1 << 7)
	151	dimm->mtype = MEM_SDR;
	152	else if (entry->type_detail & 1 << 9)
	153	dimm->mtype = MEM_EDO;
	154	else
	155	dimm->mtype = MEM_UNKNOWN;
	156	}
	157
	158	/*
	159	* Actually, we can only detect if the memory has bits for
	160	* checksum or not
	161	*/
	162	if (entry->total_width == entry->data_width)
	163	dimm->edac_mode = EDAC_NONE;
	164	else
	165	dimm->edac_mode = EDAC_SECDED;
	166
	167	dimm->dtype = DEV_UNKNOWN;
	168	dimm->grain = 128; /* Likely, worse case */
	169
	170	/*
	171	* FIXME: It shouldn't be hard to also fill the DIMM labels
	172	*/
	173
	174	if (dimm->nr_pages) {
d2a68566	175	edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
32fa1f53 MCC	176	dimm_fill->count, memory_type[dimm->mtype],
	177	PAGES_TO_MiB(dimm->nr_pages),
	178	(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
d2a68566	179	edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
32fa1f53 MCC	180	entry->memory_type, entry->type_detail,
	181	entry->total_width, entry->data_width);
	182	}
	183
	184	dimm_fill->count++;
	185	}
	186	}
	187
77c5f5d2	188	void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
f04c62a7	189	struct cper_sec_mem_err *mem_err)
77c5f5d2	190	{
f04c62a7 MCC	191	enum hw_event_mc_err_type type;
	192	struct edac_raw_error_desc *e;
	193	struct mem_ctl_info *mci;
	194	struct ghes_edac_pvt *pvt = NULL;
689c9cd8	195	char *p;
8ae8f50a	196	u8 grain_bits;
f04c62a7 MCC	197
	198	list_for_each_entry(pvt, &ghes_reglist, list) {
	199	if (ghes == pvt->ghes)
	200	break;
	201	}
	202	if (!pvt) {
	203	pr_err("Internal error: Can't find EDAC structure\n");
	204	return;
	205	}
	206	mci = pvt->mci;
	207	e = &mci->error_desc;
	208
	209	/* Cleans the error report buffer */
	210	memset(e, 0, sizeof (*e));
	211	e->error_count = 1;
689c9cd8 MCC	212	strcpy(e->label, "unknown label");
	213	e->msg = pvt->msg;
	214	e->other_detail = pvt->other_detail;
	215	e->top_layer = -1;
	216	e->mid_layer = -1;
	217	e->low_layer = -1;
	218	*pvt->other_detail = '\0';
	219	*pvt->msg = '\0';
f04c62a7 MCC	220
	221	switch (sev) {
	222	case GHES_SEV_CORRECTED:
	223	type = HW_EVENT_ERR_CORRECTED;
	224	break;
	225	case GHES_SEV_RECOVERABLE:
	226	type = HW_EVENT_ERR_UNCORRECTED;
	227	break;
	228	case GHES_SEV_PANIC:
	229	type = HW_EVENT_ERR_FATAL;
	230	break;
	231	default:
	232	case GHES_SEV_NO:
	233	type = HW_EVENT_ERR_INFO;
	234	}
	235
689c9cd8 MCC	236	edac_dbg(1, "error validation_bits: 0x%08llx\n",
	237	(long long)mem_err->validation_bits);
	238
	239	/* Error type, mapped on e->msg */
	240	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
	241	p = pvt->msg;
	242	switch (mem_err->error_type) {
	243	case 0:
	244	p += sprintf(p, "Unknown");
	245	break;
	246	case 1:
	247	p += sprintf(p, "No error");
	248	break;
	249	case 2:
	250	p += sprintf(p, "Single-bit ECC");
	251	break;
	252	case 3:
	253	p += sprintf(p, "Multi-bit ECC");
	254	break;
	255	case 4:
	256	p += sprintf(p, "Single-symbol ChipKill ECC");
	257	break;
	258	case 5:
	259	p += sprintf(p, "Multi-symbol ChipKill ECC");
	260	break;
	261	case 6:
	262	p += sprintf(p, "Master abort");
	263	break;
	264	case 7:
	265	p += sprintf(p, "Target abort");
	266	break;
	267	case 8:
	268	p += sprintf(p, "Parity Error");
	269	break;
	270	case 9:
	271	p += sprintf(p, "Watchdog timeout");
	272	break;
	273	case 10:
	274	p += sprintf(p, "Invalid address");
	275	break;
	276	case 11:
	277	p += sprintf(p, "Mirror Broken");
	278	break;
	279	case 12:
	280	p += sprintf(p, "Memory Sparing");
	281	break;
	282	case 13:
	283	p += sprintf(p, "Scrub corrected error");
	284	break;
	285	case 14:
	286	p += sprintf(p, "Scrub uncorrected error");
	287	break;
	288	case 15:
	289	p += sprintf(p, "Physical Memory Map-out event");
	290	break;
	291	default:
	292	p += sprintf(p, "reserved error (%d)",
	293	mem_err->error_type);
	294	}
	295	} else {
	296	strcpy(pvt->msg, "unknown error");
	297	}
	298
	299	/* Error address */
300	if (mem_err->validation_bits & CPER_MEM_VALID_PHYSICAL_ADDRESS) {
301	e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
302	e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
303	}
304
305	/* Error grain */
306	if (mem_err->validation_bits & CPER_MEM_VALID_PHYSICAL_ADDRESS_MASK) {
307	e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
308	}
309
310	/* Memory error location, mapped on e->location */
311	p = e->location;
312	if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
313	p += sprintf(p, "node:%d ", mem_err->node);
314	if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
315	p += sprintf(p, "card:%d ", mem_err->card);
316	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
317	p += sprintf(p, "module:%d ", mem_err->module);
318	if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
319	p += sprintf(p, "bank:%d ", mem_err->bank);
320	if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
321	p += sprintf(p, "row:%d ", mem_err->row);
322	if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
323	p += sprintf(p, "col:%d ", mem_err->column);
324	if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
325	p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
326	if (p > e->location)
327	*(p - 1) = '\0';
328
329	/* All other fields are mapped on e->other_detail */
330	p = pvt->other_detail;
331	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
332	u64 status = mem_err->error_status;
333
334	p += sprintf(p, "status(0x%016llx): ", (long long)status);
335	switch ((status >> 8) & 0xff) {
336	case 1:
337	p += sprintf(p, "Error detected internal to the component ");
338	break;
339	case 16:
340	p += sprintf(p, "Error detected in the bus ");
341	break;
342	case 4:
343	p += sprintf(p, "Storage error in DRAM memory ");
344	break;
345	case 5:
346	p += sprintf(p, "Storage error in TLB ");
347	break;
348	case 6:
349	p += sprintf(p, "Storage error in cache ");
350	break;
351	case 7:
352	p += sprintf(p, "Error in one or more functional units ");
353	break;
354	case 8:
355	p += sprintf(p, "component failed self test ");
356	break;
357	case 9:
358	p += sprintf(p, "Overflow or undervalue of internal queue ");
359	break;
360	case 17:
361	p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
362	break;
363	case 18:
364	p += sprintf(p, "Improper access error ");
365	break;
366	case 19:
367	p += sprintf(p, "Access to a memory address which is not mapped to any component ");
368	break;
369	case 20:
370	p += sprintf(p, "Loss of Lockstep ");
371	break;
372	case 21:
373	p += sprintf(p, "Response not associated with a request ");
374	break;
375	case 22:
376	p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
377	break;
378	case 23:
379	p += sprintf(p, "Detection of a PATH_ERROR ");
380	break;
381	case 25:
382	p += sprintf(p, "Bus operation timeout ");
383	break;
384	case 26:
385	p += sprintf(p, "A read was issued to data that has been poisoned ");
386	break;
387	default:
388	p += sprintf(p, "reserved ");
389	break;
390	}
391	}
392	if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
393	p += sprintf(p, "requestorID: 0x%016llx ",
394	(long long)mem_err->requestor_id);
395	if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
396	p += sprintf(p, "responderID: 0x%016llx ",
397	(long long)mem_err->responder_id);
398	if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
399	p += sprintf(p, "targetID: 0x%016llx ",
400	(long long)mem_err->responder_id);
401	if (p > pvt->other_detail)
402	*(p - 1) = '\0';
f04c62a7	403
8ae8f50a MCC	404	/* Generate the trace event */
	405	grain_bits = fls_long(e->grain);
	406	sprintf(pvt->detail_location, "APEI location: %s %s",
	407	e->location, e->other_detail);
	408	trace_mc_event(type, e->msg, e->label, e->error_count,
	409	mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
	410	PAGES_TO_MiB(e->page_frame_number) \| e->offset_in_page,
	411	grain_bits, e->syndrome, pvt->detail_location);
	412
	413	/* Report the error via EDAC API */
f04c62a7	414	edac_raw_mc_handle_error(type, mci, e);
77c5f5d2 MCC	415	}
	416	EXPORT_SYMBOL_GPL(ghes_edac_report_mem_error);
	417
	418	int ghes_edac_register(struct ghes ghes, struct device dev)
	419	{
32fa1f53 MCC	420	bool fake = false;
32fa1f53 MCC	421	int rc, num_dimm = 0;
77c5f5d2 MCC	422	struct mem_ctl_info *mci;
77c5f5d2 MCC	423	struct edac_mc_layer layers[1];
77c5f5d2	424	struct ghes_edac_pvt *pvt;
32fa1f53 MCC	425	struct ghes_edac_dimm_fill dimm_fill;
	426
	427	/* Get the number of DIMMs */
	428	dmi_walk(ghes_edac_count_dimms, &num_dimm);
	429
	430	/* Check if we've got a bogus BIOS */
	431	if (num_dimm == 0) {
	432	fake = true;
	433	num_dimm = 1;
	434	}
77c5f5d2 MCC	435
77c5f5d2 MCC	436	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
32fa1f53	437	layers[0].size = num_dimm;
77c5f5d2 MCC	438	layers[0].is_virt_csrow = true;
	439
	440	/*
	441	* We need to serialize edac_mc_alloc() and edac_mc_add_mc(),
	442	* to avoid duplicated memory controller numbers
	443	*/
	444	mutex_lock(&ghes_edac_lock);
	445	mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,
	446	sizeof(*pvt));
	447	if (!mci) {
d2a68566	448	pr_info("Can't allocate memory for EDAC data\n");
77c5f5d2 MCC	449	mutex_unlock(&ghes_edac_lock);
	450	return -ENOMEM;
	451	}
	452
	453	pvt = mci->pvt_info;
	454	memset(pvt, 0, sizeof(*pvt));
f04c62a7	455	list_add_tail(&pvt->list, &ghes_reglist);
77c5f5d2 MCC	456	pvt->ghes = ghes;
	457	pvt->mci = mci;
	458	mci->pdev = dev;
	459
	460	mci->mtype_cap = MEM_FLAG_EMPTY;
	461	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	462	mci->edac_cap = EDAC_FLAG_NONE;
	463	mci->mod_name = "ghes_edac.c";
	464	mci->mod_ver = GHES_EDAC_REVISION;
	465	mci->ctl_name = "ghes_edac";
	466	mci->dev_name = "ghes";
	467
d2a68566 MCC	468	if (!ghes_edac_mc_num) {
	469	if (!fake) {
	470	pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
	471	pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
	472	pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
	473	pr_info("If you find incorrect reports, please contact your hardware vendor\n");
	474	pr_info("to correct its BIOS.\n");
	475	pr_info("This system has %d DIMM sockets.\n",
	476	num_dimm);
	477	} else {
	478	pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
	479	pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
	480	pr_info("work on such system. Use this driver with caution\n");
	481	}
	482	}
	483
32fa1f53	484	if (!fake) {
5ee726db MCC	485	/*
	486	* Fill DIMM info from DMI for the memory controller #0
	487	*
	488	* Keep it in blank for the other memory controllers, as
	489	* there's no reliable way to properly credit each DIMM to
	490	* the memory controller, as different BIOSes fill the
	491	* DMI bank location fields on different ways
	492	*/
	493	if (!ghes_edac_mc_num) {
	494	dimm_fill.count = 0;
	495	dimm_fill.mci = mci;
	496	dmi_walk(ghes_edac_dmidecode, &dimm_fill);
	497	}
32fa1f53 MCC	498	} else {
	499	struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
	500	mci->n_layers, 0, 0, 0);
77c5f5d2	501
d2a68566	502	dimm->nr_pages = 1;
32fa1f53 MCC	503	dimm->grain = 128;
	504	dimm->mtype = MEM_UNKNOWN;
	505	dimm->dtype = DEV_UNKNOWN;
	506	dimm->edac_mode = EDAC_SECDED;
	507	}
77c5f5d2 MCC	508
	509	rc = edac_mc_add_mc(mci);
	510	if (rc < 0) {
d2a68566	511	pr_info("Can't register at EDAC core\n");
77c5f5d2 MCC	512	edac_mc_free(mci);
	513	mutex_unlock(&ghes_edac_lock);
	514	return -ENODEV;
	515	}
	516
	517	ghes_edac_mc_num++;
	518	mutex_unlock(&ghes_edac_lock);
	519	return 0;
	520	}
	521	EXPORT_SYMBOL_GPL(ghes_edac_register);
	522
	523	void ghes_edac_unregister(struct ghes *ghes)
	524	{
	525	struct mem_ctl_info *mci;
5dae92a7	526	struct ghes_edac_pvt pvt, tmp;
77c5f5d2	527
5dae92a7	528	list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) {
77c5f5d2 MCC	529	if (ghes == pvt->ghes) {
	530	mci = pvt->mci;
	531	edac_mc_del_mc(mci->pdev);
	532	edac_mc_free(mci);
	533	list_del(&pvt->list);
	534	}
	535	}
	536	}
	537	EXPORT_SYMBOL_GPL(ghes_edac_unregister);