[linux-block.git] / drivers / edac / ghes_edac.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GHES/EDAC Linux driver
 *
 * Copyright (c) 2013 by Mauro Carvalho Chehab
 *
 * Red Hat Inc. https://www.redhat.com
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <acpi/ghes.h>
#include <linux/edac.h>
#include <linux/dmi.h>
#include "edac_module.h"
#include <ras/ras_event.h>

#define OTHER_DETAIL_LEN	400

struct ghes_pvt {
	struct mem_ctl_info *mci;

	/* Buffers for the error handling routine */
	char other_detail[OTHER_DETAIL_LEN];
	char msg[80];
};

static refcount_t ghes_refcount = REFCOUNT_INIT(0);

/*
 * Access to ghes_pvt must be protected by ghes_lock. The spinlock
 * also provides the necessary (implicit) memory barrier for the SMP
 * case to make the pointer visible on another CPU.
 */
static struct ghes_pvt *ghes_pvt;

/*
 * This driver's representation of the system hardware, as collected
 * from DMI.
 */
static struct ghes_hw_desc {
	int num_dimms;
	struct dimm_info *dimms;
} ghes_hw;

/* GHES registration mutex */
static DEFINE_MUTEX(ghes_reg_mutex);

/*
 * Sync with other, potentially concurrent callers of
 * ghes_edac_report_mem_error(). We don't know what the
 * "inventive" firmware would do.
 */
static DEFINE_SPINLOCK(ghes_lock);

/* "ghes_edac.force_load=1" skips the platform check */
static bool __read_mostly force_load;
module_param(force_load, bool, 0);

static bool system_scanned;

/* Memory Device - Type 17 of SMBIOS spec */
struct memdev_dmi_entry {
	u8 type;
	u8 length;
	u16 handle;
	u16 phys_mem_array_handle;
	u16 mem_err_info_handle;
	u16 total_width;
	u16 data_width;
	u16 size;
	u8 form_factor;
	u8 device_set;
	u8 device_locator;
	u8 bank_locator;
	u8 memory_type;
	u16 type_detail;
	u16 speed;
	u8 manufacturer;
	u8 serial_number;
	u8 asset_tag;
	u8 part_number;
	u8 attributes;
	u32 extended_size;
	u16 conf_mem_clk_speed;
} __attribute__((__packed__));

static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
{
	struct dimm_info *dimm;

	mci_for_each_dimm(mci, dimm) {
		if (dimm->smbios_handle == handle)
			return dimm;
	}

	return NULL;
}

static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
{
	const char *bank = NULL, *device = NULL;

	dmi_memdev_name(handle, &bank, &device);

	/* both strings must be non-zero */
	if (bank && *bank && device && *device)
		snprintf(dimm->label, sizeof(dimm->label), "%s %s", bank, device);
}

static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
{
	u16 rdr_mask = BIT(7) | BIT(13);

	if (entry->size == 0xffff) {
		pr_info("Can't get DIMM%i size\n", dimm->idx);
		dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
	} else if (entry->size == 0x7fff) {
		dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
	} else {
		if (entry->size & BIT(15))
			dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
		else
			dimm->nr_pages = MiB_TO_PAGES(entry->size);
	}

	switch (entry->memory_type) {
	case 0x12:
		if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR;
		else
			dimm->mtype = MEM_DDR;
		break;
	case 0x13:
		if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR2;
		else
			dimm->mtype = MEM_DDR2;
		break;
	case 0x14:
		dimm->mtype = MEM_FB_DDR2;
		break;
	case 0x18:
		if (entry->type_detail & BIT(12))
			dimm->mtype = MEM_NVDIMM;
		else if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR3;
		else
			dimm->mtype = MEM_DDR3;
		break;
	case 0x1a:
		if (entry->type_detail & BIT(12))
			dimm->mtype = MEM_NVDIMM;
		else if (entry->type_detail & BIT(13))
			dimm->mtype = MEM_RDDR4;
		else
			dimm->mtype = MEM_DDR4;
		break;
	default:
		if (entry->type_detail & BIT(6))
			dimm->mtype = MEM_RMBS;
		else if ((entry->type_detail & rdr_mask) == rdr_mask)
			dimm->mtype = MEM_RDR;
		else if (entry->type_detail & BIT(7))
			dimm->mtype = MEM_SDR;
		else if (entry->type_detail & BIT(9))
			dimm->mtype = MEM_EDO;
		else
			dimm->mtype = MEM_UNKNOWN;
	}

	/*
	 * Actually, we can only detect if the memory has bits for
	 * checksum or not
	 */
	if (entry->total_width == entry->data_width)
		dimm->edac_mode = EDAC_NONE;
	else
		dimm->edac_mode = EDAC_SECDED;

	dimm->dtype = DEV_UNKNOWN;
	dimm->grain = 128;		/* Likely, worse case */

	dimm_setup_label(dimm, entry->handle);

	if (dimm->nr_pages) {
		edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
			dimm->idx, edac_mem_types[dimm->mtype],
			PAGES_TO_MiB(dimm->nr_pages),
			(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
		edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
			entry->memory_type, entry->type_detail,
			entry->total_width, entry->data_width);
	}

	dimm->smbios_handle = entry->handle;
}

static void enumerate_dimms(const struct dmi_header *dh, void *arg)
{
	struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
	struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
	struct dimm_info *d;

	if (dh->type != DMI_ENTRY_MEM_DEVICE)
		return;

	/* Enlarge the array with additional 16 */
	if (!hw->num_dimms || !(hw->num_dimms % 16)) {
		struct dimm_info *new;

		new = krealloc_array(hw->dimms, hw->num_dimms + 16,
				     sizeof(struct dimm_info), GFP_KERNEL);
		if (!new) {
			WARN_ON_ONCE(1);
			return;
		}

		hw->dimms = new;
	}

	d = &hw->dimms[hw->num_dimms];
	d->idx = hw->num_dimms;

	assign_dmi_dimm_info(d, entry);

	hw->num_dimms++;
}

static void ghes_scan_system(void)
{
	if (system_scanned)
		return;

	dmi_walk(enumerate_dimms, &ghes_hw);

	system_scanned = true;
}

static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
					const char *location, unsigned int len)
{
	u32 n;

	if (!msg)
		return 0;

	n = 0;
	len -= 1;

	n += scnprintf(msg + n, len - n, "APEI location: %s ", location);

	if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
		goto out;

	n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
	n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));

out:
	msg[n] = '\0';

	return n;
}

void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
{
	struct cper_mem_err_compact cmem;
	struct edac_raw_error_desc *e;
	struct mem_ctl_info *mci;
	struct ghes_pvt *pvt;
	unsigned long flags;
	char *p;

	/*
	 * We can do the locking below because GHES defers error processing
	 * from NMI to IRQ context. Whenever that changes, we'd at least
	 * know.
	 */
	if (WARN_ON_ONCE(in_nmi()))
		return;

	spin_lock_irqsave(&ghes_lock, flags);

	pvt = ghes_pvt;
	if (!pvt)
		goto unlock;

	mci = pvt->mci;
	e = &mci->error_desc;

	/* Cleans the error report buffer */
	memset(e, 0, sizeof (*e));
	e->error_count = 1;
	e->grain = 1;
	e->msg = pvt->msg;
	e->other_detail = pvt->other_detail;
	e->top_layer = -1;
	e->mid_layer = -1;
	e->low_layer = -1;
	*pvt->other_detail = '\0';
	*pvt->msg = '\0';

	switch (sev) {
	case GHES_SEV_CORRECTED:
		e->type = HW_EVENT_ERR_CORRECTED;
		break;
	case GHES_SEV_RECOVERABLE:
		e->type = HW_EVENT_ERR_UNCORRECTED;
		break;
	case GHES_SEV_PANIC:
		e->type = HW_EVENT_ERR_FATAL;
		break;
	default:
	case GHES_SEV_NO:
		e->type = HW_EVENT_ERR_INFO;
	}

	edac_dbg(1, "error validation_bits: 0x%08llx\n",
		 (long long)mem_err->validation_bits);

	/* Error type, mapped on e->msg */
	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
		u8 etype = mem_err->error_type;

		p = pvt->msg;
		p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
	} else {
		strcpy(pvt->msg, "unknown error");
	}

	/* Error address */
	if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
		e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
		e->offset_in_page = offset_in_page(mem_err->physical_addr);
	}

	/* Error grain */
	if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
		e->grain = ~mem_err->physical_addr_mask + 1;

	/* Memory error location, mapped on e->location */
	p = e->location;
	cper_mem_err_pack(mem_err, &cmem);
	p += cper_mem_err_location(&cmem, p);

	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
		struct dimm_info *dimm;

		p += cper_dimm_err_location(&cmem, p);
		dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
		if (dimm) {
			e->top_layer = dimm->idx;
			strcpy(e->label, dimm->label);
		}
	}
	if (p > e->location)
		*(p - 1) = '\0';

	if (!*e->label)
		strcpy(e->label, "unknown memory");

	/* All other fields are mapped on e->other_detail */
	p = pvt->other_detail;
	p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
	if (p > pvt->other_detail)
		*(p - 1) = '\0';

	edac_raw_mc_handle_error(e);

unlock:
	spin_unlock_irqrestore(&ghes_lock, flags);
}

/*
 * Known systems that are safe to enable this module.
 */
static struct acpi_platform_list plat_list[] = {
	{"HPE   ", "Server  ", 0, ACPI_SIG_FADT, all_versions},
	{ } /* End */
};

int ghes_edac_register(struct ghes *ghes, struct device *dev)
{
	bool fake = false;
	struct mem_ctl_info *mci;
	struct ghes_pvt *pvt;
	struct edac_mc_layer layers[1];
	unsigned long flags;
	int idx = -1;
	int rc = 0;

	if (IS_ENABLED(CONFIG_X86)) {
		/* Check if safe to enable on this system */
		idx = acpi_match_platform_list(plat_list);
		if (!force_load && idx < 0)
			return -ENODEV;
	} else {
		force_load = true;
		idx = 0;
	}

	/* finish another registration/unregistration instance first */
	mutex_lock(&ghes_reg_mutex);

	/*
	 * We have only one logical memory controller to which all DIMMs belong.
	 */
	if (refcount_inc_not_zero(&ghes_refcount))
		goto unlock;

	ghes_scan_system();

	/* Check if we've got a bogus BIOS */
	if (!ghes_hw.num_dimms) {
		fake = true;
		ghes_hw.num_dimms = 1;
	}

	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
	layers[0].size = ghes_hw.num_dimms;
	layers[0].is_virt_csrow = true;

	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
	if (!mci) {
		pr_info("Can't allocate memory for EDAC data\n");
		rc = -ENOMEM;
		goto unlock;
	}

	pvt		= mci->pvt_info;
	pvt->mci	= mci;

	mci->pdev = dev;
	mci->mtype_cap = MEM_FLAG_EMPTY;
	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	mci->edac_cap = EDAC_FLAG_NONE;
	mci->mod_name = "ghes_edac.c";
	mci->ctl_name = "ghes_edac";
	mci->dev_name = "ghes";

	if (fake) {
		pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
		pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
		pr_info("work on such system. Use this driver with caution\n");
	} else if (idx < 0) {
		pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
		pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
		pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
		pr_info("If you find incorrect reports, please contact your hardware vendor\n");
		pr_info("to correct its BIOS.\n");
		pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
	}

	if (!fake) {
		struct dimm_info *src, *dst;
		int i = 0;

		mci_for_each_dimm(mci, dst) {
			src = &ghes_hw.dimms[i];

			dst->idx	   = src->idx;
			dst->smbios_handle = src->smbios_handle;
			dst->nr_pages	   = src->nr_pages;
			dst->mtype	   = src->mtype;
			dst->edac_mode	   = src->edac_mode;
			dst->dtype	   = src->dtype;
			dst->grain	   = src->grain;

			/*
			 * If no src->label, preserve default label assigned
			 * from EDAC core.
			 */
			if (strlen(src->label))
				memcpy(dst->label, src->label, sizeof(src->label));

			i++;
		}

	} else {
		struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);

		dimm->nr_pages = 1;
		dimm->grain = 128;
		dimm->mtype = MEM_UNKNOWN;
		dimm->dtype = DEV_UNKNOWN;
		dimm->edac_mode = EDAC_SECDED;
	}

	rc = edac_mc_add_mc(mci);
	if (rc < 0) {
		pr_info("Can't register with the EDAC core\n");
		edac_mc_free(mci);
		rc = -ENODEV;
		goto unlock;
	}

	spin_lock_irqsave(&ghes_lock, flags);
	ghes_pvt = pvt;
	spin_unlock_irqrestore(&ghes_lock, flags);

	/* only set on success */
	refcount_set(&ghes_refcount, 1);

unlock:

	/* Not needed anymore */
	kfree(ghes_hw.dimms);
	ghes_hw.dimms = NULL;

	mutex_unlock(&ghes_reg_mutex);

	return rc;
}

void ghes_edac_unregister(struct ghes *ghes)
{
	struct mem_ctl_info *mci;
	unsigned long flags;

	if (!force_load)
		return;

	mutex_lock(&ghes_reg_mutex);

	system_scanned = false;
	memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));

	if (!refcount_dec_and_test(&ghes_refcount))
		goto unlock;

	/*
	 * Wait for the irq handler being finished.
	 */
	spin_lock_irqsave(&ghes_lock, flags);
	mci = ghes_pvt ? ghes_pvt->mci : NULL;
	ghes_pvt = NULL;
	spin_unlock_irqrestore(&ghes_lock, flags);

	if (!mci)
		goto unlock;

	mci = edac_mc_del_mc(mci->pdev);
	if (mci)
		edac_mc_free(mci);

unlock:
	mutex_unlock(&ghes_reg_mutex);
}
Commit	Line	Data
12237550	1	// SPDX-License-Identifier: GPL-2.0-only
77c5f5d2 MCC	2	/*
	3	* GHES/EDAC Linux driver
	4	*
37e59f87	5	* Copyright (c) 2013 by Mauro Carvalho Chehab
77c5f5d2	6	*
7d4c1ea2	7	* Red Hat Inc. https://www.redhat.com
77c5f5d2 MCC	8	*/
77c5f5d2 MCC	9
d2a68566 MCC	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
d2a68566 MCC	11
77c5f5d2 MCC	12	#include <acpi/ghes.h>
77c5f5d2 MCC	13	#include <linux/edac.h>
32fa1f53	14	#include <linux/dmi.h>
78d88e8a	15	#include "edac_module.h"
8ae8f50a	16	#include <ras/ras_event.h>
77c5f5d2	17
ed27b5df SX	18	#define OTHER_DETAIL_LEN 400
ed27b5df SX	19
b001694d	20	struct ghes_pvt {
77c5f5d2	21	struct mem_ctl_info *mci;
689c9cd8 MCC	22
689c9cd8 MCC	23	/* Buffers for the error handling routine */
ed27b5df	24	char other_detail[OTHER_DETAIL_LEN];
689c9cd8	25	char msg[80];
77c5f5d2 MCC	26	};
77c5f5d2 MCC	27
23f61b9f RR	28	static refcount_t ghes_refcount = REFCOUNT_INIT(0);
	29
	30	/*
	31	* Access to ghes_pvt must be protected by ghes_lock. The spinlock
	32	* also provides the necessary (implicit) memory barrier for the SMP
	33	* case to make the pointer visible on another CPU.
	34	*/
b001694d	35	static struct ghes_pvt *ghes_pvt;
77c5f5d2	36
b9cae277 BP	37	/*
	38	* This driver's representation of the system hardware, as collected
	39	* from DMI.
	40	*/
815fad6e	41	static struct ghes_hw_desc {
b9cae277 BP	42	int num_dimms;
	43	struct dimm_info *dimms;
	44	} ghes_hw;
	45
23f61b9f RR	46	/* GHES registration mutex */
	47	static DEFINE_MUTEX(ghes_reg_mutex);
	48
0fe5f281 BP	49	/*
	50	* Sync with other, potentially concurrent callers of
	51	* ghes_edac_report_mem_error(). We don't know what the
	52	* "inventive" firmware would do.
	53	*/
	54	static DEFINE_SPINLOCK(ghes_lock);
d2a68566	55
5deed6b6 TK	56	/* "ghes_edac.force_load=1" skips the platform check */
	57	static bool __read_mostly force_load;
	58	module_param(force_load, bool, 0);
	59
b972fdba SJ	60	static bool system_scanned;
b972fdba SJ	61
32fa1f53 MCC	62	/* Memory Device - Type 17 of SMBIOS spec */
	63	struct memdev_dmi_entry {
	64	u8 type;
	65	u8 length;
	66	u16 handle;
	67	u16 phys_mem_array_handle;
	68	u16 mem_err_info_handle;
	69	u16 total_width;
	70	u16 data_width;
	71	u16 size;
	72	u8 form_factor;
	73	u8 device_set;
	74	u8 device_locator;
	75	u8 bank_locator;
	76	u8 memory_type;
	77	u16 type_detail;
	78	u16 speed;
	79	u8 manufacturer;
	80	u8 serial_number;
	81	u8 asset_tag;
	82	u8 part_number;
	83	u8 attributes;
	84	u32 extended_size;
	85	u16 conf_mem_clk_speed;
	86	} __attribute__((__packed__));
	87
cb51a371	88	static struct dimm_info find_dimm_by_handle(struct mem_ctl_info mci, u16 handle)
c798c88f	89	{
c498afaf	90	struct dimm_info *dimm;
c798c88f	91
c498afaf RR	92	mci_for_each_dimm(mci, dimm) {
c498afaf RR	93	if (dimm->smbios_handle == handle)
cb51a371	94	return dimm;
c798c88f	95	}
c498afaf	96
cb51a371 RR	97	return NULL;
	98	}
	99
	100	static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
	101	{
	102	const char bank = NULL, device = NULL;
	103
	104	dmi_memdev_name(handle, &bank, &device);
	105
	106	/* both strings must be non-zero */
	107	if (bank && bank && device && device)
	108	snprintf(dimm->label, sizeof(dimm->label), "%s %s", bank, device);
c798c88f FW	109	}
c798c88f FW	110
b9cae277	111	static void assign_dmi_dimm_info(struct dimm_info dimm, struct memdev_dmi_entry entry)
32fa1f53	112	{
b9cae277	113	u16 rdr_mask = BIT(7) \| BIT(13);
32fa1f53	114
b9cae277 BP	115	if (entry->size == 0xffff) {
	116	pr_info("Can't get DIMM%i size\n", dimm->idx);
	117	dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
	118	} else if (entry->size == 0x7fff) {
	119	dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
	120	} else {
	121	if (entry->size & BIT(15))
	122	dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
	123	else
	124	dimm->nr_pages = MiB_TO_PAGES(entry->size);
	125	}
32fa1f53	126
b9cae277 BP	127	switch (entry->memory_type) {
	128	case 0x12:
	129	if (entry->type_detail & BIT(13))
	130	dimm->mtype = MEM_RDDR;
	131	else
	132	dimm->mtype = MEM_DDR;
	133	break;
	134	case 0x13:
	135	if (entry->type_detail & BIT(13))
	136	dimm->mtype = MEM_RDDR2;
32fa1f53	137	else
b9cae277 BP	138	dimm->mtype = MEM_DDR2;
	139	break;
	140	case 0x14:
	141	dimm->mtype = MEM_FB_DDR2;
	142	break;
	143	case 0x18:
	144	if (entry->type_detail & BIT(12))
	145	dimm->mtype = MEM_NVDIMM;
	146	else if (entry->type_detail & BIT(13))
	147	dimm->mtype = MEM_RDDR3;
	148	else
	149	dimm->mtype = MEM_DDR3;
	150	break;
	151	case 0x1a:
	152	if (entry->type_detail & BIT(12))
	153	dimm->mtype = MEM_NVDIMM;
	154	else if (entry->type_detail & BIT(13))
	155	dimm->mtype = MEM_RDDR4;
	156	else
	157	dimm->mtype = MEM_DDR4;
	158	break;
	159	default:
	160	if (entry->type_detail & BIT(6))
	161	dimm->mtype = MEM_RMBS;
	162	else if ((entry->type_detail & rdr_mask) == rdr_mask)
	163	dimm->mtype = MEM_RDR;
	164	else if (entry->type_detail & BIT(7))
	165	dimm->mtype = MEM_SDR;
	166	else if (entry->type_detail & BIT(9))
	167	dimm->mtype = MEM_EDO;
	168	else
	169	dimm->mtype = MEM_UNKNOWN;
	170	}
32fa1f53	171
b9cae277 BP	172	/*
	173	* Actually, we can only detect if the memory has bits for
	174	* checksum or not
	175	*/
	176	if (entry->total_width == entry->data_width)
	177	dimm->edac_mode = EDAC_NONE;
	178	else
	179	dimm->edac_mode = EDAC_SECDED;
	180
	181	dimm->dtype = DEV_UNKNOWN;
	182	dimm->grain = 128; /* Likely, worse case */
32fa1f53	183
b9cae277	184	dimm_setup_label(dimm, entry->handle);
c798c88f	185
b9cae277 BP	186	if (dimm->nr_pages) {
	187	edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
	188	dimm->idx, edac_mem_types[dimm->mtype],
	189	PAGES_TO_MiB(dimm->nr_pages),
	190	(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
	191	edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
	192	entry->memory_type, entry->type_detail,
	193	entry->total_width, entry->data_width);
32fa1f53	194	}
b9cae277 BP	195
	196	dimm->smbios_handle = entry->handle;
	197	}
	198
	199	static void enumerate_dimms(const struct dmi_header dh, void arg)
	200	{
	201	struct memdev_dmi_entry entry = (struct memdev_dmi_entry )dh;
	202	struct ghes_hw_desc hw = (struct ghes_hw_desc )arg;
	203	struct dimm_info *d;
	204
	205	if (dh->type != DMI_ENTRY_MEM_DEVICE)
	206	return;
	207
	208	/* Enlarge the array with additional 16 */
	209	if (!hw->num_dimms \|\| !(hw->num_dimms % 16)) {
	210	struct dimm_info *new;
	211
af11be05 BG	212	new = krealloc_array(hw->dimms, hw->num_dimms + 16,
af11be05 BG	213	sizeof(struct dimm_info), GFP_KERNEL);
b9cae277 BP	214	if (!new) {
	215	WARN_ON_ONCE(1);
	216	return;
	217	}
	218
	219	hw->dimms = new;
	220	}
	221
	222	d = &hw->dimms[hw->num_dimms];
	223	d->idx = hw->num_dimms;
	224
	225	assign_dmi_dimm_info(d, entry);
	226
	227	hw->num_dimms++;
	228	}
	229
	230	static void ghes_scan_system(void)
	231	{
b972fdba	232	if (system_scanned)
b9cae277 BP	233	return;
	234
	235	dmi_walk(enumerate_dimms, &ghes_hw);
	236
b972fdba	237	system_scanned = true;
32fa1f53 MCC	238	}
32fa1f53 MCC	239
ed27b5df SX	240	static int print_mem_error_other_detail(const struct cper_sec_mem_err mem, char msg,
	241	const char *location, unsigned int len)
	242	{
	243	u32 n;
	244
	245	if (!msg)
	246	return 0;
	247
	248	n = 0;
	249	len -= 1;
	250
	251	n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
	252
	253	if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
	254	goto out;
	255
	256	n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
	257	n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
	258
	259	out:
	260	msg[n] = '\0';
	261
	262	return n;
	263	}
	264
305d0e00	265	void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
77c5f5d2	266	{
ed27b5df	267	struct cper_mem_err_compact cmem;
f04c62a7 MCC	268	struct edac_raw_error_desc *e;
f04c62a7 MCC	269	struct mem_ctl_info *mci;
b001694d	270	struct ghes_pvt *pvt;
0fe5f281	271	unsigned long flags;
689c9cd8	272	char *p;
f04c62a7	273
0fe5f281 BP	274	/*
	275	* We can do the locking below because GHES defers error processing
	276	* from NMI to IRQ context. Whenever that changes, we'd at least
	277	* know.
	278	*/
	279	if (WARN_ON_ONCE(in_nmi()))
	280	return;
	281
	282	spin_lock_irqsave(&ghes_lock, flags);
	283
23f61b9f RR	284	pvt = ghes_pvt;
	285	if (!pvt)
	286	goto unlock;
	287
f04c62a7 MCC	288	mci = pvt->mci;
	289	e = &mci->error_desc;
	290
	291	/* Cleans the error report buffer */
	292	memset(e, 0, sizeof (*e));
	293	e->error_count = 1;
7088e29e	294	e->grain = 1;
689c9cd8 MCC	295	e->msg = pvt->msg;
	296	e->other_detail = pvt->other_detail;
	297	e->top_layer = -1;
	298	e->mid_layer = -1;
	299	e->low_layer = -1;
	300	*pvt->other_detail = '\0';
	301	*pvt->msg = '\0';
f04c62a7 MCC	302
	303	switch (sev) {
	304	case GHES_SEV_CORRECTED:
672ef0e5	305	e->type = HW_EVENT_ERR_CORRECTED;
f04c62a7 MCC	306	break;
f04c62a7 MCC	307	case GHES_SEV_RECOVERABLE:
672ef0e5	308	e->type = HW_EVENT_ERR_UNCORRECTED;
f04c62a7 MCC	309	break;
f04c62a7 MCC	310	case GHES_SEV_PANIC:
672ef0e5	311	e->type = HW_EVENT_ERR_FATAL;
f04c62a7 MCC	312	break;
	313	default:
	314	case GHES_SEV_NO:
672ef0e5	315	e->type = HW_EVENT_ERR_INFO;
f04c62a7 MCC	316	}
f04c62a7 MCC	317
689c9cd8 MCC	318	edac_dbg(1, "error validation_bits: 0x%08llx\n",
	319	(long long)mem_err->validation_bits);
	320
	321	/* Error type, mapped on e->msg */
	322	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
ed27b5df SX	323	u8 etype = mem_err->error_type;
ed27b5df SX	324
689c9cd8	325	p = pvt->msg;
ed27b5df	326	p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
689c9cd8 MCC	327	} else {
	328	strcpy(pvt->msg, "unknown error");
	329	}
	330
	331	/* Error address */
147de147	332	if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
7c104931 RR	333	e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
7c104931 RR	334	e->offset_in_page = offset_in_page(mem_err->physical_addr);
689c9cd8 MCC	335	}
	336
	337	/* Error grain */
147de147	338	if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
7088e29e	339	e->grain = ~mem_err->physical_addr_mask + 1;
689c9cd8 MCC	340
	341	/* Memory error location, mapped on e->location */
	342	p = e->location;
ed27b5df SX	343	cper_mem_err_pack(mem_err, &cmem);
	344	p += cper_mem_err_location(&cmem, p);
	345
56507694	346	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
cb51a371	347	struct dimm_info *dimm;
c798c88f	348
ed27b5df	349	p += cper_dimm_err_location(&cmem, p);
cb51a371 RR	350	dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
	351	if (dimm) {
	352	e->top_layer = dimm->idx;
	353	strcpy(e->label, dimm->label);
	354	}
56507694	355	}
689c9cd8 MCC	356	if (p > e->location)
	357	*(p - 1) = '\0';
	358
cb51a371 RR	359	if (!*e->label)
	360	strcpy(e->label, "unknown memory");
	361
689c9cd8 MCC	362	/* All other fields are mapped on e->other_detail */
689c9cd8 MCC	363	p = pvt->other_detail;
ed27b5df	364	p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
689c9cd8 MCC	365	if (p > pvt->other_detail)
689c9cd8 MCC	366	*(p - 1) = '\0';
f04c62a7	367
91b327f6	368	edac_raw_mc_handle_error(e);
23f61b9f RR	369
23f61b9f RR	370	unlock:
0fe5f281	371	spin_unlock_irqrestore(&ghes_lock, flags);
77c5f5d2	372	}
77c5f5d2	373
5deed6b6 TK	374	/*
	375	* Known systems that are safe to enable this module.
	376	*/
	377	static struct acpi_platform_list plat_list[] = {
	378	{"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
	379	{ } /* End */
	380	};
	381
77c5f5d2 MCC	382	int ghes_edac_register(struct ghes ghes, struct device dev)
77c5f5d2 MCC	383	{
32fa1f53	384	bool fake = false;
77c5f5d2	385	struct mem_ctl_info *mci;
b001694d	386	struct ghes_pvt *pvt;
77c5f5d2	387	struct edac_mc_layer layers[1];
23f61b9f	388	unsigned long flags;
eaa3a1d4	389	int idx = -1;
b9cae277	390	int rc = 0;
5deed6b6	391
eaa3a1d4 BP	392	if (IS_ENABLED(CONFIG_X86)) {
	393	/* Check if safe to enable on this system */
	394	idx = acpi_match_platform_list(plat_list);
	395	if (!force_load && idx < 0)
	396	return -ENODEV;
	397	} else {
251c54ea	398	force_load = true;
eaa3a1d4 BP	399	idx = 0;
eaa3a1d4 BP	400	}
32fa1f53	401
23f61b9f RR	402	/* finish another registration/unregistration instance first */
	403	mutex_lock(&ghes_reg_mutex);
	404
0fe5f281 BP	405	/*
	406	* We have only one logical memory controller to which all DIMMs belong.
	407	*/
23f61b9f RR	408	if (refcount_inc_not_zero(&ghes_refcount))
23f61b9f RR	409	goto unlock;
0fe5f281	410
b9cae277	411	ghes_scan_system();
32fa1f53 MCC	412
32fa1f53 MCC	413	/* Check if we've got a bogus BIOS */
b9cae277	414	if (!ghes_hw.num_dimms) {
32fa1f53	415	fake = true;
b9cae277	416	ghes_hw.num_dimms = 1;
32fa1f53	417	}
77c5f5d2 MCC	418
77c5f5d2 MCC	419	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
b9cae277	420	layers[0].size = ghes_hw.num_dimms;
77c5f5d2 MCC	421	layers[0].is_virt_csrow = true;
77c5f5d2 MCC	422
b001694d	423	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
77c5f5d2	424	if (!mci) {
d2a68566	425	pr_info("Can't allocate memory for EDAC data\n");
23f61b9f RR	426	rc = -ENOMEM;
23f61b9f RR	427	goto unlock;
77c5f5d2 MCC	428	}
77c5f5d2 MCC	429
23f61b9f	430	pvt = mci->pvt_info;
23f61b9f	431	pvt->mci = mci;
77c5f5d2	432
0fe5f281	433	mci->pdev = dev;
77c5f5d2 MCC	434	mci->mtype_cap = MEM_FLAG_EMPTY;
	435	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	436	mci->edac_cap = EDAC_FLAG_NONE;
	437	mci->mod_name = "ghes_edac.c";
77c5f5d2 MCC	438	mci->ctl_name = "ghes_edac";
	439	mci->dev_name = "ghes";
	440
5deed6b6 TK	441	if (fake) {
	442	pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
	443	pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
	444	pr_info("work on such system. Use this driver with caution\n");
	445	} else if (idx < 0) {
0fe5f281 BP	446	pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
	447	pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
	448	pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
	449	pr_info("If you find incorrect reports, please contact your hardware vendor\n");
	450	pr_info("to correct its BIOS.\n");
b9cae277	451	pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
d2a68566 MCC	452	}
d2a68566 MCC	453
32fa1f53	454	if (!fake) {
b9cae277 BP	455	struct dimm_info src, dst;
	456	int i = 0;
	457
	458	mci_for_each_dimm(mci, dst) {
	459	src = &ghes_hw.dimms[i];
	460
	461	dst->idx = src->idx;
	462	dst->smbios_handle = src->smbios_handle;
	463	dst->nr_pages = src->nr_pages;
	464	dst->mtype = src->mtype;
	465	dst->edac_mode = src->edac_mode;
	466	dst->dtype = src->dtype;
	467	dst->grain = src->grain;
	468
	469	/*
	470	* If no src->label, preserve default label assigned
	471	* from EDAC core.
	472	*/
	473	if (strlen(src->label))
	474	memcpy(dst->label, src->label, sizeof(src->label));
	475
	476	i++;
	477	}
	478
32fa1f53	479	} else {
bc9ad9e4	480	struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
77c5f5d2	481
d2a68566	482	dimm->nr_pages = 1;
32fa1f53 MCC	483	dimm->grain = 128;
	484	dimm->mtype = MEM_UNKNOWN;
	485	dimm->dtype = DEV_UNKNOWN;
	486	dimm->edac_mode = EDAC_SECDED;
	487	}
77c5f5d2 MCC	488
	489	rc = edac_mc_add_mc(mci);
	490	if (rc < 0) {
b9cae277	491	pr_info("Can't register with the EDAC core\n");
77c5f5d2	492	edac_mc_free(mci);
23f61b9f RR	493	rc = -ENODEV;
23f61b9f RR	494	goto unlock;
77c5f5d2	495	}
23f61b9f RR	496
	497	spin_lock_irqsave(&ghes_lock, flags);
	498	ghes_pvt = pvt;
	499	spin_unlock_irqrestore(&ghes_lock, flags);
	500
16214bd9 RR	501	/* only set on success */
16214bd9 RR	502	refcount_set(&ghes_refcount, 1);
23f61b9f RR	503
23f61b9f RR	504	unlock:
b9cae277 BP	505
	506	/* Not needed anymore */
	507	kfree(ghes_hw.dimms);
	508	ghes_hw.dimms = NULL;
	509
23f61b9f RR	510	mutex_unlock(&ghes_reg_mutex);
	511
	512	return rc;
77c5f5d2	513	}
77c5f5d2 MCC	514
	515	void ghes_edac_unregister(struct ghes *ghes)
	516	{
	517	struct mem_ctl_info *mci;
23f61b9f	518	unsigned long flags;
0fe5f281	519
251c54ea BP	520	if (!force_load)
	521	return;
	522
23f61b9f	523	mutex_lock(&ghes_reg_mutex);
a66bdf5d	524
b972fdba	525	system_scanned = false;
cd8100f1	526	memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
b972fdba	527
23f61b9f RR	528	if (!refcount_dec_and_test(&ghes_refcount))
23f61b9f RR	529	goto unlock;
1e72e673	530
23f61b9f RR	531	/*
	532	* Wait for the irq handler being finished.
	533	*/
	534	spin_lock_irqsave(&ghes_lock, flags);
	535	mci = ghes_pvt ? ghes_pvt->mci : NULL;
1e72e673	536	ghes_pvt = NULL;
23f61b9f RR	537	spin_unlock_irqrestore(&ghes_lock, flags);
	538
	539	if (!mci)
	540	goto unlock;
	541
	542	mci = edac_mc_del_mc(mci->pdev);
	543	if (mci)
	544	edac_mc_free(mci);
	545
	546	unlock:
	547	mutex_unlock(&ghes_reg_mutex);
77c5f5d2	548	}