Commit | Line | Data |
---|---|---|
da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
da9bb1d2 | 32 | #include <asm/page.h> |
78d88e8a | 33 | #include "edac_mc.h" |
7c9281d7 | 34 | #include "edac_module.h" |
53f2d028 MCC |
35 | #include <ras/ras_event.h> |
36 | ||
b01aec9b BP |
37 | #ifdef CONFIG_EDAC_ATOMIC_SCRUB |
38 | #include <asm/edac.h> | |
39 | #else | |
40 | #define edac_atomic_scrub(va, size) do { } while (0) | |
41 | #endif | |
42 | ||
da9bb1d2 | 43 | /* lock to memory controller's control array */ |
63b7df91 | 44 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 45 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 46 | |
80cc7d87 MCC |
47 | /* |
48 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
49 | * apei/ghes and i7core_edac to be used at the same time. | |
50 | */ | |
51 | static void const *edac_mc_owner; | |
52 | ||
88d84ac9 BP |
53 | static struct bus_type mc_bus[EDAC_MAX_MCS]; |
54 | ||
6e84d359 MCC |
55 | unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
56 | unsigned len) | |
57 | { | |
58 | struct mem_ctl_info *mci = dimm->mci; | |
59 | int i, n, count = 0; | |
60 | char *p = buf; | |
61 | ||
62 | for (i = 0; i < mci->n_layers; i++) { | |
63 | n = snprintf(p, len, "%s %d ", | |
64 | edac_layer_name[mci->layers[i].type], | |
65 | dimm->location[i]); | |
66 | p += n; | |
67 | len -= n; | |
68 | count += n; | |
69 | if (!len) | |
70 | break; | |
71 | } | |
72 | ||
73 | return count; | |
74 | } | |
75 | ||
da9bb1d2 AC |
76 | #ifdef CONFIG_EDAC_DEBUG |
77 | ||
a4b4be3f | 78 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 79 | { |
6e84d359 MCC |
80 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
81 | edac_dbg(4, " channel = %p\n", chan); | |
82 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
83 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
84 | } |
85 | ||
6e84d359 | 86 | static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) |
4275be63 | 87 | { |
6e84d359 MCC |
88 | char location[80]; |
89 | ||
90 | edac_dimm_info_location(dimm, location, sizeof(location)); | |
91 | ||
92 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 93 | dimm->mci->csbased ? "rank" : "dimm", |
6e84d359 MCC |
94 | number, location, dimm->csrow, dimm->cschannel); |
95 | edac_dbg(4, " dimm = %p\n", dimm); | |
96 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
97 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
98 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
99 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
100 | } |
101 | ||
2da1c119 | 102 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 103 | { |
6e84d359 MCC |
104 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
105 | edac_dbg(4, " csrow = %p\n", csrow); | |
106 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
107 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
108 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
109 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
110 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
111 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
112 | } |
113 | ||
2da1c119 | 114 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 115 | { |
956b9ba1 JP |
116 | edac_dbg(3, "\tmci = %p\n", mci); |
117 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
118 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
119 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
120 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
121 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
122 | mci->nr_csrows, mci->csrows); | |
123 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
124 | mci->tot_dimms, mci->dimms); | |
125 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
126 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
127 | mci->mod_name, mci->ctl_name); | |
128 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
129 | } |
130 | ||
24f9a7fe BP |
131 | #endif /* CONFIG_EDAC_DEBUG */ |
132 | ||
f4ce6eca | 133 | const char * const edac_mem_types[] = { |
4cfc3a40 BP |
134 | [MEM_EMPTY] = "Empty csrow", |
135 | [MEM_RESERVED] = "Reserved csrow type", | |
136 | [MEM_UNKNOWN] = "Unknown csrow type", | |
137 | [MEM_FPM] = "Fast page mode RAM", | |
138 | [MEM_EDO] = "Extended data out RAM", | |
139 | [MEM_BEDO] = "Burst Extended data out RAM", | |
140 | [MEM_SDR] = "Single data rate SDRAM", | |
141 | [MEM_RDR] = "Registered single data rate SDRAM", | |
142 | [MEM_DDR] = "Double data rate SDRAM", | |
143 | [MEM_RDDR] = "Registered Double data rate SDRAM", | |
144 | [MEM_RMBS] = "Rambus DRAM", | |
145 | [MEM_DDR2] = "Unbuffered DDR2 RAM", | |
146 | [MEM_FB_DDR2] = "Fully buffered DDR2", | |
147 | [MEM_RDDR2] = "Registered DDR2 RAM", | |
148 | [MEM_XDR] = "Rambus XDR", | |
149 | [MEM_DDR3] = "Unbuffered DDR3 RAM", | |
150 | [MEM_RDDR3] = "Registered DDR3 RAM", | |
151 | [MEM_LRDDR3] = "Load-Reduced DDR3 RAM", | |
152 | [MEM_DDR4] = "Unbuffered DDR4 RAM", | |
153 | [MEM_RDDR4] = "Registered DDR4 RAM", | |
239642fe BP |
154 | }; |
155 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
156 | ||
93e4fe64 MCC |
157 | /** |
158 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation | |
159 | * @p: pointer to a pointer with the memory offset to be used. At | |
160 | * return, this will be incremented to point to the next offset | |
161 | * @size: Size of the data structure to be reserved | |
162 | * @n_elems: Number of elements that should be reserved | |
da9bb1d2 AC |
163 | * |
164 | * If 'size' is a constant, the compiler will optimize this whole function | |
93e4fe64 MCC |
165 | * down to either a no-op or the addition of a constant to the value of '*p'. |
166 | * | |
167 | * The 'p' pointer is absolutely needed to keep the proper advancing | |
168 | * further in memory to the proper offsets when allocating the struct along | |
169 | * with its embedded structs, as edac_device_alloc_ctl_info() does it | |
170 | * above, for example. | |
171 | * | |
172 | * At return, the pointer 'p' will be incremented to be used on a next call | |
173 | * to this function. | |
da9bb1d2 | 174 | */ |
93e4fe64 | 175 | void *edac_align_ptr(void **p, unsigned size, int n_elems) |
da9bb1d2 AC |
176 | { |
177 | unsigned align, r; | |
93e4fe64 | 178 | void *ptr = *p; |
da9bb1d2 | 179 | |
93e4fe64 MCC |
180 | *p += size * n_elems; |
181 | ||
182 | /* | |
183 | * 'p' can possibly be an unaligned item X such that sizeof(X) is | |
184 | * 'size'. Adjust 'p' so that its alignment is at least as | |
185 | * stringent as what the compiler would provide for X and return | |
186 | * the aligned result. | |
187 | * Here we assume that the alignment of a "long long" is the most | |
da9bb1d2 AC |
188 | * stringent alignment that the compiler will ever provide by default. |
189 | * As far as I know, this is a reasonable assumption. | |
190 | */ | |
191 | if (size > sizeof(long)) | |
192 | align = sizeof(long long); | |
193 | else if (size > sizeof(int)) | |
194 | align = sizeof(long); | |
195 | else if (size > sizeof(short)) | |
196 | align = sizeof(int); | |
197 | else if (size > sizeof(char)) | |
198 | align = sizeof(short); | |
199 | else | |
079708b9 | 200 | return (char *)ptr; |
da9bb1d2 | 201 | |
8447c4d1 | 202 | r = (unsigned long)p % align; |
da9bb1d2 AC |
203 | |
204 | if (r == 0) | |
079708b9 | 205 | return (char *)ptr; |
da9bb1d2 | 206 | |
93e4fe64 MCC |
207 | *p += align - r; |
208 | ||
7391c6dc | 209 | return (void *)(((unsigned long)ptr) + align - r); |
da9bb1d2 AC |
210 | } |
211 | ||
faa2ad09 SR |
212 | static void _edac_mc_free(struct mem_ctl_info *mci) |
213 | { | |
214 | int i, chn, row; | |
215 | struct csrow_info *csr; | |
216 | const unsigned int tot_dimms = mci->tot_dimms; | |
217 | const unsigned int tot_channels = mci->num_cschannel; | |
218 | const unsigned int tot_csrows = mci->nr_csrows; | |
219 | ||
220 | if (mci->dimms) { | |
221 | for (i = 0; i < tot_dimms; i++) | |
222 | kfree(mci->dimms[i]); | |
223 | kfree(mci->dimms); | |
224 | } | |
225 | if (mci->csrows) { | |
226 | for (row = 0; row < tot_csrows; row++) { | |
227 | csr = mci->csrows[row]; | |
228 | if (csr) { | |
229 | if (csr->channels) { | |
230 | for (chn = 0; chn < tot_channels; chn++) | |
231 | kfree(csr->channels[chn]); | |
232 | kfree(csr->channels); | |
233 | } | |
234 | kfree(csr); | |
235 | } | |
236 | } | |
237 | kfree(mci->csrows); | |
238 | } | |
239 | kfree(mci); | |
240 | } | |
241 | ||
ca0907b9 MCC |
242 | struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, |
243 | unsigned n_layers, | |
244 | struct edac_mc_layer *layers, | |
245 | unsigned sz_pvt) | |
da9bb1d2 AC |
246 | { |
247 | struct mem_ctl_info *mci; | |
4275be63 | 248 | struct edac_mc_layer *layer; |
de3910eb MCC |
249 | struct csrow_info *csr; |
250 | struct rank_info *chan; | |
a7d7d2e1 | 251 | struct dimm_info *dimm; |
4275be63 MCC |
252 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; |
253 | unsigned pos[EDAC_MAX_LAYERS]; | |
4275be63 MCC |
254 | unsigned size, tot_dimms = 1, count = 1; |
255 | unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; | |
5926ff50 | 256 | void *pvt, *p, *ptr = NULL; |
de3910eb | 257 | int i, j, row, chn, n, len, off; |
4275be63 MCC |
258 | bool per_rank = false; |
259 | ||
260 | BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); | |
261 | /* | |
262 | * Calculate the total amount of dimms and csrows/cschannels while | |
263 | * in the old API emulation mode | |
264 | */ | |
265 | for (i = 0; i < n_layers; i++) { | |
266 | tot_dimms *= layers[i].size; | |
267 | if (layers[i].is_virt_csrow) | |
268 | tot_csrows *= layers[i].size; | |
269 | else | |
270 | tot_channels *= layers[i].size; | |
271 | ||
272 | if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) | |
273 | per_rank = true; | |
274 | } | |
da9bb1d2 AC |
275 | |
276 | /* Figure out the offsets of the various items from the start of an mc | |
277 | * structure. We want the alignment of each item to be at least as | |
278 | * stringent as what the compiler would provide if we could simply | |
279 | * hardcode everything into a single struct. | |
280 | */ | |
93e4fe64 | 281 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
4275be63 | 282 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); |
4275be63 MCC |
283 | for (i = 0; i < n_layers; i++) { |
284 | count *= layers[i].size; | |
956b9ba1 | 285 | edac_dbg(4, "errcount layer %d size %d\n", i, count); |
4275be63 MCC |
286 | ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
287 | ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); | |
288 | tot_errcount += 2 * count; | |
289 | } | |
290 | ||
956b9ba1 | 291 | edac_dbg(4, "allocating %d error counters\n", tot_errcount); |
93e4fe64 | 292 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); |
079708b9 | 293 | size = ((unsigned long)pvt) + sz_pvt; |
da9bb1d2 | 294 | |
956b9ba1 JP |
295 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", |
296 | size, | |
297 | tot_dimms, | |
298 | per_rank ? "ranks" : "dimms", | |
299 | tot_csrows * tot_channels); | |
de3910eb | 300 | |
8096cfaf DT |
301 | mci = kzalloc(size, GFP_KERNEL); |
302 | if (mci == NULL) | |
da9bb1d2 AC |
303 | return NULL; |
304 | ||
305 | /* Adjust pointers so they point within the memory we just allocated | |
306 | * rather than an imaginary chunk of memory located at address 0. | |
307 | */ | |
4275be63 | 308 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); |
4275be63 MCC |
309 | for (i = 0; i < n_layers; i++) { |
310 | mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); | |
311 | mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); | |
312 | } | |
079708b9 | 313 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
da9bb1d2 | 314 | |
b8f6f975 | 315 | /* setup index and various internal pointers */ |
4275be63 | 316 | mci->mc_idx = mc_num; |
4275be63 | 317 | mci->tot_dimms = tot_dimms; |
da9bb1d2 | 318 | mci->pvt_info = pvt; |
4275be63 MCC |
319 | mci->n_layers = n_layers; |
320 | mci->layers = layer; | |
321 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); | |
322 | mci->nr_csrows = tot_csrows; | |
323 | mci->num_cschannel = tot_channels; | |
9713faec | 324 | mci->csbased = per_rank; |
da9bb1d2 | 325 | |
a7d7d2e1 | 326 | /* |
de3910eb | 327 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 328 | */ |
d3d09e18 | 329 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb MCC |
330 | if (!mci->csrows) |
331 | goto error; | |
4275be63 | 332 | for (row = 0; row < tot_csrows; row++) { |
de3910eb MCC |
333 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
334 | if (!csr) | |
335 | goto error; | |
336 | mci->csrows[row] = csr; | |
4275be63 MCC |
337 | csr->csrow_idx = row; |
338 | csr->mci = mci; | |
339 | csr->nr_channels = tot_channels; | |
d3d09e18 | 340 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
341 | GFP_KERNEL); |
342 | if (!csr->channels) | |
343 | goto error; | |
4275be63 MCC |
344 | |
345 | for (chn = 0; chn < tot_channels; chn++) { | |
de3910eb MCC |
346 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
347 | if (!chan) | |
348 | goto error; | |
349 | csr->channels[chn] = chan; | |
da9bb1d2 | 350 | chan->chan_idx = chn; |
4275be63 MCC |
351 | chan->csrow = csr; |
352 | } | |
353 | } | |
354 | ||
355 | /* | |
de3910eb | 356 | * Allocate and fill the dimm structs |
4275be63 | 357 | */ |
d3d09e18 | 358 | mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb MCC |
359 | if (!mci->dimms) |
360 | goto error; | |
361 | ||
4275be63 MCC |
362 | memset(&pos, 0, sizeof(pos)); |
363 | row = 0; | |
364 | chn = 0; | |
4275be63 | 365 | for (i = 0; i < tot_dimms; i++) { |
de3910eb MCC |
366 | chan = mci->csrows[row]->channels[chn]; |
367 | off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); | |
368 | if (off < 0 || off >= tot_dimms) { | |
369 | edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); | |
370 | goto error; | |
371 | } | |
4275be63 | 372 | |
de3910eb | 373 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 DC |
374 | if (!dimm) |
375 | goto error; | |
de3910eb | 376 | mci->dimms[off] = dimm; |
4275be63 | 377 | dimm->mci = mci; |
4275be63 | 378 | |
5926ff50 MCC |
379 | /* |
380 | * Copy DIMM location and initialize it. | |
381 | */ | |
382 | len = sizeof(dimm->label); | |
383 | p = dimm->label; | |
384 | n = snprintf(p, len, "mc#%u", mc_num); | |
385 | p += n; | |
386 | len -= n; | |
387 | for (j = 0; j < n_layers; j++) { | |
388 | n = snprintf(p, len, "%s#%u", | |
389 | edac_layer_name[layers[j].type], | |
390 | pos[j]); | |
391 | p += n; | |
392 | len -= n; | |
4275be63 MCC |
393 | dimm->location[j] = pos[j]; |
394 | ||
5926ff50 MCC |
395 | if (len <= 0) |
396 | break; | |
397 | } | |
398 | ||
4275be63 MCC |
399 | /* Link it to the csrows old API data */ |
400 | chan->dimm = dimm; | |
401 | dimm->csrow = row; | |
402 | dimm->cschannel = chn; | |
403 | ||
404 | /* Increment csrow location */ | |
24bef66e | 405 | if (layers[0].is_virt_csrow) { |
4275be63 | 406 | chn++; |
24bef66e MCC |
407 | if (chn == tot_channels) { |
408 | chn = 0; | |
409 | row++; | |
410 | } | |
411 | } else { | |
412 | row++; | |
413 | if (row == tot_csrows) { | |
414 | row = 0; | |
415 | chn++; | |
416 | } | |
4275be63 | 417 | } |
a7d7d2e1 | 418 | |
4275be63 MCC |
419 | /* Increment dimm location */ |
420 | for (j = n_layers - 1; j >= 0; j--) { | |
421 | pos[j]++; | |
422 | if (pos[j] < layers[j].size) | |
423 | break; | |
424 | pos[j] = 0; | |
da9bb1d2 AC |
425 | } |
426 | } | |
427 | ||
81d87cb1 | 428 | mci->op_state = OP_ALLOC; |
8096cfaf | 429 | |
da9bb1d2 | 430 | return mci; |
de3910eb MCC |
431 | |
432 | error: | |
faa2ad09 | 433 | _edac_mc_free(mci); |
de3910eb MCC |
434 | |
435 | return NULL; | |
4275be63 | 436 | } |
9110540f | 437 | EXPORT_SYMBOL_GPL(edac_mc_alloc); |
da9bb1d2 | 438 | |
da9bb1d2 AC |
439 | void edac_mc_free(struct mem_ctl_info *mci) |
440 | { | |
956b9ba1 | 441 | edac_dbg(1, "\n"); |
bbc560ae | 442 | |
faa2ad09 SR |
443 | /* If we're not yet registered with sysfs free only what was allocated |
444 | * in edac_mc_alloc(). | |
445 | */ | |
446 | if (!device_is_registered(&mci->dev)) { | |
447 | _edac_mc_free(mci); | |
448 | return; | |
449 | } | |
450 | ||
de3910eb | 451 | /* the mci instance is freed here, when the sysfs object is dropped */ |
7a623c03 | 452 | edac_unregister_sysfs(mci); |
da9bb1d2 | 453 | } |
9110540f | 454 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 455 | |
d7fc9d77 YG |
456 | bool edac_has_mcs(void) |
457 | { | |
458 | bool ret; | |
459 | ||
460 | mutex_lock(&mem_ctls_mutex); | |
461 | ||
462 | ret = list_empty(&mc_devices); | |
463 | ||
464 | mutex_unlock(&mem_ctls_mutex); | |
465 | ||
466 | return !ret; | |
467 | } | |
468 | EXPORT_SYMBOL_GPL(edac_has_mcs); | |
469 | ||
c73e8833 BP |
470 | /* Caller must hold mem_ctls_mutex */ |
471 | static struct mem_ctl_info *__find_mci_by_dev(struct device *dev) | |
da9bb1d2 AC |
472 | { |
473 | struct mem_ctl_info *mci; | |
474 | struct list_head *item; | |
475 | ||
956b9ba1 | 476 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
477 | |
478 | list_for_each(item, &mc_devices) { | |
479 | mci = list_entry(item, struct mem_ctl_info, link); | |
480 | ||
fd687502 | 481 | if (mci->pdev == dev) |
da9bb1d2 AC |
482 | return mci; |
483 | } | |
484 | ||
485 | return NULL; | |
486 | } | |
c73e8833 BP |
487 | |
488 | /** | |
489 | * find_mci_by_dev | |
490 | * | |
491 | * scan list of controllers looking for the one that manages | |
492 | * the 'dev' device | |
493 | * @dev: pointer to a struct device related with the MCI | |
494 | */ | |
495 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) | |
496 | { | |
497 | struct mem_ctl_info *ret; | |
498 | ||
499 | mutex_lock(&mem_ctls_mutex); | |
500 | ret = __find_mci_by_dev(dev); | |
501 | mutex_unlock(&mem_ctls_mutex); | |
502 | ||
503 | return ret; | |
504 | } | |
939747bd | 505 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 506 | |
81d87cb1 DJ |
507 | /* |
508 | * edac_mc_workq_function | |
509 | * performs the operation scheduled by a workq request | |
510 | */ | |
81d87cb1 DJ |
511 | static void edac_mc_workq_function(struct work_struct *work_req) |
512 | { | |
fbeb4384 | 513 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 514 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
515 | |
516 | mutex_lock(&mem_ctls_mutex); | |
517 | ||
06e912d4 | 518 | if (mci->op_state != OP_RUNNING_POLL) { |
bf52fa4a DT |
519 | mutex_unlock(&mem_ctls_mutex); |
520 | return; | |
521 | } | |
522 | ||
d3116a08 | 523 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
524 | mci->edac_check(mci); |
525 | ||
81d87cb1 DJ |
526 | mutex_unlock(&mem_ctls_mutex); |
527 | ||
06e912d4 | 528 | /* Queue ourselves again. */ |
c4cf3b45 | 529 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
530 | } |
531 | ||
81d87cb1 | 532 | /* |
bce19683 DT |
533 | * edac_mc_reset_delay_period(unsigned long value) |
534 | * | |
535 | * user space has updated our poll period value, need to | |
536 | * reset our workq delays | |
81d87cb1 | 537 | */ |
9da21b15 | 538 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 539 | { |
bce19683 DT |
540 | struct mem_ctl_info *mci; |
541 | struct list_head *item; | |
542 | ||
543 | mutex_lock(&mem_ctls_mutex); | |
544 | ||
bce19683 DT |
545 | list_for_each(item, &mc_devices) { |
546 | mci = list_entry(item, struct mem_ctl_info, link); | |
547 | ||
fbedcaf4 NK |
548 | if (mci->op_state == OP_RUNNING_POLL) |
549 | edac_mod_work(&mci->work, value); | |
bce19683 | 550 | } |
81d87cb1 DJ |
551 | mutex_unlock(&mem_ctls_mutex); |
552 | } | |
553 | ||
bce19683 DT |
554 | |
555 | ||
2d7bbb91 DT |
556 | /* Return 0 on success, 1 on failure. |
557 | * Before calling this function, caller must | |
558 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
559 | * |
560 | * locking model: | |
561 | * | |
562 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 563 | */ |
079708b9 | 564 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
565 | { |
566 | struct list_head *item, *insert_before; | |
567 | struct mem_ctl_info *p; | |
da9bb1d2 | 568 | |
2d7bbb91 | 569 | insert_before = &mc_devices; |
da9bb1d2 | 570 | |
c73e8833 | 571 | p = __find_mci_by_dev(mci->pdev); |
bf52fa4a | 572 | if (unlikely(p != NULL)) |
2d7bbb91 | 573 | goto fail0; |
da9bb1d2 | 574 | |
2d7bbb91 DT |
575 | list_for_each(item, &mc_devices) { |
576 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 577 | |
2d7bbb91 DT |
578 | if (p->mc_idx >= mci->mc_idx) { |
579 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
580 | goto fail1; | |
da9bb1d2 | 581 | |
2d7bbb91 DT |
582 | insert_before = item; |
583 | break; | |
da9bb1d2 | 584 | } |
da9bb1d2 AC |
585 | } |
586 | ||
587 | list_add_tail_rcu(&mci->link, insert_before); | |
588 | return 0; | |
2d7bbb91 | 589 | |
052dfb45 | 590 | fail0: |
2d7bbb91 | 591 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 592 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 593 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
594 | return 1; |
595 | ||
052dfb45 | 596 | fail1: |
2d7bbb91 | 597 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
598 | "bug in low-level driver: attempt to assign\n" |
599 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 600 | return 1; |
da9bb1d2 AC |
601 | } |
602 | ||
80cc7d87 | 603 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc DP |
604 | { |
605 | list_del_rcu(&mci->link); | |
e2e77098 LJ |
606 | |
607 | /* these are for safe removal of devices from global list while | |
608 | * NMI handlers may be traversing list | |
609 | */ | |
610 | synchronize_rcu(); | |
611 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 | 612 | |
97bb6c17 | 613 | return list_empty(&mc_devices); |
a1d03fcc DP |
614 | } |
615 | ||
079708b9 | 616 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c | 617 | { |
c73e8833 | 618 | struct mem_ctl_info *mci = NULL; |
5da0831c | 619 | struct list_head *item; |
c73e8833 BP |
620 | |
621 | mutex_lock(&mem_ctls_mutex); | |
5da0831c DT |
622 | |
623 | list_for_each(item, &mc_devices) { | |
624 | mci = list_entry(item, struct mem_ctl_info, link); | |
625 | ||
626 | if (mci->mc_idx >= idx) { | |
c73e8833 BP |
627 | if (mci->mc_idx == idx) { |
628 | goto unlock; | |
629 | } | |
5da0831c DT |
630 | break; |
631 | } | |
632 | } | |
633 | ||
c73e8833 BP |
634 | unlock: |
635 | mutex_unlock(&mem_ctls_mutex); | |
636 | return mci; | |
5da0831c DT |
637 | } |
638 | EXPORT_SYMBOL(edac_mc_find); | |
639 | ||
da9bb1d2 AC |
640 | |
641 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
642 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
643 | const struct attribute_group **groups) | |
da9bb1d2 | 644 | { |
80cc7d87 | 645 | int ret = -EINVAL; |
956b9ba1 | 646 | edac_dbg(0, "\n"); |
b8f6f975 | 647 | |
88d84ac9 BP |
648 | if (mci->mc_idx >= EDAC_MAX_MCS) { |
649 | pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx); | |
650 | return -ENODEV; | |
651 | } | |
652 | ||
da9bb1d2 AC |
653 | #ifdef CONFIG_EDAC_DEBUG |
654 | if (edac_debug_level >= 3) | |
655 | edac_mc_dump_mci(mci); | |
e7ecd891 | 656 | |
da9bb1d2 AC |
657 | if (edac_debug_level >= 4) { |
658 | int i; | |
659 | ||
660 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
661 | struct csrow_info *csrow = mci->csrows[i]; |
662 | u32 nr_pages = 0; | |
da9bb1d2 | 663 | int j; |
e7ecd891 | 664 | |
6e84d359 MCC |
665 | for (j = 0; j < csrow->nr_channels; j++) |
666 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
667 | if (!nr_pages) | |
668 | continue; | |
669 | edac_mc_dump_csrow(csrow); | |
670 | for (j = 0; j < csrow->nr_channels; j++) | |
671 | if (csrow->channels[j]->dimm->nr_pages) | |
672 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 673 | } |
4275be63 | 674 | for (i = 0; i < mci->tot_dimms; i++) |
6e84d359 MCC |
675 | if (mci->dimms[i]->nr_pages) |
676 | edac_mc_dump_dimm(mci->dimms[i], i); | |
da9bb1d2 AC |
677 | } |
678 | #endif | |
63b7df91 | 679 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 680 | |
80cc7d87 MCC |
681 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
682 | ret = -EPERM; | |
683 | goto fail0; | |
684 | } | |
685 | ||
da9bb1d2 | 686 | if (add_mc_to_global_list(mci)) |
028a7b6d | 687 | goto fail0; |
da9bb1d2 AC |
688 | |
689 | /* set load time so that error rate can be tracked */ | |
690 | mci->start_time = jiffies; | |
691 | ||
88d84ac9 BP |
692 | mci->bus = &mc_bus[mci->mc_idx]; |
693 | ||
4e8d230d | 694 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 695 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 696 | "failed to create sysfs device\n"); |
9794f33d | 697 | goto fail1; |
698 | } | |
da9bb1d2 | 699 | |
09667606 | 700 | if (mci->edac_check) { |
81d87cb1 DJ |
701 | mci->op_state = OP_RUNNING_POLL; |
702 | ||
626a7a4d BP |
703 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
704 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); | |
705 | ||
81d87cb1 DJ |
706 | } else { |
707 | mci->op_state = OP_RUNNING_INTERRUPT; | |
708 | } | |
709 | ||
da9bb1d2 | 710 | /* Report action taken */ |
7270a608 RR |
711 | edac_mc_printk(mci, KERN_INFO, |
712 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
713 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
714 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 715 | |
80cc7d87 MCC |
716 | edac_mc_owner = mci->mod_name; |
717 | ||
63b7df91 | 718 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 719 | return 0; |
da9bb1d2 | 720 | |
052dfb45 | 721 | fail1: |
028a7b6d DP |
722 | del_mc_from_global_list(mci); |
723 | ||
052dfb45 | 724 | fail0: |
63b7df91 | 725 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 726 | return ret; |
da9bb1d2 | 727 | } |
4e8d230d | 728 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 729 | |
079708b9 | 730 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 731 | { |
18dbc337 | 732 | struct mem_ctl_info *mci; |
da9bb1d2 | 733 | |
956b9ba1 | 734 | edac_dbg(0, "\n"); |
bf52fa4a | 735 | |
63b7df91 | 736 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 737 | |
bf52fa4a | 738 | /* find the requested mci struct in the global list */ |
c73e8833 | 739 | mci = __find_mci_by_dev(dev); |
bf52fa4a | 740 | if (mci == NULL) { |
63b7df91 | 741 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
742 | return NULL; |
743 | } | |
744 | ||
09667606 BP |
745 | /* mark MCI offline: */ |
746 | mci->op_state = OP_OFFLINE; | |
747 | ||
97bb6c17 | 748 | if (del_mc_from_global_list(mci)) |
80cc7d87 | 749 | edac_mc_owner = NULL; |
bf52fa4a | 750 | |
09667606 | 751 | mutex_unlock(&mem_ctls_mutex); |
bb31b312 | 752 | |
09667606 | 753 | if (mci->edac_check) |
626a7a4d | 754 | edac_stop_work(&mci->work); |
bb31b312 BP |
755 | |
756 | /* remove from sysfs */ | |
bf52fa4a DT |
757 | edac_remove_sysfs_mci_device(mci); |
758 | ||
537fba28 | 759 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 760 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 761 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 762 | |
18dbc337 | 763 | return mci; |
da9bb1d2 | 764 | } |
9110540f | 765 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 766 | |
2da1c119 AB |
767 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
768 | u32 size) | |
da9bb1d2 AC |
769 | { |
770 | struct page *pg; | |
771 | void *virt_addr; | |
772 | unsigned long flags = 0; | |
773 | ||
956b9ba1 | 774 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
775 | |
776 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 777 | if (!pfn_valid(page)) |
da9bb1d2 AC |
778 | return; |
779 | ||
780 | /* Find the actual page structure then map it and fix */ | |
781 | pg = pfn_to_page(page); | |
782 | ||
783 | if (PageHighMem(pg)) | |
784 | local_irq_save(flags); | |
785 | ||
4e5df7ca | 786 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
787 | |
788 | /* Perform architecture specific atomic scrub operation */ | |
b01aec9b | 789 | edac_atomic_scrub(virt_addr + offset, size); |
da9bb1d2 AC |
790 | |
791 | /* Unmap and complete */ | |
4e5df7ca | 792 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
793 | |
794 | if (PageHighMem(pg)) | |
795 | local_irq_restore(flags); | |
796 | } | |
797 | ||
da9bb1d2 | 798 | /* FIXME - should return -1 */ |
e7ecd891 | 799 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 800 | { |
de3910eb | 801 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 802 | int row, i, j, n; |
da9bb1d2 | 803 | |
956b9ba1 | 804 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
805 | row = -1; |
806 | ||
807 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 808 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
809 | n = 0; |
810 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 811 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
812 | n += dimm->nr_pages; |
813 | } | |
814 | if (n == 0) | |
da9bb1d2 AC |
815 | continue; |
816 | ||
956b9ba1 JP |
817 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
818 | mci->mc_idx, | |
819 | csrow->first_page, page, csrow->last_page, | |
820 | csrow->page_mask); | |
da9bb1d2 AC |
821 | |
822 | if ((page >= csrow->first_page) && | |
823 | (page <= csrow->last_page) && | |
824 | ((page & csrow->page_mask) == | |
825 | (csrow->first_page & csrow->page_mask))) { | |
826 | row = i; | |
827 | break; | |
828 | } | |
829 | } | |
830 | ||
831 | if (row == -1) | |
537fba28 | 832 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
833 | "could not look up page error address %lx\n", |
834 | (unsigned long)page); | |
da9bb1d2 AC |
835 | |
836 | return row; | |
837 | } | |
9110540f | 838 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 839 | |
4275be63 MCC |
840 | const char *edac_layer_name[] = { |
841 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
842 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
843 | [EDAC_MC_LAYER_SLOT] = "slot", | |
844 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 845 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
846 | }; |
847 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
848 | ||
849 | static void edac_inc_ce_error(struct mem_ctl_info *mci, | |
9eb07a7f MCC |
850 | bool enable_per_layer_report, |
851 | const int pos[EDAC_MAX_LAYERS], | |
852 | const u16 count) | |
da9bb1d2 | 853 | { |
4275be63 | 854 | int i, index = 0; |
da9bb1d2 | 855 | |
9eb07a7f | 856 | mci->ce_mc += count; |
da9bb1d2 | 857 | |
4275be63 | 858 | if (!enable_per_layer_report) { |
9eb07a7f | 859 | mci->ce_noinfo_count += count; |
da9bb1d2 AC |
860 | return; |
861 | } | |
e7ecd891 | 862 | |
4275be63 MCC |
863 | for (i = 0; i < mci->n_layers; i++) { |
864 | if (pos[i] < 0) | |
865 | break; | |
866 | index += pos[i]; | |
9eb07a7f | 867 | mci->ce_per_layer[i][index] += count; |
4275be63 MCC |
868 | |
869 | if (i < mci->n_layers - 1) | |
870 | index *= mci->layers[i + 1].size; | |
871 | } | |
872 | } | |
873 | ||
874 | static void edac_inc_ue_error(struct mem_ctl_info *mci, | |
875 | bool enable_per_layer_report, | |
9eb07a7f MCC |
876 | const int pos[EDAC_MAX_LAYERS], |
877 | const u16 count) | |
4275be63 MCC |
878 | { |
879 | int i, index = 0; | |
880 | ||
9eb07a7f | 881 | mci->ue_mc += count; |
4275be63 MCC |
882 | |
883 | if (!enable_per_layer_report) { | |
993f88f1 | 884 | mci->ue_noinfo_count += count; |
da9bb1d2 AC |
885 | return; |
886 | } | |
887 | ||
4275be63 MCC |
888 | for (i = 0; i < mci->n_layers; i++) { |
889 | if (pos[i] < 0) | |
890 | break; | |
891 | index += pos[i]; | |
9eb07a7f | 892 | mci->ue_per_layer[i][index] += count; |
a7d7d2e1 | 893 | |
4275be63 MCC |
894 | if (i < mci->n_layers - 1) |
895 | index *= mci->layers[i + 1].size; | |
896 | } | |
897 | } | |
da9bb1d2 | 898 | |
4275be63 | 899 | static void edac_ce_error(struct mem_ctl_info *mci, |
9eb07a7f | 900 | const u16 error_count, |
4275be63 MCC |
901 | const int pos[EDAC_MAX_LAYERS], |
902 | const char *msg, | |
903 | const char *location, | |
904 | const char *label, | |
905 | const char *detail, | |
906 | const char *other_detail, | |
907 | const bool enable_per_layer_report, | |
908 | const unsigned long page_frame_number, | |
909 | const unsigned long offset_in_page, | |
53f2d028 | 910 | long grain) |
4275be63 MCC |
911 | { |
912 | unsigned long remapped_page; | |
f430d570 BP |
913 | char *msg_aux = ""; |
914 | ||
915 | if (*msg) | |
916 | msg_aux = " "; | |
4275be63 MCC |
917 | |
918 | if (edac_mc_get_log_ce()) { | |
919 | if (other_detail && *other_detail) | |
920 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
921 | "%d CE %s%son %s (%s %s - %s)\n", |
922 | error_count, msg, msg_aux, label, | |
923 | location, detail, other_detail); | |
4275be63 MCC |
924 | else |
925 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
926 | "%d CE %s%son %s (%s %s)\n", |
927 | error_count, msg, msg_aux, label, | |
928 | location, detail); | |
4275be63 | 929 | } |
9eb07a7f | 930 | edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 | 931 | |
aa2064d7 | 932 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 933 | /* |
4275be63 MCC |
934 | * Some memory controllers (called MCs below) can remap |
935 | * memory so that it is still available at a different | |
936 | * address when PCI devices map into memory. | |
937 | * MC's that can't do this, lose the memory where PCI | |
938 | * devices are mapped. This mapping is MC-dependent | |
939 | * and so we call back into the MC driver for it to | |
940 | * map the MC page to a physical (CPU) page which can | |
941 | * then be mapped to a virtual page - which can then | |
942 | * be scrubbed. | |
943 | */ | |
da9bb1d2 | 944 | remapped_page = mci->ctl_page_to_phys ? |
052dfb45 DT |
945 | mci->ctl_page_to_phys(mci, page_frame_number) : |
946 | page_frame_number; | |
da9bb1d2 | 947 | |
4275be63 MCC |
948 | edac_mc_scrub_block(remapped_page, |
949 | offset_in_page, grain); | |
da9bb1d2 AC |
950 | } |
951 | } | |
952 | ||
4275be63 | 953 | static void edac_ue_error(struct mem_ctl_info *mci, |
9eb07a7f | 954 | const u16 error_count, |
4275be63 MCC |
955 | const int pos[EDAC_MAX_LAYERS], |
956 | const char *msg, | |
957 | const char *location, | |
958 | const char *label, | |
959 | const char *detail, | |
960 | const char *other_detail, | |
961 | const bool enable_per_layer_report) | |
da9bb1d2 | 962 | { |
f430d570 BP |
963 | char *msg_aux = ""; |
964 | ||
965 | if (*msg) | |
966 | msg_aux = " "; | |
967 | ||
4275be63 MCC |
968 | if (edac_mc_get_log_ue()) { |
969 | if (other_detail && *other_detail) | |
970 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
971 | "%d UE %s%son %s (%s %s - %s)\n", |
972 | error_count, msg, msg_aux, label, | |
973 | location, detail, other_detail); | |
4275be63 MCC |
974 | else |
975 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
976 | "%d UE %s%son %s (%s %s)\n", |
977 | error_count, msg, msg_aux, label, | |
978 | location, detail); | |
4275be63 | 979 | } |
e7ecd891 | 980 | |
4275be63 MCC |
981 | if (edac_mc_get_panic_on_ue()) { |
982 | if (other_detail && *other_detail) | |
f430d570 BP |
983 | panic("UE %s%son %s (%s%s - %s)\n", |
984 | msg, msg_aux, label, location, detail, other_detail); | |
4275be63 | 985 | else |
f430d570 BP |
986 | panic("UE %s%son %s (%s%s)\n", |
987 | msg, msg_aux, label, location, detail); | |
4275be63 MCC |
988 | } |
989 | ||
9eb07a7f | 990 | edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 AC |
991 | } |
992 | ||
e7e24830 MCC |
993 | void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, |
994 | struct mem_ctl_info *mci, | |
995 | struct edac_raw_error_desc *e) | |
996 | { | |
997 | char detail[80]; | |
998 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; | |
999 | ||
1000 | /* Memory type dependent details about the error */ | |
1001 | if (type == HW_EVENT_ERR_CORRECTED) { | |
1002 | snprintf(detail, sizeof(detail), | |
1003 | "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", | |
1004 | e->page_frame_number, e->offset_in_page, | |
1005 | e->grain, e->syndrome); | |
1006 | edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1007 | detail, e->other_detail, e->enable_per_layer_report, | |
1008 | e->page_frame_number, e->offset_in_page, e->grain); | |
1009 | } else { | |
1010 | snprintf(detail, sizeof(detail), | |
1011 | "page:0x%lx offset:0x%lx grain:%ld", | |
1012 | e->page_frame_number, e->offset_in_page, e->grain); | |
1013 | ||
1014 | edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1015 | detail, e->other_detail, e->enable_per_layer_report); | |
1016 | } | |
1017 | ||
1018 | ||
1019 | } | |
1020 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 | 1021 | |
4275be63 MCC |
1022 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
1023 | struct mem_ctl_info *mci, | |
9eb07a7f | 1024 | const u16 error_count, |
4275be63 MCC |
1025 | const unsigned long page_frame_number, |
1026 | const unsigned long offset_in_page, | |
1027 | const unsigned long syndrome, | |
53f2d028 MCC |
1028 | const int top_layer, |
1029 | const int mid_layer, | |
1030 | const int low_layer, | |
4275be63 | 1031 | const char *msg, |
03f7eae8 | 1032 | const char *other_detail) |
da9bb1d2 | 1033 | { |
4275be63 MCC |
1034 | char *p; |
1035 | int row = -1, chan = -1; | |
53f2d028 | 1036 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 1037 | int i, n_labels = 0; |
53f2d028 | 1038 | u8 grain_bits; |
c7ef7645 | 1039 | struct edac_raw_error_desc *e = &mci->error_desc; |
da9bb1d2 | 1040 | |
956b9ba1 | 1041 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 1042 | |
c7ef7645 MCC |
1043 | /* Fills the error report buffer */ |
1044 | memset(e, 0, sizeof (*e)); | |
1045 | e->error_count = error_count; | |
1046 | e->top_layer = top_layer; | |
1047 | e->mid_layer = mid_layer; | |
1048 | e->low_layer = low_layer; | |
1049 | e->page_frame_number = page_frame_number; | |
1050 | e->offset_in_page = offset_in_page; | |
1051 | e->syndrome = syndrome; | |
1052 | e->msg = msg; | |
1053 | e->other_detail = other_detail; | |
1054 | ||
4275be63 MCC |
1055 | /* |
1056 | * Check if the event report is consistent and if the memory | |
1057 | * location is known. If it is known, enable_per_layer_report will be | |
1058 | * true, the DIMM(s) label info will be filled and the per-layer | |
1059 | * error counters will be incremented. | |
1060 | */ | |
1061 | for (i = 0; i < mci->n_layers; i++) { | |
1062 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
1063 | |
1064 | edac_mc_printk(mci, KERN_ERR, | |
1065 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
1066 | edac_layer_name[mci->layers[i].type], | |
1067 | pos[i], mci->layers[i].size); | |
1068 | /* | |
1069 | * Instead of just returning it, let's use what's | |
1070 | * known about the error. The increment routines and | |
1071 | * the DIMM filter logic will do the right thing by | |
1072 | * pointing the likely damaged DIMMs. | |
1073 | */ | |
1074 | pos[i] = -1; | |
1075 | } | |
1076 | if (pos[i] >= 0) | |
c7ef7645 | 1077 | e->enable_per_layer_report = true; |
da9bb1d2 AC |
1078 | } |
1079 | ||
4275be63 MCC |
1080 | /* |
1081 | * Get the dimm label/grain that applies to the match criteria. | |
1082 | * As the error algorithm may not be able to point to just one memory | |
1083 | * stick, the logic here will get all possible labels that could | |
1084 | * pottentially be affected by the error. | |
1085 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1086 | * to have only the MC channel and the MC dimm (also called "branch") | |
1087 | * but the channel is not known, as the memory is arranged in pairs, | |
1088 | * where each memory belongs to a separate channel within the same | |
1089 | * branch. | |
1090 | */ | |
c7ef7645 | 1091 | p = e->label; |
4275be63 | 1092 | *p = '\0'; |
4da1b7bf | 1093 | |
4275be63 | 1094 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1095 | struct dimm_info *dimm = mci->dimms[i]; |
da9bb1d2 | 1096 | |
53f2d028 | 1097 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1098 | continue; |
53f2d028 | 1099 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1100 | continue; |
53f2d028 | 1101 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1102 | continue; |
da9bb1d2 | 1103 | |
4275be63 | 1104 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1105 | if (dimm->grain > e->grain) |
1106 | e->grain = dimm->grain; | |
9794f33d | 1107 | |
4275be63 MCC |
1108 | /* |
1109 | * If the error is memory-controller wide, there's no need to | |
1110 | * seek for the affected DIMMs because the whole | |
1111 | * channel/memory controller/... may be affected. | |
1112 | * Also, don't show errors for empty DIMM slots. | |
1113 | */ | |
c7ef7645 MCC |
1114 | if (e->enable_per_layer_report && dimm->nr_pages) { |
1115 | if (n_labels >= EDAC_MAX_LABELS) { | |
1116 | e->enable_per_layer_report = false; | |
1117 | break; | |
1118 | } | |
1119 | n_labels++; | |
1120 | if (p != e->label) { | |
4275be63 MCC |
1121 | strcpy(p, OTHER_LABEL); |
1122 | p += strlen(OTHER_LABEL); | |
1123 | } | |
1124 | strcpy(p, dimm->label); | |
1125 | p += strlen(p); | |
1126 | *p = '\0'; | |
1127 | ||
1128 | /* | |
1129 | * get csrow/channel of the DIMM, in order to allow | |
1130 | * incrementing the compat API counters | |
1131 | */ | |
956b9ba1 | 1132 | edac_dbg(4, "%s csrows map: (%d,%d)\n", |
9713faec | 1133 | mci->csbased ? "rank" : "dimm", |
956b9ba1 | 1134 | dimm->csrow, dimm->cschannel); |
4275be63 MCC |
1135 | if (row == -1) |
1136 | row = dimm->csrow; | |
1137 | else if (row >= 0 && row != dimm->csrow) | |
1138 | row = -2; | |
1139 | ||
1140 | if (chan == -1) | |
1141 | chan = dimm->cschannel; | |
1142 | else if (chan >= 0 && chan != dimm->cschannel) | |
1143 | chan = -2; | |
1144 | } | |
9794f33d | 1145 | } |
1146 | ||
c7ef7645 MCC |
1147 | if (!e->enable_per_layer_report) { |
1148 | strcpy(e->label, "any memory"); | |
4275be63 | 1149 | } else { |
956b9ba1 | 1150 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); |
c7ef7645 MCC |
1151 | if (p == e->label) |
1152 | strcpy(e->label, "unknown memory"); | |
4275be63 MCC |
1153 | if (type == HW_EVENT_ERR_CORRECTED) { |
1154 | if (row >= 0) { | |
9eb07a7f | 1155 | mci->csrows[row]->ce_count += error_count; |
4275be63 | 1156 | if (chan >= 0) |
9eb07a7f | 1157 | mci->csrows[row]->channels[chan]->ce_count += error_count; |
4275be63 MCC |
1158 | } |
1159 | } else | |
1160 | if (row >= 0) | |
9eb07a7f | 1161 | mci->csrows[row]->ue_count += error_count; |
9794f33d | 1162 | } |
1163 | ||
4275be63 | 1164 | /* Fill the RAM location data */ |
c7ef7645 | 1165 | p = e->location; |
4da1b7bf | 1166 | |
4275be63 MCC |
1167 | for (i = 0; i < mci->n_layers; i++) { |
1168 | if (pos[i] < 0) | |
1169 | continue; | |
9794f33d | 1170 | |
4275be63 MCC |
1171 | p += sprintf(p, "%s:%d ", |
1172 | edac_layer_name[mci->layers[i].type], | |
1173 | pos[i]); | |
9794f33d | 1174 | } |
c7ef7645 | 1175 | if (p > e->location) |
53f2d028 MCC |
1176 | *(p - 1) = '\0'; |
1177 | ||
1178 | /* Report the error via the trace interface */ | |
c7ef7645 MCC |
1179 | grain_bits = fls_long(e->grain) + 1; |
1180 | trace_mc_event(type, e->msg, e->label, e->error_count, | |
1181 | mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, | |
990995ba | 1182 | (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, |
e7e24830 | 1183 | grain_bits, e->syndrome, e->other_detail); |
a7d7d2e1 | 1184 | |
e7e24830 | 1185 | edac_raw_mc_handle_error(type, mci, e); |
9794f33d | 1186 | } |
4275be63 | 1187 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |