Commit | Line | Data |
---|---|---|
da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
da9bb1d2 | 32 | #include <asm/page.h> |
78d88e8a | 33 | #include "edac_mc.h" |
7c9281d7 | 34 | #include "edac_module.h" |
53f2d028 MCC |
35 | #include <ras/ras_event.h> |
36 | ||
b01aec9b BP |
37 | #ifdef CONFIG_EDAC_ATOMIC_SCRUB |
38 | #include <asm/edac.h> | |
39 | #else | |
40 | #define edac_atomic_scrub(va, size) do { } while (0) | |
41 | #endif | |
42 | ||
8c22b4fe BP |
43 | int edac_op_state = EDAC_OPSTATE_INVAL; |
44 | EXPORT_SYMBOL_GPL(edac_op_state); | |
45 | ||
da9bb1d2 | 46 | /* lock to memory controller's control array */ |
63b7df91 | 47 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 48 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 49 | |
80cc7d87 MCC |
50 | /* |
51 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
52 | * apei/ghes and i7core_edac to be used at the same time. | |
53 | */ | |
3877c7d1 | 54 | static const char *edac_mc_owner; |
80cc7d87 | 55 | |
91b327f6 RR |
56 | static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e) |
57 | { | |
58 | return container_of(e, struct mem_ctl_info, error_desc); | |
59 | } | |
60 | ||
d55c79ac RR |
61 | unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
62 | unsigned int len) | |
6e84d359 MCC |
63 | { |
64 | struct mem_ctl_info *mci = dimm->mci; | |
65 | int i, n, count = 0; | |
66 | char *p = buf; | |
67 | ||
68 | for (i = 0; i < mci->n_layers; i++) { | |
fca61165 | 69 | n = scnprintf(p, len, "%s %d ", |
6e84d359 MCC |
70 | edac_layer_name[mci->layers[i].type], |
71 | dimm->location[i]); | |
72 | p += n; | |
73 | len -= n; | |
74 | count += n; | |
6e84d359 MCC |
75 | } |
76 | ||
77 | return count; | |
78 | } | |
79 | ||
da9bb1d2 AC |
80 | #ifdef CONFIG_EDAC_DEBUG |
81 | ||
a4b4be3f | 82 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 83 | { |
6e84d359 MCC |
84 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
85 | edac_dbg(4, " channel = %p\n", chan); | |
86 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
87 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
88 | } |
89 | ||
c498afaf | 90 | static void edac_mc_dump_dimm(struct dimm_info *dimm) |
4275be63 | 91 | { |
6e84d359 MCC |
92 | char location[80]; |
93 | ||
c498afaf RR |
94 | if (!dimm->nr_pages) |
95 | return; | |
96 | ||
6e84d359 MCC |
97 | edac_dimm_info_location(dimm, location, sizeof(location)); |
98 | ||
99 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 100 | dimm->mci->csbased ? "rank" : "dimm", |
c498afaf | 101 | dimm->idx, location, dimm->csrow, dimm->cschannel); |
6e84d359 MCC |
102 | edac_dbg(4, " dimm = %p\n", dimm); |
103 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
104 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
105 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
106 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
107 | } |
108 | ||
2da1c119 | 109 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 110 | { |
6e84d359 MCC |
111 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
112 | edac_dbg(4, " csrow = %p\n", csrow); | |
113 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
114 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
115 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
116 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
117 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
118 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
119 | } |
120 | ||
2da1c119 | 121 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 122 | { |
956b9ba1 JP |
123 | edac_dbg(3, "\tmci = %p\n", mci); |
124 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
125 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
126 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
127 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
128 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
129 | mci->nr_csrows, mci->csrows); | |
130 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
131 | mci->tot_dimms, mci->dimms); | |
132 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
133 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
134 | mci->mod_name, mci->ctl_name); | |
135 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
136 | } |
137 | ||
24f9a7fe BP |
138 | #endif /* CONFIG_EDAC_DEBUG */ |
139 | ||
f4ce6eca | 140 | const char * const edac_mem_types[] = { |
d6dd77eb TL |
141 | [MEM_EMPTY] = "Empty", |
142 | [MEM_RESERVED] = "Reserved", | |
143 | [MEM_UNKNOWN] = "Unknown", | |
144 | [MEM_FPM] = "FPM", | |
145 | [MEM_EDO] = "EDO", | |
146 | [MEM_BEDO] = "BEDO", | |
147 | [MEM_SDR] = "Unbuffered-SDR", | |
148 | [MEM_RDR] = "Registered-SDR", | |
149 | [MEM_DDR] = "Unbuffered-DDR", | |
150 | [MEM_RDDR] = "Registered-DDR", | |
151 | [MEM_RMBS] = "RMBS", | |
152 | [MEM_DDR2] = "Unbuffered-DDR2", | |
153 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
154 | [MEM_RDDR2] = "Registered-DDR2", | |
155 | [MEM_XDR] = "XDR", | |
156 | [MEM_DDR3] = "Unbuffered-DDR3", | |
157 | [MEM_RDDR3] = "Registered-DDR3", | |
158 | [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM", | |
3b203693 | 159 | [MEM_LPDDR3] = "Low-Power-DDR3-RAM", |
d6dd77eb | 160 | [MEM_DDR4] = "Unbuffered-DDR4", |
001f8613 | 161 | [MEM_RDDR4] = "Registered-DDR4", |
3b203693 | 162 | [MEM_LPDDR4] = "Low-Power-DDR4-RAM", |
b748f2de | 163 | [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM", |
bc1c99a5 | 164 | [MEM_DDR5] = "Unbuffered-DDR5", |
001f8613 | 165 | [MEM_NVDIMM] = "Non-volatile-RAM", |
3b203693 | 166 | [MEM_WIO2] = "Wide-IO-2", |
e1ca90b7 | 167 | [MEM_HBM2] = "High-bandwidth-memory-Gen2", |
239642fe BP |
168 | }; |
169 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
170 | ||
93e4fe64 MCC |
171 | /** |
172 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation | |
173 | * @p: pointer to a pointer with the memory offset to be used. At | |
174 | * return, this will be incremented to point to the next offset | |
175 | * @size: Size of the data structure to be reserved | |
176 | * @n_elems: Number of elements that should be reserved | |
da9bb1d2 AC |
177 | * |
178 | * If 'size' is a constant, the compiler will optimize this whole function | |
93e4fe64 MCC |
179 | * down to either a no-op or the addition of a constant to the value of '*p'. |
180 | * | |
181 | * The 'p' pointer is absolutely needed to keep the proper advancing | |
182 | * further in memory to the proper offsets when allocating the struct along | |
183 | * with its embedded structs, as edac_device_alloc_ctl_info() does it | |
184 | * above, for example. | |
185 | * | |
186 | * At return, the pointer 'p' will be incremented to be used on a next call | |
187 | * to this function. | |
da9bb1d2 | 188 | */ |
d55c79ac | 189 | void *edac_align_ptr(void **p, unsigned int size, int n_elems) |
da9bb1d2 | 190 | { |
d55c79ac | 191 | unsigned int align, r; |
93e4fe64 | 192 | void *ptr = *p; |
da9bb1d2 | 193 | |
93e4fe64 MCC |
194 | *p += size * n_elems; |
195 | ||
196 | /* | |
197 | * 'p' can possibly be an unaligned item X such that sizeof(X) is | |
198 | * 'size'. Adjust 'p' so that its alignment is at least as | |
199 | * stringent as what the compiler would provide for X and return | |
200 | * the aligned result. | |
201 | * Here we assume that the alignment of a "long long" is the most | |
da9bb1d2 AC |
202 | * stringent alignment that the compiler will ever provide by default. |
203 | * As far as I know, this is a reasonable assumption. | |
204 | */ | |
205 | if (size > sizeof(long)) | |
206 | align = sizeof(long long); | |
207 | else if (size > sizeof(int)) | |
208 | align = sizeof(long); | |
209 | else if (size > sizeof(short)) | |
210 | align = sizeof(int); | |
211 | else if (size > sizeof(char)) | |
212 | align = sizeof(short); | |
213 | else | |
079708b9 | 214 | return (char *)ptr; |
da9bb1d2 | 215 | |
8447c4d1 | 216 | r = (unsigned long)p % align; |
da9bb1d2 AC |
217 | |
218 | if (r == 0) | |
079708b9 | 219 | return (char *)ptr; |
da9bb1d2 | 220 | |
93e4fe64 MCC |
221 | *p += align - r; |
222 | ||
7391c6dc | 223 | return (void *)(((unsigned long)ptr) + align - r); |
da9bb1d2 AC |
224 | } |
225 | ||
faa2ad09 SR |
226 | static void _edac_mc_free(struct mem_ctl_info *mci) |
227 | { | |
bea1bfd5 RR |
228 | put_device(&mci->dev); |
229 | } | |
230 | ||
231 | static void mci_release(struct device *dev) | |
232 | { | |
233 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); | |
faa2ad09 | 234 | struct csrow_info *csr; |
718d5851 | 235 | int i, chn, row; |
faa2ad09 SR |
236 | |
237 | if (mci->dimms) { | |
718d5851 | 238 | for (i = 0; i < mci->tot_dimms; i++) |
faa2ad09 SR |
239 | kfree(mci->dimms[i]); |
240 | kfree(mci->dimms); | |
241 | } | |
718d5851 | 242 | |
faa2ad09 | 243 | if (mci->csrows) { |
718d5851 | 244 | for (row = 0; row < mci->nr_csrows; row++) { |
faa2ad09 | 245 | csr = mci->csrows[row]; |
718d5851 RR |
246 | if (!csr) |
247 | continue; | |
248 | ||
249 | if (csr->channels) { | |
250 | for (chn = 0; chn < mci->num_cschannel; chn++) | |
251 | kfree(csr->channels[chn]); | |
252 | kfree(csr->channels); | |
faa2ad09 | 253 | } |
718d5851 | 254 | kfree(csr); |
faa2ad09 SR |
255 | } |
256 | kfree(mci->csrows); | |
257 | } | |
258 | kfree(mci); | |
259 | } | |
260 | ||
aad28c6f RR |
261 | static int edac_mc_alloc_csrows(struct mem_ctl_info *mci) |
262 | { | |
263 | unsigned int tot_channels = mci->num_cschannel; | |
264 | unsigned int tot_csrows = mci->nr_csrows; | |
265 | unsigned int row, chn; | |
266 | ||
a7d7d2e1 | 267 | /* |
de3910eb | 268 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 269 | */ |
d3d09e18 | 270 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb | 271 | if (!mci->csrows) |
aad28c6f RR |
272 | return -ENOMEM; |
273 | ||
4275be63 | 274 | for (row = 0; row < tot_csrows; row++) { |
aad28c6f RR |
275 | struct csrow_info *csr; |
276 | ||
de3910eb MCC |
277 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
278 | if (!csr) | |
aad28c6f RR |
279 | return -ENOMEM; |
280 | ||
de3910eb | 281 | mci->csrows[row] = csr; |
4275be63 MCC |
282 | csr->csrow_idx = row; |
283 | csr->mci = mci; | |
284 | csr->nr_channels = tot_channels; | |
d3d09e18 | 285 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
286 | GFP_KERNEL); |
287 | if (!csr->channels) | |
aad28c6f | 288 | return -ENOMEM; |
4275be63 MCC |
289 | |
290 | for (chn = 0; chn < tot_channels; chn++) { | |
aad28c6f RR |
291 | struct rank_info *chan; |
292 | ||
de3910eb MCC |
293 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
294 | if (!chan) | |
aad28c6f RR |
295 | return -ENOMEM; |
296 | ||
de3910eb | 297 | csr->channels[chn] = chan; |
da9bb1d2 | 298 | chan->chan_idx = chn; |
4275be63 MCC |
299 | chan->csrow = csr; |
300 | } | |
301 | } | |
302 | ||
aad28c6f RR |
303 | return 0; |
304 | } | |
305 | ||
306 | static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) | |
307 | { | |
308 | unsigned int pos[EDAC_MAX_LAYERS]; | |
309 | unsigned int row, chn, idx; | |
310 | int layer; | |
311 | void *p; | |
312 | ||
4275be63 | 313 | /* |
de3910eb | 314 | * Allocate and fill the dimm structs |
4275be63 | 315 | */ |
aad28c6f | 316 | mci->dimms = kcalloc(mci->tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb | 317 | if (!mci->dimms) |
aad28c6f | 318 | return -ENOMEM; |
de3910eb | 319 | |
4275be63 MCC |
320 | memset(&pos, 0, sizeof(pos)); |
321 | row = 0; | |
322 | chn = 0; | |
aad28c6f RR |
323 | for (idx = 0; idx < mci->tot_dimms; idx++) { |
324 | struct dimm_info *dimm; | |
325 | struct rank_info *chan; | |
326 | int n, len; | |
327 | ||
de3910eb | 328 | chan = mci->csrows[row]->channels[chn]; |
4275be63 | 329 | |
de3910eb | 330 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 | 331 | if (!dimm) |
aad28c6f | 332 | return -ENOMEM; |
977b1ce7 | 333 | mci->dimms[idx] = dimm; |
4275be63 | 334 | dimm->mci = mci; |
977b1ce7 | 335 | dimm->idx = idx; |
4275be63 | 336 | |
5926ff50 MCC |
337 | /* |
338 | * Copy DIMM location and initialize it. | |
339 | */ | |
340 | len = sizeof(dimm->label); | |
341 | p = dimm->label; | |
fca61165 | 342 | n = scnprintf(p, len, "mc#%u", mci->mc_idx); |
5926ff50 MCC |
343 | p += n; |
344 | len -= n; | |
aad28c6f | 345 | for (layer = 0; layer < mci->n_layers; layer++) { |
fca61165 LB |
346 | n = scnprintf(p, len, "%s#%u", |
347 | edac_layer_name[mci->layers[layer].type], | |
348 | pos[layer]); | |
5926ff50 MCC |
349 | p += n; |
350 | len -= n; | |
aad28c6f | 351 | dimm->location[layer] = pos[layer]; |
5926ff50 MCC |
352 | } |
353 | ||
4275be63 MCC |
354 | /* Link it to the csrows old API data */ |
355 | chan->dimm = dimm; | |
356 | dimm->csrow = row; | |
357 | dimm->cschannel = chn; | |
358 | ||
359 | /* Increment csrow location */ | |
aad28c6f | 360 | if (mci->layers[0].is_virt_csrow) { |
4275be63 | 361 | chn++; |
aad28c6f | 362 | if (chn == mci->num_cschannel) { |
24bef66e MCC |
363 | chn = 0; |
364 | row++; | |
365 | } | |
366 | } else { | |
367 | row++; | |
aad28c6f | 368 | if (row == mci->nr_csrows) { |
24bef66e MCC |
369 | row = 0; |
370 | chn++; | |
371 | } | |
4275be63 | 372 | } |
a7d7d2e1 | 373 | |
4275be63 | 374 | /* Increment dimm location */ |
aad28c6f RR |
375 | for (layer = mci->n_layers - 1; layer >= 0; layer--) { |
376 | pos[layer]++; | |
377 | if (pos[layer] < mci->layers[layer].size) | |
4275be63 | 378 | break; |
aad28c6f | 379 | pos[layer] = 0; |
da9bb1d2 AC |
380 | } |
381 | } | |
382 | ||
aad28c6f | 383 | return 0; |
4275be63 | 384 | } |
da9bb1d2 | 385 | |
1f27c790 RR |
386 | struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, |
387 | unsigned int n_layers, | |
388 | struct edac_mc_layer *layers, | |
389 | unsigned int sz_pvt) | |
390 | { | |
391 | struct mem_ctl_info *mci; | |
392 | struct edac_mc_layer *layer; | |
4aa92c86 RR |
393 | unsigned int idx, size, tot_dimms = 1; |
394 | unsigned int tot_csrows = 1, tot_channels = 1; | |
1f27c790 | 395 | void *pvt, *ptr = NULL; |
1f27c790 RR |
396 | bool per_rank = false; |
397 | ||
398 | if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) | |
399 | return NULL; | |
400 | ||
401 | /* | |
402 | * Calculate the total amount of dimms and csrows/cschannels while | |
403 | * in the old API emulation mode | |
404 | */ | |
405 | for (idx = 0; idx < n_layers; idx++) { | |
406 | tot_dimms *= layers[idx].size; | |
407 | ||
408 | if (layers[idx].is_virt_csrow) | |
409 | tot_csrows *= layers[idx].size; | |
410 | else | |
411 | tot_channels *= layers[idx].size; | |
412 | ||
413 | if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) | |
414 | per_rank = true; | |
415 | } | |
416 | ||
417 | /* Figure out the offsets of the various items from the start of an mc | |
418 | * structure. We want the alignment of each item to be at least as | |
419 | * stringent as what the compiler would provide if we could simply | |
420 | * hardcode everything into a single struct. | |
421 | */ | |
4aa92c86 RR |
422 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
423 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); | |
424 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); | |
425 | size = ((unsigned long)pvt) + sz_pvt; | |
1f27c790 RR |
426 | |
427 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", | |
428 | size, | |
429 | tot_dimms, | |
430 | per_rank ? "ranks" : "dimms", | |
431 | tot_csrows * tot_channels); | |
432 | ||
433 | mci = kzalloc(size, GFP_KERNEL); | |
434 | if (mci == NULL) | |
435 | return NULL; | |
436 | ||
437 | mci->dev.release = mci_release; | |
438 | device_initialize(&mci->dev); | |
439 | ||
440 | /* Adjust pointers so they point within the memory we just allocated | |
441 | * rather than an imaginary chunk of memory located at address 0. | |
442 | */ | |
443 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); | |
1f27c790 RR |
444 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
445 | ||
446 | /* setup index and various internal pointers */ | |
447 | mci->mc_idx = mc_num; | |
448 | mci->tot_dimms = tot_dimms; | |
449 | mci->pvt_info = pvt; | |
450 | mci->n_layers = n_layers; | |
451 | mci->layers = layer; | |
452 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); | |
453 | mci->nr_csrows = tot_csrows; | |
454 | mci->num_cschannel = tot_channels; | |
455 | mci->csbased = per_rank; | |
456 | ||
457 | if (edac_mc_alloc_csrows(mci)) | |
458 | goto error; | |
459 | ||
460 | if (edac_mc_alloc_dimms(mci)) | |
461 | goto error; | |
462 | ||
463 | mci->op_state = OP_ALLOC; | |
464 | ||
465 | return mci; | |
466 | ||
467 | error: | |
468 | _edac_mc_free(mci); | |
469 | ||
470 | return NULL; | |
471 | } | |
472 | EXPORT_SYMBOL_GPL(edac_mc_alloc); | |
473 | ||
da9bb1d2 AC |
474 | void edac_mc_free(struct mem_ctl_info *mci) |
475 | { | |
956b9ba1 | 476 | edac_dbg(1, "\n"); |
bbc560ae | 477 | |
216aa145 | 478 | _edac_mc_free(mci); |
da9bb1d2 | 479 | } |
9110540f | 480 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 481 | |
d7fc9d77 YG |
482 | bool edac_has_mcs(void) |
483 | { | |
484 | bool ret; | |
485 | ||
486 | mutex_lock(&mem_ctls_mutex); | |
487 | ||
488 | ret = list_empty(&mc_devices); | |
489 | ||
490 | mutex_unlock(&mem_ctls_mutex); | |
491 | ||
492 | return !ret; | |
493 | } | |
494 | EXPORT_SYMBOL_GPL(edac_has_mcs); | |
495 | ||
c73e8833 BP |
496 | /* Caller must hold mem_ctls_mutex */ |
497 | static struct mem_ctl_info *__find_mci_by_dev(struct device *dev) | |
da9bb1d2 AC |
498 | { |
499 | struct mem_ctl_info *mci; | |
500 | struct list_head *item; | |
501 | ||
956b9ba1 | 502 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
503 | |
504 | list_for_each(item, &mc_devices) { | |
505 | mci = list_entry(item, struct mem_ctl_info, link); | |
506 | ||
fd687502 | 507 | if (mci->pdev == dev) |
da9bb1d2 AC |
508 | return mci; |
509 | } | |
510 | ||
511 | return NULL; | |
512 | } | |
c73e8833 BP |
513 | |
514 | /** | |
515 | * find_mci_by_dev | |
516 | * | |
517 | * scan list of controllers looking for the one that manages | |
518 | * the 'dev' device | |
519 | * @dev: pointer to a struct device related with the MCI | |
520 | */ | |
521 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) | |
522 | { | |
523 | struct mem_ctl_info *ret; | |
524 | ||
525 | mutex_lock(&mem_ctls_mutex); | |
526 | ret = __find_mci_by_dev(dev); | |
527 | mutex_unlock(&mem_ctls_mutex); | |
528 | ||
529 | return ret; | |
530 | } | |
939747bd | 531 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 532 | |
81d87cb1 DJ |
533 | /* |
534 | * edac_mc_workq_function | |
535 | * performs the operation scheduled by a workq request | |
536 | */ | |
81d87cb1 DJ |
537 | static void edac_mc_workq_function(struct work_struct *work_req) |
538 | { | |
fbeb4384 | 539 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 540 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
541 | |
542 | mutex_lock(&mem_ctls_mutex); | |
543 | ||
06e912d4 | 544 | if (mci->op_state != OP_RUNNING_POLL) { |
bf52fa4a DT |
545 | mutex_unlock(&mem_ctls_mutex); |
546 | return; | |
547 | } | |
548 | ||
d3116a08 | 549 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
550 | mci->edac_check(mci); |
551 | ||
81d87cb1 DJ |
552 | mutex_unlock(&mem_ctls_mutex); |
553 | ||
06e912d4 | 554 | /* Queue ourselves again. */ |
c4cf3b45 | 555 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
556 | } |
557 | ||
81d87cb1 | 558 | /* |
bce19683 DT |
559 | * edac_mc_reset_delay_period(unsigned long value) |
560 | * | |
561 | * user space has updated our poll period value, need to | |
562 | * reset our workq delays | |
81d87cb1 | 563 | */ |
9da21b15 | 564 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 565 | { |
bce19683 DT |
566 | struct mem_ctl_info *mci; |
567 | struct list_head *item; | |
568 | ||
569 | mutex_lock(&mem_ctls_mutex); | |
570 | ||
bce19683 DT |
571 | list_for_each(item, &mc_devices) { |
572 | mci = list_entry(item, struct mem_ctl_info, link); | |
573 | ||
fbedcaf4 NK |
574 | if (mci->op_state == OP_RUNNING_POLL) |
575 | edac_mod_work(&mci->work, value); | |
bce19683 | 576 | } |
81d87cb1 DJ |
577 | mutex_unlock(&mem_ctls_mutex); |
578 | } | |
579 | ||
bce19683 DT |
580 | |
581 | ||
2d7bbb91 DT |
582 | /* Return 0 on success, 1 on failure. |
583 | * Before calling this function, caller must | |
584 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
585 | * |
586 | * locking model: | |
587 | * | |
588 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 589 | */ |
079708b9 | 590 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
591 | { |
592 | struct list_head *item, *insert_before; | |
593 | struct mem_ctl_info *p; | |
da9bb1d2 | 594 | |
2d7bbb91 | 595 | insert_before = &mc_devices; |
da9bb1d2 | 596 | |
c73e8833 | 597 | p = __find_mci_by_dev(mci->pdev); |
bf52fa4a | 598 | if (unlikely(p != NULL)) |
2d7bbb91 | 599 | goto fail0; |
da9bb1d2 | 600 | |
2d7bbb91 DT |
601 | list_for_each(item, &mc_devices) { |
602 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 603 | |
2d7bbb91 DT |
604 | if (p->mc_idx >= mci->mc_idx) { |
605 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
606 | goto fail1; | |
da9bb1d2 | 607 | |
2d7bbb91 DT |
608 | insert_before = item; |
609 | break; | |
da9bb1d2 | 610 | } |
da9bb1d2 AC |
611 | } |
612 | ||
613 | list_add_tail_rcu(&mci->link, insert_before); | |
614 | return 0; | |
2d7bbb91 | 615 | |
052dfb45 | 616 | fail0: |
2d7bbb91 | 617 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 618 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 619 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
620 | return 1; |
621 | ||
052dfb45 | 622 | fail1: |
2d7bbb91 | 623 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
624 | "bug in low-level driver: attempt to assign\n" |
625 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 626 | return 1; |
da9bb1d2 AC |
627 | } |
628 | ||
80cc7d87 | 629 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc DP |
630 | { |
631 | list_del_rcu(&mci->link); | |
e2e77098 LJ |
632 | |
633 | /* these are for safe removal of devices from global list while | |
634 | * NMI handlers may be traversing list | |
635 | */ | |
636 | synchronize_rcu(); | |
637 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 | 638 | |
97bb6c17 | 639 | return list_empty(&mc_devices); |
a1d03fcc DP |
640 | } |
641 | ||
079708b9 | 642 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c | 643 | { |
29a0c843 | 644 | struct mem_ctl_info *mci; |
5da0831c | 645 | struct list_head *item; |
c73e8833 BP |
646 | |
647 | mutex_lock(&mem_ctls_mutex); | |
5da0831c DT |
648 | |
649 | list_for_each(item, &mc_devices) { | |
650 | mci = list_entry(item, struct mem_ctl_info, link); | |
29a0c843 RR |
651 | if (mci->mc_idx == idx) |
652 | goto unlock; | |
5da0831c DT |
653 | } |
654 | ||
29a0c843 | 655 | mci = NULL; |
c73e8833 BP |
656 | unlock: |
657 | mutex_unlock(&mem_ctls_mutex); | |
658 | return mci; | |
5da0831c DT |
659 | } |
660 | EXPORT_SYMBOL(edac_mc_find); | |
661 | ||
3877c7d1 TK |
662 | const char *edac_get_owner(void) |
663 | { | |
664 | return edac_mc_owner; | |
665 | } | |
666 | EXPORT_SYMBOL_GPL(edac_get_owner); | |
da9bb1d2 AC |
667 | |
668 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
669 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
670 | const struct attribute_group **groups) | |
da9bb1d2 | 671 | { |
80cc7d87 | 672 | int ret = -EINVAL; |
956b9ba1 | 673 | edac_dbg(0, "\n"); |
b8f6f975 | 674 | |
da9bb1d2 AC |
675 | #ifdef CONFIG_EDAC_DEBUG |
676 | if (edac_debug_level >= 3) | |
677 | edac_mc_dump_mci(mci); | |
e7ecd891 | 678 | |
da9bb1d2 | 679 | if (edac_debug_level >= 4) { |
c498afaf | 680 | struct dimm_info *dimm; |
da9bb1d2 AC |
681 | int i; |
682 | ||
683 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
684 | struct csrow_info *csrow = mci->csrows[i]; |
685 | u32 nr_pages = 0; | |
da9bb1d2 | 686 | int j; |
e7ecd891 | 687 | |
6e84d359 MCC |
688 | for (j = 0; j < csrow->nr_channels; j++) |
689 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
690 | if (!nr_pages) | |
691 | continue; | |
692 | edac_mc_dump_csrow(csrow); | |
693 | for (j = 0; j < csrow->nr_channels; j++) | |
694 | if (csrow->channels[j]->dimm->nr_pages) | |
695 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 696 | } |
c498afaf RR |
697 | |
698 | mci_for_each_dimm(mci, dimm) | |
699 | edac_mc_dump_dimm(dimm); | |
da9bb1d2 AC |
700 | } |
701 | #endif | |
63b7df91 | 702 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 703 | |
80cc7d87 MCC |
704 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
705 | ret = -EPERM; | |
706 | goto fail0; | |
707 | } | |
708 | ||
da9bb1d2 | 709 | if (add_mc_to_global_list(mci)) |
028a7b6d | 710 | goto fail0; |
da9bb1d2 AC |
711 | |
712 | /* set load time so that error rate can be tracked */ | |
713 | mci->start_time = jiffies; | |
714 | ||
861e6ed6 | 715 | mci->bus = edac_get_sysfs_subsys(); |
88d84ac9 | 716 | |
4e8d230d | 717 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 718 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 719 | "failed to create sysfs device\n"); |
9794f33d | 720 | goto fail1; |
721 | } | |
da9bb1d2 | 722 | |
09667606 | 723 | if (mci->edac_check) { |
81d87cb1 DJ |
724 | mci->op_state = OP_RUNNING_POLL; |
725 | ||
626a7a4d BP |
726 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
727 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); | |
728 | ||
81d87cb1 DJ |
729 | } else { |
730 | mci->op_state = OP_RUNNING_INTERRUPT; | |
731 | } | |
732 | ||
da9bb1d2 | 733 | /* Report action taken */ |
7270a608 RR |
734 | edac_mc_printk(mci, KERN_INFO, |
735 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
736 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
737 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 738 | |
80cc7d87 MCC |
739 | edac_mc_owner = mci->mod_name; |
740 | ||
63b7df91 | 741 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 742 | return 0; |
da9bb1d2 | 743 | |
052dfb45 | 744 | fail1: |
028a7b6d DP |
745 | del_mc_from_global_list(mci); |
746 | ||
052dfb45 | 747 | fail0: |
63b7df91 | 748 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 749 | return ret; |
da9bb1d2 | 750 | } |
4e8d230d | 751 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 752 | |
079708b9 | 753 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 754 | { |
18dbc337 | 755 | struct mem_ctl_info *mci; |
da9bb1d2 | 756 | |
956b9ba1 | 757 | edac_dbg(0, "\n"); |
bf52fa4a | 758 | |
63b7df91 | 759 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 760 | |
bf52fa4a | 761 | /* find the requested mci struct in the global list */ |
c73e8833 | 762 | mci = __find_mci_by_dev(dev); |
bf52fa4a | 763 | if (mci == NULL) { |
63b7df91 | 764 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
765 | return NULL; |
766 | } | |
767 | ||
09667606 BP |
768 | /* mark MCI offline: */ |
769 | mci->op_state = OP_OFFLINE; | |
770 | ||
97bb6c17 | 771 | if (del_mc_from_global_list(mci)) |
80cc7d87 | 772 | edac_mc_owner = NULL; |
bf52fa4a | 773 | |
09667606 | 774 | mutex_unlock(&mem_ctls_mutex); |
bb31b312 | 775 | |
09667606 | 776 | if (mci->edac_check) |
626a7a4d | 777 | edac_stop_work(&mci->work); |
bb31b312 BP |
778 | |
779 | /* remove from sysfs */ | |
bf52fa4a DT |
780 | edac_remove_sysfs_mci_device(mci); |
781 | ||
537fba28 | 782 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 783 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 784 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 785 | |
18dbc337 | 786 | return mci; |
da9bb1d2 | 787 | } |
9110540f | 788 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 789 | |
2da1c119 AB |
790 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
791 | u32 size) | |
da9bb1d2 AC |
792 | { |
793 | struct page *pg; | |
794 | void *virt_addr; | |
795 | unsigned long flags = 0; | |
796 | ||
956b9ba1 | 797 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
798 | |
799 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 800 | if (!pfn_valid(page)) |
da9bb1d2 AC |
801 | return; |
802 | ||
803 | /* Find the actual page structure then map it and fix */ | |
804 | pg = pfn_to_page(page); | |
805 | ||
806 | if (PageHighMem(pg)) | |
807 | local_irq_save(flags); | |
808 | ||
4e5df7ca | 809 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
810 | |
811 | /* Perform architecture specific atomic scrub operation */ | |
b01aec9b | 812 | edac_atomic_scrub(virt_addr + offset, size); |
da9bb1d2 AC |
813 | |
814 | /* Unmap and complete */ | |
4e5df7ca | 815 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
816 | |
817 | if (PageHighMem(pg)) | |
818 | local_irq_restore(flags); | |
819 | } | |
820 | ||
da9bb1d2 | 821 | /* FIXME - should return -1 */ |
e7ecd891 | 822 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 823 | { |
de3910eb | 824 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 825 | int row, i, j, n; |
da9bb1d2 | 826 | |
956b9ba1 | 827 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
828 | row = -1; |
829 | ||
830 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 831 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
832 | n = 0; |
833 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 834 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
835 | n += dimm->nr_pages; |
836 | } | |
837 | if (n == 0) | |
da9bb1d2 AC |
838 | continue; |
839 | ||
956b9ba1 JP |
840 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
841 | mci->mc_idx, | |
842 | csrow->first_page, page, csrow->last_page, | |
843 | csrow->page_mask); | |
da9bb1d2 AC |
844 | |
845 | if ((page >= csrow->first_page) && | |
846 | (page <= csrow->last_page) && | |
847 | ((page & csrow->page_mask) == | |
848 | (csrow->first_page & csrow->page_mask))) { | |
849 | row = i; | |
850 | break; | |
851 | } | |
852 | } | |
853 | ||
854 | if (row == -1) | |
537fba28 | 855 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
856 | "could not look up page error address %lx\n", |
857 | (unsigned long)page); | |
da9bb1d2 AC |
858 | |
859 | return row; | |
860 | } | |
9110540f | 861 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 862 | |
4275be63 MCC |
863 | const char *edac_layer_name[] = { |
864 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
865 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
866 | [EDAC_MC_LAYER_SLOT] = "slot", | |
867 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 868 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
869 | }; |
870 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
871 | ||
6ab76179 | 872 | static void edac_inc_ce_error(struct edac_raw_error_desc *e) |
da9bb1d2 | 873 | { |
6ab76179 RR |
874 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; |
875 | struct mem_ctl_info *mci = error_desc_to_mci(e); | |
4aa92c86 | 876 | struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); |
da9bb1d2 | 877 | |
6ab76179 | 878 | mci->ce_mc += e->error_count; |
da9bb1d2 | 879 | |
4aa92c86 RR |
880 | if (dimm) |
881 | dimm->ce_count += e->error_count; | |
882 | else | |
6ab76179 | 883 | mci->ce_noinfo_count += e->error_count; |
4275be63 MCC |
884 | } |
885 | ||
6ab76179 | 886 | static void edac_inc_ue_error(struct edac_raw_error_desc *e) |
4275be63 | 887 | { |
6ab76179 RR |
888 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; |
889 | struct mem_ctl_info *mci = error_desc_to_mci(e); | |
4aa92c86 | 890 | struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); |
4275be63 | 891 | |
6ab76179 | 892 | mci->ue_mc += e->error_count; |
4275be63 | 893 | |
4aa92c86 RR |
894 | if (dimm) |
895 | dimm->ue_count += e->error_count; | |
896 | else | |
6ab76179 | 897 | mci->ue_noinfo_count += e->error_count; |
4275be63 | 898 | } |
da9bb1d2 | 899 | |
1853ee72 | 900 | static void edac_ce_error(struct edac_raw_error_desc *e) |
4275be63 | 901 | { |
6ab76179 | 902 | struct mem_ctl_info *mci = error_desc_to_mci(e); |
4275be63 MCC |
903 | unsigned long remapped_page; |
904 | ||
905 | if (edac_mc_get_log_ce()) { | |
1853ee72 RR |
906 | edac_mc_printk(mci, KERN_WARNING, |
907 | "%d CE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx%s%s)\n", | |
908 | e->error_count, e->msg, | |
909 | *e->msg ? " " : "", | |
910 | e->label, e->location, e->page_frame_number, e->offset_in_page, | |
911 | e->grain, e->syndrome, | |
912 | *e->other_detail ? " - " : "", | |
913 | e->other_detail); | |
4275be63 | 914 | } |
6ab76179 RR |
915 | |
916 | edac_inc_ce_error(e); | |
da9bb1d2 | 917 | |
aa2064d7 | 918 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 919 | /* |
4275be63 MCC |
920 | * Some memory controllers (called MCs below) can remap |
921 | * memory so that it is still available at a different | |
922 | * address when PCI devices map into memory. | |
923 | * MC's that can't do this, lose the memory where PCI | |
924 | * devices are mapped. This mapping is MC-dependent | |
925 | * and so we call back into the MC driver for it to | |
926 | * map the MC page to a physical (CPU) page which can | |
927 | * then be mapped to a virtual page - which can then | |
928 | * be scrubbed. | |
929 | */ | |
da9bb1d2 | 930 | remapped_page = mci->ctl_page_to_phys ? |
6ab76179 RR |
931 | mci->ctl_page_to_phys(mci, e->page_frame_number) : |
932 | e->page_frame_number; | |
da9bb1d2 | 933 | |
6ab76179 | 934 | edac_mc_scrub_block(remapped_page, e->offset_in_page, e->grain); |
da9bb1d2 AC |
935 | } |
936 | } | |
937 | ||
1853ee72 | 938 | static void edac_ue_error(struct edac_raw_error_desc *e) |
da9bb1d2 | 939 | { |
6ab76179 | 940 | struct mem_ctl_info *mci = error_desc_to_mci(e); |
f430d570 | 941 | |
4275be63 | 942 | if (edac_mc_get_log_ue()) { |
1853ee72 RR |
943 | edac_mc_printk(mci, KERN_WARNING, |
944 | "%d UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n", | |
945 | e->error_count, e->msg, | |
946 | *e->msg ? " " : "", | |
947 | e->label, e->location, e->page_frame_number, e->offset_in_page, | |
948 | e->grain, | |
949 | *e->other_detail ? " - " : "", | |
950 | e->other_detail); | |
4275be63 | 951 | } |
e7ecd891 | 952 | |
e9ff6636 ZD |
953 | edac_inc_ue_error(e); |
954 | ||
4275be63 | 955 | if (edac_mc_get_panic_on_ue()) { |
1853ee72 RR |
956 | panic("UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n", |
957 | e->msg, | |
958 | *e->msg ? " " : "", | |
959 | e->label, e->location, e->page_frame_number, e->offset_in_page, | |
960 | e->grain, | |
961 | *e->other_detail ? " - " : "", | |
962 | e->other_detail); | |
4275be63 | 963 | } |
da9bb1d2 AC |
964 | } |
965 | ||
6334dc4e RR |
966 | static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan) |
967 | { | |
968 | struct mem_ctl_info *mci = error_desc_to_mci(e); | |
969 | enum hw_event_mc_err_type type = e->type; | |
970 | u16 count = e->error_count; | |
971 | ||
972 | if (row < 0) | |
973 | return; | |
974 | ||
975 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); | |
976 | ||
977 | if (type == HW_EVENT_ERR_CORRECTED) { | |
978 | mci->csrows[row]->ce_count += count; | |
979 | if (chan >= 0) | |
980 | mci->csrows[row]->channels[chan]->ce_count += count; | |
981 | } else { | |
982 | mci->csrows[row]->ue_count += count; | |
983 | } | |
984 | } | |
985 | ||
91b327f6 | 986 | void edac_raw_mc_handle_error(struct edac_raw_error_desc *e) |
e7e24830 | 987 | { |
91b327f6 | 988 | struct mem_ctl_info *mci = error_desc_to_mci(e); |
787d8999 RR |
989 | u8 grain_bits; |
990 | ||
991 | /* Sanity-check driver-supplied grain value. */ | |
992 | if (WARN_ON_ONCE(!e->grain)) | |
993 | e->grain = 1; | |
994 | ||
995 | grain_bits = fls_long(e->grain - 1); | |
996 | ||
997 | /* Report the error via the trace interface */ | |
998 | if (IS_ENABLED(CONFIG_RAS)) | |
672ef0e5 | 999 | trace_mc_event(e->type, e->msg, e->label, e->error_count, |
787d8999 RR |
1000 | mci->mc_idx, e->top_layer, e->mid_layer, |
1001 | e->low_layer, | |
1002 | (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, | |
1003 | grain_bits, e->syndrome, e->other_detail); | |
e7e24830 | 1004 | |
1853ee72 RR |
1005 | if (e->type == HW_EVENT_ERR_CORRECTED) |
1006 | edac_ce_error(e); | |
1007 | else | |
1008 | edac_ue_error(e); | |
e7e24830 MCC |
1009 | } |
1010 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 | 1011 | |
4275be63 MCC |
1012 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
1013 | struct mem_ctl_info *mci, | |
9eb07a7f | 1014 | const u16 error_count, |
4275be63 MCC |
1015 | const unsigned long page_frame_number, |
1016 | const unsigned long offset_in_page, | |
1017 | const unsigned long syndrome, | |
53f2d028 MCC |
1018 | const int top_layer, |
1019 | const int mid_layer, | |
1020 | const int low_layer, | |
4275be63 | 1021 | const char *msg, |
03f7eae8 | 1022 | const char *other_detail) |
da9bb1d2 | 1023 | { |
c498afaf | 1024 | struct dimm_info *dimm; |
fca61165 | 1025 | char *p, *end; |
4275be63 | 1026 | int row = -1, chan = -1; |
53f2d028 | 1027 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 1028 | int i, n_labels = 0; |
c7ef7645 | 1029 | struct edac_raw_error_desc *e = &mci->error_desc; |
67792cf9 | 1030 | bool any_memory = true; |
fca61165 | 1031 | const char *prefix; |
da9bb1d2 | 1032 | |
956b9ba1 | 1033 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 1034 | |
c7ef7645 MCC |
1035 | /* Fills the error report buffer */ |
1036 | memset(e, 0, sizeof (*e)); | |
1037 | e->error_count = error_count; | |
672ef0e5 | 1038 | e->type = type; |
c7ef7645 MCC |
1039 | e->top_layer = top_layer; |
1040 | e->mid_layer = mid_layer; | |
1041 | e->low_layer = low_layer; | |
1042 | e->page_frame_number = page_frame_number; | |
1043 | e->offset_in_page = offset_in_page; | |
1044 | e->syndrome = syndrome; | |
1853ee72 RR |
1045 | /* need valid strings here for both: */ |
1046 | e->msg = msg ?: ""; | |
1047 | e->other_detail = other_detail ?: ""; | |
c7ef7645 | 1048 | |
4275be63 | 1049 | /* |
67792cf9 | 1050 | * Check if the event report is consistent and if the memory location is |
4aa92c86 RR |
1051 | * known. If it is, the DIMM(s) label info will be filled and the DIMM's |
1052 | * error counters will be incremented. | |
4275be63 MCC |
1053 | */ |
1054 | for (i = 0; i < mci->n_layers; i++) { | |
1055 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
1056 | |
1057 | edac_mc_printk(mci, KERN_ERR, | |
1058 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
1059 | edac_layer_name[mci->layers[i].type], | |
1060 | pos[i], mci->layers[i].size); | |
1061 | /* | |
1062 | * Instead of just returning it, let's use what's | |
1063 | * known about the error. The increment routines and | |
1064 | * the DIMM filter logic will do the right thing by | |
1065 | * pointing the likely damaged DIMMs. | |
1066 | */ | |
1067 | pos[i] = -1; | |
1068 | } | |
1069 | if (pos[i] >= 0) | |
67792cf9 | 1070 | any_memory = false; |
da9bb1d2 AC |
1071 | } |
1072 | ||
4275be63 MCC |
1073 | /* |
1074 | * Get the dimm label/grain that applies to the match criteria. | |
1075 | * As the error algorithm may not be able to point to just one memory | |
1076 | * stick, the logic here will get all possible labels that could | |
1077 | * pottentially be affected by the error. | |
1078 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1079 | * to have only the MC channel and the MC dimm (also called "branch") | |
1080 | * but the channel is not known, as the memory is arranged in pairs, | |
1081 | * where each memory belongs to a separate channel within the same | |
1082 | * branch. | |
1083 | */ | |
c7ef7645 | 1084 | p = e->label; |
4275be63 | 1085 | *p = '\0'; |
fca61165 LB |
1086 | end = p + sizeof(e->label); |
1087 | prefix = ""; | |
4da1b7bf | 1088 | |
c498afaf | 1089 | mci_for_each_dimm(mci, dimm) { |
53f2d028 | 1090 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1091 | continue; |
53f2d028 | 1092 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1093 | continue; |
53f2d028 | 1094 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1095 | continue; |
da9bb1d2 | 1096 | |
4275be63 | 1097 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1098 | if (dimm->grain > e->grain) |
1099 | e->grain = dimm->grain; | |
9794f33d | 1100 | |
4275be63 MCC |
1101 | /* |
1102 | * If the error is memory-controller wide, there's no need to | |
67792cf9 RR |
1103 | * seek for the affected DIMMs because the whole channel/memory |
1104 | * controller/... may be affected. Also, don't show errors for | |
1105 | * empty DIMM slots. | |
4275be63 | 1106 | */ |
65bb4d1a | 1107 | if (!dimm->nr_pages) |
0d8292e0 | 1108 | continue; |
4275be63 | 1109 | |
0d8292e0 | 1110 | n_labels++; |
65bb4d1a RR |
1111 | if (n_labels > EDAC_MAX_LABELS) { |
1112 | p = e->label; | |
1113 | *p = '\0'; | |
1114 | } else { | |
fca61165 LB |
1115 | p += scnprintf(p, end - p, "%s%s", prefix, dimm->label); |
1116 | prefix = OTHER_LABEL; | |
4275be63 | 1117 | } |
0d8292e0 RR |
1118 | |
1119 | /* | |
1120 | * get csrow/channel of the DIMM, in order to allow | |
1121 | * incrementing the compat API counters | |
1122 | */ | |
1123 | edac_dbg(4, "%s csrows map: (%d,%d)\n", | |
1124 | mci->csbased ? "rank" : "dimm", | |
1125 | dimm->csrow, dimm->cschannel); | |
1126 | if (row == -1) | |
1127 | row = dimm->csrow; | |
1128 | else if (row >= 0 && row != dimm->csrow) | |
1129 | row = -2; | |
1130 | ||
1131 | if (chan == -1) | |
1132 | chan = dimm->cschannel; | |
1133 | else if (chan >= 0 && chan != dimm->cschannel) | |
1134 | chan = -2; | |
9794f33d | 1135 | } |
1136 | ||
67792cf9 | 1137 | if (any_memory) |
fca61165 | 1138 | strscpy(e->label, "any memory", sizeof(e->label)); |
6334dc4e | 1139 | else if (!*e->label) |
fca61165 | 1140 | strscpy(e->label, "unknown memory", sizeof(e->label)); |
6334dc4e RR |
1141 | |
1142 | edac_inc_csrow(e, row, chan); | |
9794f33d | 1143 | |
4275be63 | 1144 | /* Fill the RAM location data */ |
c7ef7645 | 1145 | p = e->location; |
fca61165 LB |
1146 | end = p + sizeof(e->location); |
1147 | prefix = ""; | |
4da1b7bf | 1148 | |
4275be63 MCC |
1149 | for (i = 0; i < mci->n_layers; i++) { |
1150 | if (pos[i] < 0) | |
1151 | continue; | |
9794f33d | 1152 | |
fca61165 LB |
1153 | p += scnprintf(p, end - p, "%s%s:%d", prefix, |
1154 | edac_layer_name[mci->layers[i].type], pos[i]); | |
1155 | prefix = " "; | |
9794f33d | 1156 | } |
53f2d028 | 1157 | |
91b327f6 | 1158 | edac_raw_mc_handle_error(e); |
9794f33d | 1159 | } |
4275be63 | 1160 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |