Commit | Line | Data |
---|---|---|
da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
da9bb1d2 | 32 | #include <asm/page.h> |
78d88e8a | 33 | #include "edac_mc.h" |
7c9281d7 | 34 | #include "edac_module.h" |
53f2d028 MCC |
35 | #include <ras/ras_event.h> |
36 | ||
b01aec9b BP |
37 | #ifdef CONFIG_EDAC_ATOMIC_SCRUB |
38 | #include <asm/edac.h> | |
39 | #else | |
40 | #define edac_atomic_scrub(va, size) do { } while (0) | |
41 | #endif | |
42 | ||
8c22b4fe BP |
43 | int edac_op_state = EDAC_OPSTATE_INVAL; |
44 | EXPORT_SYMBOL_GPL(edac_op_state); | |
45 | ||
da9bb1d2 | 46 | /* lock to memory controller's control array */ |
63b7df91 | 47 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 48 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 49 | |
80cc7d87 MCC |
50 | /* |
51 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
52 | * apei/ghes and i7core_edac to be used at the same time. | |
53 | */ | |
3877c7d1 | 54 | static const char *edac_mc_owner; |
80cc7d87 | 55 | |
91b327f6 RR |
56 | static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e) |
57 | { | |
58 | return container_of(e, struct mem_ctl_info, error_desc); | |
59 | } | |
60 | ||
d55c79ac RR |
61 | unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
62 | unsigned int len) | |
6e84d359 MCC |
63 | { |
64 | struct mem_ctl_info *mci = dimm->mci; | |
65 | int i, n, count = 0; | |
66 | char *p = buf; | |
67 | ||
68 | for (i = 0; i < mci->n_layers; i++) { | |
fca61165 | 69 | n = scnprintf(p, len, "%s %d ", |
6e84d359 MCC |
70 | edac_layer_name[mci->layers[i].type], |
71 | dimm->location[i]); | |
72 | p += n; | |
73 | len -= n; | |
74 | count += n; | |
6e84d359 MCC |
75 | } |
76 | ||
77 | return count; | |
78 | } | |
79 | ||
da9bb1d2 AC |
80 | #ifdef CONFIG_EDAC_DEBUG |
81 | ||
a4b4be3f | 82 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 83 | { |
6e84d359 MCC |
84 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
85 | edac_dbg(4, " channel = %p\n", chan); | |
86 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
87 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
88 | } |
89 | ||
c498afaf | 90 | static void edac_mc_dump_dimm(struct dimm_info *dimm) |
4275be63 | 91 | { |
6e84d359 MCC |
92 | char location[80]; |
93 | ||
c498afaf RR |
94 | if (!dimm->nr_pages) |
95 | return; | |
96 | ||
6e84d359 MCC |
97 | edac_dimm_info_location(dimm, location, sizeof(location)); |
98 | ||
99 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 100 | dimm->mci->csbased ? "rank" : "dimm", |
c498afaf | 101 | dimm->idx, location, dimm->csrow, dimm->cschannel); |
6e84d359 MCC |
102 | edac_dbg(4, " dimm = %p\n", dimm); |
103 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
104 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
105 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
106 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
107 | } |
108 | ||
2da1c119 | 109 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 110 | { |
6e84d359 MCC |
111 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
112 | edac_dbg(4, " csrow = %p\n", csrow); | |
113 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
114 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
115 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
116 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
117 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
118 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
119 | } |
120 | ||
2da1c119 | 121 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 122 | { |
956b9ba1 JP |
123 | edac_dbg(3, "\tmci = %p\n", mci); |
124 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
125 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
126 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
127 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
128 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
129 | mci->nr_csrows, mci->csrows); | |
130 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
131 | mci->tot_dimms, mci->dimms); | |
132 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
133 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
134 | mci->mod_name, mci->ctl_name); | |
135 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
136 | } |
137 | ||
24f9a7fe BP |
138 | #endif /* CONFIG_EDAC_DEBUG */ |
139 | ||
f4ce6eca | 140 | const char * const edac_mem_types[] = { |
d6dd77eb TL |
141 | [MEM_EMPTY] = "Empty", |
142 | [MEM_RESERVED] = "Reserved", | |
143 | [MEM_UNKNOWN] = "Unknown", | |
144 | [MEM_FPM] = "FPM", | |
145 | [MEM_EDO] = "EDO", | |
146 | [MEM_BEDO] = "BEDO", | |
147 | [MEM_SDR] = "Unbuffered-SDR", | |
148 | [MEM_RDR] = "Registered-SDR", | |
149 | [MEM_DDR] = "Unbuffered-DDR", | |
150 | [MEM_RDDR] = "Registered-DDR", | |
151 | [MEM_RMBS] = "RMBS", | |
152 | [MEM_DDR2] = "Unbuffered-DDR2", | |
153 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
154 | [MEM_RDDR2] = "Registered-DDR2", | |
155 | [MEM_XDR] = "XDR", | |
156 | [MEM_DDR3] = "Unbuffered-DDR3", | |
157 | [MEM_RDDR3] = "Registered-DDR3", | |
158 | [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM", | |
3b203693 | 159 | [MEM_LPDDR3] = "Low-Power-DDR3-RAM", |
d6dd77eb | 160 | [MEM_DDR4] = "Unbuffered-DDR4", |
001f8613 | 161 | [MEM_RDDR4] = "Registered-DDR4", |
3b203693 | 162 | [MEM_LPDDR4] = "Low-Power-DDR4-RAM", |
b748f2de | 163 | [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM", |
bc1c99a5 | 164 | [MEM_DDR5] = "Unbuffered-DDR5", |
f9571124 YG |
165 | [MEM_RDDR5] = "Registered-DDR5", |
166 | [MEM_LRDDR5] = "Load-Reduced-DDR5-RAM", | |
001f8613 | 167 | [MEM_NVDIMM] = "Non-volatile-RAM", |
3b203693 | 168 | [MEM_WIO2] = "Wide-IO-2", |
e1ca90b7 | 169 | [MEM_HBM2] = "High-bandwidth-memory-Gen2", |
239642fe BP |
170 | }; |
171 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
172 | ||
faa2ad09 SR |
173 | static void _edac_mc_free(struct mem_ctl_info *mci) |
174 | { | |
bea1bfd5 RR |
175 | put_device(&mci->dev); |
176 | } | |
177 | ||
178 | static void mci_release(struct device *dev) | |
179 | { | |
180 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); | |
faa2ad09 | 181 | struct csrow_info *csr; |
718d5851 | 182 | int i, chn, row; |
faa2ad09 SR |
183 | |
184 | if (mci->dimms) { | |
718d5851 | 185 | for (i = 0; i < mci->tot_dimms; i++) |
faa2ad09 SR |
186 | kfree(mci->dimms[i]); |
187 | kfree(mci->dimms); | |
188 | } | |
718d5851 | 189 | |
faa2ad09 | 190 | if (mci->csrows) { |
718d5851 | 191 | for (row = 0; row < mci->nr_csrows; row++) { |
faa2ad09 | 192 | csr = mci->csrows[row]; |
718d5851 RR |
193 | if (!csr) |
194 | continue; | |
195 | ||
196 | if (csr->channels) { | |
197 | for (chn = 0; chn < mci->num_cschannel; chn++) | |
198 | kfree(csr->channels[chn]); | |
199 | kfree(csr->channels); | |
faa2ad09 | 200 | } |
718d5851 | 201 | kfree(csr); |
faa2ad09 SR |
202 | } |
203 | kfree(mci->csrows); | |
204 | } | |
0bbb265f BP |
205 | kfree(mci->pvt_info); |
206 | kfree(mci->layers); | |
faa2ad09 SR |
207 | kfree(mci); |
208 | } | |
209 | ||
aad28c6f RR |
210 | static int edac_mc_alloc_csrows(struct mem_ctl_info *mci) |
211 | { | |
212 | unsigned int tot_channels = mci->num_cschannel; | |
213 | unsigned int tot_csrows = mci->nr_csrows; | |
214 | unsigned int row, chn; | |
215 | ||
a7d7d2e1 | 216 | /* |
de3910eb | 217 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 218 | */ |
d3d09e18 | 219 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb | 220 | if (!mci->csrows) |
aad28c6f RR |
221 | return -ENOMEM; |
222 | ||
4275be63 | 223 | for (row = 0; row < tot_csrows; row++) { |
aad28c6f RR |
224 | struct csrow_info *csr; |
225 | ||
de3910eb MCC |
226 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
227 | if (!csr) | |
aad28c6f RR |
228 | return -ENOMEM; |
229 | ||
de3910eb | 230 | mci->csrows[row] = csr; |
4275be63 MCC |
231 | csr->csrow_idx = row; |
232 | csr->mci = mci; | |
233 | csr->nr_channels = tot_channels; | |
d3d09e18 | 234 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
235 | GFP_KERNEL); |
236 | if (!csr->channels) | |
aad28c6f | 237 | return -ENOMEM; |
4275be63 MCC |
238 | |
239 | for (chn = 0; chn < tot_channels; chn++) { | |
aad28c6f RR |
240 | struct rank_info *chan; |
241 | ||
de3910eb MCC |
242 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
243 | if (!chan) | |
aad28c6f RR |
244 | return -ENOMEM; |
245 | ||
de3910eb | 246 | csr->channels[chn] = chan; |
da9bb1d2 | 247 | chan->chan_idx = chn; |
4275be63 MCC |
248 | chan->csrow = csr; |
249 | } | |
250 | } | |
251 | ||
aad28c6f RR |
252 | return 0; |
253 | } | |
254 | ||
255 | static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) | |
256 | { | |
257 | unsigned int pos[EDAC_MAX_LAYERS]; | |
258 | unsigned int row, chn, idx; | |
259 | int layer; | |
260 | void *p; | |
261 | ||
4275be63 | 262 | /* |
de3910eb | 263 | * Allocate and fill the dimm structs |
4275be63 | 264 | */ |
aad28c6f | 265 | mci->dimms = kcalloc(mci->tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb | 266 | if (!mci->dimms) |
aad28c6f | 267 | return -ENOMEM; |
de3910eb | 268 | |
4275be63 MCC |
269 | memset(&pos, 0, sizeof(pos)); |
270 | row = 0; | |
271 | chn = 0; | |
aad28c6f RR |
272 | for (idx = 0; idx < mci->tot_dimms; idx++) { |
273 | struct dimm_info *dimm; | |
274 | struct rank_info *chan; | |
275 | int n, len; | |
276 | ||
de3910eb | 277 | chan = mci->csrows[row]->channels[chn]; |
4275be63 | 278 | |
de3910eb | 279 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 | 280 | if (!dimm) |
aad28c6f | 281 | return -ENOMEM; |
977b1ce7 | 282 | mci->dimms[idx] = dimm; |
4275be63 | 283 | dimm->mci = mci; |
977b1ce7 | 284 | dimm->idx = idx; |
4275be63 | 285 | |
5926ff50 MCC |
286 | /* |
287 | * Copy DIMM location and initialize it. | |
288 | */ | |
289 | len = sizeof(dimm->label); | |
290 | p = dimm->label; | |
fca61165 | 291 | n = scnprintf(p, len, "mc#%u", mci->mc_idx); |
5926ff50 MCC |
292 | p += n; |
293 | len -= n; | |
aad28c6f | 294 | for (layer = 0; layer < mci->n_layers; layer++) { |
fca61165 LB |
295 | n = scnprintf(p, len, "%s#%u", |
296 | edac_layer_name[mci->layers[layer].type], | |
297 | pos[layer]); | |
5926ff50 MCC |
298 | p += n; |
299 | len -= n; | |
aad28c6f | 300 | dimm->location[layer] = pos[layer]; |
5926ff50 MCC |
301 | } |
302 | ||
4275be63 MCC |
303 | /* Link it to the csrows old API data */ |
304 | chan->dimm = dimm; | |
305 | dimm->csrow = row; | |
306 | dimm->cschannel = chn; | |
307 | ||
308 | /* Increment csrow location */ | |
aad28c6f | 309 | if (mci->layers[0].is_virt_csrow) { |
4275be63 | 310 | chn++; |
aad28c6f | 311 | if (chn == mci->num_cschannel) { |
24bef66e MCC |
312 | chn = 0; |
313 | row++; | |
314 | } | |
315 | } else { | |
316 | row++; | |
aad28c6f | 317 | if (row == mci->nr_csrows) { |
24bef66e MCC |
318 | row = 0; |
319 | chn++; | |
320 | } | |
4275be63 | 321 | } |
a7d7d2e1 | 322 | |
4275be63 | 323 | /* Increment dimm location */ |
aad28c6f RR |
324 | for (layer = mci->n_layers - 1; layer >= 0; layer--) { |
325 | pos[layer]++; | |
326 | if (pos[layer] < mci->layers[layer].size) | |
4275be63 | 327 | break; |
aad28c6f | 328 | pos[layer] = 0; |
da9bb1d2 AC |
329 | } |
330 | } | |
331 | ||
aad28c6f | 332 | return 0; |
4275be63 | 333 | } |
da9bb1d2 | 334 | |
1f27c790 RR |
335 | struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, |
336 | unsigned int n_layers, | |
337 | struct edac_mc_layer *layers, | |
338 | unsigned int sz_pvt) | |
339 | { | |
340 | struct mem_ctl_info *mci; | |
341 | struct edac_mc_layer *layer; | |
0bbb265f | 342 | unsigned int idx, tot_dimms = 1; |
4aa92c86 | 343 | unsigned int tot_csrows = 1, tot_channels = 1; |
1f27c790 RR |
344 | bool per_rank = false; |
345 | ||
346 | if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) | |
347 | return NULL; | |
348 | ||
349 | /* | |
350 | * Calculate the total amount of dimms and csrows/cschannels while | |
351 | * in the old API emulation mode | |
352 | */ | |
353 | for (idx = 0; idx < n_layers; idx++) { | |
354 | tot_dimms *= layers[idx].size; | |
355 | ||
356 | if (layers[idx].is_virt_csrow) | |
357 | tot_csrows *= layers[idx].size; | |
358 | else | |
359 | tot_channels *= layers[idx].size; | |
360 | ||
361 | if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) | |
362 | per_rank = true; | |
363 | } | |
364 | ||
0bbb265f BP |
365 | mci = kzalloc(sizeof(struct mem_ctl_info), GFP_KERNEL); |
366 | if (!mci) | |
1f27c790 RR |
367 | return NULL; |
368 | ||
13088b65 | 369 | mci->layers = kcalloc(n_layers, sizeof(struct edac_mc_layer), GFP_KERNEL); |
0bbb265f BP |
370 | if (!mci->layers) |
371 | goto error; | |
372 | ||
373 | mci->pvt_info = kzalloc(sz_pvt, GFP_KERNEL); | |
374 | if (!mci->pvt_info) | |
375 | goto error; | |
376 | ||
1f27c790 RR |
377 | mci->dev.release = mci_release; |
378 | device_initialize(&mci->dev); | |
379 | ||
1f27c790 RR |
380 | /* setup index and various internal pointers */ |
381 | mci->mc_idx = mc_num; | |
382 | mci->tot_dimms = tot_dimms; | |
1f27c790 | 383 | mci->n_layers = n_layers; |
1f27c790 RR |
384 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); |
385 | mci->nr_csrows = tot_csrows; | |
386 | mci->num_cschannel = tot_channels; | |
387 | mci->csbased = per_rank; | |
388 | ||
389 | if (edac_mc_alloc_csrows(mci)) | |
390 | goto error; | |
391 | ||
392 | if (edac_mc_alloc_dimms(mci)) | |
393 | goto error; | |
394 | ||
395 | mci->op_state = OP_ALLOC; | |
396 | ||
397 | return mci; | |
398 | ||
399 | error: | |
400 | _edac_mc_free(mci); | |
401 | ||
402 | return NULL; | |
403 | } | |
404 | EXPORT_SYMBOL_GPL(edac_mc_alloc); | |
405 | ||
da9bb1d2 AC |
406 | void edac_mc_free(struct mem_ctl_info *mci) |
407 | { | |
956b9ba1 | 408 | edac_dbg(1, "\n"); |
bbc560ae | 409 | |
216aa145 | 410 | _edac_mc_free(mci); |
da9bb1d2 | 411 | } |
9110540f | 412 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 413 | |
d7fc9d77 YG |
414 | bool edac_has_mcs(void) |
415 | { | |
416 | bool ret; | |
417 | ||
418 | mutex_lock(&mem_ctls_mutex); | |
419 | ||
420 | ret = list_empty(&mc_devices); | |
421 | ||
422 | mutex_unlock(&mem_ctls_mutex); | |
423 | ||
424 | return !ret; | |
425 | } | |
426 | EXPORT_SYMBOL_GPL(edac_has_mcs); | |
427 | ||
c73e8833 BP |
428 | /* Caller must hold mem_ctls_mutex */ |
429 | static struct mem_ctl_info *__find_mci_by_dev(struct device *dev) | |
da9bb1d2 AC |
430 | { |
431 | struct mem_ctl_info *mci; | |
432 | struct list_head *item; | |
433 | ||
956b9ba1 | 434 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
435 | |
436 | list_for_each(item, &mc_devices) { | |
437 | mci = list_entry(item, struct mem_ctl_info, link); | |
438 | ||
fd687502 | 439 | if (mci->pdev == dev) |
da9bb1d2 AC |
440 | return mci; |
441 | } | |
442 | ||
443 | return NULL; | |
444 | } | |
c73e8833 BP |
445 | |
446 | /** | |
447 | * find_mci_by_dev | |
448 | * | |
449 | * scan list of controllers looking for the one that manages | |
450 | * the 'dev' device | |
451 | * @dev: pointer to a struct device related with the MCI | |
452 | */ | |
453 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) | |
454 | { | |
455 | struct mem_ctl_info *ret; | |
456 | ||
457 | mutex_lock(&mem_ctls_mutex); | |
458 | ret = __find_mci_by_dev(dev); | |
459 | mutex_unlock(&mem_ctls_mutex); | |
460 | ||
461 | return ret; | |
462 | } | |
939747bd | 463 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 464 | |
81d87cb1 DJ |
465 | /* |
466 | * edac_mc_workq_function | |
467 | * performs the operation scheduled by a workq request | |
468 | */ | |
81d87cb1 DJ |
469 | static void edac_mc_workq_function(struct work_struct *work_req) |
470 | { | |
fbeb4384 | 471 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 472 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
473 | |
474 | mutex_lock(&mem_ctls_mutex); | |
475 | ||
06e912d4 | 476 | if (mci->op_state != OP_RUNNING_POLL) { |
bf52fa4a DT |
477 | mutex_unlock(&mem_ctls_mutex); |
478 | return; | |
479 | } | |
480 | ||
d3116a08 | 481 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
482 | mci->edac_check(mci); |
483 | ||
81d87cb1 DJ |
484 | mutex_unlock(&mem_ctls_mutex); |
485 | ||
06e912d4 | 486 | /* Queue ourselves again. */ |
c4cf3b45 | 487 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
488 | } |
489 | ||
81d87cb1 | 490 | /* |
bce19683 DT |
491 | * edac_mc_reset_delay_period(unsigned long value) |
492 | * | |
493 | * user space has updated our poll period value, need to | |
494 | * reset our workq delays | |
81d87cb1 | 495 | */ |
9da21b15 | 496 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 497 | { |
bce19683 DT |
498 | struct mem_ctl_info *mci; |
499 | struct list_head *item; | |
500 | ||
501 | mutex_lock(&mem_ctls_mutex); | |
502 | ||
bce19683 DT |
503 | list_for_each(item, &mc_devices) { |
504 | mci = list_entry(item, struct mem_ctl_info, link); | |
505 | ||
fbedcaf4 NK |
506 | if (mci->op_state == OP_RUNNING_POLL) |
507 | edac_mod_work(&mci->work, value); | |
bce19683 | 508 | } |
81d87cb1 DJ |
509 | mutex_unlock(&mem_ctls_mutex); |
510 | } | |
511 | ||
bce19683 DT |
512 | |
513 | ||
2d7bbb91 DT |
514 | /* Return 0 on success, 1 on failure. |
515 | * Before calling this function, caller must | |
516 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
517 | * |
518 | * locking model: | |
519 | * | |
520 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 521 | */ |
079708b9 | 522 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
523 | { |
524 | struct list_head *item, *insert_before; | |
525 | struct mem_ctl_info *p; | |
da9bb1d2 | 526 | |
2d7bbb91 | 527 | insert_before = &mc_devices; |
da9bb1d2 | 528 | |
c73e8833 | 529 | p = __find_mci_by_dev(mci->pdev); |
bf52fa4a | 530 | if (unlikely(p != NULL)) |
2d7bbb91 | 531 | goto fail0; |
da9bb1d2 | 532 | |
2d7bbb91 DT |
533 | list_for_each(item, &mc_devices) { |
534 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 535 | |
2d7bbb91 DT |
536 | if (p->mc_idx >= mci->mc_idx) { |
537 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
538 | goto fail1; | |
da9bb1d2 | 539 | |
2d7bbb91 DT |
540 | insert_before = item; |
541 | break; | |
da9bb1d2 | 542 | } |
da9bb1d2 AC |
543 | } |
544 | ||
545 | list_add_tail_rcu(&mci->link, insert_before); | |
546 | return 0; | |
2d7bbb91 | 547 | |
052dfb45 | 548 | fail0: |
2d7bbb91 | 549 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 550 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 551 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
552 | return 1; |
553 | ||
052dfb45 | 554 | fail1: |
2d7bbb91 | 555 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
556 | "bug in low-level driver: attempt to assign\n" |
557 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 558 | return 1; |
da9bb1d2 AC |
559 | } |
560 | ||
80cc7d87 | 561 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc DP |
562 | { |
563 | list_del_rcu(&mci->link); | |
e2e77098 LJ |
564 | |
565 | /* these are for safe removal of devices from global list while | |
566 | * NMI handlers may be traversing list | |
567 | */ | |
568 | synchronize_rcu(); | |
569 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 | 570 | |
97bb6c17 | 571 | return list_empty(&mc_devices); |
a1d03fcc DP |
572 | } |
573 | ||
079708b9 | 574 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c | 575 | { |
29a0c843 | 576 | struct mem_ctl_info *mci; |
5da0831c | 577 | struct list_head *item; |
c73e8833 BP |
578 | |
579 | mutex_lock(&mem_ctls_mutex); | |
5da0831c DT |
580 | |
581 | list_for_each(item, &mc_devices) { | |
582 | mci = list_entry(item, struct mem_ctl_info, link); | |
29a0c843 RR |
583 | if (mci->mc_idx == idx) |
584 | goto unlock; | |
5da0831c DT |
585 | } |
586 | ||
29a0c843 | 587 | mci = NULL; |
c73e8833 BP |
588 | unlock: |
589 | mutex_unlock(&mem_ctls_mutex); | |
590 | return mci; | |
5da0831c DT |
591 | } |
592 | EXPORT_SYMBOL(edac_mc_find); | |
593 | ||
3877c7d1 TK |
594 | const char *edac_get_owner(void) |
595 | { | |
596 | return edac_mc_owner; | |
597 | } | |
598 | EXPORT_SYMBOL_GPL(edac_get_owner); | |
da9bb1d2 AC |
599 | |
600 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
601 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
602 | const struct attribute_group **groups) | |
da9bb1d2 | 603 | { |
80cc7d87 | 604 | int ret = -EINVAL; |
956b9ba1 | 605 | edac_dbg(0, "\n"); |
b8f6f975 | 606 | |
da9bb1d2 AC |
607 | #ifdef CONFIG_EDAC_DEBUG |
608 | if (edac_debug_level >= 3) | |
609 | edac_mc_dump_mci(mci); | |
e7ecd891 | 610 | |
da9bb1d2 | 611 | if (edac_debug_level >= 4) { |
c498afaf | 612 | struct dimm_info *dimm; |
da9bb1d2 AC |
613 | int i; |
614 | ||
615 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
616 | struct csrow_info *csrow = mci->csrows[i]; |
617 | u32 nr_pages = 0; | |
da9bb1d2 | 618 | int j; |
e7ecd891 | 619 | |
6e84d359 MCC |
620 | for (j = 0; j < csrow->nr_channels; j++) |
621 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
622 | if (!nr_pages) | |
623 | continue; | |
624 | edac_mc_dump_csrow(csrow); | |
625 | for (j = 0; j < csrow->nr_channels; j++) | |
626 | if (csrow->channels[j]->dimm->nr_pages) | |
627 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 628 | } |
c498afaf RR |
629 | |
630 | mci_for_each_dimm(mci, dimm) | |
631 | edac_mc_dump_dimm(dimm); | |
da9bb1d2 AC |
632 | } |
633 | #endif | |
63b7df91 | 634 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 635 | |
80cc7d87 MCC |
636 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
637 | ret = -EPERM; | |
638 | goto fail0; | |
639 | } | |
640 | ||
da9bb1d2 | 641 | if (add_mc_to_global_list(mci)) |
028a7b6d | 642 | goto fail0; |
da9bb1d2 AC |
643 | |
644 | /* set load time so that error rate can be tracked */ | |
645 | mci->start_time = jiffies; | |
646 | ||
861e6ed6 | 647 | mci->bus = edac_get_sysfs_subsys(); |
88d84ac9 | 648 | |
4e8d230d | 649 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 650 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 651 | "failed to create sysfs device\n"); |
9794f33d | 652 | goto fail1; |
653 | } | |
da9bb1d2 | 654 | |
09667606 | 655 | if (mci->edac_check) { |
81d87cb1 DJ |
656 | mci->op_state = OP_RUNNING_POLL; |
657 | ||
626a7a4d BP |
658 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
659 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); | |
660 | ||
81d87cb1 DJ |
661 | } else { |
662 | mci->op_state = OP_RUNNING_INTERRUPT; | |
663 | } | |
664 | ||
da9bb1d2 | 665 | /* Report action taken */ |
7270a608 RR |
666 | edac_mc_printk(mci, KERN_INFO, |
667 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
668 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
669 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 670 | |
80cc7d87 MCC |
671 | edac_mc_owner = mci->mod_name; |
672 | ||
63b7df91 | 673 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 674 | return 0; |
da9bb1d2 | 675 | |
052dfb45 | 676 | fail1: |
028a7b6d DP |
677 | del_mc_from_global_list(mci); |
678 | ||
052dfb45 | 679 | fail0: |
63b7df91 | 680 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 681 | return ret; |
da9bb1d2 | 682 | } |
4e8d230d | 683 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 684 | |
079708b9 | 685 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 686 | { |
18dbc337 | 687 | struct mem_ctl_info *mci; |
da9bb1d2 | 688 | |
956b9ba1 | 689 | edac_dbg(0, "\n"); |
bf52fa4a | 690 | |
63b7df91 | 691 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 692 | |
bf52fa4a | 693 | /* find the requested mci struct in the global list */ |
c73e8833 | 694 | mci = __find_mci_by_dev(dev); |
bf52fa4a | 695 | if (mci == NULL) { |
63b7df91 | 696 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
697 | return NULL; |
698 | } | |
699 | ||
09667606 BP |
700 | /* mark MCI offline: */ |
701 | mci->op_state = OP_OFFLINE; | |
702 | ||
97bb6c17 | 703 | if (del_mc_from_global_list(mci)) |
80cc7d87 | 704 | edac_mc_owner = NULL; |
bf52fa4a | 705 | |
09667606 | 706 | mutex_unlock(&mem_ctls_mutex); |
bb31b312 | 707 | |
09667606 | 708 | if (mci->edac_check) |
626a7a4d | 709 | edac_stop_work(&mci->work); |
bb31b312 BP |
710 | |
711 | /* remove from sysfs */ | |
bf52fa4a DT |
712 | edac_remove_sysfs_mci_device(mci); |
713 | ||
537fba28 | 714 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 715 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 716 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 717 | |
18dbc337 | 718 | return mci; |
da9bb1d2 | 719 | } |
9110540f | 720 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 721 | |
2da1c119 AB |
722 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
723 | u32 size) | |
da9bb1d2 AC |
724 | { |
725 | struct page *pg; | |
726 | void *virt_addr; | |
727 | unsigned long flags = 0; | |
728 | ||
956b9ba1 | 729 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
730 | |
731 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 732 | if (!pfn_valid(page)) |
da9bb1d2 AC |
733 | return; |
734 | ||
735 | /* Find the actual page structure then map it and fix */ | |
736 | pg = pfn_to_page(page); | |
737 | ||
738 | if (PageHighMem(pg)) | |
739 | local_irq_save(flags); | |
740 | ||
4e5df7ca | 741 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
742 | |
743 | /* Perform architecture specific atomic scrub operation */ | |
b01aec9b | 744 | edac_atomic_scrub(virt_addr + offset, size); |
da9bb1d2 AC |
745 | |
746 | /* Unmap and complete */ | |
4e5df7ca | 747 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
748 | |
749 | if (PageHighMem(pg)) | |
750 | local_irq_restore(flags); | |
751 | } | |
752 | ||
da9bb1d2 | 753 | /* FIXME - should return -1 */ |
e7ecd891 | 754 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 755 | { |
de3910eb | 756 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 757 | int row, i, j, n; |
da9bb1d2 | 758 | |
956b9ba1 | 759 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
760 | row = -1; |
761 | ||
762 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 763 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
764 | n = 0; |
765 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 766 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
767 | n += dimm->nr_pages; |
768 | } | |
769 | if (n == 0) | |
da9bb1d2 AC |
770 | continue; |
771 | ||
956b9ba1 JP |
772 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
773 | mci->mc_idx, | |
774 | csrow->first_page, page, csrow->last_page, | |
775 | csrow->page_mask); | |
da9bb1d2 AC |
776 | |
777 | if ((page >= csrow->first_page) && | |
778 | (page <= csrow->last_page) && | |
779 | ((page & csrow->page_mask) == | |
780 | (csrow->first_page & csrow->page_mask))) { | |
781 | row = i; | |
782 | break; | |
783 | } | |
784 | } | |
785 | ||
786 | if (row == -1) | |
537fba28 | 787 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
788 | "could not look up page error address %lx\n", |
789 | (unsigned long)page); | |
da9bb1d2 AC |
790 | |
791 | return row; | |
792 | } | |
9110540f | 793 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 794 | |
4275be63 MCC |
795 | const char *edac_layer_name[] = { |
796 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
797 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
798 | [EDAC_MC_LAYER_SLOT] = "slot", | |
799 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 800 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
801 | }; |
802 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
803 | ||
6ab76179 | 804 | static void edac_inc_ce_error(struct edac_raw_error_desc *e) |
da9bb1d2 | 805 | { |
6ab76179 RR |
806 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; |
807 | struct mem_ctl_info *mci = error_desc_to_mci(e); | |
4aa92c86 | 808 | struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); |
da9bb1d2 | 809 | |
6ab76179 | 810 | mci->ce_mc += e->error_count; |
da9bb1d2 | 811 | |
4aa92c86 RR |
812 | if (dimm) |
813 | dimm->ce_count += e->error_count; | |
814 | else | |
6ab76179 | 815 | mci->ce_noinfo_count += e->error_count; |
4275be63 MCC |
816 | } |
817 | ||
6ab76179 | 818 | static void edac_inc_ue_error(struct edac_raw_error_desc *e) |
4275be63 | 819 | { |
6ab76179 RR |
820 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; |
821 | struct mem_ctl_info *mci = error_desc_to_mci(e); | |
4aa92c86 | 822 | struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); |
4275be63 | 823 | |
6ab76179 | 824 | mci->ue_mc += e->error_count; |
4275be63 | 825 | |
4aa92c86 RR |
826 | if (dimm) |
827 | dimm->ue_count += e->error_count; | |
828 | else | |
6ab76179 | 829 | mci->ue_noinfo_count += e->error_count; |
4275be63 | 830 | } |
da9bb1d2 | 831 | |
1853ee72 | 832 | static void edac_ce_error(struct edac_raw_error_desc *e) |
4275be63 | 833 | { |
6ab76179 | 834 | struct mem_ctl_info *mci = error_desc_to_mci(e); |
4275be63 MCC |
835 | unsigned long remapped_page; |
836 | ||
837 | if (edac_mc_get_log_ce()) { | |
1853ee72 RR |
838 | edac_mc_printk(mci, KERN_WARNING, |
839 | "%d CE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx%s%s)\n", | |
840 | e->error_count, e->msg, | |
841 | *e->msg ? " " : "", | |
842 | e->label, e->location, e->page_frame_number, e->offset_in_page, | |
843 | e->grain, e->syndrome, | |
844 | *e->other_detail ? " - " : "", | |
845 | e->other_detail); | |
4275be63 | 846 | } |
6ab76179 RR |
847 | |
848 | edac_inc_ce_error(e); | |
da9bb1d2 | 849 | |
aa2064d7 | 850 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 851 | /* |
4275be63 MCC |
852 | * Some memory controllers (called MCs below) can remap |
853 | * memory so that it is still available at a different | |
854 | * address when PCI devices map into memory. | |
855 | * MC's that can't do this, lose the memory where PCI | |
856 | * devices are mapped. This mapping is MC-dependent | |
857 | * and so we call back into the MC driver for it to | |
858 | * map the MC page to a physical (CPU) page which can | |
859 | * then be mapped to a virtual page - which can then | |
860 | * be scrubbed. | |
861 | */ | |
da9bb1d2 | 862 | remapped_page = mci->ctl_page_to_phys ? |
6ab76179 RR |
863 | mci->ctl_page_to_phys(mci, e->page_frame_number) : |
864 | e->page_frame_number; | |
da9bb1d2 | 865 | |
6ab76179 | 866 | edac_mc_scrub_block(remapped_page, e->offset_in_page, e->grain); |
da9bb1d2 AC |
867 | } |
868 | } | |
869 | ||
1853ee72 | 870 | static void edac_ue_error(struct edac_raw_error_desc *e) |
da9bb1d2 | 871 | { |
6ab76179 | 872 | struct mem_ctl_info *mci = error_desc_to_mci(e); |
f430d570 | 873 | |
4275be63 | 874 | if (edac_mc_get_log_ue()) { |
1853ee72 RR |
875 | edac_mc_printk(mci, KERN_WARNING, |
876 | "%d UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n", | |
877 | e->error_count, e->msg, | |
878 | *e->msg ? " " : "", | |
879 | e->label, e->location, e->page_frame_number, e->offset_in_page, | |
880 | e->grain, | |
881 | *e->other_detail ? " - " : "", | |
882 | e->other_detail); | |
4275be63 | 883 | } |
e7ecd891 | 884 | |
e9ff6636 ZD |
885 | edac_inc_ue_error(e); |
886 | ||
4275be63 | 887 | if (edac_mc_get_panic_on_ue()) { |
1853ee72 RR |
888 | panic("UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n", |
889 | e->msg, | |
890 | *e->msg ? " " : "", | |
891 | e->label, e->location, e->page_frame_number, e->offset_in_page, | |
892 | e->grain, | |
893 | *e->other_detail ? " - " : "", | |
894 | e->other_detail); | |
4275be63 | 895 | } |
da9bb1d2 AC |
896 | } |
897 | ||
6334dc4e RR |
898 | static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan) |
899 | { | |
900 | struct mem_ctl_info *mci = error_desc_to_mci(e); | |
901 | enum hw_event_mc_err_type type = e->type; | |
902 | u16 count = e->error_count; | |
903 | ||
904 | if (row < 0) | |
905 | return; | |
906 | ||
907 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); | |
908 | ||
909 | if (type == HW_EVENT_ERR_CORRECTED) { | |
910 | mci->csrows[row]->ce_count += count; | |
911 | if (chan >= 0) | |
912 | mci->csrows[row]->channels[chan]->ce_count += count; | |
913 | } else { | |
914 | mci->csrows[row]->ue_count += count; | |
915 | } | |
916 | } | |
917 | ||
91b327f6 | 918 | void edac_raw_mc_handle_error(struct edac_raw_error_desc *e) |
e7e24830 | 919 | { |
91b327f6 | 920 | struct mem_ctl_info *mci = error_desc_to_mci(e); |
787d8999 RR |
921 | u8 grain_bits; |
922 | ||
923 | /* Sanity-check driver-supplied grain value. */ | |
924 | if (WARN_ON_ONCE(!e->grain)) | |
925 | e->grain = 1; | |
926 | ||
927 | grain_bits = fls_long(e->grain - 1); | |
928 | ||
929 | /* Report the error via the trace interface */ | |
930 | if (IS_ENABLED(CONFIG_RAS)) | |
672ef0e5 | 931 | trace_mc_event(e->type, e->msg, e->label, e->error_count, |
787d8999 RR |
932 | mci->mc_idx, e->top_layer, e->mid_layer, |
933 | e->low_layer, | |
934 | (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, | |
935 | grain_bits, e->syndrome, e->other_detail); | |
e7e24830 | 936 | |
1853ee72 RR |
937 | if (e->type == HW_EVENT_ERR_CORRECTED) |
938 | edac_ce_error(e); | |
939 | else | |
940 | edac_ue_error(e); | |
e7e24830 MCC |
941 | } |
942 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 | 943 | |
4275be63 MCC |
944 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
945 | struct mem_ctl_info *mci, | |
9eb07a7f | 946 | const u16 error_count, |
4275be63 MCC |
947 | const unsigned long page_frame_number, |
948 | const unsigned long offset_in_page, | |
949 | const unsigned long syndrome, | |
53f2d028 MCC |
950 | const int top_layer, |
951 | const int mid_layer, | |
952 | const int low_layer, | |
4275be63 | 953 | const char *msg, |
03f7eae8 | 954 | const char *other_detail) |
da9bb1d2 | 955 | { |
c498afaf | 956 | struct dimm_info *dimm; |
fca61165 | 957 | char *p, *end; |
4275be63 | 958 | int row = -1, chan = -1; |
53f2d028 | 959 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 960 | int i, n_labels = 0; |
c7ef7645 | 961 | struct edac_raw_error_desc *e = &mci->error_desc; |
67792cf9 | 962 | bool any_memory = true; |
fca61165 | 963 | const char *prefix; |
da9bb1d2 | 964 | |
956b9ba1 | 965 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 966 | |
c7ef7645 MCC |
967 | /* Fills the error report buffer */ |
968 | memset(e, 0, sizeof (*e)); | |
969 | e->error_count = error_count; | |
672ef0e5 | 970 | e->type = type; |
c7ef7645 MCC |
971 | e->top_layer = top_layer; |
972 | e->mid_layer = mid_layer; | |
973 | e->low_layer = low_layer; | |
974 | e->page_frame_number = page_frame_number; | |
975 | e->offset_in_page = offset_in_page; | |
976 | e->syndrome = syndrome; | |
1853ee72 RR |
977 | /* need valid strings here for both: */ |
978 | e->msg = msg ?: ""; | |
979 | e->other_detail = other_detail ?: ""; | |
c7ef7645 | 980 | |
4275be63 | 981 | /* |
67792cf9 | 982 | * Check if the event report is consistent and if the memory location is |
4aa92c86 RR |
983 | * known. If it is, the DIMM(s) label info will be filled and the DIMM's |
984 | * error counters will be incremented. | |
4275be63 MCC |
985 | */ |
986 | for (i = 0; i < mci->n_layers; i++) { | |
987 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
988 | |
989 | edac_mc_printk(mci, KERN_ERR, | |
990 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
991 | edac_layer_name[mci->layers[i].type], | |
992 | pos[i], mci->layers[i].size); | |
993 | /* | |
994 | * Instead of just returning it, let's use what's | |
995 | * known about the error. The increment routines and | |
996 | * the DIMM filter logic will do the right thing by | |
997 | * pointing the likely damaged DIMMs. | |
998 | */ | |
999 | pos[i] = -1; | |
1000 | } | |
1001 | if (pos[i] >= 0) | |
67792cf9 | 1002 | any_memory = false; |
da9bb1d2 AC |
1003 | } |
1004 | ||
4275be63 MCC |
1005 | /* |
1006 | * Get the dimm label/grain that applies to the match criteria. | |
1007 | * As the error algorithm may not be able to point to just one memory | |
1008 | * stick, the logic here will get all possible labels that could | |
1009 | * pottentially be affected by the error. | |
1010 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1011 | * to have only the MC channel and the MC dimm (also called "branch") | |
1012 | * but the channel is not known, as the memory is arranged in pairs, | |
1013 | * where each memory belongs to a separate channel within the same | |
1014 | * branch. | |
1015 | */ | |
c7ef7645 | 1016 | p = e->label; |
4275be63 | 1017 | *p = '\0'; |
fca61165 LB |
1018 | end = p + sizeof(e->label); |
1019 | prefix = ""; | |
4da1b7bf | 1020 | |
c498afaf | 1021 | mci_for_each_dimm(mci, dimm) { |
53f2d028 | 1022 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1023 | continue; |
53f2d028 | 1024 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1025 | continue; |
53f2d028 | 1026 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1027 | continue; |
da9bb1d2 | 1028 | |
4275be63 | 1029 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1030 | if (dimm->grain > e->grain) |
1031 | e->grain = dimm->grain; | |
9794f33d | 1032 | |
4275be63 MCC |
1033 | /* |
1034 | * If the error is memory-controller wide, there's no need to | |
67792cf9 RR |
1035 | * seek for the affected DIMMs because the whole channel/memory |
1036 | * controller/... may be affected. Also, don't show errors for | |
1037 | * empty DIMM slots. | |
4275be63 | 1038 | */ |
65bb4d1a | 1039 | if (!dimm->nr_pages) |
0d8292e0 | 1040 | continue; |
4275be63 | 1041 | |
0d8292e0 | 1042 | n_labels++; |
65bb4d1a RR |
1043 | if (n_labels > EDAC_MAX_LABELS) { |
1044 | p = e->label; | |
1045 | *p = '\0'; | |
1046 | } else { | |
fca61165 LB |
1047 | p += scnprintf(p, end - p, "%s%s", prefix, dimm->label); |
1048 | prefix = OTHER_LABEL; | |
4275be63 | 1049 | } |
0d8292e0 RR |
1050 | |
1051 | /* | |
1052 | * get csrow/channel of the DIMM, in order to allow | |
1053 | * incrementing the compat API counters | |
1054 | */ | |
1055 | edac_dbg(4, "%s csrows map: (%d,%d)\n", | |
1056 | mci->csbased ? "rank" : "dimm", | |
1057 | dimm->csrow, dimm->cschannel); | |
1058 | if (row == -1) | |
1059 | row = dimm->csrow; | |
1060 | else if (row >= 0 && row != dimm->csrow) | |
1061 | row = -2; | |
1062 | ||
1063 | if (chan == -1) | |
1064 | chan = dimm->cschannel; | |
1065 | else if (chan >= 0 && chan != dimm->cschannel) | |
1066 | chan = -2; | |
9794f33d | 1067 | } |
1068 | ||
67792cf9 | 1069 | if (any_memory) |
fca61165 | 1070 | strscpy(e->label, "any memory", sizeof(e->label)); |
6334dc4e | 1071 | else if (!*e->label) |
fca61165 | 1072 | strscpy(e->label, "unknown memory", sizeof(e->label)); |
6334dc4e RR |
1073 | |
1074 | edac_inc_csrow(e, row, chan); | |
9794f33d | 1075 | |
4275be63 | 1076 | /* Fill the RAM location data */ |
c7ef7645 | 1077 | p = e->location; |
fca61165 LB |
1078 | end = p + sizeof(e->location); |
1079 | prefix = ""; | |
4da1b7bf | 1080 | |
4275be63 MCC |
1081 | for (i = 0; i < mci->n_layers; i++) { |
1082 | if (pos[i] < 0) | |
1083 | continue; | |
9794f33d | 1084 | |
fca61165 LB |
1085 | p += scnprintf(p, end - p, "%s%s:%d", prefix, |
1086 | edac_layer_name[mci->layers[i].type], pos[i]); | |
1087 | prefix = " "; | |
9794f33d | 1088 | } |
53f2d028 | 1089 | |
91b327f6 | 1090 | edac_raw_mc_handle_error(e); |
9794f33d | 1091 | } |
4275be63 | 1092 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |