Commit | Line | Data |
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7c9281d7 DT |
1 | /* |
2 | * Defines, structures, APIs for edac_core module | |
3 | * | |
4 | * (C) 2007 Linux Networx (http://lnxi.com) | |
5 | * This file may be distributed under the terms of the | |
6 | * GNU General Public License. | |
7 | * | |
8 | * Written by Thayne Harbaugh | |
9 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
10 | * http://www.anime.net/~goemon/linux-ecc/ | |
11 | * | |
12 | * NMI handling support added by | |
13 | * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com> | |
14 | * | |
15 | * Refactored for multi-source files: | |
16 | * Doug Thompson <norsk5@xmission.com> | |
17 | * | |
18 | */ | |
19 | ||
20 | #ifndef _EDAC_CORE_H_ | |
21 | #define _EDAC_CORE_H_ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/nmi.h> | |
31 | #include <linux/rcupdate.h> | |
32 | #include <linux/completion.h> | |
33 | #include <linux/kobject.h> | |
34 | #include <linux/platform_device.h> | |
e27e3dac DT |
35 | #include <linux/sysdev.h> |
36 | #include <linux/workqueue.h> | |
7c9281d7 DT |
37 | |
38 | #define EDAC_MC_LABEL_LEN 31 | |
e27e3dac DT |
39 | #define EDAC_DEVICE_NAME_LEN 31 |
40 | #define EDAC_ATTRIB_VALUE_LEN 15 | |
41 | #define MC_PROC_NAME_MAX_LEN 7 | |
7c9281d7 DT |
42 | |
43 | #if PAGE_SHIFT < 20 | |
44 | #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) ) | |
45 | #else /* PAGE_SHIFT > 20 */ | |
46 | #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) ) | |
47 | #endif | |
48 | ||
49 | #define edac_printk(level, prefix, fmt, arg...) \ | |
50 | printk(level "EDAC " prefix ": " fmt, ##arg) | |
51 | ||
cc18e3cd HM |
52 | #define edac_printk_verbose(level, prefix, fmt, arg...) \ |
53 | printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt, \ | |
54 | __FILE__, __LINE__, ##arg) | |
55 | ||
7c9281d7 DT |
56 | #define edac_mc_printk(mci, level, fmt, arg...) \ |
57 | printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg) | |
58 | ||
59 | #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \ | |
60 | printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg) | |
61 | ||
e27e3dac DT |
62 | /* edac_device printk */ |
63 | #define edac_device_printk(ctl, level, fmt, arg...) \ | |
64 | printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg) | |
65 | ||
91b99041 DJ |
66 | /* edac_pci printk */ |
67 | #define edac_pci_printk(ctl, level, fmt, arg...) \ | |
68 | printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg) | |
69 | ||
7c9281d7 DT |
70 | /* prefixes for edac_printk() and edac_mc_printk() */ |
71 | #define EDAC_MC "MC" | |
72 | #define EDAC_PCI "PCI" | |
73 | #define EDAC_DEBUG "DEBUG" | |
74 | ||
75 | #ifdef CONFIG_EDAC_DEBUG | |
76 | extern int edac_debug_level; | |
239642fe | 77 | extern const char *edac_mem_types[]; |
7c9281d7 | 78 | |
cc18e3cd | 79 | #ifndef CONFIG_EDAC_DEBUG_VERBOSE |
d357cbb4 BP |
80 | #define edac_debug_printk(level, fmt, arg...) \ |
81 | do { \ | |
82 | if (level <= edac_debug_level) \ | |
83 | edac_printk(KERN_DEBUG, EDAC_DEBUG, \ | |
84 | "%s: " fmt, __func__, ##arg); \ | |
cc18e3cd HM |
85 | } while (0) |
86 | #else /* CONFIG_EDAC_DEBUG_VERBOSE */ | |
87 | #define edac_debug_printk(level, fmt, arg...) \ | |
88 | do { \ | |
89 | if (level <= edac_debug_level) \ | |
90 | edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \ | |
91 | ##arg); \ | |
92 | } while (0) | |
93 | #endif | |
7c9281d7 DT |
94 | |
95 | #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ ) | |
96 | #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ ) | |
97 | #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ ) | |
98 | #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ ) | |
99 | #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ ) | |
100 | ||
079708b9 | 101 | #else /* !CONFIG_EDAC_DEBUG */ |
7c9281d7 DT |
102 | |
103 | #define debugf0( ... ) | |
104 | #define debugf1( ... ) | |
105 | #define debugf2( ... ) | |
106 | #define debugf3( ... ) | |
107 | #define debugf4( ... ) | |
108 | ||
079708b9 | 109 | #endif /* !CONFIG_EDAC_DEBUG */ |
7c9281d7 | 110 | |
7c9281d7 DT |
111 | #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \ |
112 | PCI_DEVICE_ID_ ## vend ## _ ## dev | |
113 | ||
17aa7e03 | 114 | #define edac_dev_name(dev) (dev)->dev_name |
7c9281d7 DT |
115 | |
116 | /* memory devices */ | |
117 | enum dev_type { | |
118 | DEV_UNKNOWN = 0, | |
119 | DEV_X1, | |
120 | DEV_X2, | |
121 | DEV_X4, | |
122 | DEV_X8, | |
123 | DEV_X16, | |
124 | DEV_X32, /* Do these parts exist? */ | |
125 | DEV_X64 /* Do these parts exist? */ | |
126 | }; | |
127 | ||
128 | #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) | |
129 | #define DEV_FLAG_X1 BIT(DEV_X1) | |
130 | #define DEV_FLAG_X2 BIT(DEV_X2) | |
131 | #define DEV_FLAG_X4 BIT(DEV_X4) | |
132 | #define DEV_FLAG_X8 BIT(DEV_X8) | |
133 | #define DEV_FLAG_X16 BIT(DEV_X16) | |
134 | #define DEV_FLAG_X32 BIT(DEV_X32) | |
135 | #define DEV_FLAG_X64 BIT(DEV_X64) | |
136 | ||
137 | /* memory types */ | |
138 | enum mem_type { | |
139 | MEM_EMPTY = 0, /* Empty csrow */ | |
140 | MEM_RESERVED, /* Reserved csrow type */ | |
141 | MEM_UNKNOWN, /* Unknown csrow type */ | |
142 | MEM_FPM, /* Fast page mode */ | |
143 | MEM_EDO, /* Extended data out */ | |
144 | MEM_BEDO, /* Burst Extended data out */ | |
145 | MEM_SDR, /* Single data rate SDRAM */ | |
146 | MEM_RDR, /* Registered single data rate SDRAM */ | |
147 | MEM_DDR, /* Double data rate SDRAM */ | |
148 | MEM_RDDR, /* Registered Double data rate SDRAM */ | |
149 | MEM_RMBS, /* Rambus DRAM */ | |
079708b9 DT |
150 | MEM_DDR2, /* DDR2 RAM */ |
151 | MEM_FB_DDR2, /* fully buffered DDR2 */ | |
152 | MEM_RDDR2, /* Registered DDR2 RAM */ | |
1d5f726c | 153 | MEM_XDR, /* Rambus XDR */ |
b1cfebc9 YS |
154 | MEM_DDR3, /* DDR3 RAM */ |
155 | MEM_RDDR3, /* Registered DDR3 RAM */ | |
7c9281d7 DT |
156 | }; |
157 | ||
158 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) | |
159 | #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) | |
160 | #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) | |
161 | #define MEM_FLAG_FPM BIT(MEM_FPM) | |
162 | #define MEM_FLAG_EDO BIT(MEM_EDO) | |
163 | #define MEM_FLAG_BEDO BIT(MEM_BEDO) | |
164 | #define MEM_FLAG_SDR BIT(MEM_SDR) | |
165 | #define MEM_FLAG_RDR BIT(MEM_RDR) | |
166 | #define MEM_FLAG_DDR BIT(MEM_DDR) | |
167 | #define MEM_FLAG_RDDR BIT(MEM_RDDR) | |
168 | #define MEM_FLAG_RMBS BIT(MEM_RMBS) | |
169 | #define MEM_FLAG_DDR2 BIT(MEM_DDR2) | |
170 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) | |
171 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) | |
1d5f726c | 172 | #define MEM_FLAG_XDR BIT(MEM_XDR) |
b1cfebc9 YS |
173 | #define MEM_FLAG_DDR3 BIT(MEM_DDR3) |
174 | #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) | |
7c9281d7 DT |
175 | |
176 | /* chipset Error Detection and Correction capabilities and mode */ | |
177 | enum edac_type { | |
178 | EDAC_UNKNOWN = 0, /* Unknown if ECC is available */ | |
179 | EDAC_NONE, /* Doesnt support ECC */ | |
180 | EDAC_RESERVED, /* Reserved ECC type */ | |
181 | EDAC_PARITY, /* Detects parity errors */ | |
182 | EDAC_EC, /* Error Checking - no correction */ | |
183 | EDAC_SECDED, /* Single bit error correction, Double detection */ | |
184 | EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */ | |
185 | EDAC_S4ECD4ED, /* Chipkill x4 devices */ | |
186 | EDAC_S8ECD8ED, /* Chipkill x8 devices */ | |
187 | EDAC_S16ECD16ED, /* Chipkill x16 devices */ | |
188 | }; | |
189 | ||
190 | #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) | |
191 | #define EDAC_FLAG_NONE BIT(EDAC_NONE) | |
192 | #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) | |
193 | #define EDAC_FLAG_EC BIT(EDAC_EC) | |
194 | #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) | |
195 | #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) | |
196 | #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) | |
197 | #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) | |
198 | #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) | |
199 | ||
200 | /* scrubbing capabilities */ | |
201 | enum scrub_type { | |
202 | SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */ | |
203 | SCRUB_NONE, /* No scrubber */ | |
204 | SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */ | |
205 | SCRUB_SW_SRC, /* Software scrub only errors */ | |
206 | SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */ | |
207 | SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */ | |
208 | SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */ | |
209 | SCRUB_HW_SRC, /* Hardware scrub only errors */ | |
210 | SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */ | |
211 | SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */ | |
212 | }; | |
213 | ||
214 | #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) | |
522a94bd DT |
215 | #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) |
216 | #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) | |
7c9281d7 DT |
217 | #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) |
218 | #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) | |
522a94bd DT |
219 | #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) |
220 | #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) | |
7c9281d7 DT |
221 | #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) |
222 | ||
223 | /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ | |
224 | ||
91b99041 DJ |
225 | /* EDAC internal operation states */ |
226 | #define OP_ALLOC 0x100 | |
227 | #define OP_RUNNING_POLL 0x201 | |
228 | #define OP_RUNNING_INTERRUPT 0x202 | |
229 | #define OP_RUNNING_POLL_INTR 0x203 | |
230 | #define OP_OFFLINE 0x300 | |
231 | ||
7c9281d7 DT |
232 | /* |
233 | * There are several things to be aware of that aren't at all obvious: | |
234 | * | |
235 | * | |
236 | * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. | |
237 | * | |
238 | * These are some of the many terms that are thrown about that don't always | |
239 | * mean what people think they mean (Inconceivable!). In the interest of | |
240 | * creating a common ground for discussion, terms and their definitions | |
241 | * will be established. | |
242 | * | |
243 | * Memory devices: The individual chip on a memory stick. These devices | |
244 | * commonly output 4 and 8 bits each. Grouping several | |
245 | * of these in parallel provides 64 bits which is common | |
246 | * for a memory stick. | |
247 | * | |
248 | * Memory Stick: A printed circuit board that agregates multiple | |
249 | * memory devices in parallel. This is the atomic | |
250 | * memory component that is purchaseable by Joe consumer | |
251 | * and loaded into a memory socket. | |
252 | * | |
253 | * Socket: A physical connector on the motherboard that accepts | |
254 | * a single memory stick. | |
255 | * | |
256 | * Channel: Set of memory devices on a memory stick that must be | |
257 | * grouped in parallel with one or more additional | |
258 | * channels from other memory sticks. This parallel | |
259 | * grouping of the output from multiple channels are | |
260 | * necessary for the smallest granularity of memory access. | |
261 | * Some memory controllers are capable of single channel - | |
262 | * which means that memory sticks can be loaded | |
263 | * individually. Other memory controllers are only | |
264 | * capable of dual channel - which means that memory | |
265 | * sticks must be loaded as pairs (see "socket set"). | |
266 | * | |
267 | * Chip-select row: All of the memory devices that are selected together. | |
268 | * for a single, minimum grain of memory access. | |
269 | * This selects all of the parallel memory devices across | |
270 | * all of the parallel channels. Common chip-select rows | |
271 | * for single channel are 64 bits, for dual channel 128 | |
272 | * bits. | |
273 | * | |
274 | * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory. | |
275 | * Motherboards commonly drive two chip-select pins to | |
276 | * a memory stick. A single-ranked stick, will occupy | |
277 | * only one of those rows. The other will be unused. | |
278 | * | |
279 | * Double-Ranked stick: A double-ranked stick has two chip-select rows which | |
280 | * access different sets of memory devices. The two | |
281 | * rows cannot be accessed concurrently. | |
282 | * | |
283 | * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. | |
284 | * A double-sided stick has two chip-select rows which | |
285 | * access different sets of memory devices. The two | |
286 | * rows cannot be accessed concurrently. "Double-sided" | |
287 | * is irrespective of the memory devices being mounted | |
288 | * on both sides of the memory stick. | |
289 | * | |
411c9403 | 290 | * Socket set: All of the memory sticks that are required for |
7c9281d7 DT |
291 | * a single memory access or all of the memory sticks |
292 | * spanned by a chip-select row. A single socket set | |
293 | * has two chip-select rows and if double-sided sticks | |
294 | * are used these will occupy those chip-select rows. | |
295 | * | |
296 | * Bank: This term is avoided because it is unclear when | |
297 | * needing to distinguish between chip-select rows and | |
298 | * socket sets. | |
299 | * | |
300 | * Controller pages: | |
301 | * | |
302 | * Physical pages: | |
303 | * | |
304 | * Virtual pages: | |
305 | * | |
306 | * | |
307 | * STRUCTURE ORGANIZATION AND CHOICES | |
308 | * | |
309 | * | |
310 | * | |
311 | * PS - I enjoyed writing all that about as much as you enjoyed reading it. | |
312 | */ | |
313 | ||
314 | struct channel_info { | |
315 | int chan_idx; /* channel index */ | |
316 | u32 ce_count; /* Correctable Errors for this CHANNEL */ | |
079708b9 | 317 | char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ |
7c9281d7 DT |
318 | struct csrow_info *csrow; /* the parent */ |
319 | }; | |
320 | ||
321 | struct csrow_info { | |
322 | unsigned long first_page; /* first page number in dimm */ | |
323 | unsigned long last_page; /* last page number in dimm */ | |
324 | unsigned long page_mask; /* used for interleaving - | |
325 | * 0UL for non intlv | |
326 | */ | |
327 | u32 nr_pages; /* number of pages in csrow */ | |
328 | u32 grain; /* granularity of reported error in bytes */ | |
329 | int csrow_idx; /* the chip-select row */ | |
330 | enum dev_type dtype; /* memory device type */ | |
331 | u32 ue_count; /* Uncorrectable Errors for this csrow */ | |
332 | u32 ce_count; /* Correctable Errors for this csrow */ | |
333 | enum mem_type mtype; /* memory csrow type */ | |
334 | enum edac_type edac_mode; /* EDAC mode for this csrow */ | |
335 | struct mem_ctl_info *mci; /* the parent */ | |
336 | ||
337 | struct kobject kobj; /* sysfs kobject for this csrow */ | |
7c9281d7 | 338 | |
8096cfaf | 339 | /* channel information for this csrow */ |
7c9281d7 DT |
340 | u32 nr_channels; |
341 | struct channel_info *channels; | |
342 | }; | |
343 | ||
9fa2fc2e MCC |
344 | struct mcidev_sysfs_group { |
345 | const char *name; | |
346 | struct mcidev_sysfs_attribute *mcidev_attr; | |
347 | struct kobject kobj; | |
348 | }; | |
349 | ||
350 | ||
42a8e397 DT |
351 | /* mcidev_sysfs_attribute structure |
352 | * used for driver sysfs attributes and in mem_ctl_info | |
353 | * sysfs top level entries | |
354 | */ | |
355 | struct mcidev_sysfs_attribute { | |
9fa2fc2e MCC |
356 | struct attribute attr; |
357 | ||
358 | struct mcidev_sysfs_group *grp; | |
359 | ||
42a8e397 DT |
360 | ssize_t (*show)(struct mem_ctl_info *,char *); |
361 | ssize_t (*store)(struct mem_ctl_info *, const char *,size_t); | |
362 | }; | |
363 | ||
364 | /* MEMORY controller information structure | |
365 | */ | |
7c9281d7 | 366 | struct mem_ctl_info { |
079708b9 | 367 | struct list_head link; /* for global list of mem_ctl_info structs */ |
1c3631ff DT |
368 | |
369 | struct module *owner; /* Module owner of this control struct */ | |
370 | ||
7c9281d7 DT |
371 | unsigned long mtype_cap; /* memory types supported by mc */ |
372 | unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ | |
373 | unsigned long edac_cap; /* configuration capabilities - this is | |
374 | * closely related to edac_ctl_cap. The | |
375 | * difference is that the controller may be | |
376 | * capable of s4ecd4ed which would be listed | |
377 | * in edac_ctl_cap, but if channels aren't | |
378 | * capable of s4ecd4ed then the edac_cap would | |
379 | * not have that capability. | |
380 | */ | |
381 | unsigned long scrub_cap; /* chipset scrub capabilities */ | |
382 | enum scrub_type scrub_mode; /* current scrub mode */ | |
383 | ||
384 | /* Translates sdram memory scrub rate given in bytes/sec to the | |
385 | internal representation and configures whatever else needs | |
386 | to be configured. | |
079708b9 DT |
387 | */ |
388 | int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw); | |
7c9281d7 DT |
389 | |
390 | /* Get the current sdram memory scrub rate from the internal | |
391 | representation and converts it to the closest matching | |
392 | bandwith in bytes/sec. | |
079708b9 DT |
393 | */ |
394 | int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw); | |
7c9281d7 | 395 | |
42a8e397 | 396 | |
7c9281d7 DT |
397 | /* pointer to edac checking routine */ |
398 | void (*edac_check) (struct mem_ctl_info * mci); | |
399 | ||
400 | /* | |
401 | * Remaps memory pages: controller pages to physical pages. | |
402 | * For most MC's, this will be NULL. | |
403 | */ | |
404 | /* FIXME - why not send the phys page to begin with? */ | |
405 | unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, | |
079708b9 | 406 | unsigned long page); |
7c9281d7 DT |
407 | int mc_idx; |
408 | int nr_csrows; | |
409 | struct csrow_info *csrows; | |
410 | /* | |
411 | * FIXME - what about controllers on other busses? - IDs must be | |
412 | * unique. dev pointer should be sufficiently unique, but | |
413 | * BUS:SLOT.FUNC numbers may not be unique. | |
414 | */ | |
415 | struct device *dev; | |
416 | const char *mod_name; | |
417 | const char *mod_ver; | |
418 | const char *ctl_name; | |
c4192705 | 419 | const char *dev_name; |
7c9281d7 DT |
420 | char proc_name[MC_PROC_NAME_MAX_LEN + 1]; |
421 | void *pvt_info; | |
422 | u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */ | |
423 | u32 ce_noinfo_count; /* Correctable Errors w/o info */ | |
424 | u32 ue_count; /* Total Uncorrectable Errors for this MC */ | |
425 | u32 ce_count; /* Total Correctable Errors for this MC */ | |
426 | unsigned long start_time; /* mci load start time (in jiffies) */ | |
427 | ||
428 | /* this stuff is for safe removal of mc devices from global list while | |
429 | * NMI handlers may be traversing list | |
430 | */ | |
431 | struct rcu_head rcu; | |
432 | struct completion complete; | |
433 | ||
434 | /* edac sysfs device control */ | |
435 | struct kobject edac_mci_kobj; | |
81d87cb1 | 436 | |
42a8e397 DT |
437 | /* Additional top controller level attributes, but specified |
438 | * by the low level driver. | |
439 | * | |
440 | * Set by the low level driver to provide attributes at the | |
441 | * controller level, same level as 'ue_count' and 'ce_count' above. | |
442 | * An array of structures, NULL terminated | |
443 | * | |
444 | * If attributes are desired, then set to array of attributes | |
445 | * If no attributes are desired, leave NULL | |
446 | */ | |
447 | struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; | |
448 | ||
81d87cb1 | 449 | /* work struct for this MC */ |
81d87cb1 | 450 | struct delayed_work work; |
86aa8cb7 | 451 | |
81d87cb1 DJ |
452 | /* the internal state of this controller instance */ |
453 | int op_state; | |
7c9281d7 DT |
454 | }; |
455 | ||
e27e3dac | 456 | /* |
42a8e397 | 457 | * The following are the structures to provide for a generic |
e27e3dac DT |
458 | * or abstract 'edac_device'. This set of structures and the |
459 | * code that implements the APIs for the same, provide for | |
460 | * registering EDAC type devices which are NOT standard memory. | |
461 | * | |
462 | * CPU caches (L1 and L2) | |
463 | * DMA engines | |
464 | * Core CPU swithces | |
465 | * Fabric switch units | |
466 | * PCIe interface controllers | |
467 | * other EDAC/ECC type devices that can be monitored for | |
468 | * errors, etc. | |
469 | * | |
470 | * It allows for a 2 level set of hiearchry. For example: | |
471 | * | |
472 | * cache could be composed of L1, L2 and L3 levels of cache. | |
473 | * Each CPU core would have its own L1 cache, while sharing | |
474 | * L2 and maybe L3 caches. | |
475 | * | |
476 | * View them arranged, via the sysfs presentation: | |
477 | * /sys/devices/system/edac/.. | |
478 | * | |
479 | * mc/ <existing memory device directory> | |
480 | * cpu/cpu0/.. <L1 and L2 block directory> | |
481 | * /L1-cache/ce_count | |
482 | * /ue_count | |
483 | * /L2-cache/ce_count | |
484 | * /ue_count | |
485 | * cpu/cpu1/.. <L1 and L2 block directory> | |
486 | * /L1-cache/ce_count | |
487 | * /ue_count | |
488 | * /L2-cache/ce_count | |
489 | * /ue_count | |
490 | * ... | |
491 | * | |
492 | * the L1 and L2 directories would be "edac_device_block's" | |
493 | */ | |
494 | ||
495 | struct edac_device_counter { | |
079708b9 DT |
496 | u32 ue_count; |
497 | u32 ce_count; | |
e27e3dac DT |
498 | }; |
499 | ||
fd309a9d DT |
500 | /* forward reference */ |
501 | struct edac_device_ctl_info; | |
502 | struct edac_device_block; | |
e27e3dac | 503 | |
fd309a9d DT |
504 | /* edac_dev_sysfs_attribute structure |
505 | * used for driver sysfs attributes in mem_ctl_info | |
506 | * for extra controls and attributes: | |
507 | * like high level error Injection controls | |
508 | */ | |
509 | struct edac_dev_sysfs_attribute { | |
510 | struct attribute attr; | |
511 | ssize_t (*show)(struct edac_device_ctl_info *, char *); | |
512 | ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t); | |
e27e3dac DT |
513 | }; |
514 | ||
fd309a9d | 515 | /* edac_dev_sysfs_block_attribute structure |
b2a4ac0c | 516 | * |
fd309a9d | 517 | * used in leaf 'block' nodes for adding controls/attributes |
b2a4ac0c DT |
518 | * |
519 | * each block in each instance of the containing control structure | |
520 | * can have an array of the following. The show and store functions | |
521 | * will be filled in with the show/store function in the | |
522 | * low level driver. | |
523 | * | |
524 | * The 'value' field will be the actual value field used for | |
525 | * counting | |
e27e3dac | 526 | */ |
fd309a9d DT |
527 | struct edac_dev_sysfs_block_attribute { |
528 | struct attribute attr; | |
529 | ssize_t (*show)(struct kobject *, struct attribute *, char *); | |
530 | ssize_t (*store)(struct kobject *, struct attribute *, | |
531 | const char *, size_t); | |
532 | struct edac_device_block *block; | |
533 | ||
fd309a9d | 534 | unsigned int value; |
e27e3dac DT |
535 | }; |
536 | ||
537 | /* device block control structure */ | |
538 | struct edac_device_block { | |
539 | struct edac_device_instance *instance; /* Up Pointer */ | |
079708b9 | 540 | char name[EDAC_DEVICE_NAME_LEN + 1]; |
e27e3dac DT |
541 | |
542 | struct edac_device_counter counters; /* basic UE and CE counters */ | |
543 | ||
079708b9 | 544 | int nr_attribs; /* how many attributes */ |
fd309a9d DT |
545 | |
546 | /* this block's attributes, could be NULL */ | |
547 | struct edac_dev_sysfs_block_attribute *block_attributes; | |
e27e3dac DT |
548 | |
549 | /* edac sysfs device control */ | |
550 | struct kobject kobj; | |
e27e3dac DT |
551 | }; |
552 | ||
553 | /* device instance control structure */ | |
554 | struct edac_device_instance { | |
555 | struct edac_device_ctl_info *ctl; /* Up pointer */ | |
556 | char name[EDAC_DEVICE_NAME_LEN + 4]; | |
557 | ||
558 | struct edac_device_counter counters; /* instance counters */ | |
559 | ||
079708b9 | 560 | u32 nr_blocks; /* how many blocks */ |
e27e3dac DT |
561 | struct edac_device_block *blocks; /* block array */ |
562 | ||
563 | /* edac sysfs device control */ | |
564 | struct kobject kobj; | |
e27e3dac DT |
565 | }; |
566 | ||
42a8e397 | 567 | |
e27e3dac DT |
568 | /* |
569 | * Abstract edac_device control info structure | |
570 | * | |
571 | */ | |
572 | struct edac_device_ctl_info { | |
573 | /* for global list of edac_device_ctl_info structs */ | |
574 | struct list_head link; | |
575 | ||
1c3631ff DT |
576 | struct module *owner; /* Module owner of this control struct */ |
577 | ||
e27e3dac DT |
578 | int dev_idx; |
579 | ||
580 | /* Per instance controls for this edac_device */ | |
581 | int log_ue; /* boolean for logging UEs */ | |
582 | int log_ce; /* boolean for logging CEs */ | |
583 | int panic_on_ue; /* boolean for panic'ing on an UE */ | |
584 | unsigned poll_msec; /* number of milliseconds to poll interval */ | |
585 | unsigned long delay; /* number of jiffies for poll_msec */ | |
586 | ||
42a8e397 DT |
587 | /* Additional top controller level attributes, but specified |
588 | * by the low level driver. | |
589 | * | |
590 | * Set by the low level driver to provide attributes at the | |
591 | * controller level, same level as 'ue_count' and 'ce_count' above. | |
592 | * An array of structures, NULL terminated | |
593 | * | |
594 | * If attributes are desired, then set to array of attributes | |
595 | * If no attributes are desired, leave NULL | |
596 | */ | |
597 | struct edac_dev_sysfs_attribute *sysfs_attributes; | |
598 | ||
599 | /* pointer to main 'edac' class in sysfs */ | |
600 | struct sysdev_class *edac_class; | |
e27e3dac DT |
601 | |
602 | /* the internal state of this controller instance */ | |
603 | int op_state; | |
e27e3dac | 604 | /* work struct for this instance */ |
e27e3dac | 605 | struct delayed_work work; |
e27e3dac DT |
606 | |
607 | /* pointer to edac polling checking routine: | |
079708b9 DT |
608 | * If NOT NULL: points to polling check routine |
609 | * If NULL: Then assumes INTERRUPT operation, where | |
610 | * MC driver will receive events | |
e27e3dac DT |
611 | */ |
612 | void (*edac_check) (struct edac_device_ctl_info * edac_dev); | |
613 | ||
614 | struct device *dev; /* pointer to device structure */ | |
615 | ||
616 | const char *mod_name; /* module name */ | |
617 | const char *ctl_name; /* edac controller name */ | |
c4192705 | 618 | const char *dev_name; /* pci/platform/etc... name */ |
e27e3dac DT |
619 | |
620 | void *pvt_info; /* pointer to 'private driver' info */ | |
621 | ||
079708b9 | 622 | unsigned long start_time; /* edac_device load start time (jiffies) */ |
e27e3dac DT |
623 | |
624 | /* these are for safe removal of mc devices from global list while | |
625 | * NMI handlers may be traversing list | |
626 | */ | |
627 | struct rcu_head rcu; | |
1c3631ff | 628 | struct completion removal_complete; |
e27e3dac DT |
629 | |
630 | /* sysfs top name under 'edac' directory | |
631 | * and instance name: | |
079708b9 DT |
632 | * cpu/cpu0/... |
633 | * cpu/cpu1/... | |
634 | * cpu/cpu2/... | |
635 | * ... | |
e27e3dac DT |
636 | */ |
637 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
638 | ||
639 | /* Number of instances supported on this control structure | |
640 | * and the array of those instances | |
641 | */ | |
642 | u32 nr_instances; | |
643 | struct edac_device_instance *instances; | |
644 | ||
645 | /* Event counters for the this whole EDAC Device */ | |
646 | struct edac_device_counter counters; | |
647 | ||
648 | /* edac sysfs device control for the 'name' | |
649 | * device this structure controls | |
650 | */ | |
651 | struct kobject kobj; | |
e27e3dac DT |
652 | }; |
653 | ||
654 | /* To get from the instance's wq to the beginning of the ctl structure */ | |
81d87cb1 DJ |
655 | #define to_edac_mem_ctl_work(w) \ |
656 | container_of(w, struct mem_ctl_info, work) | |
657 | ||
e27e3dac DT |
658 | #define to_edac_device_ctl_work(w) \ |
659 | container_of(w,struct edac_device_ctl_info,work) | |
660 | ||
e27e3dac DT |
661 | /* |
662 | * The alloc() and free() functions for the 'edac_device' control info | |
663 | * structure. A MC driver will allocate one of these for each edac_device | |
664 | * it is going to control/register with the EDAC CORE. | |
665 | */ | |
666 | extern struct edac_device_ctl_info *edac_device_alloc_ctl_info( | |
079708b9 | 667 | unsigned sizeof_private, |
fd309a9d DT |
668 | char *edac_device_name, unsigned nr_instances, |
669 | char *edac_block_name, unsigned nr_blocks, | |
079708b9 | 670 | unsigned offset_value, |
fd309a9d | 671 | struct edac_dev_sysfs_block_attribute *block_attributes, |
d45e7823 DT |
672 | unsigned nr_attribs, |
673 | int device_index); | |
e27e3dac DT |
674 | |
675 | /* The offset value can be: | |
676 | * -1 indicating no offset value | |
677 | * 0 for zero-based block numbers | |
678 | * 1 for 1-based block number | |
679 | * other for other-based block number | |
680 | */ | |
681 | #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1) | |
682 | ||
079708b9 | 683 | extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info); |
e27e3dac | 684 | |
7c9281d7 DT |
685 | #ifdef CONFIG_PCI |
686 | ||
91b99041 | 687 | struct edac_pci_counter { |
079708b9 DT |
688 | atomic_t pe_count; |
689 | atomic_t npe_count; | |
91b99041 DJ |
690 | }; |
691 | ||
692 | /* | |
693 | * Abstract edac_pci control info structure | |
694 | * | |
695 | */ | |
696 | struct edac_pci_ctl_info { | |
697 | /* for global list of edac_pci_ctl_info structs */ | |
698 | struct list_head link; | |
699 | ||
700 | int pci_idx; | |
701 | ||
91b99041 DJ |
702 | struct sysdev_class *edac_class; /* pointer to class */ |
703 | ||
704 | /* the internal state of this controller instance */ | |
705 | int op_state; | |
706 | /* work struct for this instance */ | |
91b99041 | 707 | struct delayed_work work; |
91b99041 DJ |
708 | |
709 | /* pointer to edac polling checking routine: | |
079708b9 DT |
710 | * If NOT NULL: points to polling check routine |
711 | * If NULL: Then assumes INTERRUPT operation, where | |
712 | * MC driver will receive events | |
91b99041 DJ |
713 | */ |
714 | void (*edac_check) (struct edac_pci_ctl_info * edac_dev); | |
715 | ||
716 | struct device *dev; /* pointer to device structure */ | |
717 | ||
718 | const char *mod_name; /* module name */ | |
719 | const char *ctl_name; /* edac controller name */ | |
720 | const char *dev_name; /* pci/platform/etc... name */ | |
721 | ||
722 | void *pvt_info; /* pointer to 'private driver' info */ | |
723 | ||
079708b9 | 724 | unsigned long start_time; /* edac_pci load start time (jiffies) */ |
91b99041 DJ |
725 | |
726 | /* these are for safe removal of devices from global list while | |
727 | * NMI handlers may be traversing list | |
728 | */ | |
729 | struct rcu_head rcu; | |
730 | struct completion complete; | |
731 | ||
732 | /* sysfs top name under 'edac' directory | |
733 | * and instance name: | |
079708b9 DT |
734 | * cpu/cpu0/... |
735 | * cpu/cpu1/... | |
736 | * cpu/cpu2/... | |
737 | * ... | |
91b99041 DJ |
738 | */ |
739 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
740 | ||
741 | /* Event counters for the this whole EDAC Device */ | |
742 | struct edac_pci_counter counters; | |
743 | ||
744 | /* edac sysfs device control for the 'name' | |
745 | * device this structure controls | |
746 | */ | |
747 | struct kobject kobj; | |
748 | struct completion kobj_complete; | |
749 | }; | |
750 | ||
751 | #define to_edac_pci_ctl_work(w) \ | |
752 | container_of(w, struct edac_pci_ctl_info,work) | |
753 | ||
7c9281d7 DT |
754 | /* write all or some bits in a byte-register*/ |
755 | static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value, | |
079708b9 | 756 | u8 mask) |
7c9281d7 DT |
757 | { |
758 | if (mask != 0xff) { | |
759 | u8 buf; | |
760 | ||
761 | pci_read_config_byte(pdev, offset, &buf); | |
762 | value &= mask; | |
763 | buf &= ~mask; | |
764 | value |= buf; | |
765 | } | |
766 | ||
767 | pci_write_config_byte(pdev, offset, value); | |
768 | } | |
769 | ||
770 | /* write all or some bits in a word-register*/ | |
771 | static inline void pci_write_bits16(struct pci_dev *pdev, int offset, | |
079708b9 | 772 | u16 value, u16 mask) |
7c9281d7 DT |
773 | { |
774 | if (mask != 0xffff) { | |
775 | u16 buf; | |
776 | ||
777 | pci_read_config_word(pdev, offset, &buf); | |
778 | value &= mask; | |
779 | buf &= ~mask; | |
780 | value |= buf; | |
781 | } | |
782 | ||
783 | pci_write_config_word(pdev, offset, value); | |
784 | } | |
785 | ||
e6da46b2 JH |
786 | /* |
787 | * pci_write_bits32 | |
788 | * | |
789 | * edac local routine to do pci_write_config_dword, but adds | |
790 | * a mask parameter. If mask is all ones, ignore the mask. | |
791 | * Otherwise utilize the mask to isolate specified bits | |
792 | * | |
793 | * write all or some bits in a dword-register | |
794 | */ | |
7c9281d7 | 795 | static inline void pci_write_bits32(struct pci_dev *pdev, int offset, |
079708b9 | 796 | u32 value, u32 mask) |
7c9281d7 | 797 | { |
e6da46b2 | 798 | if (mask != 0xffffffff) { |
7c9281d7 DT |
799 | u32 buf; |
800 | ||
801 | pci_read_config_dword(pdev, offset, &buf); | |
802 | value &= mask; | |
803 | buf &= ~mask; | |
804 | value |= buf; | |
805 | } | |
806 | ||
807 | pci_write_config_dword(pdev, offset, value); | |
808 | } | |
809 | ||
079708b9 | 810 | #endif /* CONFIG_PCI */ |
7c9281d7 | 811 | |
b8f6f975 DT |
812 | extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows, |
813 | unsigned nr_chans, int edac_index); | |
814 | extern int edac_mc_add_mc(struct mem_ctl_info *mci); | |
815 | extern void edac_mc_free(struct mem_ctl_info *mci); | |
079708b9 | 816 | extern struct mem_ctl_info *edac_mc_find(int idx); |
079708b9 | 817 | extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev); |
7c9281d7 | 818 | extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, |
079708b9 | 819 | unsigned long page); |
7c9281d7 DT |
820 | |
821 | /* | |
822 | * The no info errors are used when error overflows are reported. | |
823 | * There are a limited number of error logging registers that can | |
824 | * be exausted. When all registers are exhausted and an additional | |
825 | * error occurs then an error overflow register records that an | |
826 | * error occured and the type of error, but doesn't have any | |
827 | * further information. The ce/ue versions make for cleaner | |
828 | * reporting logic and function interface - reduces conditional | |
829 | * statement clutter and extra function arguments. | |
830 | */ | |
831 | extern void edac_mc_handle_ce(struct mem_ctl_info *mci, | |
079708b9 DT |
832 | unsigned long page_frame_number, |
833 | unsigned long offset_in_page, | |
834 | unsigned long syndrome, int row, int channel, | |
835 | const char *msg); | |
7c9281d7 | 836 | extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci, |
079708b9 | 837 | const char *msg); |
7c9281d7 | 838 | extern void edac_mc_handle_ue(struct mem_ctl_info *mci, |
079708b9 DT |
839 | unsigned long page_frame_number, |
840 | unsigned long offset_in_page, int row, | |
841 | const char *msg); | |
7c9281d7 | 842 | extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci, |
079708b9 DT |
843 | const char *msg); |
844 | extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow, | |
845 | unsigned int channel0, unsigned int channel1, | |
846 | char *msg); | |
847 | extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow, | |
848 | unsigned int channel, char *msg); | |
7c9281d7 DT |
849 | |
850 | /* | |
e27e3dac | 851 | * edac_device APIs |
7c9281d7 | 852 | */ |
d45e7823 | 853 | extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev); |
079708b9 | 854 | extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev); |
e27e3dac | 855 | extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev, |
b8f6f975 | 856 | int inst_nr, int block_nr, const char *msg); |
e27e3dac | 857 | extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev, |
b8f6f975 | 858 | int inst_nr, int block_nr, const char *msg); |
1dc9b70d | 859 | extern int edac_device_alloc_index(void); |
e27e3dac | 860 | |
91b99041 DJ |
861 | /* |
862 | * edac_pci APIs | |
863 | */ | |
b8f6f975 DT |
864 | extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt, |
865 | const char *edac_pci_name); | |
91b99041 DJ |
866 | |
867 | extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci); | |
868 | ||
b8f6f975 DT |
869 | extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci, |
870 | unsigned long value); | |
91b99041 | 871 | |
8641a384 | 872 | extern int edac_pci_alloc_index(void); |
91b99041 | 873 | extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx); |
079708b9 | 874 | extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev); |
91b99041 | 875 | |
b8f6f975 DT |
876 | extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl( |
877 | struct device *dev, | |
878 | const char *mod_name); | |
91b99041 DJ |
879 | |
880 | extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci); | |
881 | extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci); | |
882 | extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci); | |
883 | ||
884 | /* | |
885 | * edac misc APIs | |
886 | */ | |
494d0d55 | 887 | extern char *edac_op_state_to_string(int op_state); |
7c9281d7 DT |
888 | |
889 | #endif /* _EDAC_CORE_H_ */ |