projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier...
[linux-2.6-block.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/module.h>
21#include <linux/init.h>
806c35f5
AC		 22#include <linux/pci.h>
23#include <linux/pci_ids.h>
806c35f5 24#include <linux/slab.h>
c0d12172 25#include <linux/edac.h>
20bcb7a8 26#include "edac_core.h"
806c35f5 27
20bcb7a8 28#define E752X_REVISION " Ver: 2.0.2 " __DATE__
929a40ec 29#define EDAC_MOD_STR "e752x_edac"
37f04581 30
10d33e9c 31static int report_non_memory_errors;
96941026 32static int force_function_unhide;
94ee1cf5 33static int sysbus_parity = -1;
96941026 34
91b99041
DJ		 35static struct edac_pci_ctl_info *e752x_pci;
36
537fba28 37#define e752x_printk(level, fmt, arg...) \
e7ecd891 38 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 39
40#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 41 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 42
806c35f5
AC		 43#ifndef PCI_DEVICE_ID_INTEL_7520_0
44#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
45#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
46
47#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
48#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
49#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
50
51#ifndef PCI_DEVICE_ID_INTEL_7525_0
52#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
53#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
54
55#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
56#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
57#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
58
59#ifndef PCI_DEVICE_ID_INTEL_7320_0
60#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
61#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
62
63#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
64#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
65#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
66
5135b797
AK		 67#ifndef PCI_DEVICE_ID_INTEL_3100_0
68#define PCI_DEVICE_ID_INTEL_3100_0 0x35B0
69#endif /* PCI_DEVICE_ID_INTEL_3100_0 */
70
71#ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR
72#define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1
73#endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */
74
806c35f5
AC		 75#define E752X_NR_CSROWS 8 /* number of csrows */
76
806c35f5 77/* E752X register addresses - device 0 function 0 */
8004fd2a
PT		 78#define E752X_MCHSCRB 0x52 /* Memory Scrub register (16b) */
79 /*
80 * 6:5 Scrub Completion Count
81 * 3:2 Scrub Rate (i3100 only)
82 * 01=fast 10=normal
83 * 1:0 Scrub Mode enable
84 * 00=off 10=on
85 */
806c35f5
AC		 86#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
87#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
88 /*
89 * 31:30 Device width row 7
90 * 01=x8 10=x4 11=x8 DDR2
91 * 27:26 Device width row 6
92 * 23:22 Device width row 5
93 * 19:20 Device width row 4
94 * 15:14 Device width row 3
95 * 11:10 Device width row 2
96 * 7:6 Device width row 1
97 * 3:2 Device width row 0
98 */
99#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
100 /* FIXME:IS THIS RIGHT? */
101 /*
102 * 22 Number channels 0=1,1=2
103 * 19:18 DRB Granularity 32/64MB
104 */
105#define E752X_DRM 0x80 /* Dimm mapping register */
106#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
107 /*
108 * 14:12 1 single A, 2 single B, 3 dual
109 */
110#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
111#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
112#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
113#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
114
115/* E752X register addresses - device 0 function 1 */
116#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
117#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
118#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
119#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
120#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
121#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
122#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
123#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
124#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
125#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
126#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
127#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
128#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
10d33e9c 129#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI cmd reg (8b) */
806c35f5
AC		 130#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
131#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
132#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
133#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
134#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
135#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
136 /* error address register (32b) */
137 /*
138 * 31 Reserved
10d33e9c 139 * 30:2 CE address (64 byte block 34:6
806c35f5
AC		 140 * 1 Reserved
141 * 0 HiLoCS
142 */
143#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
144 /* error address register (32b) */
145 /*
146 * 31 Reserved
147 * 30:2 CE address (64 byte block 34:6)
148 * 1 Reserved
149 * 0 HiLoCS
150 */
151#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
152 /* error address register (32b) */
153 /*
154 * 31 Reserved
155 * 30:2 CE address (64 byte block 34:6)
156 * 1 Reserved
157 * 0 HiLoCS
158 */
10d33e9c 159#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM 1st uncorrectable scrub mem */
806c35f5
AC		 160 /* error address register (32b) */
161 /*
162 * 31 Reserved
10d33e9c 163 * 30:2 CE address (64 byte block 34:6
806c35f5
AC		 164 * 1 Reserved
165 * 0 HiLoCS
166 */
167#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
168 /* error syndrome register (16b) */
169#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
170 /* error syndrome register (16b) */
171#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
172
5135b797
AK		 173/* 3100 IMCH specific register addresses - device 0 function 1 */
174#define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */
175#define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */
176#define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */
177#define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */
178
806c35f5
AC		 179/* ICH5R register addresses - device 30 function 0 */
180#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
181#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
182#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
183
184enum e752x_chips {
185 E7520 = 0,
186 E7525 = 1,
5135b797
AK		 187 E7320 = 2,
188 I3100 = 3
806c35f5
AC		 189};
190
806c35f5
AC		 191struct e752x_pvt {
192 struct pci_dev *bridge_ck;
193 struct pci_dev *dev_d0f0;
194 struct pci_dev *dev_d0f1;
195 u32 tolm;
196 u32 remapbase;
197 u32 remaplimit;
198 int mc_symmetric;
199 u8 map[8];
200 int map_type;
201 const struct e752x_dev_info *dev_info;
202};
203
806c35f5
AC		 204struct e752x_dev_info {
205 u16 err_dev;
3847bccc 206 u16 ctl_dev;
806c35f5
AC		 207 const char *ctl_name;
208};
209
210struct e752x_error_info {
211 u32 ferr_global;
212 u32 nerr_global;
5135b797
AK		 213 u32 nsi_ferr; /* 3100 only */
214 u32 nsi_nerr; /* 3100 only */
215 u8 hi_ferr; /* all but 3100 */
216 u8 hi_nerr; /* all but 3100 */
806c35f5
AC		 217 u16 sysbus_ferr;
218 u16 sysbus_nerr;
219 u8 buf_ferr;
220 u8 buf_nerr;
221 u16 dram_ferr;
222 u16 dram_nerr;
223 u32 dram_sec1_add;
224 u32 dram_sec2_add;
225 u16 dram_sec1_syndrome;
226 u16 dram_sec2_syndrome;
227 u32 dram_ded_add;
228 u32 dram_scrb_add;
229 u32 dram_retr_add;
230};
231
232static const struct e752x_dev_info e752x_devs[] = {
233 [E7520] = {
052dfb45
DT		 234 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
235 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
236 .ctl_name = "E7520"},
806c35f5 237 [E7525] = {
052dfb45
DT		 238 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
239 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
240 .ctl_name = "E7525"},
806c35f5 241 [E7320] = {
052dfb45
DT		 242 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
243 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
244 .ctl_name = "E7320"},
5135b797
AK		 245 [I3100] = {
246 .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR,
247 .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0,
248 .ctl_name = "3100"},
806c35f5
AC		 249};
250
8004fd2a
PT		 251/* Valid scrub rates for the e752x/3100 hardware memory scrubber. We
252 * map the scrubbing bandwidth to a hardware register value. The 'set'
253 * operation finds the 'matching or higher value'. Note that scrubbing
254 * on the e752x can only be enabled/disabled. The 3100 supports
255 * a normal and fast mode.
256 */
257
258#define SDRATE_EOT 0xFFFFFFFF
259
260struct scrubrate {
261 u32 bandwidth; /* bandwidth consumed by scrubbing in bytes/sec */
262 u16 scrubval; /* register value for scrub rate */
263};
264
265/* Rate below assumes same performance as i3100 using PC3200 DDR2 in
266 * normal mode. e752x bridges don't support choosing normal or fast mode,
267 * so the scrubbing bandwidth value isn't all that important - scrubbing is
268 * either on or off.
269 */
270static const struct scrubrate scrubrates_e752x[] = {
271 {0, 0x00}, /* Scrubbing Off */
272 {500000, 0x02}, /* Scrubbing On */
273 {SDRATE_EOT, 0x00} /* End of Table */
274};
275
276/* Fast mode: 2 GByte PC3200 DDR2 scrubbed in 33s = 63161283 bytes/s
277 * Normal mode: 125 (32000 / 256) times slower than fast mode.
278 */
279static const struct scrubrate scrubrates_i3100[] = {
280 {0, 0x00}, /* Scrubbing Off */
281 {500000, 0x0a}, /* Normal mode - 32k clocks */
282 {62500000, 0x06}, /* Fast mode - 256 clocks */
283 {SDRATE_EOT, 0x00} /* End of Table */
284};
285
806c35f5 286static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
052dfb45 287 unsigned long page)
806c35f5
AC		 288{
289 u32 remap;
203333cb 290 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 291
537fba28 292 debugf3("%s()\n", __func__);
806c35f5
AC		 293
294 if (page < pvt->tolm)
295 return page;
e7ecd891 296
806c35f5
AC		 297 if ((page >= 0x100000) && (page < pvt->remapbase))
298 return page;
e7ecd891 299
806c35f5 300 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 301
806c35f5
AC		 302 if (remap < pvt->remaplimit)
303 return remap;
e7ecd891 304
537fba28 305 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 306 return pvt->tolm - 1;
307}
308
309static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
052dfb45 310 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 311{
312 u32 page;
313 int row;
314 int channel;
315 int i;
203333cb 316 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 317
537fba28 318 debugf3("%s()\n", __func__);
806c35f5
AC		 319
320 /* convert the addr to 4k page */
321 page = sec1_add >> (PAGE_SHIFT - 4);
322
323 /* FIXME - check for -1 */
324 if (pvt->mc_symmetric) {
325 /* chip select are bits 14 & 13 */
326 row = ((page >> 1) & 3);
537fba28 327 e752x_printk(KERN_WARNING,
052dfb45
DT		 328 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
329 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
330 pvt->map[4], pvt->map[5], pvt->map[6],
331 pvt->map[7]);
806c35f5
AC		 332
333 /* test for channel remapping */
334 for (i = 0; i < 8; i++) {
335 if (pvt->map[i] == row)
336 break;
337 }
e7ecd891 338
537fba28 339 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 340
806c35f5
AC		 341 if (i < 8)
342 row = i;
343 else
537fba28 344 e752x_mc_printk(mci, KERN_WARNING,
203333cb
DJ		 345 "row %d not found in remap table\n",
346 row);
806c35f5
AC		 347 } else
348 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 349
806c35f5
AC		 350 /* 0 = channel A, 1 = channel B */
351 channel = !(error_one & 1);
352
84db003f
MC		 353 /* e752x mc reads 34:6 of the DRAM linear address */
354 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
052dfb45 355 sec1_syndrome, row, channel, "e752x CE");
806c35f5
AC		 356}
357
806c35f5 358static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
052dfb45
DT		 359 u32 sec1_add, u16 sec1_syndrome, int *error_found,
360 int handle_error)
806c35f5
AC		 361{
362 *error_found = 1;
363
364 if (handle_error)
365 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
366}
367
e7ecd891 368static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
052dfb45 369 u32 ded_add, u32 scrb_add)
806c35f5
AC		 370{
371 u32 error_2b, block_page;
372 int row;
203333cb 373 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 374
537fba28 375 debugf3("%s()\n", __func__);
806c35f5
AC		 376
377 if (error_one & 0x0202) {
378 error_2b = ded_add;
e7ecd891 379
806c35f5
AC		 380 /* convert to 4k address */
381 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 382
806c35f5 383 row = pvt->mc_symmetric ?
052dfb45
DT		 384 /* chip select are bits 14 & 13 */
385 ((block_page >> 1) & 3) :
386 edac_mc_find_csrow_by_page(mci, block_page);
e7ecd891 387
84db003f
MC		 388 /* e752x mc reads 34:6 of the DRAM linear address */
389 edac_mc_handle_ue(mci, block_page,
052dfb45
DT		 390 offset_in_page(error_2b << 4),
391 row, "e752x UE from Read");
806c35f5
AC		 392 }
393 if (error_one & 0x0404) {
394 error_2b = scrb_add;
e7ecd891 395
806c35f5
AC		 396 /* convert to 4k address */
397 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 398
806c35f5 399 row = pvt->mc_symmetric ?
052dfb45
DT		 400 /* chip select are bits 14 & 13 */
401 ((block_page >> 1) & 3) :
402 edac_mc_find_csrow_by_page(mci, block_page);
e7ecd891 403
84db003f
MC		 404 /* e752x mc reads 34:6 of the DRAM linear address */
405 edac_mc_handle_ue(mci, block_page,
052dfb45
DT		 406 offset_in_page(error_2b << 4),
407 row, "e752x UE from Scruber");
806c35f5
AC		 408 }
409}
410
411static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
052dfb45
DT		 412 u32 ded_add, u32 scrb_add, int *error_found,
413 int handle_error)
806c35f5
AC		 414{
415 *error_found = 1;
416
417 if (handle_error)
418 do_process_ue(mci, error_one, ded_add, scrb_add);
419}
420
421static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
203333cb 422 int *error_found, int handle_error)
806c35f5
AC		 423{
424 *error_found = 1;
425
426 if (!handle_error)
427 return;
428
537fba28 429 debugf3("%s()\n", __func__);
806c35f5
AC		 430 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
431}
432
433static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
203333cb 434 u32 retry_add)
806c35f5
AC		 435{
436 u32 error_1b, page;
437 int row;
203333cb 438 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5
AC		 439
440 error_1b = retry_add;
10d33e9c
DT		 441 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
442
443 /* chip select are bits 14 & 13 */
444 row = pvt->mc_symmetric ? ((page >> 1) & 3) :
052dfb45 445 edac_mc_find_csrow_by_page(mci, page);
10d33e9c 446
537fba28 447 e752x_mc_printk(mci, KERN_WARNING,
203333cb
DJ		 448 "CE page 0x%lx, row %d : Memory read retry\n",
449 (long unsigned int)page, row);
806c35f5
AC		 450}
451
452static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
052dfb45
DT		 453 u32 retry_add, int *error_found,
454 int handle_error)
806c35f5
AC		 455{
456 *error_found = 1;
457
458 if (handle_error)
459 do_process_ded_retry(mci, error, retry_add);
460}
461
462static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
203333cb 463 int *error_found, int handle_error)
806c35f5
AC		 464{
465 *error_found = 1;
466
467 if (handle_error)
537fba28 468 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 469}
470
da9bb1d2 471static char *global_message[11] = {
10d33e9c
DT		 472 "PCI Express C1",
473 "PCI Express C",
474 "PCI Express B1",
475 "PCI Express B",
476 "PCI Express A1",
477 "PCI Express A",
478 "DMA Controller",
479 "HUB or NS Interface",
480 "System Bus",
481 "DRAM Controller", /* 9th entry */
482 "Internal Buffer"
806c35f5
AC		 483};
484
10d33e9c
DT		 485#define DRAM_ENTRY 9
486
da9bb1d2 487static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 488
489static void do_global_error(int fatal, u32 errors)
490{
491 int i;
492
493 for (i = 0; i < 11; i++) {
10d33e9c
DT		 494 if (errors & (1 << i)) {
495 /* If the error is from DRAM Controller OR
496 * we are to report ALL errors, then
497 * report the error
498 */
499 if ((i == DRAM_ENTRY) || report_non_memory_errors)
500 e752x_printk(KERN_WARNING, "%sError %s\n",
501 fatal_message[fatal],
502 global_message[i]);
503 }
806c35f5
AC		 504 }
505}
506
507static inline void global_error(int fatal, u32 errors, int *error_found,
203333cb 508 int handle_error)
806c35f5
AC		 509{
510 *error_found = 1;
511
512 if (handle_error)
513 do_global_error(fatal, errors);
514}
515
da9bb1d2 516static char *hub_message[7] = {
806c35f5
AC		 517 "HI Address or Command Parity", "HI Illegal Access",
518 "HI Internal Parity", "Out of Range Access",
519 "HI Data Parity", "Enhanced Config Access",
520 "Hub Interface Target Abort"
521};
522
523static void do_hub_error(int fatal, u8 errors)
524{
525 int i;
526
527 for (i = 0; i < 7; i++) {
528 if (errors & (1 << i))
537fba28 529 e752x_printk(KERN_WARNING, "%sError %s\n",
052dfb45 530 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 531 }
532}
533
534static inline void hub_error(int fatal, u8 errors, int *error_found,
052dfb45 535 int handle_error)
806c35f5
AC		 536{
537 *error_found = 1;
538
539 if (handle_error)
540 do_hub_error(fatal, errors);
541}
542
5135b797
AK		 543#define NSI_FATAL_MASK 0x0c080081
544#define NSI_NON_FATAL_MASK 0x23a0ba64
545#define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK)
546
547static char *nsi_message[30] = {
548 "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */
549 "", /* reserved */
550 "NSI Parity Error", /* bit 2, non-fatal */
551 "", /* reserved */
552 "", /* reserved */
553 "Correctable Error Message", /* bit 5, non-fatal */
554 "Non-Fatal Error Message", /* bit 6, non-fatal */
555 "Fatal Error Message", /* bit 7, fatal */
556 "", /* reserved */
557 "Receiver Error", /* bit 9, non-fatal */
558 "", /* reserved */
559 "Bad TLP", /* bit 11, non-fatal */
560 "Bad DLLP", /* bit 12, non-fatal */
561 "REPLAY_NUM Rollover", /* bit 13, non-fatal */
562 "", /* reserved */
563 "Replay Timer Timeout", /* bit 15, non-fatal */
564 "", /* reserved */
565 "", /* reserved */
566 "", /* reserved */
567 "Data Link Protocol Error", /* bit 19, fatal */
568 "", /* reserved */
569 "Poisoned TLP", /* bit 21, non-fatal */
570 "", /* reserved */
571 "Completion Timeout", /* bit 23, non-fatal */
572 "Completer Abort", /* bit 24, non-fatal */
573 "Unexpected Completion", /* bit 25, non-fatal */
574 "Receiver Overflow", /* bit 26, fatal */
575 "Malformed TLP", /* bit 27, fatal */
576 "", /* reserved */
577 "Unsupported Request" /* bit 29, non-fatal */
578};
579
580static void do_nsi_error(int fatal, u32 errors)
581{
582 int i;
583
584 for (i = 0; i < 30; i++) {
585 if (errors & (1 << i))
586 printk(KERN_WARNING "%sError %s\n",
587 fatal_message[fatal], nsi_message[i]);
588 }
589}
590
591static inline void nsi_error(int fatal, u32 errors, int *error_found,
592 int handle_error)
593{
594 *error_found = 1;
595
596 if (handle_error)
597 do_nsi_error(fatal, errors);
598}
599
da9bb1d2 600static char *membuf_message[4] = {
806c35f5
AC		 601 "Internal PMWB to DRAM parity",
602 "Internal PMWB to System Bus Parity",
603 "Internal System Bus or IO to PMWB Parity",
604 "Internal DRAM to PMWB Parity"
605};
606
607static void do_membuf_error(u8 errors)
608{
609 int i;
610
611 for (i = 0; i < 4; i++) {
612 if (errors & (1 << i))
537fba28 613 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
052dfb45 614 membuf_message[i]);
806c35f5
AC		 615 }
616}
617
618static inline void membuf_error(u8 errors, int *error_found, int handle_error)
619{
620 *error_found = 1;
621
622 if (handle_error)
623 do_membuf_error(errors);
624}
625
e009356f 626static char *sysbus_message[10] = {
806c35f5
AC		 627 "Addr or Request Parity",
628 "Data Strobe Glitch",
629 "Addr Strobe Glitch",
630 "Data Parity",
631 "Addr Above TOM",
632 "Non DRAM Lock Error",
633 "MCERR", "BINIT",
634 "Memory Parity",
635 "IO Subsystem Parity"
636};
637
638static void do_sysbus_error(int fatal, u32 errors)
639{
640 int i;
641
642 for (i = 0; i < 10; i++) {
643 if (errors & (1 << i))
537fba28 644 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
052dfb45 645 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 646 }
647}
648
649static inline void sysbus_error(int fatal, u32 errors, int *error_found,
203333cb 650 int handle_error)
806c35f5
AC		 651{
652 *error_found = 1;
653
654 if (handle_error)
655 do_sysbus_error(fatal, errors);
656}
657
e7ecd891 658static void e752x_check_hub_interface(struct e752x_error_info *info,
052dfb45 659 int *error_found, int handle_error)
806c35f5
AC		 660{
661 u8 stat8;
662
663 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 664
806c35f5 665 stat8 = info->hi_ferr;
e7ecd891 666
203333cb 667 if (stat8 & 0x7f) { /* Error, so process */
806c35f5 668 stat8 &= 0x7f;
e7ecd891 669
203333cb 670 if (stat8 & 0x2b)
806c35f5 671 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 672
203333cb 673 if (stat8 & 0x54)
806c35f5
AC		 674 hub_error(0, stat8 & 0x54, error_found, handle_error);
675 }
676 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 677
806c35f5 678 stat8 = info->hi_nerr;
e7ecd891 679
203333cb 680 if (stat8 & 0x7f) { /* Error, so process */
806c35f5 681 stat8 &= 0x7f;
e7ecd891 682
806c35f5
AC		 683 if (stat8 & 0x2b)
684 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 685
203333cb 686 if (stat8 & 0x54)
806c35f5
AC		 687 hub_error(0, stat8 & 0x54, error_found, handle_error);
688 }
689}
690
5135b797
AK		 691static void e752x_check_ns_interface(struct e752x_error_info *info,
692 int *error_found, int handle_error)
693{
694 u32 stat32;
695
696 stat32 = info->nsi_ferr;
697 if (stat32 & NSI_ERR_MASK) { /* Error, so process */
698 if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */
699 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
700 handle_error);
701 if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */
702 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
703 handle_error);
704 }
705 stat32 = info->nsi_nerr;
706 if (stat32 & NSI_ERR_MASK) {
707 if (stat32 & NSI_FATAL_MASK)
708 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
709 handle_error);
710 if (stat32 & NSI_NON_FATAL_MASK)
711 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
712 handle_error);
713 }
714}
715
e7ecd891 716static void e752x_check_sysbus(struct e752x_error_info *info,
052dfb45 717 int *error_found, int handle_error)
806c35f5
AC		 718{
719 u32 stat32, error32;
720
721 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
722 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
723
724 if (stat32 == 0)
203333cb 725 return; /* no errors */
806c35f5
AC		 726
727 error32 = (stat32 >> 16) & 0x3ff;
728 stat32 = stat32 & 0x3ff;
e7ecd891 729
203333cb 730 if (stat32 & 0x087)
dfb2a763 731 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
e7ecd891 732
203333cb 733 if (stat32 & 0x378)
dfb2a763 734 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
e7ecd891 735
203333cb 736 if (error32 & 0x087)
dfb2a763 737 sysbus_error(1, error32 & 0x087, error_found, handle_error);
e7ecd891 738
203333cb 739 if (error32 & 0x378)
dfb2a763 740 sysbus_error(0, error32 & 0x378, error_found, handle_error);
806c35f5
AC		 741}
742
203333cb 743static void e752x_check_membuf(struct e752x_error_info *info,
052dfb45 744 int *error_found, int handle_error)
806c35f5
AC		 745{
746 u8 stat8;
747
748 stat8 = info->buf_ferr;
e7ecd891 749
203333cb 750 if (stat8 & 0x0f) { /* Error, so process */
806c35f5
AC		 751 stat8 &= 0x0f;
752 membuf_error(stat8, error_found, handle_error);
753 }
e7ecd891 754
806c35f5 755 stat8 = info->buf_nerr;
e7ecd891 756
203333cb 757 if (stat8 & 0x0f) { /* Error, so process */
806c35f5
AC		 758 stat8 &= 0x0f;
759 membuf_error(stat8, error_found, handle_error);
760 }
761}
762
203333cb 763static void e752x_check_dram(struct mem_ctl_info *mci,
052dfb45
DT		 764 struct e752x_error_info *info, int *error_found,
765 int handle_error)
806c35f5
AC		 766{
767 u16 error_one, error_next;
768
769 error_one = info->dram_ferr;
770 error_next = info->dram_nerr;
771
772 /* decode and report errors */
203333cb 773 if (error_one & 0x0101) /* check first error correctable */
806c35f5 774 process_ce(mci, error_one, info->dram_sec1_add,
052dfb45 775 info->dram_sec1_syndrome, error_found, handle_error);
806c35f5 776
203333cb 777 if (error_next & 0x0101) /* check next error correctable */
806c35f5 778 process_ce(mci, error_next, info->dram_sec2_add,
052dfb45 779 info->dram_sec2_syndrome, error_found, handle_error);
806c35f5 780
203333cb 781 if (error_one & 0x4040)
806c35f5
AC		 782 process_ue_no_info_wr(mci, error_found, handle_error);
783
203333cb 784 if (error_next & 0x4040)
806c35f5
AC		 785 process_ue_no_info_wr(mci, error_found, handle_error);
786
203333cb 787 if (error_one & 0x2020)
806c35f5 788 process_ded_retry(mci, error_one, info->dram_retr_add,
052dfb45 789 error_found, handle_error);
806c35f5 790
203333cb 791 if (error_next & 0x2020)
806c35f5 792 process_ded_retry(mci, error_next, info->dram_retr_add,
052dfb45 793 error_found, handle_error);
806c35f5 794
203333cb
DJ		 795 if (error_one & 0x0808)
796 process_threshold_ce(mci, error_one, error_found, handle_error);
806c35f5 797
203333cb 798 if (error_next & 0x0808)
806c35f5 799 process_threshold_ce(mci, error_next, error_found,
052dfb45 800 handle_error);
806c35f5 801
203333cb 802 if (error_one & 0x0606)
806c35f5 803 process_ue(mci, error_one, info->dram_ded_add,
052dfb45 804 info->dram_scrb_add, error_found, handle_error);
806c35f5 805
203333cb 806 if (error_next & 0x0606)
806c35f5 807 process_ue(mci, error_next, info->dram_ded_add,
052dfb45 808 info->dram_scrb_add, error_found, handle_error);
806c35f5
AC		 809}
810
203333cb
DJ		 811static void e752x_get_error_info(struct mem_ctl_info *mci,
812 struct e752x_error_info *info)
806c35f5
AC		 813{
814 struct pci_dev *dev;
815 struct e752x_pvt *pvt;
816
817 memset(info, 0, sizeof(*info));
203333cb 818 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 819 dev = pvt->dev_d0f1;
806c35f5
AC		 820 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
821
822 if (info->ferr_global) {
5135b797
AK		 823 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
824 pci_read_config_dword(dev, I3100_NSI_FERR,
825 &info->nsi_ferr);
826 info->hi_ferr = 0;
827 } else {
828 pci_read_config_byte(dev, E752X_HI_FERR,
829 &info->hi_ferr);
830 info->nsi_ferr = 0;
831 }
806c35f5 832 pci_read_config_word(dev, E752X_SYSBUS_FERR,
052dfb45 833 &info->sysbus_ferr);
806c35f5 834 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
203333cb 835 pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr);
806c35f5 836 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
052dfb45 837 &info->dram_sec1_add);
806c35f5 838 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
052dfb45 839 &info->dram_sec1_syndrome);
806c35f5 840 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
052dfb45 841 &info->dram_ded_add);
806c35f5 842 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
052dfb45 843 &info->dram_scrb_add);
806c35f5 844 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
052dfb45 845 &info->dram_retr_add);
806c35f5 846
5135b797 847 /* ignore the reserved bits just in case */
806c35f5
AC		 848 if (info->hi_ferr & 0x7f)
849 pci_write_config_byte(dev, E752X_HI_FERR,
052dfb45 850 info->hi_ferr);
806c35f5 851
5135b797
AK		 852 if (info->nsi_ferr & NSI_ERR_MASK)
853 pci_write_config_dword(dev, I3100_NSI_FERR,
854 info->nsi_ferr);
855
806c35f5
AC		 856 if (info->sysbus_ferr)
857 pci_write_config_word(dev, E752X_SYSBUS_FERR,
052dfb45 858 info->sysbus_ferr);
806c35f5
AC		 859
860 if (info->buf_ferr & 0x0f)
861 pci_write_config_byte(dev, E752X_BUF_FERR,
052dfb45 862 info->buf_ferr);
806c35f5
AC		 863
864 if (info->dram_ferr)
865 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
203333cb 866 info->dram_ferr, info->dram_ferr);
806c35f5
AC		 867
868 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
052dfb45 869 info->ferr_global);
806c35f5
AC		 870 }
871
872 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
873
874 if (info->nerr_global) {
5135b797
AK		 875 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
876 pci_read_config_dword(dev, I3100_NSI_NERR,
877 &info->nsi_nerr);
878 info->hi_nerr = 0;
879 } else {
880 pci_read_config_byte(dev, E752X_HI_NERR,
881 &info->hi_nerr);
882 info->nsi_nerr = 0;
883 }
806c35f5 884 pci_read_config_word(dev, E752X_SYSBUS_NERR,
052dfb45 885 &info->sysbus_nerr);
806c35f5 886 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
203333cb 887 pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr);
806c35f5 888 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
052dfb45 889 &info->dram_sec2_add);
806c35f5 890 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
052dfb45 891 &info->dram_sec2_syndrome);
806c35f5
AC		 892
893 if (info->hi_nerr & 0x7f)
894 pci_write_config_byte(dev, E752X_HI_NERR,
052dfb45 895 info->hi_nerr);
806c35f5 896
5135b797
AK		 897 if (info->nsi_nerr & NSI_ERR_MASK)
898 pci_write_config_dword(dev, I3100_NSI_NERR,
899 info->nsi_nerr);
900
806c35f5
AC		 901 if (info->sysbus_nerr)
902 pci_write_config_word(dev, E752X_SYSBUS_NERR,
052dfb45 903 info->sysbus_nerr);
806c35f5
AC		 904
905 if (info->buf_nerr & 0x0f)
906 pci_write_config_byte(dev, E752X_BUF_NERR,
052dfb45 907 info->buf_nerr);
806c35f5
AC		 908
909 if (info->dram_nerr)
910 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
203333cb 911 info->dram_nerr, info->dram_nerr);
806c35f5
AC		 912
913 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
052dfb45 914 info->nerr_global);
806c35f5
AC		 915 }
916}
917
203333cb 918static int e752x_process_error_info(struct mem_ctl_info *mci,
052dfb45
DT		 919 struct e752x_error_info *info,
920 int handle_errors)
806c35f5
AC		 921{
922 u32 error32, stat32;
923 int error_found;
924
925 error_found = 0;
926 error32 = (info->ferr_global >> 18) & 0x3ff;
927 stat32 = (info->ferr_global >> 4) & 0x7ff;
928
929 if (error32)
930 global_error(1, error32, &error_found, handle_errors);
931
932 if (stat32)
933 global_error(0, stat32, &error_found, handle_errors);
934
935 error32 = (info->nerr_global >> 18) & 0x3ff;
936 stat32 = (info->nerr_global >> 4) & 0x7ff;
937
938 if (error32)
939 global_error(1, error32, &error_found, handle_errors);
940
941 if (stat32)
942 global_error(0, stat32, &error_found, handle_errors);
943
944 e752x_check_hub_interface(info, &error_found, handle_errors);
5135b797 945 e752x_check_ns_interface(info, &error_found, handle_errors);
806c35f5
AC		 946 e752x_check_sysbus(info, &error_found, handle_errors);
947 e752x_check_membuf(info, &error_found, handle_errors);
948 e752x_check_dram(mci, info, &error_found, handle_errors);
949 return error_found;
950}
951
952static void e752x_check(struct mem_ctl_info *mci)
953{
954 struct e752x_error_info info;
e7ecd891 955
537fba28 956 debugf3("%s()\n", __func__);
806c35f5
AC		 957 e752x_get_error_info(mci, &info);
958 e752x_process_error_info(mci, &info, 1);
959}
960
8004fd2a
PT		 961/* Program byte/sec bandwidth scrub rate to hardware */
962static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *new_bw)
963{
964 const struct scrubrate *scrubrates;
965 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
966 struct pci_dev *pdev = pvt->dev_d0f0;
967 int i;
968
969 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0)
970 scrubrates = scrubrates_i3100;
971 else
972 scrubrates = scrubrates_e752x;
973
974 /* Translate the desired scrub rate to a e752x/3100 register value.
975 * Search for the bandwidth that is equal or greater than the
976 * desired rate and program the cooresponding register value.
977 */
978 for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++)
979 if (scrubrates[i].bandwidth >= *new_bw)
980 break;
981
982 if (scrubrates[i].bandwidth == SDRATE_EOT)
983 return -1;
984
985 pci_write_config_word(pdev, E752X_MCHSCRB, scrubrates[i].scrubval);
986
987 return 0;
988}
989
990/* Convert current scrub rate value into byte/sec bandwidth */
991static int get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
992{
993 const struct scrubrate *scrubrates;
994 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
995 struct pci_dev *pdev = pvt->dev_d0f0;
996 u16 scrubval;
997 int i;
998
999 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0)
1000 scrubrates = scrubrates_i3100;
1001 else
1002 scrubrates = scrubrates_e752x;
1003
1004 /* Find the bandwidth matching the memory scrubber configuration */
1005 pci_read_config_word(pdev, E752X_MCHSCRB, &scrubval);
1006 scrubval = scrubval & 0x0f;
1007
1008 for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++)
1009 if (scrubrates[i].scrubval == scrubval)
1010 break;
1011
1012 if (scrubrates[i].bandwidth == SDRATE_EOT) {
1013 e752x_printk(KERN_WARNING,
1014 "Invalid sdram scrub control value: 0x%x\n", scrubval);
1015 return -1;
1016 }
1017
1018 *bw = scrubrates[i].bandwidth;
1019
1020 return 0;
1021}
1022
13189525
DT		 1023/* Return 1 if dual channel mode is active. Else return 0. */
1024static inline int dual_channel_active(u16 ddrcsr)
1025{
1026 return (((ddrcsr >> 12) & 3) == 3);
1027}
1028
7297c261
MG		 1029/* Remap csrow index numbers if map_type is "reverse"
1030 */
1031static inline int remap_csrow_index(struct mem_ctl_info *mci, int index)
1032{
1033 struct e752x_pvt *pvt = mci->pvt_info;
1034
1035 if (!pvt->map_type)
1036 return (7 - index);
1037
1038 return (index);
1039}
1040
13189525 1041static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
052dfb45 1042 u16 ddrcsr)
13189525
DT		 1043{
1044 struct csrow_info *csrow;
1045 unsigned long last_cumul_size;
1046 int index, mem_dev, drc_chan;
203333cb
DJ		 1047 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
1048 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
13189525
DT		 1049 u8 value;
1050 u32 dra, drc, cumul_size;
1051
9962fd01 1052 dra = 0;
203333cb 1053 for (index = 0; index < 4; index++) {
9962fd01 1054 u8 dra_reg;
203333cb 1055 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
9962fd01
BP		 1056 dra |= dra_reg << (index * 8);
1057 }
13189525
DT		 1058 pci_read_config_dword(pdev, E752X_DRC, &drc);
1059 drc_chan = dual_channel_active(ddrcsr);
203333cb 1060 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
13189525
DT		 1061 drc_ddim = (drc >> 20) & 0x3;
1062
1063 /* The dram row boundary (DRB) reg values are boundary address for
1064 * each DRAM row with a granularity of 64 or 128MB (single/dual
1065 * channel operation). DRB regs are cumulative; therefore DRB7 will
1066 * contain the total memory contained in all eight rows.
1067 */
1068 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
1069 /* mem_dev 0=x8, 1=x4 */
1070 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
7297c261 1071 csrow = &mci->csrows[remap_csrow_index(mci, index)];
13189525
DT		 1072
1073 mem_dev = (mem_dev == 2);
1074 pci_read_config_byte(pdev, E752X_DRB + index, &value);
1075 /* convert a 128 or 64 MiB DRB to a page size. */
1076 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
1077 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
1078 cumul_size);
1079 if (cumul_size == last_cumul_size)
1080 continue; /* not populated */
1081
1082 csrow->first_page = last_cumul_size;
1083 csrow->last_page = cumul_size - 1;
1084 csrow->nr_pages = cumul_size - last_cumul_size;
1085 last_cumul_size = cumul_size;
1086 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1087 csrow->mtype = MEM_RDDR; /* only one type supported */
1088 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
1089
1090 /*
1091 * if single channel or x8 devices then SECDED
1092 * if dual channel and x4 then S4ECD4ED
1093 */
1094 if (drc_ddim) {
1095 if (drc_chan && mem_dev) {
1096 csrow->edac_mode = EDAC_S4ECD4ED;
1097 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
1098 } else {
1099 csrow->edac_mode = EDAC_SECDED;
1100 mci->edac_cap |= EDAC_FLAG_SECDED;
1101 }
1102 } else
1103 csrow->edac_mode = EDAC_NONE;
1104 }
1105}
1106
1107static void e752x_init_mem_map_table(struct pci_dev *pdev,
052dfb45 1108 struct e752x_pvt *pvt)
806c35f5 1109{
806c35f5 1110 int index;
7297c261 1111 u8 value, last, row;
13189525
DT		 1112
1113 last = 0;
1114 row = 0;
1115
1116 for (index = 0; index < 8; index += 2) {
1117 pci_read_config_byte(pdev, E752X_DRB + index, &value);
1118 /* test if there is a dimm in this slot */
1119 if (value == last) {
1120 /* no dimm in the slot, so flag it as empty */
1121 pvt->map[index] = 0xff;
1122 pvt->map[index + 1] = 0xff;
203333cb 1123 } else { /* there is a dimm in the slot */
13189525
DT		 1124 pvt->map[index] = row;
1125 row++;
1126 last = value;
1127 /* test the next value to see if the dimm is double
1128 * sided
1129 */
1130 pci_read_config_byte(pdev, E752X_DRB + index + 1,
052dfb45
DT		 1131 &value);
1132
1133 /* the dimm is single sided, so flag as empty */
1134 /* this is a double sided dimm to save the next row #*/
1135 pvt->map[index + 1] = (value == last) ? 0xff : row;
13189525
DT		 1136 row++;
1137 last = value;
1138 }
1139 }
13189525
DT		 1140}
1141
1142/* Return 0 on success or 1 on failure. */
1143static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
052dfb45 1144 struct e752x_pvt *pvt)
13189525
DT		 1145{
1146 struct pci_dev *dev;
1147
1148 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
10d33e9c 1149 pvt->dev_info->err_dev, pvt->bridge_ck);
13189525
DT		 1150
1151 if (pvt->bridge_ck == NULL)
1152 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
1153 PCI_DEVFN(0, 1));
1154
1155 if (pvt->bridge_ck == NULL) {
1156 e752x_printk(KERN_ERR, "error reporting device not found:"
052dfb45
DT		 1157 "vendor %x device 0x%x (broken BIOS?)\n",
1158 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
13189525
DT		 1159 return 1;
1160 }
1161
10d33e9c
DT		 1162 dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1163 e752x_devs[dev_idx].ctl_dev,
1164 NULL);
13189525
DT		 1165
1166 if (dev == NULL)
1167 goto fail;
1168
1169 pvt->dev_d0f0 = dev;
1170 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
1171
1172 return 0;
1173
052dfb45 1174fail:
13189525
DT		 1175 pci_dev_put(pvt->bridge_ck);
1176 return 1;
1177}
1178
94ee1cf5
PT		 1179/* Setup system bus parity mask register.
1180 * Sysbus parity supported on:
8de5c1a1 1181 * e7320/e7520/e7525 + Xeon
94ee1cf5
PT		 1182 */
1183static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt)
1184{
1185 char *cpu_id = cpu_data(0).x86_model_id;
1186 struct pci_dev *dev = pvt->dev_d0f1;
1187 int enable = 1;
1188
98a1708d 1189 /* Allow module parameter override, else see if CPU supports parity */
94ee1cf5
PT		 1190 if (sysbus_parity != -1) {
1191 enable = sysbus_parity;
8de5c1a1 1192 } else if (cpu_id[0] && !strstr(cpu_id, "Xeon")) {
94ee1cf5
PT		 1193 e752x_printk(KERN_INFO, "System Bus Parity not "
1194 "supported by CPU, disabling\n");
1195 enable = 0;
1196 }
1197
1198 if (enable)
1199 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000);
1200 else
1201 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309);
1202}
1203
13189525
DT		 1204static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
1205{
1206 struct pci_dev *dev;
1207
1208 dev = pvt->dev_d0f1;
1209 /* Turn off error disable & SMI in case the BIOS turned it on */
5135b797
AK		 1210 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
1211 pci_write_config_dword(dev, I3100_NSI_EMASK, 0);
1212 pci_write_config_dword(dev, I3100_NSI_SMICMD, 0);
1213 } else {
1214 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
1215 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
1216 }
94ee1cf5
PT		 1217
1218 e752x_init_sysbus_parity_mask(pvt);
1219
13189525
DT		 1220 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
1221 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
1222 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
1223 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
1224 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
1225}
1226
1227static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1228{
3847bccc 1229 u16 pci_data;
806c35f5 1230 u8 stat8;
13189525
DT		 1231 struct mem_ctl_info *mci;
1232 struct e752x_pvt *pvt;
806c35f5 1233 u16 ddrcsr;
203333cb 1234 int drc_chan; /* Number of channels 0=1chan,1=2chan */
749ede57 1235 struct e752x_error_info discard;
806c35f5 1236
537fba28 1237 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 1238 debugf0("Starting Probe1\n");
1239
96941026 1240 /* check to see if device 0 function 1 is enabled; if it isn't, we
1241 * assume the BIOS has reserved it for a reason and is expecting
1242 * exclusive access, we take care not to violate that assumption and
1243 * fail the probe. */
806c35f5 1244 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 1245 if (!force_function_unhide && !(stat8 & (1 << 5))) {
1246 printk(KERN_INFO "Contact your BIOS vendor to see if the "
052dfb45 1247 "E752x error registers can be safely un-hidden\n");
f9b5a5d1 1248 return -ENODEV;
96941026 1249 }
806c35f5
AC		 1250 stat8 |= (1 << 5);
1251 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
1252
806c35f5
AC		 1253 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
1254 /* FIXME: should check >>12 or 0xf, true for all? */
1255 /* Dual channel = 1, Single channel = 0 */
13189525 1256 drc_chan = dual_channel_active(ddrcsr);
806c35f5 1257
b8f6f975 1258 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0);
806c35f5
AC		 1259
1260 if (mci == NULL) {
13189525 1261 return -ENOMEM;
806c35f5
AC		 1262 }
1263
537fba28 1264 debugf3("%s(): init mci\n", __func__);
806c35f5 1265 mci->mtype_cap = MEM_FLAG_RDDR;
5135b797
AK		 1266 /* 3100 IMCH supports SECDEC only */
1267 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
1268 (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED);
806c35f5 1269 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 1270 mci->mod_name = EDAC_MOD_STR;
37f04581
DT		 1271 mci->mod_ver = E752X_REVISION;
1272 mci->dev = &pdev->dev;
806c35f5 1273
537fba28 1274 debugf3("%s(): init pvt\n", __func__);
203333cb 1275 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 1276 pvt->dev_info = &e752x_devs[dev_idx];
13189525 1277 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
e7ecd891 1278
13189525
DT		 1279 if (e752x_get_devs(pdev, dev_idx, pvt)) {
1280 edac_mc_free(mci);
1281 return -ENODEV;
806c35f5 1282 }
806c35f5 1283
537fba28 1284 debugf3("%s(): more mci init\n", __func__);
806c35f5 1285 mci->ctl_name = pvt->dev_info->ctl_name;
c4192705 1286 mci->dev_name = pci_name(pdev);
806c35f5
AC		 1287 mci->edac_check = e752x_check;
1288 mci->ctl_page_to_phys = ctl_page_to_phys;
8004fd2a
PT		 1289 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
1290 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
806c35f5 1291
7297c261
MG		 1292 /* set the map type. 1 = normal, 0 = reversed
1293 * Must be set before e752x_init_csrows in case csrow mapping
1294 * is reversed.
1295 */
37f04581 1296 pci_read_config_byte(pdev, E752X_DRM, &stat8);
806c35f5
AC		 1297 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1298
7297c261
MG		 1299 e752x_init_csrows(mci, pdev, ddrcsr);
1300 e752x_init_mem_map_table(pdev, pvt);
1301
5135b797
AK		 1302 if (dev_idx == I3100)
1303 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
1304 else
1305 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 1306 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 1307
806c35f5 1308 /* load the top of low memory, remap base, and remap limit vars */
37f04581 1309 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
806c35f5 1310 pvt->tolm = ((u32) pci_data) << 4;
37f04581 1311 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
806c35f5 1312 pvt->remapbase = ((u32) pci_data) << 14;
37f04581 1313 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
806c35f5 1314 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 1315 e752x_printk(KERN_INFO,
052dfb45
DT		 1316 "tolm = %x, remapbase = %x, remaplimit = %x\n",
1317 pvt->tolm, pvt->remapbase, pvt->remaplimit);
806c35f5 1318
2d7bbb91
DT		 1319 /* Here we assume that we will never see multiple instances of this
1320 * type of memory controller. The ID is therefore hardcoded to 0.
1321 */
b8f6f975 1322 if (edac_mc_add_mc(mci)) {
537fba28 1323 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 1324 goto fail;
1325 }
1326
13189525 1327 e752x_init_error_reporting_regs(pvt);
203333cb 1328 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5 1329
91b99041
DJ		 1330 /* allocating generic PCI control info */
1331 e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1332 if (!e752x_pci) {
1333 printk(KERN_WARNING
052dfb45 1334 "%s(): Unable to create PCI control\n", __func__);
91b99041 1335 printk(KERN_WARNING
052dfb45
DT		 1336 "%s(): PCI error report via EDAC not setup\n",
1337 __func__);
91b99041
DJ		 1338 }
1339
806c35f5 1340 /* get this far and it's successful */
537fba28 1341 debugf3("%s(): success\n", __func__);
806c35f5
AC		 1342 return 0;
1343
052dfb45 1344fail:
13189525
DT		 1345 pci_dev_put(pvt->dev_d0f0);
1346 pci_dev_put(pvt->dev_d0f1);
1347 pci_dev_put(pvt->bridge_ck);
1348 edac_mc_free(mci);
e7ecd891 1349
13189525 1350 return -ENODEV;
806c35f5
AC		 1351}
1352
1353/* returns count (>= 0), or negative on error */
1354static int __devinit e752x_init_one(struct pci_dev *pdev,
052dfb45 1355 const struct pci_device_id *ent)
806c35f5 1356{
537fba28 1357 debugf0("%s()\n", __func__);
806c35f5
AC		 1358
1359 /* wake up and enable device */
203333cb 1360 if (pci_enable_device(pdev) < 0)
806c35f5 1361 return -EIO;
e7ecd891 1362
806c35f5
AC		 1363 return e752x_probe1(pdev, ent->driver_data);
1364}
1365
806c35f5
AC		 1366static void __devexit e752x_remove_one(struct pci_dev *pdev)
1367{
1368 struct mem_ctl_info *mci;
1369 struct e752x_pvt *pvt;
1370
537fba28 1371 debugf0("%s()\n", __func__);
806c35f5 1372
91b99041
DJ		 1373 if (e752x_pci)
1374 edac_pci_release_generic_ctl(e752x_pci);
1375
37f04581 1376 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5
AC		 1377 return;
1378
203333cb 1379 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5
AC		 1380 pci_dev_put(pvt->dev_d0f0);
1381 pci_dev_put(pvt->dev_d0f1);
1382 pci_dev_put(pvt->bridge_ck);
1383 edac_mc_free(mci);
1384}
1385
806c35f5 1386static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891 1387 {
203333cb
DJ		 1388 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1389 E7520},
e7ecd891 1390 {
203333cb
DJ		 1391 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1392 E7525},
e7ecd891 1393 {
203333cb
DJ		 1394 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1395 E7320},
5135b797
AK		 1396 {
1397 PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1398 I3100},
e7ecd891 1399 {
203333cb
DJ		 1400 0,
1401 } /* 0 terminated list. */
806c35f5
AC		 1402};
1403
1404MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1405
806c35f5 1406static struct pci_driver e752x_driver = {
680cbbbb 1407 .name = EDAC_MOD_STR,
0d38b049
RD		 1408 .probe = e752x_init_one,
1409 .remove = __devexit_p(e752x_remove_one),
1410 .id_table = e752x_pci_tbl,
806c35f5
AC		 1411};
1412
da9bb1d2 1413static int __init e752x_init(void)
806c35f5
AC		 1414{
1415 int pci_rc;
1416
537fba28 1417 debugf3("%s()\n", __func__);
c3c52bce
HM		 1418
1419 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1420 opstate_init();
1421
806c35f5
AC		 1422 pci_rc = pci_register_driver(&e752x_driver);
1423 return (pci_rc < 0) ? pci_rc : 0;
1424}
1425
806c35f5
AC		 1426static void __exit e752x_exit(void)
1427{
537fba28 1428 debugf3("%s()\n", __func__);
806c35f5
AC		 1429 pci_unregister_driver(&e752x_driver);
1430}
1431
806c35f5
AC		 1432module_init(e752x_init);
1433module_exit(e752x_exit);
1434
1435MODULE_LICENSE("GPL");
1436MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
5135b797 1437MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers");
96941026 1438
1439module_param(force_function_unhide, int, 0444);
1440MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
10d33e9c
DT		 1441 " 1=force unhide and hope BIOS doesn't fight driver for "
1442 "Dev0:Fun1 access");
c3c52bce 1443
c0d12172
DJ		 1444module_param(edac_op_state, int, 0444);
1445MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
94ee1cf5
PT		 1446
1447module_param(sysbus_parity, int, 0444);
1448MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking,"
1449 " 1=enable system bus parity checking, default=auto-detect");
10d33e9c
DT		 1450module_param(report_non_memory_errors, int, 0644);
1451MODULE_PARM_DESC(report_non_memory_errors, "0=disable non-memory error "
1452 "reporting, 1=enable non-memory error reporting");
Linux 6.x block layer and io_uring tree(s)