Commit | Line | Data |
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cfe40fdb DT |
1 | /* |
2 | * AMD64 class Memory Controller kernel module | |
3 | * | |
4 | * Copyright (c) 2009 SoftwareBitMaker. | |
1a8bc770 | 5 | * Copyright (c) 2009-15 Advanced Micro Devices, Inc. |
cfe40fdb DT |
6 | * |
7 | * This file may be distributed under the terms of the | |
8 | * GNU General Public License. | |
cfe40fdb DT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/ctype.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/pci_ids.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/mmzone.h> | |
18 | #include <linux/edac.h> | |
f9431992 | 19 | #include <asm/msr.h> |
78d88e8a | 20 | #include "edac_module.h" |
47ca08a4 | 21 | #include "mce_amd.h" |
cfe40fdb | 22 | |
24f9a7fe BP |
23 | #define amd64_debug(fmt, arg...) \ |
24 | edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) | |
cfe40fdb | 25 | |
24f9a7fe BP |
26 | #define amd64_info(fmt, arg...) \ |
27 | edac_printk(KERN_INFO, "amd64", fmt, ##arg) | |
28 | ||
29 | #define amd64_notice(fmt, arg...) \ | |
30 | edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) | |
31 | ||
32 | #define amd64_warn(fmt, arg...) \ | |
5246c540 | 33 | edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg) |
24f9a7fe BP |
34 | |
35 | #define amd64_err(fmt, arg...) \ | |
5246c540 | 36 | edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg) |
24f9a7fe BP |
37 | |
38 | #define amd64_mc_warn(mci, fmt, arg...) \ | |
39 | edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) | |
40 | ||
41 | #define amd64_mc_err(mci, fmt, arg...) \ | |
42 | edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) | |
cfe40fdb DT |
43 | |
44 | /* | |
45 | * Throughout the comments in this code, the following terms are used: | |
46 | * | |
47 | * SysAddr, DramAddr, and InputAddr | |
48 | * | |
49 | * These terms come directly from the amd64 documentation | |
50 | * (AMD publication #26094). They are defined as follows: | |
51 | * | |
52 | * SysAddr: | |
53 | * This is a physical address generated by a CPU core or a device | |
54 | * doing DMA. If generated by a CPU core, a SysAddr is the result of | |
55 | * a virtual to physical address translation by the CPU core's address | |
56 | * translation mechanism (MMU). | |
57 | * | |
58 | * DramAddr: | |
59 | * A DramAddr is derived from a SysAddr by subtracting an offset that | |
60 | * depends on which node the SysAddr maps to and whether the SysAddr | |
61 | * is within a range affected by memory hoisting. The DRAM Base | |
62 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers | |
63 | * determine which node a SysAddr maps to. | |
64 | * | |
65 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr | |
66 | * is within the range of addresses specified by this register, then | |
67 | * a value x from the DHAR is subtracted from the SysAddr to produce a | |
68 | * DramAddr. Here, x represents the base address for the node that | |
69 | * the SysAddr maps to plus an offset due to memory hoisting. See | |
70 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and | |
71 | * sys_addr_to_dram_addr() below for more information. | |
72 | * | |
73 | * If the SysAddr is not affected by the DHAR then a value y is | |
74 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the | |
75 | * base address for the node that the SysAddr maps to. See section | |
76 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more | |
77 | * information. | |
78 | * | |
79 | * InputAddr: | |
80 | * A DramAddr is translated to an InputAddr before being passed to the | |
81 | * memory controller for the node that the DramAddr is associated | |
82 | * with. The memory controller then maps the InputAddr to a csrow. | |
83 | * If node interleaving is not in use, then the InputAddr has the same | |
84 | * value as the DramAddr. Otherwise, the InputAddr is produced by | |
85 | * discarding the bits used for node interleaving from the DramAddr. | |
86 | * See section 3.4.4 for more information. | |
87 | * | |
88 | * The memory controller for a given node uses its DRAM CS Base and | |
89 | * DRAM CS Mask registers to map an InputAddr to a csrow. See | |
90 | * sections 3.5.4 and 3.5.5 for more information. | |
91 | */ | |
92 | ||
df71a053 | 93 | #define EDAC_AMD64_VERSION "3.4.0" |
cfe40fdb DT |
94 | #define EDAC_MOD_STR "amd64_edac" |
95 | ||
96 | /* Extended Model from CPUID, for CPU Revision numbers */ | |
1433eb99 BP |
97 | #define K8_REV_D 1 |
98 | #define K8_REV_E 2 | |
99 | #define K8_REV_F 4 | |
cfe40fdb DT |
100 | |
101 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | |
7f19bf75 BP |
102 | #define NUM_CHIPSELECTS 8 |
103 | #define DRAM_RANGES 8 | |
cfe40fdb | 104 | |
f6d6ae96 BP |
105 | #define ON true |
106 | #define OFF false | |
cfe40fdb DT |
107 | |
108 | /* | |
109 | * PCI-defined configuration space registers | |
110 | */ | |
df71a053 BP |
111 | #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 |
112 | #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 | |
a597d2a5 AG |
113 | #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b |
114 | #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c | |
115 | #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 | |
116 | #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 | |
94c1acf2 AG |
117 | #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 |
118 | #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 | |
85a8885b AG |
119 | #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 |
120 | #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 | |
f1cbbec9 YG |
121 | #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 |
122 | #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 | |
cfe40fdb DT |
123 | |
124 | /* | |
125 | * Function 1 - Address Map | |
126 | */ | |
7f19bf75 BP |
127 | #define DRAM_BASE_LO 0x40 |
128 | #define DRAM_LIMIT_LO 0x44 | |
129 | ||
18b94f66 AG |
130 | /* |
131 | * F15 M30h D18F1x2[1C:00] | |
132 | */ | |
133 | #define DRAM_CONT_BASE 0x200 | |
134 | #define DRAM_CONT_LIMIT 0x204 | |
135 | ||
136 | /* | |
137 | * F15 M30h D18F1x2[4C:40] | |
138 | */ | |
139 | #define DRAM_CONT_HIGH_OFF 0x240 | |
140 | ||
151fa71c BP |
141 | #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) |
142 | #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) | |
143 | #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) | |
7f19bf75 | 144 | |
bc21fa57 | 145 | #define DHAR 0xf0 |
c8e518d5 BP |
146 | #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) |
147 | #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) | |
148 | #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) | |
cfe40fdb | 149 | |
cfe40fdb | 150 | /* NOTE: Extra mask bit vs K8 */ |
c8e518d5 | 151 | #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) |
cfe40fdb | 152 | |
b2b0c605 | 153 | #define DCT_CFG_SEL 0x10C |
cfe40fdb | 154 | |
c1ae6830 | 155 | #define DRAM_LOCAL_NODE_BASE 0x120 |
f08e457c BP |
156 | #define DRAM_LOCAL_NODE_LIM 0x124 |
157 | ||
7f19bf75 BP |
158 | #define DRAM_BASE_HI 0x140 |
159 | #define DRAM_LIMIT_HI 0x144 | |
cfe40fdb DT |
160 | |
161 | ||
162 | /* | |
163 | * Function 2 - DRAM controller | |
164 | */ | |
11c75ead BP |
165 | #define DCSB0 0x40 |
166 | #define DCSB1 0x140 | |
167 | #define DCSB_CS_ENABLE BIT(0) | |
cfe40fdb | 168 | |
11c75ead BP |
169 | #define DCSM0 0x60 |
170 | #define DCSM1 0x160 | |
cfe40fdb | 171 | |
11c75ead | 172 | #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) |
cfe40fdb | 173 | |
a597d2a5 AG |
174 | #define DRAM_CONTROL 0x78 |
175 | ||
cfe40fdb DT |
176 | #define DBAM0 0x80 |
177 | #define DBAM1 0x180 | |
178 | ||
179 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ | |
0a5dfc31 | 180 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) |
cfe40fdb DT |
181 | |
182 | #define DBAM_MAX_VALUE 11 | |
183 | ||
cb328507 BP |
184 | #define DCLR0 0x90 |
185 | #define DCLR1 0x190 | |
cfe40fdb | 186 | #define REVE_WIDTH_128 BIT(16) |
41d8bfab | 187 | #define WIDTH_128 BIT(11) |
cfe40fdb | 188 | |
cb328507 BP |
189 | #define DCHR0 0x94 |
190 | #define DCHR1 0x194 | |
1433eb99 | 191 | #define DDR3_MODE BIT(8) |
cfe40fdb | 192 | |
78da121e | 193 | #define DCT_SEL_LO 0x110 |
78da121e BP |
194 | #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) |
195 | #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) | |
cb328507 | 196 | |
78da121e | 197 | #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) |
cb328507 | 198 | |
78da121e | 199 | #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) |
78da121e | 200 | #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) |
cfe40fdb | 201 | |
95b0ef55 BP |
202 | #define SWAP_INTLV_REG 0x10c |
203 | ||
78da121e | 204 | #define DCT_SEL_HI 0x114 |
cfe40fdb | 205 | |
da92110d | 206 | #define F15H_M60H_SCRCTRL 0x1C8 |
8051c0af YG |
207 | #define F17H_SCR_BASE_ADDR 0x48 |
208 | #define F17H_SCR_LIMIT_ADDR 0x4C | |
da92110d | 209 | |
cfe40fdb DT |
210 | /* |
211 | * Function 3 - Misc Control | |
212 | */ | |
c9f4f26e | 213 | #define NBCTL 0x40 |
cfe40fdb | 214 | |
a97fa68e BP |
215 | #define NBCFG 0x44 |
216 | #define NBCFG_CHIPKILL BIT(23) | |
217 | #define NBCFG_ECC_ENABLE BIT(22) | |
cfe40fdb | 218 | |
5980bb9c | 219 | /* F3x48: NBSL */ |
cfe40fdb | 220 | #define F10_NBSL_EXT_ERR_ECC 0x8 |
5980bb9c | 221 | #define NBSL_PP_OBS 0x2 |
cfe40fdb | 222 | |
5980bb9c | 223 | #define SCRCTRL 0x58 |
cfe40fdb DT |
224 | |
225 | #define F10_ONLINE_SPARE 0xB0 | |
614ec9d8 BP |
226 | #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) |
227 | #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) | |
cfe40fdb DT |
228 | |
229 | #define F10_NB_ARRAY_ADDR 0xB8 | |
6e71a870 | 230 | #define F10_NB_ARRAY_DRAM BIT(31) |
cfe40fdb DT |
231 | |
232 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | |
6e71a870 | 233 | #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) |
cfe40fdb DT |
234 | |
235 | #define F10_NB_ARRAY_DATA 0xBC | |
66fed2d4 | 236 | #define F10_NB_ARR_ECC_WR_REQ BIT(17) |
6e71a870 BP |
237 | #define SET_NB_DRAM_INJECTION_WRITE(inj) \ |
238 | (BIT(((inj.word) & 0xF) + 20) | \ | |
66fed2d4 | 239 | F10_NB_ARR_ECC_WR_REQ | inj.bit_map) |
6e71a870 BP |
240 | #define SET_NB_DRAM_INJECTION_READ(inj) \ |
241 | (BIT(((inj.word) & 0xF) + 20) | \ | |
242 | BIT(16) | inj.bit_map) | |
243 | ||
cfe40fdb | 244 | |
5980bb9c BP |
245 | #define NBCAP 0xE8 |
246 | #define NBCAP_CHIPKILL BIT(4) | |
247 | #define NBCAP_SECDED BIT(3) | |
248 | #define NBCAP_DCT_DUAL BIT(0) | |
cfe40fdb | 249 | |
ad6a32e9 BP |
250 | #define EXT_NB_MCA_CFG 0x180 |
251 | ||
f6d6ae96 | 252 | /* MSRs */ |
5980bb9c | 253 | #define MSR_MCGCTL_NBE BIT(4) |
cfe40fdb | 254 | |
b64ce7cd YG |
255 | /* F17h */ |
256 | ||
257 | /* F0: */ | |
258 | #define DF_DHAR 0x104 | |
259 | ||
196b79fc | 260 | /* UMC CH register offsets */ |
b64ce7cd YG |
261 | #define UMCCH_BASE_ADDR 0x0 |
262 | #define UMCCH_ADDR_MASK 0x20 | |
07ed82ef | 263 | #define UMCCH_ADDR_CFG 0x30 |
b64ce7cd | 264 | #define UMCCH_DIMM_CFG 0x80 |
07ed82ef | 265 | #define UMCCH_UMC_CFG 0x100 |
196b79fc | 266 | #define UMCCH_SDP_CTRL 0x104 |
b64ce7cd | 267 | #define UMCCH_ECC_CTRL 0x14C |
07ed82ef YG |
268 | #define UMCCH_ECC_BAD_SYMBOL 0xD90 |
269 | #define UMCCH_UMC_CAP 0xDF0 | |
196b79fc YG |
270 | #define UMCCH_UMC_CAP_HI 0xDF4 |
271 | ||
272 | /* UMC CH bitfields */ | |
b64ce7cd | 273 | #define UMC_ECC_CHIPKILL_CAP BIT(31) |
196b79fc | 274 | #define UMC_ECC_ENABLED BIT(30) |
b64ce7cd | 275 | |
196b79fc YG |
276 | #define UMC_SDP_INIT BIT(31) |
277 | ||
278 | #define NUM_UMCS 2 | |
279 | ||
b2b0c605 | 280 | enum amd_families { |
cfe40fdb DT |
281 | K8_CPUS = 0, |
282 | F10_CPUS, | |
b2b0c605 | 283 | F15_CPUS, |
18b94f66 | 284 | F15_M30H_CPUS, |
a597d2a5 | 285 | F15_M60H_CPUS, |
94c1acf2 | 286 | F16_CPUS, |
85a8885b | 287 | F16_M30H_CPUS, |
f1cbbec9 | 288 | F17_CPUS, |
b2b0c605 | 289 | NUM_FAMILIES, |
cfe40fdb DT |
290 | }; |
291 | ||
cfe40fdb DT |
292 | /* Error injection control structure */ |
293 | struct error_injection { | |
66fed2d4 BP |
294 | u32 section; |
295 | u32 word; | |
296 | u32 bit_map; | |
cfe40fdb DT |
297 | }; |
298 | ||
7f19bf75 BP |
299 | /* low and high part of PCI config space regs */ |
300 | struct reg_pair { | |
301 | u32 lo, hi; | |
302 | }; | |
303 | ||
304 | /* | |
305 | * See F1x[1, 0][7C:40] DRAM Base/Limit Registers | |
306 | */ | |
307 | struct dram_range { | |
308 | struct reg_pair base; | |
309 | struct reg_pair lim; | |
310 | }; | |
311 | ||
11c75ead BP |
312 | /* A DCT chip selects collection */ |
313 | struct chip_select { | |
314 | u32 csbases[NUM_CHIPSELECTS]; | |
315 | u8 b_cnt; | |
316 | ||
317 | u32 csmasks[NUM_CHIPSELECTS]; | |
318 | u8 m_cnt; | |
319 | }; | |
320 | ||
f1cbbec9 | 321 | struct amd64_umc { |
b64ce7cd | 322 | u32 dimm_cfg; /* DIMM Configuration reg */ |
07ed82ef | 323 | u32 umc_cfg; /* Configuration reg */ |
f1cbbec9 | 324 | u32 sdp_ctrl; /* SDP Control reg */ |
b64ce7cd | 325 | u32 ecc_ctrl; /* DRAM ECC Control reg */ |
07ed82ef | 326 | u32 umc_cap_hi; /* Capabilities High reg */ |
f1cbbec9 YG |
327 | }; |
328 | ||
cfe40fdb | 329 | struct amd64_pvt { |
b8cfa02f BP |
330 | struct low_ops *ops; |
331 | ||
cfe40fdb | 332 | /* pci_device handles which we utilize */ |
936fc3af | 333 | struct pci_dev *F0, *F1, *F2, *F3, *F6; |
cfe40fdb | 334 | |
c7e5301a | 335 | u16 mc_node_id; /* MC index of this MC node */ |
18b94f66 | 336 | u8 fam; /* CPU family */ |
a4b4bedc BP |
337 | u8 model; /* ... model */ |
338 | u8 stepping; /* ... stepping */ | |
339 | ||
cfe40fdb | 340 | int ext_model; /* extended model value of this node */ |
cfe40fdb DT |
341 | int channel_count; |
342 | ||
343 | /* Raw registers */ | |
344 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ | |
345 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ | |
346 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ | |
347 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ | |
348 | u32 nbcap; /* North Bridge Capabilities */ | |
349 | u32 nbcfg; /* F10 North Bridge Configuration */ | |
350 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ | |
351 | u32 dhar; /* DRAM Hoist reg */ | |
352 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ | |
353 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | |
354 | ||
11c75ead BP |
355 | /* one for each DCT */ |
356 | struct chip_select csels[2]; | |
cfe40fdb | 357 | |
7f19bf75 BP |
358 | /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ |
359 | struct dram_range ranges[DRAM_RANGES]; | |
cfe40fdb | 360 | |
cfe40fdb DT |
361 | u64 top_mem; /* top of memory below 4GB */ |
362 | u64 top_mem2; /* top of memory above 4GB */ | |
363 | ||
78da121e BP |
364 | u32 dct_sel_lo; /* DRAM Controller Select Low */ |
365 | u32 dct_sel_hi; /* DRAM Controller Select High */ | |
b2b0c605 | 366 | u32 online_spare; /* On-Line spare Reg */ |
cfe40fdb | 367 | |
ad6a32e9 | 368 | /* x4 or x8 syndromes in use */ |
a3b7db09 | 369 | u8 ecc_sym_sz; |
ad6a32e9 | 370 | |
cfe40fdb DT |
371 | /* place to store error injection parameters prior to issue */ |
372 | struct error_injection injection; | |
a597d2a5 AG |
373 | |
374 | /* cache the dram_type */ | |
375 | enum mem_type dram_type; | |
f1cbbec9 YG |
376 | |
377 | struct amd64_umc *umc; /* UMC registers */ | |
ae7bb7c6 BP |
378 | }; |
379 | ||
33ca0643 BP |
380 | enum err_codes { |
381 | DECODE_OK = 0, | |
382 | ERR_NODE = -1, | |
383 | ERR_CSROW = -2, | |
384 | ERR_CHANNEL = -3, | |
713ad546 YG |
385 | ERR_SYND = -4, |
386 | ERR_NORM_ADDR = -5, | |
33ca0643 BP |
387 | }; |
388 | ||
389 | struct err_info { | |
390 | int err_code; | |
391 | struct mem_ctl_info *src_mci; | |
392 | int csrow; | |
393 | int channel; | |
394 | u16 syndrome; | |
395 | u32 page; | |
396 | u32 offset; | |
397 | }; | |
398 | ||
196b79fc YG |
399 | static inline u32 get_umc_base(u8 channel) |
400 | { | |
401 | /* ch0: 0x50000, ch1: 0x150000 */ | |
402 | return 0x50000 + (!!channel << 20); | |
403 | } | |
404 | ||
c7e5301a | 405 | static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) |
7f19bf75 BP |
406 | { |
407 | u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; | |
408 | ||
409 | if (boot_cpu_data.x86 == 0xf) | |
410 | return addr; | |
411 | ||
412 | return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; | |
413 | } | |
414 | ||
c7e5301a | 415 | static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) |
7f19bf75 BP |
416 | { |
417 | u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; | |
418 | ||
419 | if (boot_cpu_data.x86 == 0xf) | |
420 | return lim; | |
421 | ||
422 | return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; | |
423 | } | |
424 | ||
f192c7b1 BP |
425 | static inline u16 extract_syndrome(u64 status) |
426 | { | |
427 | return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); | |
428 | } | |
429 | ||
18b94f66 AG |
430 | static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) |
431 | { | |
432 | if (pvt->fam == 0x15 && pvt->model >= 0x30) | |
433 | return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | | |
434 | ((pvt->dct_sel_lo >> 6) & 0x3); | |
435 | ||
436 | return ((pvt)->dct_sel_lo >> 6) & 0x3; | |
437 | } | |
ae7bb7c6 BP |
438 | /* |
439 | * per-node ECC settings descriptor | |
440 | */ | |
441 | struct ecc_settings { | |
442 | u32 old_nbctl; | |
443 | bool nbctl_valid; | |
444 | ||
cfe40fdb | 445 | struct flags { |
d95cf4de BP |
446 | unsigned long nb_mce_enable:1; |
447 | unsigned long nb_ecc_prev:1; | |
cfe40fdb DT |
448 | } flags; |
449 | }; | |
450 | ||
7d6034d3 | 451 | #ifdef CONFIG_EDAC_DEBUG |
e339f1ec | 452 | extern const struct attribute_group amd64_edac_dbg_group; |
7d6034d3 DT |
453 | #endif |
454 | ||
455 | #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION | |
e339f1ec | 456 | extern const struct attribute_group amd64_edac_inj_group; |
7d6034d3 DT |
457 | #endif |
458 | ||
cfe40fdb DT |
459 | /* |
460 | * Each of the PCI Device IDs types have their own set of hardware accessor | |
461 | * functions and per device encoding/decoding logic. | |
462 | */ | |
463 | struct low_ops { | |
1433eb99 | 464 | int (*early_channel_count) (struct amd64_pvt *pvt); |
f192c7b1 | 465 | void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 466 | struct err_info *); |
a597d2a5 AG |
467 | int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, |
468 | unsigned cs_mode, int cs_mask_nr); | |
cfe40fdb DT |
469 | }; |
470 | ||
471 | struct amd64_family_type { | |
472 | const char *ctl_name; | |
f1cbbec9 | 473 | u16 f0_id, f1_id, f2_id, f6_id; |
cfe40fdb DT |
474 | struct low_ops ops; |
475 | }; | |
476 | ||
66fed2d4 BP |
477 | int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
478 | u32 *val, const char *func); | |
b2b0c605 BP |
479 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, |
480 | u32 val, const char *func); | |
6ba5dcdc | 481 | |
b2b0c605 BP |
482 | #define amd64_read_pci_cfg(pdev, offset, val) \ |
483 | __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) | |
6ba5dcdc | 484 | |
b2b0c605 BP |
485 | #define amd64_write_pci_cfg(pdev, offset, val) \ |
486 | __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) | |
6ba5dcdc | 487 | |
cfe40fdb DT |
488 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, |
489 | u64 *hole_offset, u64 *hole_size); | |
c5608759 MCC |
490 | |
491 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
66fed2d4 BP |
492 | |
493 | /* Injection helpers */ | |
494 | static inline void disable_caches(void *dummy) | |
495 | { | |
496 | write_cr0(read_cr0() | X86_CR0_CD); | |
497 | wbinvd(); | |
498 | } | |
499 | ||
500 | static inline void enable_caches(void *dummy) | |
501 | { | |
502 | write_cr0(read_cr0() & ~X86_CR0_CD); | |
503 | } | |
18b94f66 AG |
504 | |
505 | static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) | |
506 | { | |
507 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
508 | u32 tmp; | |
509 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); | |
510 | return (u8) tmp & 0xF; | |
511 | } | |
512 | return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; | |
513 | } | |
514 | ||
515 | static inline u8 dhar_valid(struct amd64_pvt *pvt) | |
516 | { | |
517 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
518 | u32 tmp; | |
519 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); | |
520 | return (tmp >> 1) & BIT(0); | |
521 | } | |
522 | return (pvt)->dhar & BIT(0); | |
523 | } | |
524 | ||
525 | static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) | |
526 | { | |
527 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
528 | u32 tmp; | |
529 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); | |
530 | return (tmp >> 11) & 0x1FFF; | |
531 | } | |
532 | return (pvt)->dct_sel_lo & 0xFFFFF800; | |
533 | } |