[linux-2.6-block.git] / drivers / edac / amd64_edac.h

/*
 * AMD64 class Memory Controller kernel module
 *
 * Copyright (c) 2009 SoftwareBitMaker.
 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <asm/cpu_device_id.h>
#include <asm/msr.h>
#include "edac_module.h"
#include "mce_amd.h"

#define amd64_info(fmt, arg...) \
	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define amd64_warn(fmt, arg...) \
	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)

#define amd64_err(fmt, arg...) \
	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)

#define amd64_mc_warn(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_mc_err(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

/*
 * Throughout the comments in this code, the following terms are used:
 *
 *	SysAddr, DramAddr, and InputAddr
 *
 *  These terms come directly from the amd64 documentation
 * (AMD publication #26094).  They are defined as follows:
 *
 *     SysAddr:
 *         This is a physical address generated by a CPU core or a device
 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 *         a virtual to physical address translation by the CPU core's address
 *         translation mechanism (MMU).
 *
 *     DramAddr:
 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 *         depends on which node the SysAddr maps to and whether the SysAddr
 *         is within a range affected by memory hoisting.  The DRAM Base
 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 *         determine which node a SysAddr maps to.
 *
 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 *         is within the range of addresses specified by this register, then
 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 *         DramAddr.  Here, x represents the base address for the node that
 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 *         sys_addr_to_dram_addr() below for more information.
 *
 *         If the SysAddr is not affected by the DHAR then a value y is
 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 *         base address for the node that the SysAddr maps to.  See section
 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 *         information.
 *
 *     InputAddr:
 *         A DramAddr is translated to an InputAddr before being passed to the
 *         memory controller for the node that the DramAddr is associated
 *         with.  The memory controller then maps the InputAddr to a csrow.
 *         If node interleaving is not in use, then the InputAddr has the same
 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 *         discarding the bits used for node interleaving from the DramAddr.
 *         See section 3.4.4 for more information.
 *
 *         The memory controller for a given node uses its DRAM CS Base and
 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 *         sections 3.5.4 and 3.5.5 for more information.
 */

#define EDAC_AMD64_VERSION		"3.5.0"
#define EDAC_MOD_STR			"amd64_edac"

/* Extended Model from CPUID, for CPU Revision numbers */
#define K8_REV_D			1
#define K8_REV_E			2
#define K8_REV_F			4

/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS			8
#define DRAM_RANGES			8
#define NUM_CONTROLLERS			8

#define ON true
#define OFF false

/*
 * PCI-defined configuration space registers
 */
#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
#define PCI_DEVICE_ID_AMD_17H_DF_F0	0x1460
#define PCI_DEVICE_ID_AMD_17H_DF_F6	0x1466
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446

/*
 * Function 1 - Address Map
 */
#define DRAM_BASE_LO			0x40
#define DRAM_LIMIT_LO			0x44

/*
 * F15 M30h D18F1x2[1C:00]
 */
#define DRAM_CONT_BASE			0x200
#define DRAM_CONT_LIMIT			0x204

/*
 * F15 M30h D18F1x2[4C:40]
 */
#define DRAM_CONT_HIGH_OFF		0x240

#define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
#define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
#define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))

#define DHAR				0xf0
#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)

					/* NOTE: Extra mask bit vs K8 */
#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)

#define DCT_CFG_SEL			0x10C

#define DRAM_LOCAL_NODE_BASE		0x120
#define DRAM_LOCAL_NODE_LIM		0x124

#define DRAM_BASE_HI			0x140
#define DRAM_LIMIT_HI			0x144


/*
 * Function 2 - DRAM controller
 */
#define DCSB0				0x40
#define DCSB1				0x140
#define DCSB_CS_ENABLE			BIT(0)

#define DCSM0				0x60
#define DCSM1				0x160

#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
#define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)

#define DRAM_CONTROL			0x78

#define DBAM0				0x80
#define DBAM1				0x180

/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg)		((((reg) >> (4*(i)))) & 0xF)

#define DBAM_MAX_VALUE			11

#define DCLR0				0x90
#define DCLR1				0x190
#define REVE_WIDTH_128			BIT(16)
#define WIDTH_128			BIT(11)

#define DCHR0				0x94
#define DCHR1				0x194
#define DDR3_MODE			BIT(8)

#define DCT_SEL_LO			0x110
#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))

#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))

#define SWAP_INTLV_REG			0x10c

#define DCT_SEL_HI			0x114

#define F15H_M60H_SCRCTRL		0x1C8
#define F17H_SCR_BASE_ADDR		0x48
#define F17H_SCR_LIMIT_ADDR		0x4C

/*
 * Function 3 - Misc Control
 */
#define NBCTL				0x40

#define NBCFG				0x44
#define NBCFG_CHIPKILL			BIT(23)
#define NBCFG_ECC_ENABLE		BIT(22)

/* F3x48: NBSL */
#define F10_NBSL_EXT_ERR_ECC		0x8
#define NBSL_PP_OBS			0x2

#define SCRCTRL				0x58

#define F10_ONLINE_SPARE		0xB0
#define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
#define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

#define F10_NB_ARRAY_ADDR		0xB8
#define F10_NB_ARRAY_DRAM		BIT(31)

/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
#define SET_NB_ARRAY_ADDR(section)	(((section) & 0x3) << 1)

#define F10_NB_ARRAY_DATA		0xBC
#define F10_NB_ARR_ECC_WR_REQ		BIT(17)
#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
#define SET_NB_DRAM_INJECTION_READ(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					BIT(16) |  inj.bit_map)


#define NBCAP				0xE8
#define NBCAP_CHIPKILL			BIT(4)
#define NBCAP_SECDED			BIT(3)
#define NBCAP_DCT_DUAL			BIT(0)

#define EXT_NB_MCA_CFG			0x180

/* MSRs */
#define MSR_MCGCTL_NBE			BIT(4)

/* F17h */

/* F0: */
#define DF_DHAR				0x104

/* UMC CH register offsets */
#define UMCCH_BASE_ADDR			0x0
#define UMCCH_BASE_ADDR_SEC		0x10
#define UMCCH_ADDR_MASK			0x20
#define UMCCH_ADDR_MASK_SEC		0x28
#define UMCCH_ADDR_CFG			0x30
#define UMCCH_DIMM_CFG			0x80
#define UMCCH_UMC_CFG			0x100
#define UMCCH_SDP_CTRL			0x104
#define UMCCH_ECC_CTRL			0x14C
#define UMCCH_ECC_BAD_SYMBOL		0xD90
#define UMCCH_UMC_CAP			0xDF0
#define UMCCH_UMC_CAP_HI		0xDF4

/* UMC CH bitfields */
#define UMC_ECC_CHIPKILL_CAP		BIT(31)
#define UMC_ECC_ENABLED			BIT(30)

#define UMC_SDP_INIT			BIT(31)

enum amd_families {
	K8_CPUS = 0,
	F10_CPUS,
	F15_CPUS,
	F15_M30H_CPUS,
	F15_M60H_CPUS,
	F16_CPUS,
	F16_M30H_CPUS,
	F17_CPUS,
	F17_M10H_CPUS,
	F17_M30H_CPUS,
	F17_M70H_CPUS,
	NUM_FAMILIES,
};

/* Error injection control structure */
struct error_injection {
	u32	 section;
	u32	 word;
	u32	 bit_map;
};

/* low and high part of PCI config space regs */
struct reg_pair {
	u32 lo, hi;
};

/*
 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 */
struct dram_range {
	struct reg_pair base;
	struct reg_pair lim;
};

/* A DCT chip selects collection */
struct chip_select {
	u32 csbases[NUM_CHIPSELECTS];
	u32 csbases_sec[NUM_CHIPSELECTS];
	u8 b_cnt;

	u32 csmasks[NUM_CHIPSELECTS];
	u32 csmasks_sec[NUM_CHIPSELECTS];
	u8 m_cnt;
};

struct amd64_umc {
	u32 dimm_cfg;		/* DIMM Configuration reg */
	u32 umc_cfg;		/* Configuration reg */
	u32 sdp_ctrl;		/* SDP Control reg */
	u32 ecc_ctrl;		/* DRAM ECC Control reg */
	u32 umc_cap_hi;		/* Capabilities High reg */
};

struct amd64_pvt {
	struct low_ops *ops;

	/* pci_device handles which we utilize */
	struct pci_dev *F0, *F1, *F2, *F3, *F6;

	u16 mc_node_id;		/* MC index of this MC node */
	u8 fam;			/* CPU family */
	u8 model;		/* ... model */
	u8 stepping;		/* ... stepping */

	int ext_model;		/* extended model value of this node */
	int channel_count;

	/* Raw registers */
	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
	u32 nbcap;		/* North Bridge Capabilities */
	u32 nbcfg;		/* F10 North Bridge Configuration */
	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
	u32 dhar;		/* DRAM Hoist reg */
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	/* one for each DCT/UMC */
	struct chip_select csels[NUM_CONTROLLERS];

	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
	struct dram_range ranges[DRAM_RANGES];

	u64 top_mem;		/* top of memory below 4GB */
	u64 top_mem2;		/* top of memory above 4GB */

	u32 dct_sel_lo;		/* DRAM Controller Select Low */
	u32 dct_sel_hi;		/* DRAM Controller Select High */
	u32 online_spare;	/* On-Line spare Reg */

	/* x4, x8, or x16 syndromes in use */
	u8 ecc_sym_sz;

	/* place to store error injection parameters prior to issue */
	struct error_injection injection;

	/* cache the dram_type */
	enum mem_type dram_type;

	struct amd64_umc *umc;	/* UMC registers */
};

enum err_codes {
	DECODE_OK	=  0,
	ERR_NODE	= -1,
	ERR_CSROW	= -2,
	ERR_CHANNEL	= -3,
	ERR_SYND	= -4,
	ERR_NORM_ADDR	= -5,
};

struct err_info {
	int err_code;
	struct mem_ctl_info *src_mci;
	int csrow;
	int channel;
	u16 syndrome;
	u32 page;
	u32 offset;
};

static inline u32 get_umc_base(u8 channel)
{
	/* chY: 0xY50000 */
	return 0x50000 + (channel << 20);
}

static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
{
	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;

	if (boot_cpu_data.x86 == 0xf)
		return addr;

	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
}

static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
{
	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;

	if (boot_cpu_data.x86 == 0xf)
		return lim;

	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
}

static inline u16 extract_syndrome(u64 status)
{
	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
}

static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30)
		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
			((pvt->dct_sel_lo >> 6) & 0x3);

	return	((pvt)->dct_sel_lo >> 6) & 0x3;
}
/*
 * per-node ECC settings descriptor
 */
struct ecc_settings {
	u32 old_nbctl;
	bool nbctl_valid;

	struct flags {
		unsigned long nb_mce_enable:1;
		unsigned long nb_ecc_prev:1;
	} flags;
};

#ifdef CONFIG_EDAC_DEBUG
extern const struct attribute_group amd64_edac_dbg_group;
#endif

#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
extern const struct attribute_group amd64_edac_inj_group;
#endif

/*
 * Each of the PCI Device IDs types have their own set of hardware accessor
 * functions and per device encoding/decoding logic.
 */
struct low_ops {
	int (*early_channel_count)	(struct amd64_pvt *pvt);
	void (*map_sysaddr_to_csrow)	(struct mem_ctl_info *mci, u64 sys_addr,
					 struct err_info *);
	int (*dbam_to_cs)		(struct amd64_pvt *pvt, u8 dct,
					 unsigned cs_mode, int cs_mask_nr);
};

struct amd64_family_type {
	const char *ctl_name;
	u16 f0_id, f1_id, f2_id, f6_id;
	struct low_ops ops;
};

int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func);
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func);

#define amd64_read_pci_cfg(pdev, offset, val)	\
	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_write_pci_cfg(pdev, offset, val)	\
	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size);

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

/* Injection helpers */
static inline void disable_caches(void *dummy)
{
	write_cr0(read_cr0() | X86_CR0_CD);
	wbinvd();
}

static inline void enable_caches(void *dummy)
{
	write_cr0(read_cr0() & ~X86_CR0_CD);
}

static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
		return (u8) tmp & 0xF;
	}
	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
}

static inline u8 dhar_valid(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 1) & BIT(0);
	}
	return (pvt)->dhar & BIT(0);
}

static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 11) & 0x1FFF;
	}
	return (pvt)->dct_sel_lo & 0xFFFFF800;
}
Commit	Line	Data
cfe40fdb DT	1	/*
	2	* AMD64 class Memory Controller kernel module
	3	*
	4	* Copyright (c) 2009 SoftwareBitMaker.
1a8bc770	5	* Copyright (c) 2009-15 Advanced Micro Devices, Inc.
cfe40fdb DT	6	*
	7	* This file may be distributed under the terms of the
	8	* GNU General Public License.
cfe40fdb DT	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/ctype.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
	16	#include <linux/slab.h>
	17	#include <linux/mmzone.h>
	18	#include <linux/edac.h>
1bd9900b	19	#include <asm/cpu_device_id.h>
f9431992	20	#include <asm/msr.h>
78d88e8a	21	#include "edac_module.h"
47ca08a4	22	#include "mce_amd.h"
cfe40fdb	23
24f9a7fe BP	24	#define amd64_info(fmt, arg...) \
	25	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
	26
24f9a7fe	27	#define amd64_warn(fmt, arg...) \
5246c540	28	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
24f9a7fe BP	29
24f9a7fe BP	30	#define amd64_err(fmt, arg...) \
5246c540	31	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
24f9a7fe BP	32
	33	#define amd64_mc_warn(mci, fmt, arg...) \
	34	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
	35
	36	#define amd64_mc_err(mci, fmt, arg...) \
	37	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
cfe40fdb DT	38
	39	/*
	40	* Throughout the comments in this code, the following terms are used:
	41	*
	42	* SysAddr, DramAddr, and InputAddr
	43	*
	44	* These terms come directly from the amd64 documentation
	45	* (AMD publication #26094). They are defined as follows:
	46	*
	47	* SysAddr:
	48	* This is a physical address generated by a CPU core or a device
	49	* doing DMA. If generated by a CPU core, a SysAddr is the result of
	50	* a virtual to physical address translation by the CPU core's address
	51	* translation mechanism (MMU).
	52	*
	53	* DramAddr:
	54	* A DramAddr is derived from a SysAddr by subtracting an offset that
	55	* depends on which node the SysAddr maps to and whether the SysAddr
	56	* is within a range affected by memory hoisting. The DRAM Base
	57	* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
	58	* determine which node a SysAddr maps to.
	59	*
	60	* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
	61	* is within the range of addresses specified by this register, then
	62	* a value x from the DHAR is subtracted from the SysAddr to produce a
	63	* DramAddr. Here, x represents the base address for the node that
	64	* the SysAddr maps to plus an offset due to memory hoisting. See
	65	* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
	66	* sys_addr_to_dram_addr() below for more information.
	67	*
	68	* If the SysAddr is not affected by the DHAR then a value y is
	69	* subtracted from the SysAddr to produce a DramAddr. Here, y is the
	70	* base address for the node that the SysAddr maps to. See section
	71	* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
	72	* information.
	73	*
	74	* InputAddr:
	75	* A DramAddr is translated to an InputAddr before being passed to the
	76	* memory controller for the node that the DramAddr is associated
	77	* with. The memory controller then maps the InputAddr to a csrow.
	78	* If node interleaving is not in use, then the InputAddr has the same
	79	* value as the DramAddr. Otherwise, the InputAddr is produced by
	80	* discarding the bits used for node interleaving from the DramAddr.
	81	* See section 3.4.4 for more information.
	82	*
	83	* The memory controller for a given node uses its DRAM CS Base and
	84	* DRAM CS Mask registers to map an InputAddr to a csrow. See
	85	* sections 3.5.4 and 3.5.5 for more information.
	86	*/
	87
e62d2ca9	88	#define EDAC_AMD64_VERSION "3.5.0"
cfe40fdb DT	89	#define EDAC_MOD_STR "amd64_edac"
	90
	91	/* Extended Model from CPUID, for CPU Revision numbers */
1433eb99 BP	92	#define K8_REV_D 1
	93	#define K8_REV_E 2
	94	#define K8_REV_F 4
cfe40fdb DT	95
cfe40fdb DT	96	/* Hardware limit on ChipSelect rows per MC and processors per system */
7f19bf75 BP	97	#define NUM_CHIPSELECTS 8
7f19bf75 BP	98	#define DRAM_RANGES 8
d971e28e	99	#define NUM_CONTROLLERS 8
cfe40fdb	100
f6d6ae96 BP	101	#define ON true
f6d6ae96 BP	102	#define OFF false
cfe40fdb DT	103
	104	/*
	105	* PCI-defined configuration space registers
	106	*/
df71a053 BP	107	#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
df71a053 BP	108	#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
a597d2a5 AG	109	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
	110	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
	111	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
	112	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
94c1acf2 AG	113	#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
94c1acf2 AG	114	#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
85a8885b AG	115	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
85a8885b AG	116	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
f1cbbec9 YG	117	#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
f1cbbec9 YG	118	#define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
8960de4a MJ	119	#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
8960de4a MJ	120	#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
6e846239 YG	121	#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
6e846239 YG	122	#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
3e443eb3 IV	123	#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
3e443eb3 IV	124	#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
cfe40fdb DT	125
	126	/*
	127	* Function 1 - Address Map
	128	*/
7f19bf75 BP	129	#define DRAM_BASE_LO 0x40
	130	#define DRAM_LIMIT_LO 0x44
	131
18b94f66 AG	132	/*
	133	* F15 M30h D18F1x2[1C:00]
	134	*/
	135	#define DRAM_CONT_BASE 0x200
	136	#define DRAM_CONT_LIMIT 0x204
	137
	138	/*
	139	* F15 M30h D18F1x2[4C:40]
	140	*/
	141	#define DRAM_CONT_HIGH_OFF 0x240
	142
151fa71c BP	143	#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
	144	#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
	145	#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
7f19bf75	146
bc21fa57	147	#define DHAR 0xf0
c8e518d5 BP	148	#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
	149	#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
	150	#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
cfe40fdb	151
cfe40fdb	152	/* NOTE: Extra mask bit vs K8 */
c8e518d5	153	#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
cfe40fdb	154
b2b0c605	155	#define DCT_CFG_SEL 0x10C
cfe40fdb	156
c1ae6830	157	#define DRAM_LOCAL_NODE_BASE 0x120
f08e457c BP	158	#define DRAM_LOCAL_NODE_LIM 0x124
f08e457c BP	159
7f19bf75 BP	160	#define DRAM_BASE_HI 0x140
7f19bf75 BP	161	#define DRAM_LIMIT_HI 0x144
cfe40fdb DT	162
	163
	164	/*
	165	* Function 2 - DRAM controller
	166	*/
11c75ead BP	167	#define DCSB0 0x40
	168	#define DCSB1 0x140
	169	#define DCSB_CS_ENABLE BIT(0)
cfe40fdb	170
11c75ead BP	171	#define DCSM0 0x60
11c75ead BP	172	#define DCSM1 0x160
cfe40fdb	173
81f5090d YG	174	#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
81f5090d YG	175	#define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
cfe40fdb	176
a597d2a5 AG	177	#define DRAM_CONTROL 0x78
a597d2a5 AG	178
cfe40fdb DT	179	#define DBAM0 0x80
	180	#define DBAM1 0x180
	181
	182	/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
0a5dfc31	183	#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
cfe40fdb DT	184
	185	#define DBAM_MAX_VALUE 11
	186
cb328507 BP	187	#define DCLR0 0x90
cb328507 BP	188	#define DCLR1 0x190
cfe40fdb	189	#define REVE_WIDTH_128 BIT(16)
41d8bfab	190	#define WIDTH_128 BIT(11)
cfe40fdb	191
cb328507 BP	192	#define DCHR0 0x94
cb328507 BP	193	#define DCHR1 0x194
1433eb99	194	#define DDR3_MODE BIT(8)
cfe40fdb	195
78da121e	196	#define DCT_SEL_LO 0x110
78da121e BP	197	#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
78da121e BP	198	#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
cb328507	199
78da121e	200	#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
cb328507	201
78da121e	202	#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
78da121e	203	#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
cfe40fdb	204
95b0ef55 BP	205	#define SWAP_INTLV_REG 0x10c
95b0ef55 BP	206
78da121e	207	#define DCT_SEL_HI 0x114
cfe40fdb	208
da92110d	209	#define F15H_M60H_SCRCTRL 0x1C8
8051c0af YG	210	#define F17H_SCR_BASE_ADDR 0x48
8051c0af YG	211	#define F17H_SCR_LIMIT_ADDR 0x4C
da92110d	212
cfe40fdb DT	213	/*
	214	* Function 3 - Misc Control
	215	*/
c9f4f26e	216	#define NBCTL 0x40
cfe40fdb	217
a97fa68e BP	218	#define NBCFG 0x44
	219	#define NBCFG_CHIPKILL BIT(23)
	220	#define NBCFG_ECC_ENABLE BIT(22)
cfe40fdb	221
5980bb9c	222	/* F3x48: NBSL */
cfe40fdb	223	#define F10_NBSL_EXT_ERR_ECC 0x8
5980bb9c	224	#define NBSL_PP_OBS 0x2
cfe40fdb	225
5980bb9c	226	#define SCRCTRL 0x58
cfe40fdb DT	227
cfe40fdb DT	228	#define F10_ONLINE_SPARE 0xB0
614ec9d8 BP	229	#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
614ec9d8 BP	230	#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
cfe40fdb DT	231
cfe40fdb DT	232	#define F10_NB_ARRAY_ADDR 0xB8
6e71a870	233	#define F10_NB_ARRAY_DRAM BIT(31)
cfe40fdb DT	234
cfe40fdb DT	235	/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
6e71a870	236	#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
cfe40fdb DT	237
cfe40fdb DT	238	#define F10_NB_ARRAY_DATA 0xBC
66fed2d4	239	#define F10_NB_ARR_ECC_WR_REQ BIT(17)
6e71a870 BP	240	#define SET_NB_DRAM_INJECTION_WRITE(inj) \
6e71a870 BP	241	(BIT(((inj.word) & 0xF) + 20) \| \
66fed2d4	242	F10_NB_ARR_ECC_WR_REQ \| inj.bit_map)
6e71a870 BP	243	#define SET_NB_DRAM_INJECTION_READ(inj) \
	244	(BIT(((inj.word) & 0xF) + 20) \| \
	245	BIT(16) \| inj.bit_map)
	246
cfe40fdb	247
5980bb9c BP	248	#define NBCAP 0xE8
	249	#define NBCAP_CHIPKILL BIT(4)
	250	#define NBCAP_SECDED BIT(3)
	251	#define NBCAP_DCT_DUAL BIT(0)
cfe40fdb	252
ad6a32e9 BP	253	#define EXT_NB_MCA_CFG 0x180
ad6a32e9 BP	254
f6d6ae96	255	/* MSRs */
5980bb9c	256	#define MSR_MCGCTL_NBE BIT(4)
cfe40fdb	257
b64ce7cd YG	258	/* F17h */
	259
	260	/* F0: */
	261	#define DF_DHAR 0x104
	262
196b79fc	263	/* UMC CH register offsets */
b64ce7cd	264	#define UMCCH_BASE_ADDR 0x0
7574729e	265	#define UMCCH_BASE_ADDR_SEC 0x10
b64ce7cd	266	#define UMCCH_ADDR_MASK 0x20
7574729e	267	#define UMCCH_ADDR_MASK_SEC 0x28
07ed82ef	268	#define UMCCH_ADDR_CFG 0x30
b64ce7cd	269	#define UMCCH_DIMM_CFG 0x80
07ed82ef	270	#define UMCCH_UMC_CFG 0x100
196b79fc	271	#define UMCCH_SDP_CTRL 0x104
b64ce7cd	272	#define UMCCH_ECC_CTRL 0x14C
07ed82ef YG	273	#define UMCCH_ECC_BAD_SYMBOL 0xD90
07ed82ef YG	274	#define UMCCH_UMC_CAP 0xDF0
196b79fc YG	275	#define UMCCH_UMC_CAP_HI 0xDF4
	276
	277	/* UMC CH bitfields */
b64ce7cd	278	#define UMC_ECC_CHIPKILL_CAP BIT(31)
196b79fc	279	#define UMC_ECC_ENABLED BIT(30)
b64ce7cd	280
196b79fc YG	281	#define UMC_SDP_INIT BIT(31)
196b79fc YG	282
b2b0c605	283	enum amd_families {
cfe40fdb DT	284	K8_CPUS = 0,
cfe40fdb DT	285	F10_CPUS,
b2b0c605	286	F15_CPUS,
18b94f66	287	F15_M30H_CPUS,
a597d2a5	288	F15_M60H_CPUS,
94c1acf2	289	F16_CPUS,
85a8885b	290	F16_M30H_CPUS,
f1cbbec9	291	F17_CPUS,
8960de4a	292	F17_M10H_CPUS,
6e846239	293	F17_M30H_CPUS,
3e443eb3	294	F17_M70H_CPUS,
b2b0c605	295	NUM_FAMILIES,
cfe40fdb DT	296	};
cfe40fdb DT	297
cfe40fdb DT	298	/* Error injection control structure */
cfe40fdb DT	299	struct error_injection {
66fed2d4 BP	300	u32 section;
	301	u32 word;
	302	u32 bit_map;
cfe40fdb DT	303	};
cfe40fdb DT	304
7f19bf75 BP	305	/* low and high part of PCI config space regs */
	306	struct reg_pair {
	307	u32 lo, hi;
	308	};
	309
	310	/*
	311	* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
	312	*/
	313	struct dram_range {
	314	struct reg_pair base;
	315	struct reg_pair lim;
	316	};
	317
11c75ead BP	318	/* A DCT chip selects collection */
	319	struct chip_select {
	320	u32 csbases[NUM_CHIPSELECTS];
7574729e	321	u32 csbases_sec[NUM_CHIPSELECTS];
11c75ead BP	322	u8 b_cnt;
	323
	324	u32 csmasks[NUM_CHIPSELECTS];
7574729e	325	u32 csmasks_sec[NUM_CHIPSELECTS];
11c75ead BP	326	u8 m_cnt;
	327	};
	328
f1cbbec9	329	struct amd64_umc {
b64ce7cd	330	u32 dimm_cfg; /* DIMM Configuration reg */
07ed82ef	331	u32 umc_cfg; /* Configuration reg */
f1cbbec9	332	u32 sdp_ctrl; /* SDP Control reg */
b64ce7cd	333	u32 ecc_ctrl; /* DRAM ECC Control reg */
07ed82ef	334	u32 umc_cap_hi; /* Capabilities High reg */
f1cbbec9 YG	335	};
f1cbbec9 YG	336
cfe40fdb	337	struct amd64_pvt {
b8cfa02f BP	338	struct low_ops *ops;
b8cfa02f BP	339
cfe40fdb	340	/* pci_device handles which we utilize */
936fc3af	341	struct pci_dev F0, F1, F2, F3, *F6;
cfe40fdb	342
c7e5301a	343	u16 mc_node_id; /* MC index of this MC node */
18b94f66	344	u8 fam; /* CPU family */
a4b4bedc BP	345	u8 model; /* ... model */
	346	u8 stepping; /* ... stepping */
	347
cfe40fdb	348	int ext_model; /* extended model value of this node */
cfe40fdb DT	349	int channel_count;
	350
	351	/* Raw registers */
	352	u32 dclr0; /* DRAM Configuration Low DCT0 reg */
	353	u32 dclr1; /* DRAM Configuration Low DCT1 reg */
	354	u32 dchr0; /* DRAM Configuration High DCT0 reg */
	355	u32 dchr1; /* DRAM Configuration High DCT1 reg */
	356	u32 nbcap; /* North Bridge Capabilities */
	357	u32 nbcfg; /* F10 North Bridge Configuration */
	358	u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
	359	u32 dhar; /* DRAM Hoist reg */
	360	u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
	361	u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
	362
d971e28e YG	363	/* one for each DCT/UMC */
d971e28e YG	364	struct chip_select csels[NUM_CONTROLLERS];
cfe40fdb	365
7f19bf75 BP	366	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
7f19bf75 BP	367	struct dram_range ranges[DRAM_RANGES];
cfe40fdb	368
cfe40fdb DT	369	u64 top_mem; /* top of memory below 4GB */
	370	u64 top_mem2; /* top of memory above 4GB */
	371
78da121e BP	372	u32 dct_sel_lo; /* DRAM Controller Select Low */
78da121e BP	373	u32 dct_sel_hi; /* DRAM Controller Select High */
b2b0c605	374	u32 online_spare; /* On-Line spare Reg */
cfe40fdb	375
7835961d	376	/* x4, x8, or x16 syndromes in use */
a3b7db09	377	u8 ecc_sym_sz;
ad6a32e9	378
cfe40fdb DT	379	/* place to store error injection parameters prior to issue */
cfe40fdb DT	380	struct error_injection injection;
a597d2a5 AG	381
	382	/* cache the dram_type */
	383	enum mem_type dram_type;
f1cbbec9 YG	384
f1cbbec9 YG	385	struct amd64_umc umc; / UMC registers */
ae7bb7c6 BP	386	};
ae7bb7c6 BP	387
33ca0643 BP	388	enum err_codes {
	389	DECODE_OK = 0,
	390	ERR_NODE = -1,
	391	ERR_CSROW = -2,
	392	ERR_CHANNEL = -3,
713ad546 YG	393	ERR_SYND = -4,
713ad546 YG	394	ERR_NORM_ADDR = -5,
33ca0643 BP	395	};
	396
	397	struct err_info {
	398	int err_code;
	399	struct mem_ctl_info *src_mci;
	400	int csrow;
	401	int channel;
	402	u16 syndrome;
	403	u32 page;
	404	u32 offset;
	405	};
	406
196b79fc YG	407	static inline u32 get_umc_base(u8 channel)
196b79fc YG	408	{
bdcee774 YG	409	/* chY: 0xY50000 */
bdcee774 YG	410	return 0x50000 + (channel << 20);
196b79fc YG	411	}
196b79fc YG	412
c7e5301a	413	static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	414	{
	415	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
	416
	417	if (boot_cpu_data.x86 == 0xf)
	418	return addr;
	419
	420	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) \| addr;
	421	}
	422
c7e5301a	423	static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	424	{
	425	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) \| 0x00ffffff;
	426
	427	if (boot_cpu_data.x86 == 0xf)
	428	return lim;
	429
	430	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) \| lim;
	431	}
	432
f192c7b1 BP	433	static inline u16 extract_syndrome(u64 status)
	434	{
	435	return ((status >> 47) & 0xff) \| ((status >> 16) & 0xff00);
	436	}
	437
18b94f66 AG	438	static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
	439	{
	440	if (pvt->fam == 0x15 && pvt->model >= 0x30)
	441	return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) \|
	442	((pvt->dct_sel_lo >> 6) & 0x3);
	443
	444	return ((pvt)->dct_sel_lo >> 6) & 0x3;
	445	}
ae7bb7c6 BP	446	/*
	447	* per-node ECC settings descriptor
	448	*/
	449	struct ecc_settings {
	450	u32 old_nbctl;
	451	bool nbctl_valid;
	452
cfe40fdb	453	struct flags {
d95cf4de BP	454	unsigned long nb_mce_enable:1;
d95cf4de BP	455	unsigned long nb_ecc_prev:1;
cfe40fdb DT	456	} flags;
	457	};
	458
7d6034d3	459	#ifdef CONFIG_EDAC_DEBUG
e339f1ec	460	extern const struct attribute_group amd64_edac_dbg_group;
7d6034d3 DT	461	#endif
	462
	463	#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
e339f1ec	464	extern const struct attribute_group amd64_edac_inj_group;
7d6034d3 DT	465	#endif
7d6034d3 DT	466
cfe40fdb DT	467	/*
	468	* Each of the PCI Device IDs types have their own set of hardware accessor
	469	* functions and per device encoding/decoding logic.
	470	*/
	471	struct low_ops {
1433eb99	472	int (early_channel_count) (struct amd64_pvt pvt);
f192c7b1	473	void (map_sysaddr_to_csrow) (struct mem_ctl_info mci, u64 sys_addr,
33ca0643	474	struct err_info *);
a597d2a5 AG	475	int (dbam_to_cs) (struct amd64_pvt pvt, u8 dct,
a597d2a5 AG	476	unsigned cs_mode, int cs_mask_nr);
cfe40fdb DT	477	};
	478
	479	struct amd64_family_type {
	480	const char *ctl_name;
f1cbbec9	481	u16 f0_id, f1_id, f2_id, f6_id;
cfe40fdb DT	482	struct low_ops ops;
	483	};
	484
66fed2d4 BP	485	int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
66fed2d4 BP	486	u32 val, const char func);
b2b0c605 BP	487	int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
b2b0c605 BP	488	u32 val, const char *func);
6ba5dcdc	489
b2b0c605 BP	490	#define amd64_read_pci_cfg(pdev, offset, val) \
b2b0c605 BP	491	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	492
b2b0c605 BP	493	#define amd64_write_pci_cfg(pdev, offset, val) \
b2b0c605 BP	494	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	495
cfe40fdb DT	496	int amd64_get_dram_hole_info(struct mem_ctl_info mci, u64 hole_base,
cfe40fdb DT	497	u64 hole_offset, u64 hole_size);
c5608759 MCC	498
c5608759 MCC	499	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
66fed2d4 BP	500
	501	/* Injection helpers */
	502	static inline void disable_caches(void *dummy)
	503	{
	504	write_cr0(read_cr0() \| X86_CR0_CD);
	505	wbinvd();
	506	}
	507
	508	static inline void enable_caches(void *dummy)
	509	{
	510	write_cr0(read_cr0() & ~X86_CR0_CD);
	511	}
18b94f66 AG	512
	513	static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
	514	{
	515	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	516	u32 tmp;
	517	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
	518	return (u8) tmp & 0xF;
	519	}
	520	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
	521	}
	522
	523	static inline u8 dhar_valid(struct amd64_pvt *pvt)
	524	{
	525	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	526	u32 tmp;
	527	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	528	return (tmp >> 1) & BIT(0);
	529	}
	530	return (pvt)->dhar & BIT(0);
	531	}
	532
	533	static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
	534	{
	535	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	536	u32 tmp;
	537	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	538	return (tmp >> 11) & 0x1FFF;
	539	}
	540	return (pvt)->dct_sel_lo & 0xFFFFF800;
	541	}