[linux-2.6-block.git] / drivers / edac / amd64_edac.h

/*
 * AMD64 class Memory Controller kernel module
 *
 * Copyright (c) 2009 SoftwareBitMaker.
 * Copyright (c) 2009 Advanced Micro Devices, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 *	Originally Written by Thayne Harbaugh
 *
 *      Changes by Douglas "norsk" Thompson  <dougthompson@xmission.com>:
 *		- K8 CPU Revision D and greater support
 *
 *      Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
 *		- Module largely rewritten, with new (and hopefully correct)
 *		code for dealing with node and chip select interleaving,
 *		various code cleanup, and bug fixes
 *		- Added support for memory hoisting using DRAM hole address
 *		register
 *
 *	Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
 *		-K8 Rev (1207) revision support added, required Revision
 *		specific mini-driver code to support Rev F as well as
 *		prior revisions
 *
 *	Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
 *		-Family 10h revision support added. New PCI Device IDs,
 *		indicating new changes. Actual registers modified
 *		were slight, less than the Rev E to Rev F transition
 *		but changing the PCI Device ID was the proper thing to
 *		do, as it provides for almost automactic family
 *		detection. The mods to Rev F required more family
 *		information detection.
 *
 *	Changes/Fixes by Borislav Petkov <bp@alien8.de>:
 *		- misc fixes and code cleanups
 *
 * This module is based on the following documents
 * (available from http://www.amd.com/):
 *
 *	Title:	BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
 *		Opteron Processors
 *	AMD publication #: 26094
 *`	Revision: 3.26
 *
 *	Title:	BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
 *		Processors
 *	AMD publication #: 32559
 *	Revision: 3.00
 *	Issue Date: May 2006
 *
 *	Title:	BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
 *		Processors
 *	AMD publication #: 31116
 *	Revision: 3.00
 *	Issue Date: September 07, 2007
 *
 * Sections in the first 2 documents are no longer in sync with each other.
 * The Family 10h BKDG was totally re-written from scratch with a new
 * presentation model.
 * Therefore, comments that refer to a Document section might be off.
 */

#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <asm/msr.h>
#include "edac_core.h"
#include "mce_amd.h"

#define amd64_debug(fmt, arg...) \
	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)

#define amd64_info(fmt, arg...) \
	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define amd64_notice(fmt, arg...) \
	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)

#define amd64_warn(fmt, arg...) \
	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_err(fmt, arg...) \
	edac_printk(KERN_ERR, "amd64", fmt, ##arg)

#define amd64_mc_warn(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_mc_err(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

/*
 * Throughout the comments in this code, the following terms are used:
 *
 *	SysAddr, DramAddr, and InputAddr
 *
 *  These terms come directly from the amd64 documentation
 * (AMD publication #26094).  They are defined as follows:
 *
 *     SysAddr:
 *         This is a physical address generated by a CPU core or a device
 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 *         a virtual to physical address translation by the CPU core's address
 *         translation mechanism (MMU).
 *
 *     DramAddr:
 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 *         depends on which node the SysAddr maps to and whether the SysAddr
 *         is within a range affected by memory hoisting.  The DRAM Base
 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 *         determine which node a SysAddr maps to.
 *
 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 *         is within the range of addresses specified by this register, then
 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 *         DramAddr.  Here, x represents the base address for the node that
 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 *         sys_addr_to_dram_addr() below for more information.
 *
 *         If the SysAddr is not affected by the DHAR then a value y is
 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 *         base address for the node that the SysAddr maps to.  See section
 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 *         information.
 *
 *     InputAddr:
 *         A DramAddr is translated to an InputAddr before being passed to the
 *         memory controller for the node that the DramAddr is associated
 *         with.  The memory controller then maps the InputAddr to a csrow.
 *         If node interleaving is not in use, then the InputAddr has the same
 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 *         discarding the bits used for node interleaving from the DramAddr.
 *         See section 3.4.4 for more information.
 *
 *         The memory controller for a given node uses its DRAM CS Base and
 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 *         sections 3.5.4 and 3.5.5 for more information.
 */

#define EDAC_AMD64_VERSION		"3.4.0"
#define EDAC_MOD_STR			"amd64_edac"

/* Extended Model from CPUID, for CPU Revision numbers */
#define K8_REV_D			1
#define K8_REV_E			2
#define K8_REV_F			4

/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS			8
#define DRAM_RANGES			8

#define ON true
#define OFF false

/*
 * PCI-defined configuration space registers
 */
#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582

/*
 * Function 1 - Address Map
 */
#define DRAM_BASE_LO			0x40
#define DRAM_LIMIT_LO			0x44

/*
 * F15 M30h D18F1x2[1C:00]
 */
#define DRAM_CONT_BASE			0x200
#define DRAM_CONT_LIMIT			0x204

/*
 * F15 M30h D18F1x2[4C:40]
 */
#define DRAM_CONT_HIGH_OFF		0x240

#define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
#define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
#define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))

#define DHAR				0xf0
#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)

					/* NOTE: Extra mask bit vs K8 */
#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)

#define DCT_CFG_SEL			0x10C

#define DRAM_LOCAL_NODE_BASE		0x120
#define DRAM_LOCAL_NODE_LIM		0x124

#define DRAM_BASE_HI			0x140
#define DRAM_LIMIT_HI			0x144


/*
 * Function 2 - DRAM controller
 */
#define DCSB0				0x40
#define DCSB1				0x140
#define DCSB_CS_ENABLE			BIT(0)

#define DCSM0				0x60
#define DCSM1				0x160

#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)

#define DRAM_CONTROL			0x78

#define DBAM0				0x80
#define DBAM1				0x180

/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg)		((((reg) >> (4*(i)))) & 0xF)

#define DBAM_MAX_VALUE			11

#define DCLR0				0x90
#define DCLR1				0x190
#define REVE_WIDTH_128			BIT(16)
#define WIDTH_128			BIT(11)

#define DCHR0				0x94
#define DCHR1				0x194
#define DDR3_MODE			BIT(8)

#define DCT_SEL_LO			0x110
#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))

#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))

#define SWAP_INTLV_REG			0x10c

#define DCT_SEL_HI			0x114

/*
 * Function 3 - Misc Control
 */
#define NBCTL				0x40

#define NBCFG				0x44
#define NBCFG_CHIPKILL			BIT(23)
#define NBCFG_ECC_ENABLE		BIT(22)

/* F3x48: NBSL */
#define F10_NBSL_EXT_ERR_ECC		0x8
#define NBSL_PP_OBS			0x2

#define SCRCTRL				0x58

#define F10_ONLINE_SPARE		0xB0
#define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
#define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

#define F10_NB_ARRAY_ADDR		0xB8
#define F10_NB_ARRAY_DRAM		BIT(31)

/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
#define SET_NB_ARRAY_ADDR(section)	(((section) & 0x3) << 1)

#define F10_NB_ARRAY_DATA		0xBC
#define F10_NB_ARR_ECC_WR_REQ		BIT(17)
#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
#define SET_NB_DRAM_INJECTION_READ(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					BIT(16) |  inj.bit_map)


#define NBCAP				0xE8
#define NBCAP_CHIPKILL			BIT(4)
#define NBCAP_SECDED			BIT(3)
#define NBCAP_DCT_DUAL			BIT(0)

#define EXT_NB_MCA_CFG			0x180

/* MSRs */
#define MSR_MCGCTL_NBE			BIT(4)

enum amd_families {
	K8_CPUS = 0,
	F10_CPUS,
	F15_CPUS,
	F15_M30H_CPUS,
	F15_M60H_CPUS,
	F16_CPUS,
	F16_M30H_CPUS,
	NUM_FAMILIES,
};

/* Error injection control structure */
struct error_injection {
	u32	 section;
	u32	 word;
	u32	 bit_map;
};

/* low and high part of PCI config space regs */
struct reg_pair {
	u32 lo, hi;
};

/*
 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 */
struct dram_range {
	struct reg_pair base;
	struct reg_pair lim;
};

/* A DCT chip selects collection */
struct chip_select {
	u32 csbases[NUM_CHIPSELECTS];
	u8 b_cnt;

	u32 csmasks[NUM_CHIPSELECTS];
	u8 m_cnt;
};

struct amd64_pvt {
	struct low_ops *ops;

	/* pci_device handles which we utilize */
	struct pci_dev *F1, *F2, *F3;

	u16 mc_node_id;		/* MC index of this MC node */
	u8 fam;			/* CPU family */
	u8 model;		/* ... model */
	u8 stepping;		/* ... stepping */

	int ext_model;		/* extended model value of this node */
	int channel_count;

	/* Raw registers */
	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
	u32 nbcap;		/* North Bridge Capabilities */
	u32 nbcfg;		/* F10 North Bridge Configuration */
	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
	u32 dhar;		/* DRAM Hoist reg */
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	/* one for each DCT */
	struct chip_select csels[2];

	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
	struct dram_range ranges[DRAM_RANGES];

	u64 top_mem;		/* top of memory below 4GB */
	u64 top_mem2;		/* top of memory above 4GB */

	u32 dct_sel_lo;		/* DRAM Controller Select Low */
	u32 dct_sel_hi;		/* DRAM Controller Select High */
	u32 online_spare;	/* On-Line spare Reg */

	/* x4 or x8 syndromes in use */
	u8 ecc_sym_sz;

	/* place to store error injection parameters prior to issue */
	struct error_injection injection;

	/* cache the dram_type */
	enum mem_type dram_type;
};

enum err_codes {
	DECODE_OK	=  0,
	ERR_NODE	= -1,
	ERR_CSROW	= -2,
	ERR_CHANNEL	= -3,
};

struct err_info {
	int err_code;
	struct mem_ctl_info *src_mci;
	int csrow;
	int channel;
	u16 syndrome;
	u32 page;
	u32 offset;
};

static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
{
	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;

	if (boot_cpu_data.x86 == 0xf)
		return addr;

	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
}

static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
{
	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;

	if (boot_cpu_data.x86 == 0xf)
		return lim;

	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
}

static inline u16 extract_syndrome(u64 status)
{
	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
}

static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30)
		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
			((pvt->dct_sel_lo >> 6) & 0x3);

	return	((pvt)->dct_sel_lo >> 6) & 0x3;
}
/*
 * per-node ECC settings descriptor
 */
struct ecc_settings {
	u32 old_nbctl;
	bool nbctl_valid;

	struct flags {
		unsigned long nb_mce_enable:1;
		unsigned long nb_ecc_prev:1;
	} flags;
};

#ifdef CONFIG_EDAC_DEBUG
extern const struct attribute_group amd64_edac_dbg_group;
#endif

#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
extern const struct attribute_group amd64_edac_inj_group;
#endif

/*
 * Each of the PCI Device IDs types have their own set of hardware accessor
 * functions and per device encoding/decoding logic.
 */
struct low_ops {
	int (*early_channel_count)	(struct amd64_pvt *pvt);
	void (*map_sysaddr_to_csrow)	(struct mem_ctl_info *mci, u64 sys_addr,
					 struct err_info *);
	int (*dbam_to_cs)		(struct amd64_pvt *pvt, u8 dct,
					 unsigned cs_mode, int cs_mask_nr);
};

struct amd64_family_type {
	const char *ctl_name;
	u16 f1_id, f3_id;
	struct low_ops ops;
};

int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func);
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func);

#define amd64_read_pci_cfg(pdev, offset, val)	\
	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_write_pci_cfg(pdev, offset, val)	\
	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size);

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

/* Injection helpers */
static inline void disable_caches(void *dummy)
{
	write_cr0(read_cr0() | X86_CR0_CD);
	wbinvd();
}

static inline void enable_caches(void *dummy)
{
	write_cr0(read_cr0() & ~X86_CR0_CD);
}

static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
		return (u8) tmp & 0xF;
	}
	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
}

static inline u8 dhar_valid(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 1) & BIT(0);
	}
	return (pvt)->dhar & BIT(0);
}

static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 11) & 0x1FFF;
	}
	return (pvt)->dct_sel_lo & 0xFFFFF800;
}
Commit	Line	Data
cfe40fdb DT	1	/*
	2	* AMD64 class Memory Controller kernel module
	3	*
	4	* Copyright (c) 2009 SoftwareBitMaker.
	5	* Copyright (c) 2009 Advanced Micro Devices, Inc.
	6	*
	7	* This file may be distributed under the terms of the
	8	* GNU General Public License.
	9	*
	10	* Originally Written by Thayne Harbaugh
	11	*
	12	* Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
	13	* - K8 CPU Revision D and greater support
	14	*
	15	* Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
	16	* - Module largely rewritten, with new (and hopefully correct)
	17	* code for dealing with node and chip select interleaving,
	18	* various code cleanup, and bug fixes
	19	* - Added support for memory hoisting using DRAM hole address
	20	* register
	21	*
	22	* Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
	23	* -K8 Rev (1207) revision support added, required Revision
	24	* specific mini-driver code to support Rev F as well as
	25	* prior revisions
	26	*
	27	* Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
	28	* -Family 10h revision support added. New PCI Device IDs,
	29	* indicating new changes. Actual registers modified
	30	* were slight, less than the Rev E to Rev F transition
	31	* but changing the PCI Device ID was the proper thing to
	32	* do, as it provides for almost automactic family
	33	* detection. The mods to Rev F required more family
	34	* information detection.
	35	*
43aff26c	36	* Changes/Fixes by Borislav Petkov <bp@alien8.de>:
cfe40fdb DT	37	* - misc fixes and code cleanups
	38	*
	39	* This module is based on the following documents
	40	* (available from http://www.amd.com/):
	41	*
	42	* Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
	43	* Opteron Processors
	44	* AMD publication #: 26094
	45	*` Revision: 3.26
	46	*
	47	* Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
	48	* Processors
	49	* AMD publication #: 32559
	50	* Revision: 3.00
	51	* Issue Date: May 2006
	52	*
	53	* Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
	54	* Processors
	55	* AMD publication #: 31116
	56	* Revision: 3.00
	57	* Issue Date: September 07, 2007
	58	*
	59	* Sections in the first 2 documents are no longer in sync with each other.
	60	* The Family 10h BKDG was totally re-written from scratch with a new
	61	* presentation model.
	62	* Therefore, comments that refer to a Document section might be off.
	63	*/
	64
	65	#include <linux/module.h>
	66	#include <linux/ctype.h>
	67	#include <linux/init.h>
	68	#include <linux/pci.h>
	69	#include <linux/pci_ids.h>
	70	#include <linux/slab.h>
	71	#include <linux/mmzone.h>
	72	#include <linux/edac.h>
f9431992	73	#include <asm/msr.h>
cfe40fdb	74	#include "edac_core.h"
47ca08a4	75	#include "mce_amd.h"
cfe40fdb	76
24f9a7fe BP	77	#define amd64_debug(fmt, arg...) \
24f9a7fe BP	78	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
cfe40fdb	79
24f9a7fe BP	80	#define amd64_info(fmt, arg...) \
	81	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
	82
	83	#define amd64_notice(fmt, arg...) \
	84	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
	85
	86	#define amd64_warn(fmt, arg...) \
	87	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
	88
	89	#define amd64_err(fmt, arg...) \
	90	edac_printk(KERN_ERR, "amd64", fmt, ##arg)
	91
	92	#define amd64_mc_warn(mci, fmt, arg...) \
	93	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
	94
	95	#define amd64_mc_err(mci, fmt, arg...) \
	96	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
cfe40fdb DT	97
	98	/*
	99	* Throughout the comments in this code, the following terms are used:
	100	*
	101	* SysAddr, DramAddr, and InputAddr
	102	*
	103	* These terms come directly from the amd64 documentation
	104	* (AMD publication #26094). They are defined as follows:
	105	*
	106	* SysAddr:
	107	* This is a physical address generated by a CPU core or a device
	108	* doing DMA. If generated by a CPU core, a SysAddr is the result of
	109	* a virtual to physical address translation by the CPU core's address
	110	* translation mechanism (MMU).
	111	*
	112	* DramAddr:
	113	* A DramAddr is derived from a SysAddr by subtracting an offset that
	114	* depends on which node the SysAddr maps to and whether the SysAddr
	115	* is within a range affected by memory hoisting. The DRAM Base
	116	* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
	117	* determine which node a SysAddr maps to.
	118	*
	119	* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
	120	* is within the range of addresses specified by this register, then
	121	* a value x from the DHAR is subtracted from the SysAddr to produce a
	122	* DramAddr. Here, x represents the base address for the node that
	123	* the SysAddr maps to plus an offset due to memory hoisting. See
	124	* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
	125	* sys_addr_to_dram_addr() below for more information.
	126	*
	127	* If the SysAddr is not affected by the DHAR then a value y is
	128	* subtracted from the SysAddr to produce a DramAddr. Here, y is the
	129	* base address for the node that the SysAddr maps to. See section
	130	* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
	131	* information.
	132	*
	133	* InputAddr:
	134	* A DramAddr is translated to an InputAddr before being passed to the
	135	* memory controller for the node that the DramAddr is associated
	136	* with. The memory controller then maps the InputAddr to a csrow.
	137	* If node interleaving is not in use, then the InputAddr has the same
	138	* value as the DramAddr. Otherwise, the InputAddr is produced by
	139	* discarding the bits used for node interleaving from the DramAddr.
	140	* See section 3.4.4 for more information.
	141	*
	142	* The memory controller for a given node uses its DRAM CS Base and
	143	* DRAM CS Mask registers to map an InputAddr to a csrow. See
	144	* sections 3.5.4 and 3.5.5 for more information.
	145	*/
	146
df71a053	147	#define EDAC_AMD64_VERSION "3.4.0"
cfe40fdb DT	148	#define EDAC_MOD_STR "amd64_edac"
	149
	150	/* Extended Model from CPUID, for CPU Revision numbers */
1433eb99 BP	151	#define K8_REV_D 1
	152	#define K8_REV_E 2
	153	#define K8_REV_F 4
cfe40fdb DT	154
cfe40fdb DT	155	/* Hardware limit on ChipSelect rows per MC and processors per system */
7f19bf75 BP	156	#define NUM_CHIPSELECTS 8
7f19bf75 BP	157	#define DRAM_RANGES 8
cfe40fdb	158
f6d6ae96 BP	159	#define ON true
f6d6ae96 BP	160	#define OFF false
cfe40fdb DT	161
	162	/*
	163	* PCI-defined configuration space registers
	164	*/
df71a053 BP	165	#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
df71a053 BP	166	#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
a597d2a5 AG	167	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
	168	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
	169	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
	170	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
94c1acf2 AG	171	#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
94c1acf2 AG	172	#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
85a8885b AG	173	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
85a8885b AG	174	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
cfe40fdb DT	175
	176	/*
	177	* Function 1 - Address Map
	178	*/
7f19bf75 BP	179	#define DRAM_BASE_LO 0x40
	180	#define DRAM_LIMIT_LO 0x44
	181
18b94f66 AG	182	/*
	183	* F15 M30h D18F1x2[1C:00]
	184	*/
	185	#define DRAM_CONT_BASE 0x200
	186	#define DRAM_CONT_LIMIT 0x204
	187
	188	/*
	189	* F15 M30h D18F1x2[4C:40]
	190	*/
	191	#define DRAM_CONT_HIGH_OFF 0x240
	192
151fa71c BP	193	#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
	194	#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
	195	#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
7f19bf75	196
bc21fa57	197	#define DHAR 0xf0
c8e518d5 BP	198	#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
	199	#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
	200	#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
cfe40fdb	201
cfe40fdb	202	/* NOTE: Extra mask bit vs K8 */
c8e518d5	203	#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
cfe40fdb	204
b2b0c605	205	#define DCT_CFG_SEL 0x10C
cfe40fdb	206
c1ae6830	207	#define DRAM_LOCAL_NODE_BASE 0x120
f08e457c BP	208	#define DRAM_LOCAL_NODE_LIM 0x124
f08e457c BP	209
7f19bf75 BP	210	#define DRAM_BASE_HI 0x140
7f19bf75 BP	211	#define DRAM_LIMIT_HI 0x144
cfe40fdb DT	212
	213
	214	/*
	215	* Function 2 - DRAM controller
	216	*/
11c75ead BP	217	#define DCSB0 0x40
	218	#define DCSB1 0x140
	219	#define DCSB_CS_ENABLE BIT(0)
cfe40fdb	220
11c75ead BP	221	#define DCSM0 0x60
11c75ead BP	222	#define DCSM1 0x160
cfe40fdb	223
11c75ead	224	#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
cfe40fdb	225
a597d2a5 AG	226	#define DRAM_CONTROL 0x78
a597d2a5 AG	227
cfe40fdb DT	228	#define DBAM0 0x80
	229	#define DBAM1 0x180
	230
	231	/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
0a5dfc31	232	#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
cfe40fdb DT	233
	234	#define DBAM_MAX_VALUE 11
	235
cb328507 BP	236	#define DCLR0 0x90
cb328507 BP	237	#define DCLR1 0x190
cfe40fdb	238	#define REVE_WIDTH_128 BIT(16)
41d8bfab	239	#define WIDTH_128 BIT(11)
cfe40fdb	240
cb328507 BP	241	#define DCHR0 0x94
cb328507 BP	242	#define DCHR1 0x194
1433eb99	243	#define DDR3_MODE BIT(8)
cfe40fdb	244
78da121e	245	#define DCT_SEL_LO 0x110
78da121e BP	246	#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
78da121e BP	247	#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
cb328507	248
78da121e	249	#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
cb328507	250
78da121e	251	#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
78da121e	252	#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
cfe40fdb	253
95b0ef55 BP	254	#define SWAP_INTLV_REG 0x10c
95b0ef55 BP	255
78da121e	256	#define DCT_SEL_HI 0x114
cfe40fdb	257
cfe40fdb DT	258	/*
	259	* Function 3 - Misc Control
	260	*/
c9f4f26e	261	#define NBCTL 0x40
cfe40fdb	262
a97fa68e BP	263	#define NBCFG 0x44
	264	#define NBCFG_CHIPKILL BIT(23)
	265	#define NBCFG_ECC_ENABLE BIT(22)
cfe40fdb	266
5980bb9c	267	/* F3x48: NBSL */
cfe40fdb	268	#define F10_NBSL_EXT_ERR_ECC 0x8
5980bb9c	269	#define NBSL_PP_OBS 0x2
cfe40fdb	270
5980bb9c	271	#define SCRCTRL 0x58
cfe40fdb DT	272
cfe40fdb DT	273	#define F10_ONLINE_SPARE 0xB0
614ec9d8 BP	274	#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
614ec9d8 BP	275	#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
cfe40fdb DT	276
cfe40fdb DT	277	#define F10_NB_ARRAY_ADDR 0xB8
6e71a870	278	#define F10_NB_ARRAY_DRAM BIT(31)
cfe40fdb DT	279
cfe40fdb DT	280	/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
6e71a870	281	#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
cfe40fdb DT	282
cfe40fdb DT	283	#define F10_NB_ARRAY_DATA 0xBC
66fed2d4	284	#define F10_NB_ARR_ECC_WR_REQ BIT(17)
6e71a870 BP	285	#define SET_NB_DRAM_INJECTION_WRITE(inj) \
6e71a870 BP	286	(BIT(((inj.word) & 0xF) + 20) \| \
66fed2d4	287	F10_NB_ARR_ECC_WR_REQ \| inj.bit_map)
6e71a870 BP	288	#define SET_NB_DRAM_INJECTION_READ(inj) \
	289	(BIT(((inj.word) & 0xF) + 20) \| \
	290	BIT(16) \| inj.bit_map)
	291
cfe40fdb	292
5980bb9c BP	293	#define NBCAP 0xE8
	294	#define NBCAP_CHIPKILL BIT(4)
	295	#define NBCAP_SECDED BIT(3)
	296	#define NBCAP_DCT_DUAL BIT(0)
cfe40fdb	297
ad6a32e9 BP	298	#define EXT_NB_MCA_CFG 0x180
ad6a32e9 BP	299
f6d6ae96	300	/* MSRs */
5980bb9c	301	#define MSR_MCGCTL_NBE BIT(4)
cfe40fdb	302
b2b0c605	303	enum amd_families {
cfe40fdb DT	304	K8_CPUS = 0,
cfe40fdb DT	305	F10_CPUS,
b2b0c605	306	F15_CPUS,
18b94f66	307	F15_M30H_CPUS,
a597d2a5	308	F15_M60H_CPUS,
94c1acf2	309	F16_CPUS,
85a8885b	310	F16_M30H_CPUS,
b2b0c605	311	NUM_FAMILIES,
cfe40fdb DT	312	};
cfe40fdb DT	313
cfe40fdb DT	314	/* Error injection control structure */
cfe40fdb DT	315	struct error_injection {
66fed2d4 BP	316	u32 section;
	317	u32 word;
	318	u32 bit_map;
cfe40fdb DT	319	};
cfe40fdb DT	320
7f19bf75 BP	321	/* low and high part of PCI config space regs */
	322	struct reg_pair {
	323	u32 lo, hi;
	324	};
	325
	326	/*
	327	* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
	328	*/
	329	struct dram_range {
	330	struct reg_pair base;
	331	struct reg_pair lim;
	332	};
	333
11c75ead BP	334	/* A DCT chip selects collection */
	335	struct chip_select {
	336	u32 csbases[NUM_CHIPSELECTS];
	337	u8 b_cnt;
	338
	339	u32 csmasks[NUM_CHIPSELECTS];
	340	u8 m_cnt;
	341	};
	342
cfe40fdb	343	struct amd64_pvt {
b8cfa02f BP	344	struct low_ops *ops;
b8cfa02f BP	345
cfe40fdb	346	/* pci_device handles which we utilize */
8d5b5d9c	347	struct pci_dev F1, F2, *F3;
cfe40fdb	348
c7e5301a	349	u16 mc_node_id; /* MC index of this MC node */
18b94f66	350	u8 fam; /* CPU family */
a4b4bedc BP	351	u8 model; /* ... model */
	352	u8 stepping; /* ... stepping */
	353
cfe40fdb	354	int ext_model; /* extended model value of this node */
cfe40fdb DT	355	int channel_count;
	356
	357	/* Raw registers */
	358	u32 dclr0; /* DRAM Configuration Low DCT0 reg */
	359	u32 dclr1; /* DRAM Configuration Low DCT1 reg */
	360	u32 dchr0; /* DRAM Configuration High DCT0 reg */
	361	u32 dchr1; /* DRAM Configuration High DCT1 reg */
	362	u32 nbcap; /* North Bridge Capabilities */
	363	u32 nbcfg; /* F10 North Bridge Configuration */
	364	u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
	365	u32 dhar; /* DRAM Hoist reg */
	366	u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
	367	u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
	368
11c75ead BP	369	/* one for each DCT */
11c75ead BP	370	struct chip_select csels[2];
cfe40fdb	371
7f19bf75 BP	372	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
7f19bf75 BP	373	struct dram_range ranges[DRAM_RANGES];
cfe40fdb	374
cfe40fdb DT	375	u64 top_mem; /* top of memory below 4GB */
	376	u64 top_mem2; /* top of memory above 4GB */
	377
78da121e BP	378	u32 dct_sel_lo; /* DRAM Controller Select Low */
78da121e BP	379	u32 dct_sel_hi; /* DRAM Controller Select High */
b2b0c605	380	u32 online_spare; /* On-Line spare Reg */
cfe40fdb	381
ad6a32e9	382	/* x4 or x8 syndromes in use */
a3b7db09	383	u8 ecc_sym_sz;
ad6a32e9	384
cfe40fdb DT	385	/* place to store error injection parameters prior to issue */
cfe40fdb DT	386	struct error_injection injection;
a597d2a5 AG	387
	388	/* cache the dram_type */
	389	enum mem_type dram_type;
ae7bb7c6 BP	390	};
ae7bb7c6 BP	391
33ca0643 BP	392	enum err_codes {
	393	DECODE_OK = 0,
	394	ERR_NODE = -1,
	395	ERR_CSROW = -2,
	396	ERR_CHANNEL = -3,
	397	};
	398
	399	struct err_info {
	400	int err_code;
	401	struct mem_ctl_info *src_mci;
	402	int csrow;
	403	int channel;
	404	u16 syndrome;
	405	u32 page;
	406	u32 offset;
	407	};
	408
c7e5301a	409	static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	410	{
	411	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
	412
	413	if (boot_cpu_data.x86 == 0xf)
	414	return addr;
	415
	416	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) \| addr;
	417	}
	418
c7e5301a	419	static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	420	{
	421	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) \| 0x00ffffff;
	422
	423	if (boot_cpu_data.x86 == 0xf)
	424	return lim;
	425
	426	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) \| lim;
	427	}
	428
f192c7b1 BP	429	static inline u16 extract_syndrome(u64 status)
	430	{
	431	return ((status >> 47) & 0xff) \| ((status >> 16) & 0xff00);
	432	}
	433
18b94f66 AG	434	static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
	435	{
	436	if (pvt->fam == 0x15 && pvt->model >= 0x30)
	437	return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) \|
	438	((pvt->dct_sel_lo >> 6) & 0x3);
	439
	440	return ((pvt)->dct_sel_lo >> 6) & 0x3;
	441	}
ae7bb7c6 BP	442	/*
	443	* per-node ECC settings descriptor
	444	*/
	445	struct ecc_settings {
	446	u32 old_nbctl;
	447	bool nbctl_valid;
	448
cfe40fdb	449	struct flags {
d95cf4de BP	450	unsigned long nb_mce_enable:1;
d95cf4de BP	451	unsigned long nb_ecc_prev:1;
cfe40fdb DT	452	} flags;
	453	};
	454
7d6034d3	455	#ifdef CONFIG_EDAC_DEBUG
e339f1ec	456	extern const struct attribute_group amd64_edac_dbg_group;
7d6034d3 DT	457	#endif
	458
	459	#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
e339f1ec	460	extern const struct attribute_group amd64_edac_inj_group;
7d6034d3 DT	461	#endif
7d6034d3 DT	462
cfe40fdb DT	463	/*
	464	* Each of the PCI Device IDs types have their own set of hardware accessor
	465	* functions and per device encoding/decoding logic.
	466	*/
	467	struct low_ops {
1433eb99	468	int (early_channel_count) (struct amd64_pvt pvt);
f192c7b1	469	void (map_sysaddr_to_csrow) (struct mem_ctl_info mci, u64 sys_addr,
33ca0643	470	struct err_info *);
a597d2a5 AG	471	int (dbam_to_cs) (struct amd64_pvt pvt, u8 dct,
a597d2a5 AG	472	unsigned cs_mode, int cs_mask_nr);
cfe40fdb DT	473	};
	474
	475	struct amd64_family_type {
	476	const char *ctl_name;
8d5b5d9c	477	u16 f1_id, f3_id;
cfe40fdb DT	478	struct low_ops ops;
	479	};
	480
66fed2d4 BP	481	int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
66fed2d4 BP	482	u32 val, const char func);
b2b0c605 BP	483	int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
b2b0c605 BP	484	u32 val, const char *func);
6ba5dcdc	485
b2b0c605 BP	486	#define amd64_read_pci_cfg(pdev, offset, val) \
b2b0c605 BP	487	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	488
b2b0c605 BP	489	#define amd64_write_pci_cfg(pdev, offset, val) \
b2b0c605 BP	490	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	491
cfe40fdb DT	492	int amd64_get_dram_hole_info(struct mem_ctl_info mci, u64 hole_base,
cfe40fdb DT	493	u64 hole_offset, u64 hole_size);
c5608759 MCC	494
c5608759 MCC	495	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
66fed2d4 BP	496
	497	/* Injection helpers */
	498	static inline void disable_caches(void *dummy)
	499	{
	500	write_cr0(read_cr0() \| X86_CR0_CD);
	501	wbinvd();
	502	}
	503
	504	static inline void enable_caches(void *dummy)
	505	{
	506	write_cr0(read_cr0() & ~X86_CR0_CD);
	507	}
18b94f66 AG	508
	509	static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
	510	{
	511	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	512	u32 tmp;
	513	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
	514	return (u8) tmp & 0xF;
	515	}
	516	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
	517	}
	518
	519	static inline u8 dhar_valid(struct amd64_pvt *pvt)
	520	{
	521	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	522	u32 tmp;
	523	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	524	return (tmp >> 1) & BIT(0);
	525	}
	526	return (pvt)->dhar & BIT(0);
	527	}
	528
	529	static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
	530	{
	531	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	532	u32 tmp;
	533	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	534	return (tmp >> 11) & 0x1FFF;
	535	}
	536	return (pvt)->dct_sel_lo & 0xFFFFF800;
	537	}