[linux-block.git] / drivers / edac / amd64_edac.h

/*
 * AMD64 class Memory Controller kernel module
 *
 * Copyright (c) 2009 SoftwareBitMaker.
 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <asm/cpu_device_id.h>
#include <asm/msr.h>
#include "edac_module.h"
#include "mce_amd.h"

#define amd64_info(fmt, arg...) \
	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define amd64_warn(fmt, arg...) \
	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)

#define amd64_err(fmt, arg...) \
	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)

#define amd64_mc_warn(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_mc_err(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

/*
 * Throughout the comments in this code, the following terms are used:
 *
 *	SysAddr, DramAddr, and InputAddr
 *
 *  These terms come directly from the amd64 documentation
 * (AMD publication #26094).  They are defined as follows:
 *
 *     SysAddr:
 *         This is a physical address generated by a CPU core or a device
 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 *         a virtual to physical address translation by the CPU core's address
 *         translation mechanism (MMU).
 *
 *     DramAddr:
 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 *         depends on which node the SysAddr maps to and whether the SysAddr
 *         is within a range affected by memory hoisting.  The DRAM Base
 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 *         determine which node a SysAddr maps to.
 *
 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 *         is within the range of addresses specified by this register, then
 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 *         DramAddr.  Here, x represents the base address for the node that
 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 *         sys_addr_to_dram_addr() below for more information.
 *
 *         If the SysAddr is not affected by the DHAR then a value y is
 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 *         base address for the node that the SysAddr maps to.  See section
 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 *         information.
 *
 *     InputAddr:
 *         A DramAddr is translated to an InputAddr before being passed to the
 *         memory controller for the node that the DramAddr is associated
 *         with.  The memory controller then maps the InputAddr to a csrow.
 *         If node interleaving is not in use, then the InputAddr has the same
 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 *         discarding the bits used for node interleaving from the DramAddr.
 *         See section 3.4.4 for more information.
 *
 *         The memory controller for a given node uses its DRAM CS Base and
 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 *         sections 3.5.4 and 3.5.5 for more information.
 */

#define EDAC_AMD64_VERSION		"3.5.0"
#define EDAC_MOD_STR			"amd64_edac"

/* Extended Model from CPUID, for CPU Revision numbers */
#define K8_REV_D			1
#define K8_REV_E			2
#define K8_REV_F			4

/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS			8
#define DRAM_RANGES			8
#define NUM_CONTROLLERS			12

#define ON true
#define OFF false

/*
 * PCI-defined configuration space registers
 */
#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
#define PCI_DEVICE_ID_AMD_17H_DF_F0	0x1460
#define PCI_DEVICE_ID_AMD_17H_DF_F6	0x1466
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
#define PCI_DEVICE_ID_AMD_19H_DF_F0	0x1650
#define PCI_DEVICE_ID_AMD_19H_DF_F6	0x1656
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670

/*
 * Function 1 - Address Map
 */
#define DRAM_BASE_LO			0x40
#define DRAM_LIMIT_LO			0x44

/*
 * F15 M30h D18F1x2[1C:00]
 */
#define DRAM_CONT_BASE			0x200
#define DRAM_CONT_LIMIT			0x204

/*
 * F15 M30h D18F1x2[4C:40]
 */
#define DRAM_CONT_HIGH_OFF		0x240

#define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
#define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
#define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))

#define DHAR				0xf0
#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)

					/* NOTE: Extra mask bit vs K8 */
#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)

#define DCT_CFG_SEL			0x10C

#define DRAM_LOCAL_NODE_BASE		0x120
#define DRAM_LOCAL_NODE_LIM		0x124

#define DRAM_BASE_HI			0x140
#define DRAM_LIMIT_HI			0x144


/*
 * Function 2 - DRAM controller
 */
#define DCSB0				0x40
#define DCSB1				0x140
#define DCSB_CS_ENABLE			BIT(0)

#define DCSM0				0x60
#define DCSM1				0x160

#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
#define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)

#define DRAM_CONTROL			0x78

#define DBAM0				0x80
#define DBAM1				0x180

/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg)		((((reg) >> (4*(i)))) & 0xF)

#define DBAM_MAX_VALUE			11

#define DCLR0				0x90
#define DCLR1				0x190
#define REVE_WIDTH_128			BIT(16)
#define WIDTH_128			BIT(11)

#define DCHR0				0x94
#define DCHR1				0x194
#define DDR3_MODE			BIT(8)

#define DCT_SEL_LO			0x110
#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))

#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))

#define SWAP_INTLV_REG			0x10c

#define DCT_SEL_HI			0x114

#define F15H_M60H_SCRCTRL		0x1C8
#define F17H_SCR_BASE_ADDR		0x48
#define F17H_SCR_LIMIT_ADDR		0x4C

/*
 * Function 3 - Misc Control
 */
#define NBCTL				0x40

#define NBCFG				0x44
#define NBCFG_CHIPKILL			BIT(23)
#define NBCFG_ECC_ENABLE		BIT(22)

/* F3x48: NBSL */
#define F10_NBSL_EXT_ERR_ECC		0x8
#define NBSL_PP_OBS			0x2

#define SCRCTRL				0x58

#define F10_ONLINE_SPARE		0xB0
#define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
#define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

#define F10_NB_ARRAY_ADDR		0xB8
#define F10_NB_ARRAY_DRAM		BIT(31)

/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
#define SET_NB_ARRAY_ADDR(section)	(((section) & 0x3) << 1)

#define F10_NB_ARRAY_DATA		0xBC
#define F10_NB_ARR_ECC_WR_REQ		BIT(17)
#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
#define SET_NB_DRAM_INJECTION_READ(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					BIT(16) |  inj.bit_map)


#define NBCAP				0xE8
#define NBCAP_CHIPKILL			BIT(4)
#define NBCAP_SECDED			BIT(3)
#define NBCAP_DCT_DUAL			BIT(0)

#define EXT_NB_MCA_CFG			0x180

/* MSRs */
#define MSR_MCGCTL_NBE			BIT(4)

/* F17h */

/* F0: */
#define DF_DHAR				0x104

/* UMC CH register offsets */
#define UMCCH_BASE_ADDR			0x0
#define UMCCH_BASE_ADDR_SEC		0x10
#define UMCCH_ADDR_MASK			0x20
#define UMCCH_ADDR_MASK_SEC		0x28
#define UMCCH_ADDR_MASK_SEC_DDR5	0x30
#define UMCCH_ADDR_CFG			0x30
#define UMCCH_ADDR_CFG_DDR5		0x40
#define UMCCH_DIMM_CFG			0x80
#define UMCCH_DIMM_CFG_DDR5		0x90
#define UMCCH_UMC_CFG			0x100
#define UMCCH_SDP_CTRL			0x104
#define UMCCH_ECC_CTRL			0x14C
#define UMCCH_ECC_BAD_SYMBOL		0xD90
#define UMCCH_UMC_CAP			0xDF0
#define UMCCH_UMC_CAP_HI		0xDF4

/* UMC CH bitfields */
#define UMC_ECC_CHIPKILL_CAP		BIT(31)
#define UMC_ECC_ENABLED			BIT(30)

#define UMC_SDP_INIT			BIT(31)

enum amd_families {
	K8_CPUS = 0,
	F10_CPUS,
	F15_CPUS,
	F15_M30H_CPUS,
	F15_M60H_CPUS,
	F16_CPUS,
	F16_M30H_CPUS,
	F17_CPUS,
	F17_M10H_CPUS,
	F17_M30H_CPUS,
	F17_M60H_CPUS,
	F17_M70H_CPUS,
	F19_CPUS,
	F19_M10H_CPUS,
	F19_M50H_CPUS,
	NUM_FAMILIES,
};

/* Error injection control structure */
struct error_injection {
	u32	 section;
	u32	 word;
	u32	 bit_map;
};

/* low and high part of PCI config space regs */
struct reg_pair {
	u32 lo, hi;
};

/*
 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 */
struct dram_range {
	struct reg_pair base;
	struct reg_pair lim;
};

/* A DCT chip selects collection */
struct chip_select {
	u32 csbases[NUM_CHIPSELECTS];
	u32 csbases_sec[NUM_CHIPSELECTS];
	u8 b_cnt;

	u32 csmasks[NUM_CHIPSELECTS];
	u32 csmasks_sec[NUM_CHIPSELECTS];
	u8 m_cnt;
};

struct amd64_umc {
	u32 dimm_cfg;		/* DIMM Configuration reg */
	u32 umc_cfg;		/* Configuration reg */
	u32 sdp_ctrl;		/* SDP Control reg */
	u32 ecc_ctrl;		/* DRAM ECC Control reg */
	u32 umc_cap_hi;		/* Capabilities High reg */

	/* cache the dram_type */
	enum mem_type dram_type;
};

struct amd64_pvt {
	struct low_ops *ops;

	/* pci_device handles which we utilize */
	struct pci_dev *F0, *F1, *F2, *F3, *F6;

	u16 mc_node_id;		/* MC index of this MC node */
	u8 fam;			/* CPU family */
	u8 model;		/* ... model */
	u8 stepping;		/* ... stepping */

	int ext_model;		/* extended model value of this node */
	int channel_count;

	/* Raw registers */
	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
	u32 nbcap;		/* North Bridge Capabilities */
	u32 nbcfg;		/* F10 North Bridge Configuration */
	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
	u32 dhar;		/* DRAM Hoist reg */
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	/* one for each DCT/UMC */
	struct chip_select csels[NUM_CONTROLLERS];

	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
	struct dram_range ranges[DRAM_RANGES];

	u64 top_mem;		/* top of memory below 4GB */
	u64 top_mem2;		/* top of memory above 4GB */

	u32 dct_sel_lo;		/* DRAM Controller Select Low */
	u32 dct_sel_hi;		/* DRAM Controller Select High */
	u32 online_spare;	/* On-Line spare Reg */

	/* x4, x8, or x16 syndromes in use */
	u8 ecc_sym_sz;

	/* place to store error injection parameters prior to issue */
	struct error_injection injection;

	/*
	 * cache the dram_type
	 *
	 * NOTE: Don't use this for Family 17h and later.
	 *	 Use dram_type in struct amd64_umc instead.
	 */
	enum mem_type dram_type;

	struct amd64_umc *umc;	/* UMC registers */
};

enum err_codes {
	DECODE_OK	=  0,
	ERR_NODE	= -1,
	ERR_CSROW	= -2,
	ERR_CHANNEL	= -3,
	ERR_SYND	= -4,
	ERR_NORM_ADDR	= -5,
};

struct err_info {
	int err_code;
	struct mem_ctl_info *src_mci;
	int csrow;
	int channel;
	u16 syndrome;
	u32 page;
	u32 offset;
};

static inline u32 get_umc_base(u8 channel)
{
	/* chY: 0xY50000 */
	return 0x50000 + (channel << 20);
}

static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
{
	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;

	if (boot_cpu_data.x86 == 0xf)
		return addr;

	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
}

static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
{
	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;

	if (boot_cpu_data.x86 == 0xf)
		return lim;

	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
}

static inline u16 extract_syndrome(u64 status)
{
	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
}

static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30)
		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
			((pvt->dct_sel_lo >> 6) & 0x3);

	return	((pvt)->dct_sel_lo >> 6) & 0x3;
}
/*
 * per-node ECC settings descriptor
 */
struct ecc_settings {
	u32 old_nbctl;
	bool nbctl_valid;

	struct flags {
		unsigned long nb_mce_enable:1;
		unsigned long nb_ecc_prev:1;
	} flags;
};

/*
 * Each of the PCI Device IDs types have their own set of hardware accessor
 * functions and per device encoding/decoding logic.
 */
struct low_ops {
	int (*early_channel_count)	(struct amd64_pvt *pvt);
	void (*map_sysaddr_to_csrow)	(struct mem_ctl_info *mci, u64 sys_addr,
					 struct err_info *);
	int (*dbam_to_cs)		(struct amd64_pvt *pvt, u8 dct,
					 unsigned cs_mode, int cs_mask_nr);
};

struct amd64_family_flags {
	/*
	 * Indicates that the system supports the new register offsets, etc.
	 * first introduced with Family 19h Model 10h.
	 */
	__u64 zn_regs_v2	: 1,

	      __reserved	: 63;
};

struct amd64_family_type {
	const char *ctl_name;
	u16 f0_id, f1_id, f2_id, f6_id;
	/* Maximum number of memory controllers per die/node. */
	u8 max_mcs;
	struct amd64_family_flags flags;
	struct low_ops ops;
};

int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func);
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func);

#define amd64_read_pci_cfg(pdev, offset, val)	\
	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_write_pci_cfg(pdev, offset, val)	\
	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

/* Injection helpers */
static inline void disable_caches(void *dummy)
{
	write_cr0(read_cr0() | X86_CR0_CD);
	wbinvd();
}

static inline void enable_caches(void *dummy)
{
	write_cr0(read_cr0() & ~X86_CR0_CD);
}

static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
		return (u8) tmp & 0xF;
	}
	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
}

static inline u8 dhar_valid(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 1) & BIT(0);
	}
	return (pvt)->dhar & BIT(0);
}

static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 11) & 0x1FFF;
	}
	return (pvt)->dct_sel_lo & 0xFFFFF800;
}
Commit	Line	Data
cfe40fdb DT	1	/*
	2	* AMD64 class Memory Controller kernel module
	3	*
	4	* Copyright (c) 2009 SoftwareBitMaker.
1a8bc770	5	* Copyright (c) 2009-15 Advanced Micro Devices, Inc.
cfe40fdb DT	6	*
	7	* This file may be distributed under the terms of the
	8	* GNU General Public License.
cfe40fdb DT	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/ctype.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
	16	#include <linux/slab.h>
	17	#include <linux/mmzone.h>
	18	#include <linux/edac.h>
1bd9900b	19	#include <asm/cpu_device_id.h>
f9431992	20	#include <asm/msr.h>
78d88e8a	21	#include "edac_module.h"
47ca08a4	22	#include "mce_amd.h"
cfe40fdb	23
24f9a7fe BP	24	#define amd64_info(fmt, arg...) \
	25	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
	26
24f9a7fe	27	#define amd64_warn(fmt, arg...) \
5246c540	28	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
24f9a7fe BP	29
24f9a7fe BP	30	#define amd64_err(fmt, arg...) \
5246c540	31	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
24f9a7fe BP	32
	33	#define amd64_mc_warn(mci, fmt, arg...) \
	34	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
	35
	36	#define amd64_mc_err(mci, fmt, arg...) \
	37	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
cfe40fdb DT	38
	39	/*
	40	* Throughout the comments in this code, the following terms are used:
	41	*
	42	* SysAddr, DramAddr, and InputAddr
	43	*
	44	* These terms come directly from the amd64 documentation
	45	* (AMD publication #26094). They are defined as follows:
	46	*
	47	* SysAddr:
	48	* This is a physical address generated by a CPU core or a device
	49	* doing DMA. If generated by a CPU core, a SysAddr is the result of
	50	* a virtual to physical address translation by the CPU core's address
	51	* translation mechanism (MMU).
	52	*
	53	* DramAddr:
	54	* A DramAddr is derived from a SysAddr by subtracting an offset that
	55	* depends on which node the SysAddr maps to and whether the SysAddr
	56	* is within a range affected by memory hoisting. The DRAM Base
	57	* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
	58	* determine which node a SysAddr maps to.
	59	*
	60	* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
	61	* is within the range of addresses specified by this register, then
	62	* a value x from the DHAR is subtracted from the SysAddr to produce a
	63	* DramAddr. Here, x represents the base address for the node that
	64	* the SysAddr maps to plus an offset due to memory hoisting. See
	65	* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
	66	* sys_addr_to_dram_addr() below for more information.
	67	*
	68	* If the SysAddr is not affected by the DHAR then a value y is
	69	* subtracted from the SysAddr to produce a DramAddr. Here, y is the
	70	* base address for the node that the SysAddr maps to. See section
	71	* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
	72	* information.
	73	*
	74	* InputAddr:
	75	* A DramAddr is translated to an InputAddr before being passed to the
	76	* memory controller for the node that the DramAddr is associated
	77	* with. The memory controller then maps the InputAddr to a csrow.
	78	* If node interleaving is not in use, then the InputAddr has the same
	79	* value as the DramAddr. Otherwise, the InputAddr is produced by
	80	* discarding the bits used for node interleaving from the DramAddr.
	81	* See section 3.4.4 for more information.
	82	*
	83	* The memory controller for a given node uses its DRAM CS Base and
	84	* DRAM CS Mask registers to map an InputAddr to a csrow. See
	85	* sections 3.5.4 and 3.5.5 for more information.
	86	*/
	87
e62d2ca9	88	#define EDAC_AMD64_VERSION "3.5.0"
cfe40fdb DT	89	#define EDAC_MOD_STR "amd64_edac"
	90
	91	/* Extended Model from CPUID, for CPU Revision numbers */
1433eb99 BP	92	#define K8_REV_D 1
	93	#define K8_REV_E 2
	94	#define K8_REV_F 4
cfe40fdb DT	95
cfe40fdb DT	96	/* Hardware limit on ChipSelect rows per MC and processors per system */
7f19bf75 BP	97	#define NUM_CHIPSELECTS 8
7f19bf75 BP	98	#define DRAM_RANGES 8
e2be5955	99	#define NUM_CONTROLLERS 12
cfe40fdb	100
f6d6ae96 BP	101	#define ON true
f6d6ae96 BP	102	#define OFF false
cfe40fdb DT	103
	104	/*
	105	* PCI-defined configuration space registers
	106	*/
df71a053 BP	107	#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
df71a053 BP	108	#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
a597d2a5 AG	109	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
	110	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
	111	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
	112	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
94c1acf2 AG	113	#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
94c1acf2 AG	114	#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
85a8885b AG	115	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
85a8885b AG	116	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
f1cbbec9 YG	117	#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
f1cbbec9 YG	118	#define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
8960de4a MJ	119	#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
8960de4a MJ	120	#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
6e846239 YG	121	#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
6e846239 YG	122	#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
b6bea24d AM	123	#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
b6bea24d AM	124	#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
3e443eb3 IV	125	#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
3e443eb3 IV	126	#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
2eb61c91 YG	127	#define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
2eb61c91 YG	128	#define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656
e2be5955 YG	129	#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
e2be5955 YG	130	#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
0b8bf9cb MB	131	#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
0b8bf9cb MB	132	#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670
cfe40fdb DT	133
	134	/*
	135	* Function 1 - Address Map
	136	*/
7f19bf75 BP	137	#define DRAM_BASE_LO 0x40
	138	#define DRAM_LIMIT_LO 0x44
	139
18b94f66 AG	140	/*
	141	* F15 M30h D18F1x2[1C:00]
	142	*/
	143	#define DRAM_CONT_BASE 0x200
	144	#define DRAM_CONT_LIMIT 0x204
	145
	146	/*
	147	* F15 M30h D18F1x2[4C:40]
	148	*/
	149	#define DRAM_CONT_HIGH_OFF 0x240
	150
151fa71c BP	151	#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
	152	#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
	153	#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
7f19bf75	154
bc21fa57	155	#define DHAR 0xf0
c8e518d5 BP	156	#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
	157	#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
	158	#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
cfe40fdb	159
cfe40fdb	160	/* NOTE: Extra mask bit vs K8 */
c8e518d5	161	#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
cfe40fdb	162
b2b0c605	163	#define DCT_CFG_SEL 0x10C
cfe40fdb	164
c1ae6830	165	#define DRAM_LOCAL_NODE_BASE 0x120
f08e457c BP	166	#define DRAM_LOCAL_NODE_LIM 0x124
f08e457c BP	167
7f19bf75 BP	168	#define DRAM_BASE_HI 0x140
7f19bf75 BP	169	#define DRAM_LIMIT_HI 0x144
cfe40fdb DT	170
	171
	172	/*
	173	* Function 2 - DRAM controller
	174	*/
11c75ead BP	175	#define DCSB0 0x40
	176	#define DCSB1 0x140
	177	#define DCSB_CS_ENABLE BIT(0)
cfe40fdb	178
11c75ead BP	179	#define DCSM0 0x60
11c75ead BP	180	#define DCSM1 0x160
cfe40fdb	181
81f5090d YG	182	#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
81f5090d YG	183	#define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
cfe40fdb	184
a597d2a5 AG	185	#define DRAM_CONTROL 0x78
a597d2a5 AG	186
cfe40fdb DT	187	#define DBAM0 0x80
	188	#define DBAM1 0x180
	189
	190	/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
0a5dfc31	191	#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
cfe40fdb DT	192
	193	#define DBAM_MAX_VALUE 11
	194
cb328507 BP	195	#define DCLR0 0x90
cb328507 BP	196	#define DCLR1 0x190
cfe40fdb	197	#define REVE_WIDTH_128 BIT(16)
41d8bfab	198	#define WIDTH_128 BIT(11)
cfe40fdb	199
cb328507 BP	200	#define DCHR0 0x94
cb328507 BP	201	#define DCHR1 0x194
1433eb99	202	#define DDR3_MODE BIT(8)
cfe40fdb	203
78da121e	204	#define DCT_SEL_LO 0x110
78da121e BP	205	#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
78da121e BP	206	#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
cb328507	207
78da121e	208	#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
cb328507	209
78da121e	210	#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
78da121e	211	#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
cfe40fdb	212
95b0ef55 BP	213	#define SWAP_INTLV_REG 0x10c
95b0ef55 BP	214
78da121e	215	#define DCT_SEL_HI 0x114
cfe40fdb	216
da92110d	217	#define F15H_M60H_SCRCTRL 0x1C8
8051c0af YG	218	#define F17H_SCR_BASE_ADDR 0x48
8051c0af YG	219	#define F17H_SCR_LIMIT_ADDR 0x4C
da92110d	220
cfe40fdb DT	221	/*
	222	* Function 3 - Misc Control
	223	*/
c9f4f26e	224	#define NBCTL 0x40
cfe40fdb	225
a97fa68e BP	226	#define NBCFG 0x44
	227	#define NBCFG_CHIPKILL BIT(23)
	228	#define NBCFG_ECC_ENABLE BIT(22)
cfe40fdb	229
5980bb9c	230	/* F3x48: NBSL */
cfe40fdb	231	#define F10_NBSL_EXT_ERR_ECC 0x8
5980bb9c	232	#define NBSL_PP_OBS 0x2
cfe40fdb	233
5980bb9c	234	#define SCRCTRL 0x58
cfe40fdb DT	235
cfe40fdb DT	236	#define F10_ONLINE_SPARE 0xB0
614ec9d8 BP	237	#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
614ec9d8 BP	238	#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
cfe40fdb DT	239
cfe40fdb DT	240	#define F10_NB_ARRAY_ADDR 0xB8
6e71a870	241	#define F10_NB_ARRAY_DRAM BIT(31)
cfe40fdb DT	242
cfe40fdb DT	243	/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
6e71a870	244	#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
cfe40fdb DT	245
cfe40fdb DT	246	#define F10_NB_ARRAY_DATA 0xBC
66fed2d4	247	#define F10_NB_ARR_ECC_WR_REQ BIT(17)
6e71a870 BP	248	#define SET_NB_DRAM_INJECTION_WRITE(inj) \
6e71a870 BP	249	(BIT(((inj.word) & 0xF) + 20) \| \
66fed2d4	250	F10_NB_ARR_ECC_WR_REQ \| inj.bit_map)
6e71a870 BP	251	#define SET_NB_DRAM_INJECTION_READ(inj) \
	252	(BIT(((inj.word) & 0xF) + 20) \| \
	253	BIT(16) \| inj.bit_map)
	254
cfe40fdb	255
5980bb9c BP	256	#define NBCAP 0xE8
	257	#define NBCAP_CHIPKILL BIT(4)
	258	#define NBCAP_SECDED BIT(3)
	259	#define NBCAP_DCT_DUAL BIT(0)
cfe40fdb	260
ad6a32e9 BP	261	#define EXT_NB_MCA_CFG 0x180
ad6a32e9 BP	262
f6d6ae96	263	/* MSRs */
5980bb9c	264	#define MSR_MCGCTL_NBE BIT(4)
cfe40fdb	265
b64ce7cd YG	266	/* F17h */
	267
	268	/* F0: */
	269	#define DF_DHAR 0x104
	270
196b79fc	271	/* UMC CH register offsets */
b64ce7cd	272	#define UMCCH_BASE_ADDR 0x0
7574729e	273	#define UMCCH_BASE_ADDR_SEC 0x10
b64ce7cd	274	#define UMCCH_ADDR_MASK 0x20
7574729e	275	#define UMCCH_ADDR_MASK_SEC 0x28
2151c84e	276	#define UMCCH_ADDR_MASK_SEC_DDR5 0x30
07ed82ef	277	#define UMCCH_ADDR_CFG 0x30
2151c84e	278	#define UMCCH_ADDR_CFG_DDR5 0x40
b64ce7cd	279	#define UMCCH_DIMM_CFG 0x80
2151c84e	280	#define UMCCH_DIMM_CFG_DDR5 0x90
07ed82ef	281	#define UMCCH_UMC_CFG 0x100
196b79fc	282	#define UMCCH_SDP_CTRL 0x104
b64ce7cd	283	#define UMCCH_ECC_CTRL 0x14C
07ed82ef YG	284	#define UMCCH_ECC_BAD_SYMBOL 0xD90
07ed82ef YG	285	#define UMCCH_UMC_CAP 0xDF0
196b79fc YG	286	#define UMCCH_UMC_CAP_HI 0xDF4
	287
	288	/* UMC CH bitfields */
b64ce7cd	289	#define UMC_ECC_CHIPKILL_CAP BIT(31)
196b79fc	290	#define UMC_ECC_ENABLED BIT(30)
b64ce7cd	291
196b79fc YG	292	#define UMC_SDP_INIT BIT(31)
196b79fc YG	293
b2b0c605	294	enum amd_families {
cfe40fdb DT	295	K8_CPUS = 0,
cfe40fdb DT	296	F10_CPUS,
b2b0c605	297	F15_CPUS,
18b94f66	298	F15_M30H_CPUS,
a597d2a5	299	F15_M60H_CPUS,
94c1acf2	300	F16_CPUS,
85a8885b	301	F16_M30H_CPUS,
f1cbbec9	302	F17_CPUS,
8960de4a	303	F17_M10H_CPUS,
6e846239	304	F17_M30H_CPUS,
b6bea24d	305	F17_M60H_CPUS,
3e443eb3	306	F17_M70H_CPUS,
2eb61c91	307	F19_CPUS,
e2be5955	308	F19_M10H_CPUS,
0b8bf9cb	309	F19_M50H_CPUS,
b2b0c605	310	NUM_FAMILIES,
cfe40fdb DT	311	};
cfe40fdb DT	312
cfe40fdb DT	313	/* Error injection control structure */
cfe40fdb DT	314	struct error_injection {
66fed2d4 BP	315	u32 section;
	316	u32 word;
	317	u32 bit_map;
cfe40fdb DT	318	};
cfe40fdb DT	319
7f19bf75 BP	320	/* low and high part of PCI config space regs */
	321	struct reg_pair {
	322	u32 lo, hi;
	323	};
	324
	325	/*
	326	* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
	327	*/
	328	struct dram_range {
	329	struct reg_pair base;
	330	struct reg_pair lim;
	331	};
	332
11c75ead BP	333	/* A DCT chip selects collection */
	334	struct chip_select {
	335	u32 csbases[NUM_CHIPSELECTS];
7574729e	336	u32 csbases_sec[NUM_CHIPSELECTS];
11c75ead BP	337	u8 b_cnt;
	338
	339	u32 csmasks[NUM_CHIPSELECTS];
7574729e	340	u32 csmasks_sec[NUM_CHIPSELECTS];
11c75ead BP	341	u8 m_cnt;
	342	};
	343
f1cbbec9	344	struct amd64_umc {
b64ce7cd	345	u32 dimm_cfg; /* DIMM Configuration reg */
07ed82ef	346	u32 umc_cfg; /* Configuration reg */
f1cbbec9	347	u32 sdp_ctrl; /* SDP Control reg */
b64ce7cd	348	u32 ecc_ctrl; /* DRAM ECC Control reg */
07ed82ef	349	u32 umc_cap_hi; /* Capabilities High reg */
75aeaaf2 YG	350
	351	/* cache the dram_type */
	352	enum mem_type dram_type;
f1cbbec9 YG	353	};
f1cbbec9 YG	354
cfe40fdb	355	struct amd64_pvt {
b8cfa02f BP	356	struct low_ops *ops;
b8cfa02f BP	357
cfe40fdb	358	/* pci_device handles which we utilize */
936fc3af	359	struct pci_dev F0, F1, F2, F3, *F6;
cfe40fdb	360
c7e5301a	361	u16 mc_node_id; /* MC index of this MC node */
18b94f66	362	u8 fam; /* CPU family */
a4b4bedc BP	363	u8 model; /* ... model */
	364	u8 stepping; /* ... stepping */
	365
cfe40fdb	366	int ext_model; /* extended model value of this node */
cfe40fdb DT	367	int channel_count;
	368
	369	/* Raw registers */
	370	u32 dclr0; /* DRAM Configuration Low DCT0 reg */
	371	u32 dclr1; /* DRAM Configuration Low DCT1 reg */
	372	u32 dchr0; /* DRAM Configuration High DCT0 reg */
	373	u32 dchr1; /* DRAM Configuration High DCT1 reg */
	374	u32 nbcap; /* North Bridge Capabilities */
	375	u32 nbcfg; /* F10 North Bridge Configuration */
	376	u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
	377	u32 dhar; /* DRAM Hoist reg */
	378	u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
	379	u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
	380
d971e28e YG	381	/* one for each DCT/UMC */
d971e28e YG	382	struct chip_select csels[NUM_CONTROLLERS];
cfe40fdb	383
7f19bf75 BP	384	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
7f19bf75 BP	385	struct dram_range ranges[DRAM_RANGES];
cfe40fdb	386
cfe40fdb DT	387	u64 top_mem; /* top of memory below 4GB */
	388	u64 top_mem2; /* top of memory above 4GB */
	389
78da121e BP	390	u32 dct_sel_lo; /* DRAM Controller Select Low */
78da121e BP	391	u32 dct_sel_hi; /* DRAM Controller Select High */
b2b0c605	392	u32 online_spare; /* On-Line spare Reg */
cfe40fdb	393
7835961d	394	/* x4, x8, or x16 syndromes in use */
a3b7db09	395	u8 ecc_sym_sz;
ad6a32e9	396
cfe40fdb DT	397	/* place to store error injection parameters prior to issue */
cfe40fdb DT	398	struct error_injection injection;
a597d2a5	399
75aeaaf2 YG	400	/*
	401	* cache the dram_type
	402	*
	403	* NOTE: Don't use this for Family 17h and later.
	404	* Use dram_type in struct amd64_umc instead.
	405	*/
a597d2a5	406	enum mem_type dram_type;
f1cbbec9 YG	407
f1cbbec9 YG	408	struct amd64_umc umc; / UMC registers */
ae7bb7c6 BP	409	};
ae7bb7c6 BP	410
33ca0643 BP	411	enum err_codes {
	412	DECODE_OK = 0,
	413	ERR_NODE = -1,
	414	ERR_CSROW = -2,
	415	ERR_CHANNEL = -3,
713ad546 YG	416	ERR_SYND = -4,
713ad546 YG	417	ERR_NORM_ADDR = -5,
33ca0643 BP	418	};
	419
	420	struct err_info {
	421	int err_code;
	422	struct mem_ctl_info *src_mci;
	423	int csrow;
	424	int channel;
	425	u16 syndrome;
	426	u32 page;
	427	u32 offset;
	428	};
	429
196b79fc YG	430	static inline u32 get_umc_base(u8 channel)
196b79fc YG	431	{
bdcee774 YG	432	/* chY: 0xY50000 */
bdcee774 YG	433	return 0x50000 + (channel << 20);
196b79fc YG	434	}
196b79fc YG	435
c7e5301a	436	static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	437	{
	438	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
	439
	440	if (boot_cpu_data.x86 == 0xf)
	441	return addr;
	442
	443	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) \| addr;
	444	}
	445
c7e5301a	446	static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	447	{
	448	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) \| 0x00ffffff;
	449
	450	if (boot_cpu_data.x86 == 0xf)
	451	return lim;
	452
	453	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) \| lim;
	454	}
	455
f192c7b1 BP	456	static inline u16 extract_syndrome(u64 status)
	457	{
	458	return ((status >> 47) & 0xff) \| ((status >> 16) & 0xff00);
	459	}
	460
18b94f66 AG	461	static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
	462	{
	463	if (pvt->fam == 0x15 && pvt->model >= 0x30)
	464	return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) \|
	465	((pvt->dct_sel_lo >> 6) & 0x3);
	466
	467	return ((pvt)->dct_sel_lo >> 6) & 0x3;
	468	}
ae7bb7c6 BP	469	/*
	470	* per-node ECC settings descriptor
	471	*/
	472	struct ecc_settings {
	473	u32 old_nbctl;
	474	bool nbctl_valid;
	475
cfe40fdb	476	struct flags {
d95cf4de BP	477	unsigned long nb_mce_enable:1;
d95cf4de BP	478	unsigned long nb_ecc_prev:1;
cfe40fdb DT	479	} flags;
	480	};
	481
cfe40fdb DT	482	/*
	483	* Each of the PCI Device IDs types have their own set of hardware accessor
	484	* functions and per device encoding/decoding logic.
	485	*/
	486	struct low_ops {
1433eb99	487	int (early_channel_count) (struct amd64_pvt pvt);
f192c7b1	488	void (map_sysaddr_to_csrow) (struct mem_ctl_info mci, u64 sys_addr,
33ca0643	489	struct err_info *);
a597d2a5 AG	490	int (dbam_to_cs) (struct amd64_pvt pvt, u8 dct,
a597d2a5 AG	491	unsigned cs_mode, int cs_mask_nr);
cfe40fdb DT	492	};
cfe40fdb DT	493
2151c84e YG	494	struct amd64_family_flags {
	495	/*
	496	* Indicates that the system supports the new register offsets, etc.
	497	* first introduced with Family 19h Model 10h.
	498	*/
	499	__u64 zn_regs_v2 : 1,
	500
	501	__reserved : 63;
	502	};
	503
cfe40fdb DT	504	struct amd64_family_type {
cfe40fdb DT	505	const char *ctl_name;
f1cbbec9	506	u16 f0_id, f1_id, f2_id, f6_id;
5e4c5527 YG	507	/* Maximum number of memory controllers per die/node. */
5e4c5527 YG	508	u8 max_mcs;
2151c84e	509	struct amd64_family_flags flags;
cfe40fdb DT	510	struct low_ops ops;
	511	};
	512
66fed2d4 BP	513	int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
66fed2d4 BP	514	u32 val, const char func);
b2b0c605 BP	515	int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
b2b0c605 BP	516	u32 val, const char *func);
6ba5dcdc	517
b2b0c605 BP	518	#define amd64_read_pci_cfg(pdev, offset, val) \
b2b0c605 BP	519	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	520
b2b0c605 BP	521	#define amd64_write_pci_cfg(pdev, offset, val) \
b2b0c605 BP	522	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	523
c5608759	524	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
66fed2d4 BP	525
	526	/* Injection helpers */
	527	static inline void disable_caches(void *dummy)
	528	{
	529	write_cr0(read_cr0() \| X86_CR0_CD);
	530	wbinvd();
	531	}
	532
	533	static inline void enable_caches(void *dummy)
	534	{
	535	write_cr0(read_cr0() & ~X86_CR0_CD);
	536	}
18b94f66 AG	537
	538	static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
	539	{
	540	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	541	u32 tmp;
	542	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
	543	return (u8) tmp & 0xF;
	544	}
	545	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
	546	}
	547
	548	static inline u8 dhar_valid(struct amd64_pvt *pvt)
	549	{
	550	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	551	u32 tmp;
	552	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	553	return (tmp >> 1) & BIT(0);
	554	}
	555	return (pvt)->dhar & BIT(0);
	556	}
	557
	558	static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
	559	{
	560	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	561	u32 tmp;
	562	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	563	return (tmp >> 11) & 0x1FFF;
	564	}
	565	return (pvt)->dct_sel_lo & 0xFFFFF800;
	566	}