[linux-block.git] / drivers / edac / amd64_edac.h

/*
 * AMD64 class Memory Controller kernel module
 *
 * Copyright (c) 2009 SoftwareBitMaker.
 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <linux/bitfield.h>
#include <asm/cpu_device_id.h>
#include <asm/msr.h>
#include "edac_module.h"
#include "mce_amd.h"

#define amd64_info(fmt, arg...) \
	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define amd64_warn(fmt, arg...) \
	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)

#define amd64_err(fmt, arg...) \
	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)

#define amd64_mc_warn(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_mc_err(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

/*
 * Throughout the comments in this code, the following terms are used:
 *
 *	SysAddr, DramAddr, and InputAddr
 *
 *  These terms come directly from the amd64 documentation
 * (AMD publication #26094).  They are defined as follows:
 *
 *     SysAddr:
 *         This is a physical address generated by a CPU core or a device
 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 *         a virtual to physical address translation by the CPU core's address
 *         translation mechanism (MMU).
 *
 *     DramAddr:
 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 *         depends on which node the SysAddr maps to and whether the SysAddr
 *         is within a range affected by memory hoisting.  The DRAM Base
 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 *         determine which node a SysAddr maps to.
 *
 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 *         is within the range of addresses specified by this register, then
 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 *         DramAddr.  Here, x represents the base address for the node that
 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 *         sys_addr_to_dram_addr() below for more information.
 *
 *         If the SysAddr is not affected by the DHAR then a value y is
 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 *         base address for the node that the SysAddr maps to.  See section
 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 *         information.
 *
 *     InputAddr:
 *         A DramAddr is translated to an InputAddr before being passed to the
 *         memory controller for the node that the DramAddr is associated
 *         with.  The memory controller then maps the InputAddr to a csrow.
 *         If node interleaving is not in use, then the InputAddr has the same
 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 *         discarding the bits used for node interleaving from the DramAddr.
 *         See section 3.4.4 for more information.
 *
 *         The memory controller for a given node uses its DRAM CS Base and
 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 *         sections 3.5.4 and 3.5.5 for more information.
 */

#define EDAC_MOD_STR			"amd64_edac"

/* Extended Model from CPUID, for CPU Revision numbers */
#define K8_REV_D			1
#define K8_REV_E			2
#define K8_REV_F			4

/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS			8
#define DRAM_RANGES			8
#define NUM_CONTROLLERS			12

#define ON true
#define OFF false

/*
 * PCI-defined configuration space registers
 */
#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582

/*
 * Function 1 - Address Map
 */
#define DRAM_BASE_LO			0x40
#define DRAM_LIMIT_LO			0x44

/*
 * F15 M30h D18F1x2[1C:00]
 */
#define DRAM_CONT_BASE			0x200
#define DRAM_CONT_LIMIT			0x204

/*
 * F15 M30h D18F1x2[4C:40]
 */
#define DRAM_CONT_HIGH_OFF		0x240

#define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
#define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
#define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))

#define DHAR				0xf0
#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)

					/* NOTE: Extra mask bit vs K8 */
#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)

#define DCT_CFG_SEL			0x10C

#define DRAM_LOCAL_NODE_BASE		0x120
#define DRAM_LOCAL_NODE_LIM		0x124

#define DRAM_BASE_HI			0x140
#define DRAM_LIMIT_HI			0x144


/*
 * Function 2 - DRAM controller
 */
#define DCSB0				0x40
#define DCSB1				0x140
#define DCSB_CS_ENABLE			BIT(0)

#define DCSM0				0x60
#define DCSM1				0x160

#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
#define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)

#define DRAM_CONTROL			0x78

#define DBAM0				0x80
#define DBAM1				0x180

/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg)		((((reg) >> (4*(i)))) & 0xF)

#define DBAM_MAX_VALUE			11

#define DCLR0				0x90
#define DCLR1				0x190
#define REVE_WIDTH_128			BIT(16)
#define WIDTH_128			BIT(11)

#define DCHR0				0x94
#define DCHR1				0x194
#define DDR3_MODE			BIT(8)

#define DCT_SEL_LO			0x110
#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))

#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))

#define SWAP_INTLV_REG			0x10c

#define DCT_SEL_HI			0x114

#define F15H_M60H_SCRCTRL		0x1C8

/*
 * Function 3 - Misc Control
 */
#define NBCTL				0x40

#define NBCFG				0x44
#define NBCFG_CHIPKILL			BIT(23)
#define NBCFG_ECC_ENABLE		BIT(22)

/* F3x48: NBSL */
#define F10_NBSL_EXT_ERR_ECC		0x8
#define NBSL_PP_OBS			0x2

#define SCRCTRL				0x58

#define F10_ONLINE_SPARE		0xB0
#define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
#define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

#define F10_NB_ARRAY_ADDR		0xB8
#define F10_NB_ARRAY_DRAM		BIT(31)

/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
#define SET_NB_ARRAY_ADDR(section)	(((section) & 0x3) << 1)

#define F10_NB_ARRAY_DATA		0xBC
#define F10_NB_ARR_ECC_WR_REQ		BIT(17)
#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
#define SET_NB_DRAM_INJECTION_READ(inj)  \
					(BIT(((inj.word) & 0xF) + 20) | \
					BIT(16) |  inj.bit_map)


#define NBCAP				0xE8
#define NBCAP_CHIPKILL			BIT(4)
#define NBCAP_SECDED			BIT(3)
#define NBCAP_DCT_DUAL			BIT(0)

#define EXT_NB_MCA_CFG			0x180

/* MSRs */
#define MSR_MCGCTL_NBE			BIT(4)

/* F17h */

/* F0: */
#define DF_DHAR				0x104

/* UMC CH register offsets */
#define UMCCH_BASE_ADDR			0x0
#define UMCCH_BASE_ADDR_SEC		0x10
#define UMCCH_ADDR_MASK			0x20
#define UMCCH_ADDR_MASK_SEC		0x28
#define UMCCH_ADDR_MASK_SEC_DDR5	0x30
#define UMCCH_ADDR_CFG			0x30
#define UMCCH_ADDR_CFG_DDR5		0x40
#define UMCCH_DIMM_CFG			0x80
#define UMCCH_DIMM_CFG_DDR5		0x90
#define UMCCH_UMC_CFG			0x100
#define UMCCH_SDP_CTRL			0x104
#define UMCCH_ECC_CTRL			0x14C
#define UMCCH_ECC_BAD_SYMBOL		0xD90
#define UMCCH_UMC_CAP			0xDF0
#define UMCCH_UMC_CAP_HI		0xDF4

/* UMC CH bitfields */
#define UMC_ECC_CHIPKILL_CAP		BIT(31)
#define UMC_ECC_ENABLED			BIT(30)

#define UMC_SDP_INIT			BIT(31)

/* Error injection control structure */
struct error_injection {
	u32	 section;
	u32	 word;
	u32	 bit_map;
};

/* low and high part of PCI config space regs */
struct reg_pair {
	u32 lo, hi;
};

/*
 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 */
struct dram_range {
	struct reg_pair base;
	struct reg_pair lim;
};

/* A DCT chip selects collection */
struct chip_select {
	u32 csbases[NUM_CHIPSELECTS];
	u32 csbases_sec[NUM_CHIPSELECTS];
	u8 b_cnt;

	u32 csmasks[NUM_CHIPSELECTS];
	u32 csmasks_sec[NUM_CHIPSELECTS];
	u8 m_cnt;
};

struct amd64_umc {
	u32 dimm_cfg;		/* DIMM Configuration reg */
	u32 umc_cfg;		/* Configuration reg */
	u32 sdp_ctrl;		/* SDP Control reg */
	u32 ecc_ctrl;		/* DRAM ECC Control reg */
	u32 umc_cap_hi;		/* Capabilities High reg */

	/* cache the dram_type */
	enum mem_type dram_type;
};

struct amd64_family_flags {
	/*
	 * Indicates that the system supports the new register offsets, etc.
	 * first introduced with Family 19h Model 10h.
	 */
	__u64 zn_regs_v2	: 1,

	      __reserved	: 63;
};

struct amd64_pvt {
	struct low_ops *ops;

	/* pci_device handles which we utilize */
	struct pci_dev *F1, *F2, *F3;

	u16 mc_node_id;		/* MC index of this MC node */
	u8 fam;			/* CPU family */
	u8 model;		/* ... model */
	u8 stepping;		/* ... stepping */

	int ext_model;		/* extended model value of this node */

	/* Raw registers */
	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
	u32 nbcap;		/* North Bridge Capabilities */
	u32 nbcfg;		/* F10 North Bridge Configuration */
	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
	u32 dhar;		/* DRAM Hoist reg */
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	/* one for each DCT/UMC */
	struct chip_select csels[NUM_CONTROLLERS];

	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
	struct dram_range ranges[DRAM_RANGES];

	u64 top_mem;		/* top of memory below 4GB */
	u64 top_mem2;		/* top of memory above 4GB */

	u32 dct_sel_lo;		/* DRAM Controller Select Low */
	u32 dct_sel_hi;		/* DRAM Controller Select High */
	u32 online_spare;	/* On-Line spare Reg */
	u32 gpu_umc_base;	/* Base address used for channel selection on GPUs */

	/* x4, x8, or x16 syndromes in use */
	u8 ecc_sym_sz;

	const char *ctl_name;
	u16 f1_id, f2_id;
	/* Maximum number of memory controllers per die/node. */
	u8 max_mcs;

	struct amd64_family_flags flags;
	/* place to store error injection parameters prior to issue */
	struct error_injection injection;

	/*
	 * cache the dram_type
	 *
	 * NOTE: Don't use this for Family 17h and later.
	 *	 Use dram_type in struct amd64_umc instead.
	 */
	enum mem_type dram_type;

	struct amd64_umc *umc;	/* UMC registers */
};

enum err_codes {
	DECODE_OK	=  0,
	ERR_NODE	= -1,
	ERR_CSROW	= -2,
	ERR_CHANNEL	= -3,
	ERR_SYND	= -4,
	ERR_NORM_ADDR	= -5,
};

struct err_info {
	int err_code;
	struct mem_ctl_info *src_mci;
	int csrow;
	int channel;
	u16 syndrome;
	u32 page;
	u32 offset;
};

static inline u32 get_umc_base(u8 channel)
{
	/* chY: 0xY50000 */
	return 0x50000 + (channel << 20);
}

static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
{
	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;

	if (boot_cpu_data.x86 == 0xf)
		return addr;

	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
}

static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
{
	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;

	if (boot_cpu_data.x86 == 0xf)
		return lim;

	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
}

static inline u16 extract_syndrome(u64 status)
{
	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
}

static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30)
		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
			((pvt->dct_sel_lo >> 6) & 0x3);

	return	((pvt)->dct_sel_lo >> 6) & 0x3;
}
/*
 * per-node ECC settings descriptor
 */
struct ecc_settings {
	u32 old_nbctl;
	bool nbctl_valid;

	struct flags {
		unsigned long nb_mce_enable:1;
		unsigned long nb_ecc_prev:1;
	} flags;
};

/*
 * Each of the PCI Device IDs types have their own set of hardware accessor
 * functions and per device encoding/decoding logic.
 */
struct low_ops {
	void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, u64 sys_addr,
				     struct err_info *err);
	int  (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
			   unsigned int cs_mode, int cs_mask_nr);
	int (*hw_info_get)(struct amd64_pvt *pvt);
	bool (*ecc_enabled)(struct amd64_pvt *pvt);
	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
	void (*dump_misc_regs)(struct amd64_pvt *pvt);
	void (*get_err_info)(struct mce *m, struct err_info *err);
};

int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func);
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func);

#define amd64_read_pci_cfg(pdev, offset, val)	\
	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_write_pci_cfg(pdev, offset, val)	\
	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

/* Injection helpers */
static inline void disable_caches(void *dummy)
{
	write_cr0(read_cr0() | X86_CR0_CD);
	wbinvd();
}

static inline void enable_caches(void *dummy)
{
	write_cr0(read_cr0() & ~X86_CR0_CD);
}

static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
		return (u8) tmp & 0xF;
	}
	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
}

static inline u8 dhar_valid(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 1) & BIT(0);
	}
	return (pvt)->dhar & BIT(0);
}

static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
{
	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		u32 tmp;
		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
		return (tmp >> 11) & 0x1FFF;
	}
	return (pvt)->dct_sel_lo & 0xFFFFF800;
}
Commit	Line	Data
cfe40fdb DT	1	/*
	2	* AMD64 class Memory Controller kernel module
	3	*
	4	* Copyright (c) 2009 SoftwareBitMaker.
1a8bc770	5	* Copyright (c) 2009-15 Advanced Micro Devices, Inc.
cfe40fdb DT	6	*
	7	* This file may be distributed under the terms of the
	8	* GNU General Public License.
cfe40fdb DT	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/ctype.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
	16	#include <linux/slab.h>
	17	#include <linux/mmzone.h>
	18	#include <linux/edac.h>
4251566e	19	#include <linux/bitfield.h>
1bd9900b	20	#include <asm/cpu_device_id.h>
f9431992	21	#include <asm/msr.h>
78d88e8a	22	#include "edac_module.h"
47ca08a4	23	#include "mce_amd.h"
cfe40fdb	24
24f9a7fe BP	25	#define amd64_info(fmt, arg...) \
	26	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
	27
24f9a7fe	28	#define amd64_warn(fmt, arg...) \
5246c540	29	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
24f9a7fe BP	30
24f9a7fe BP	31	#define amd64_err(fmt, arg...) \
5246c540	32	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
24f9a7fe BP	33
	34	#define amd64_mc_warn(mci, fmt, arg...) \
	35	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
	36
	37	#define amd64_mc_err(mci, fmt, arg...) \
	38	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
cfe40fdb DT	39
	40	/*
	41	* Throughout the comments in this code, the following terms are used:
	42	*
	43	* SysAddr, DramAddr, and InputAddr
	44	*
	45	* These terms come directly from the amd64 documentation
	46	* (AMD publication #26094). They are defined as follows:
	47	*
	48	* SysAddr:
	49	* This is a physical address generated by a CPU core or a device
	50	* doing DMA. If generated by a CPU core, a SysAddr is the result of
	51	* a virtual to physical address translation by the CPU core's address
	52	* translation mechanism (MMU).
	53	*
	54	* DramAddr:
	55	* A DramAddr is derived from a SysAddr by subtracting an offset that
	56	* depends on which node the SysAddr maps to and whether the SysAddr
	57	* is within a range affected by memory hoisting. The DRAM Base
	58	* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
	59	* determine which node a SysAddr maps to.
	60	*
	61	* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
	62	* is within the range of addresses specified by this register, then
	63	* a value x from the DHAR is subtracted from the SysAddr to produce a
	64	* DramAddr. Here, x represents the base address for the node that
	65	* the SysAddr maps to plus an offset due to memory hoisting. See
	66	* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
	67	* sys_addr_to_dram_addr() below for more information.
	68	*
	69	* If the SysAddr is not affected by the DHAR then a value y is
	70	* subtracted from the SysAddr to produce a DramAddr. Here, y is the
	71	* base address for the node that the SysAddr maps to. See section
	72	* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
	73	* information.
	74	*
	75	* InputAddr:
	76	* A DramAddr is translated to an InputAddr before being passed to the
	77	* memory controller for the node that the DramAddr is associated
	78	* with. The memory controller then maps the InputAddr to a csrow.
	79	* If node interleaving is not in use, then the InputAddr has the same
	80	* value as the DramAddr. Otherwise, the InputAddr is produced by
	81	* discarding the bits used for node interleaving from the DramAddr.
	82	* See section 3.4.4 for more information.
	83	*
	84	* The memory controller for a given node uses its DRAM CS Base and
	85	* DRAM CS Mask registers to map an InputAddr to a csrow. See
	86	* sections 3.5.4 and 3.5.5 for more information.
	87	*/
	88
cfe40fdb DT	89	#define EDAC_MOD_STR "amd64_edac"
	90
	91	/* Extended Model from CPUID, for CPU Revision numbers */
1433eb99 BP	92	#define K8_REV_D 1
	93	#define K8_REV_E 2
	94	#define K8_REV_F 4
cfe40fdb DT	95
cfe40fdb DT	96	/* Hardware limit on ChipSelect rows per MC and processors per system */
7f19bf75 BP	97	#define NUM_CHIPSELECTS 8
7f19bf75 BP	98	#define DRAM_RANGES 8
e2be5955	99	#define NUM_CONTROLLERS 12
cfe40fdb	100
f6d6ae96 BP	101	#define ON true
f6d6ae96 BP	102	#define OFF false
cfe40fdb DT	103
	104	/*
	105	* PCI-defined configuration space registers
	106	*/
df71a053 BP	107	#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
df71a053 BP	108	#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
a597d2a5 AG	109	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
	110	#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
	111	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
	112	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
94c1acf2 AG	113	#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
94c1acf2 AG	114	#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
85a8885b AG	115	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
85a8885b AG	116	#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
cfe40fdb DT	117
	118	/*
	119	* Function 1 - Address Map
	120	*/
7f19bf75 BP	121	#define DRAM_BASE_LO 0x40
	122	#define DRAM_LIMIT_LO 0x44
	123
18b94f66 AG	124	/*
	125	* F15 M30h D18F1x2[1C:00]
	126	*/
	127	#define DRAM_CONT_BASE 0x200
	128	#define DRAM_CONT_LIMIT 0x204
	129
	130	/*
	131	* F15 M30h D18F1x2[4C:40]
	132	*/
	133	#define DRAM_CONT_HIGH_OFF 0x240
	134
151fa71c BP	135	#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
	136	#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
	137	#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
7f19bf75	138
bc21fa57	139	#define DHAR 0xf0
c8e518d5 BP	140	#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
	141	#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
	142	#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
cfe40fdb	143
cfe40fdb	144	/* NOTE: Extra mask bit vs K8 */
c8e518d5	145	#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
cfe40fdb	146
b2b0c605	147	#define DCT_CFG_SEL 0x10C
cfe40fdb	148
c1ae6830	149	#define DRAM_LOCAL_NODE_BASE 0x120
f08e457c BP	150	#define DRAM_LOCAL_NODE_LIM 0x124
f08e457c BP	151
7f19bf75 BP	152	#define DRAM_BASE_HI 0x140
7f19bf75 BP	153	#define DRAM_LIMIT_HI 0x144
cfe40fdb DT	154
	155
	156	/*
	157	* Function 2 - DRAM controller
	158	*/
11c75ead BP	159	#define DCSB0 0x40
	160	#define DCSB1 0x140
	161	#define DCSB_CS_ENABLE BIT(0)
cfe40fdb	162
11c75ead BP	163	#define DCSM0 0x60
11c75ead BP	164	#define DCSM1 0x160
cfe40fdb	165
81f5090d YG	166	#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
81f5090d YG	167	#define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
cfe40fdb	168
a597d2a5 AG	169	#define DRAM_CONTROL 0x78
a597d2a5 AG	170
cfe40fdb DT	171	#define DBAM0 0x80
	172	#define DBAM1 0x180
	173
	174	/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
0a5dfc31	175	#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
cfe40fdb DT	176
	177	#define DBAM_MAX_VALUE 11
	178
cb328507 BP	179	#define DCLR0 0x90
cb328507 BP	180	#define DCLR1 0x190
cfe40fdb	181	#define REVE_WIDTH_128 BIT(16)
41d8bfab	182	#define WIDTH_128 BIT(11)
cfe40fdb	183
cb328507 BP	184	#define DCHR0 0x94
cb328507 BP	185	#define DCHR1 0x194
1433eb99	186	#define DDR3_MODE BIT(8)
cfe40fdb	187
78da121e	188	#define DCT_SEL_LO 0x110
78da121e BP	189	#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
78da121e BP	190	#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
cb328507	191
78da121e	192	#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
cb328507	193
78da121e	194	#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
78da121e	195	#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
cfe40fdb	196
95b0ef55 BP	197	#define SWAP_INTLV_REG 0x10c
95b0ef55 BP	198
78da121e	199	#define DCT_SEL_HI 0x114
cfe40fdb	200
da92110d AG	201	#define F15H_M60H_SCRCTRL 0x1C8
da92110d AG	202
cfe40fdb DT	203	/*
	204	* Function 3 - Misc Control
	205	*/
c9f4f26e	206	#define NBCTL 0x40
cfe40fdb	207
a97fa68e BP	208	#define NBCFG 0x44
	209	#define NBCFG_CHIPKILL BIT(23)
	210	#define NBCFG_ECC_ENABLE BIT(22)
cfe40fdb	211
5980bb9c	212	/* F3x48: NBSL */
cfe40fdb	213	#define F10_NBSL_EXT_ERR_ECC 0x8
5980bb9c	214	#define NBSL_PP_OBS 0x2
cfe40fdb	215
5980bb9c	216	#define SCRCTRL 0x58
cfe40fdb DT	217
cfe40fdb DT	218	#define F10_ONLINE_SPARE 0xB0
614ec9d8 BP	219	#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
614ec9d8 BP	220	#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
cfe40fdb DT	221
cfe40fdb DT	222	#define F10_NB_ARRAY_ADDR 0xB8
6e71a870	223	#define F10_NB_ARRAY_DRAM BIT(31)
cfe40fdb DT	224
cfe40fdb DT	225	/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
6e71a870	226	#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
cfe40fdb DT	227
cfe40fdb DT	228	#define F10_NB_ARRAY_DATA 0xBC
66fed2d4	229	#define F10_NB_ARR_ECC_WR_REQ BIT(17)
6e71a870 BP	230	#define SET_NB_DRAM_INJECTION_WRITE(inj) \
6e71a870 BP	231	(BIT(((inj.word) & 0xF) + 20) \| \
66fed2d4	232	F10_NB_ARR_ECC_WR_REQ \| inj.bit_map)
6e71a870 BP	233	#define SET_NB_DRAM_INJECTION_READ(inj) \
	234	(BIT(((inj.word) & 0xF) + 20) \| \
	235	BIT(16) \| inj.bit_map)
	236
cfe40fdb	237
5980bb9c BP	238	#define NBCAP 0xE8
	239	#define NBCAP_CHIPKILL BIT(4)
	240	#define NBCAP_SECDED BIT(3)
	241	#define NBCAP_DCT_DUAL BIT(0)
cfe40fdb	242
ad6a32e9 BP	243	#define EXT_NB_MCA_CFG 0x180
ad6a32e9 BP	244
f6d6ae96	245	/* MSRs */
5980bb9c	246	#define MSR_MCGCTL_NBE BIT(4)
cfe40fdb	247
b64ce7cd YG	248	/* F17h */
	249
	250	/* F0: */
	251	#define DF_DHAR 0x104
	252
196b79fc	253	/* UMC CH register offsets */
b64ce7cd	254	#define UMCCH_BASE_ADDR 0x0
7574729e	255	#define UMCCH_BASE_ADDR_SEC 0x10
b64ce7cd	256	#define UMCCH_ADDR_MASK 0x20
7574729e	257	#define UMCCH_ADDR_MASK_SEC 0x28
2151c84e	258	#define UMCCH_ADDR_MASK_SEC_DDR5 0x30
07ed82ef	259	#define UMCCH_ADDR_CFG 0x30
2151c84e	260	#define UMCCH_ADDR_CFG_DDR5 0x40
b64ce7cd	261	#define UMCCH_DIMM_CFG 0x80
2151c84e	262	#define UMCCH_DIMM_CFG_DDR5 0x90
07ed82ef	263	#define UMCCH_UMC_CFG 0x100
196b79fc	264	#define UMCCH_SDP_CTRL 0x104
b64ce7cd	265	#define UMCCH_ECC_CTRL 0x14C
07ed82ef YG	266	#define UMCCH_ECC_BAD_SYMBOL 0xD90
07ed82ef YG	267	#define UMCCH_UMC_CAP 0xDF0
196b79fc YG	268	#define UMCCH_UMC_CAP_HI 0xDF4
	269
	270	/* UMC CH bitfields */
b64ce7cd	271	#define UMC_ECC_CHIPKILL_CAP BIT(31)
196b79fc	272	#define UMC_ECC_ENABLED BIT(30)
b64ce7cd	273
196b79fc YG	274	#define UMC_SDP_INIT BIT(31)
196b79fc YG	275
cfe40fdb DT	276	/* Error injection control structure */
cfe40fdb DT	277	struct error_injection {
66fed2d4 BP	278	u32 section;
	279	u32 word;
	280	u32 bit_map;
cfe40fdb DT	281	};
cfe40fdb DT	282
7f19bf75 BP	283	/* low and high part of PCI config space regs */
	284	struct reg_pair {
	285	u32 lo, hi;
	286	};
	287
	288	/*
	289	* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
	290	*/
	291	struct dram_range {
	292	struct reg_pair base;
	293	struct reg_pair lim;
	294	};
	295
11c75ead BP	296	/* A DCT chip selects collection */
	297	struct chip_select {
	298	u32 csbases[NUM_CHIPSELECTS];
7574729e	299	u32 csbases_sec[NUM_CHIPSELECTS];
11c75ead BP	300	u8 b_cnt;
	301
	302	u32 csmasks[NUM_CHIPSELECTS];
7574729e	303	u32 csmasks_sec[NUM_CHIPSELECTS];
11c75ead BP	304	u8 m_cnt;
	305	};
	306
f1cbbec9	307	struct amd64_umc {
b64ce7cd	308	u32 dimm_cfg; /* DIMM Configuration reg */
07ed82ef	309	u32 umc_cfg; /* Configuration reg */
f1cbbec9	310	u32 sdp_ctrl; /* SDP Control reg */
b64ce7cd	311	u32 ecc_ctrl; /* DRAM ECC Control reg */
07ed82ef	312	u32 umc_cap_hi; /* Capabilities High reg */
75aeaaf2 YG	313
	314	/* cache the dram_type */
	315	enum mem_type dram_type;
f1cbbec9 YG	316	};
f1cbbec9 YG	317
ed623d55 M	318	struct amd64_family_flags {
	319	/*
	320	* Indicates that the system supports the new register offsets, etc.
	321	* first introduced with Family 19h Model 10h.
	322	*/
	323	__u64 zn_regs_v2 : 1,
	324
	325	__reserved : 63;
	326	};
	327
cfe40fdb	328	struct amd64_pvt {
b8cfa02f BP	329	struct low_ops *ops;
b8cfa02f BP	330
cfe40fdb	331	/* pci_device handles which we utilize */
cf981562	332	struct pci_dev F1, F2, *F3;
cfe40fdb	333
c7e5301a	334	u16 mc_node_id; /* MC index of this MC node */
18b94f66	335	u8 fam; /* CPU family */
a4b4bedc BP	336	u8 model; /* ... model */
	337	u8 stepping; /* ... stepping */
	338
cfe40fdb	339	int ext_model; /* extended model value of this node */
cfe40fdb DT	340
	341	/* Raw registers */
	342	u32 dclr0; /* DRAM Configuration Low DCT0 reg */
	343	u32 dclr1; /* DRAM Configuration Low DCT1 reg */
	344	u32 dchr0; /* DRAM Configuration High DCT0 reg */
	345	u32 dchr1; /* DRAM Configuration High DCT1 reg */
	346	u32 nbcap; /* North Bridge Capabilities */
	347	u32 nbcfg; /* F10 North Bridge Configuration */
	348	u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
	349	u32 dhar; /* DRAM Hoist reg */
	350	u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
	351	u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
	352
d971e28e YG	353	/* one for each DCT/UMC */
d971e28e YG	354	struct chip_select csels[NUM_CONTROLLERS];
cfe40fdb	355
7f19bf75 BP	356	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
7f19bf75 BP	357	struct dram_range ranges[DRAM_RANGES];
cfe40fdb	358
cfe40fdb DT	359	u64 top_mem; /* top of memory below 4GB */
	360	u64 top_mem2; /* top of memory above 4GB */
	361
78da121e BP	362	u32 dct_sel_lo; /* DRAM Controller Select Low */
78da121e BP	363	u32 dct_sel_hi; /* DRAM Controller Select High */
b2b0c605	364	u32 online_spare; /* On-Line spare Reg */
12f230c0	365	u32 gpu_umc_base; /* Base address used for channel selection on GPUs */
cfe40fdb	366
7835961d	367	/* x4, x8, or x16 syndromes in use */
a3b7db09	368	u8 ecc_sym_sz;
ad6a32e9	369
ed623d55 M	370	const char *ctl_name;
	371	u16 f1_id, f2_id;
	372	/* Maximum number of memory controllers per die/node. */
	373	u8 max_mcs;
	374
	375	struct amd64_family_flags flags;
cfe40fdb DT	376	/* place to store error injection parameters prior to issue */
cfe40fdb DT	377	struct error_injection injection;
a597d2a5	378
75aeaaf2 YG	379	/*
	380	* cache the dram_type
	381	*
	382	* NOTE: Don't use this for Family 17h and later.
	383	* Use dram_type in struct amd64_umc instead.
	384	*/
a597d2a5	385	enum mem_type dram_type;
f1cbbec9 YG	386
f1cbbec9 YG	387	struct amd64_umc umc; / UMC registers */
ae7bb7c6 BP	388	};
ae7bb7c6 BP	389
33ca0643 BP	390	enum err_codes {
	391	DECODE_OK = 0,
	392	ERR_NODE = -1,
	393	ERR_CSROW = -2,
	394	ERR_CHANNEL = -3,
713ad546 YG	395	ERR_SYND = -4,
713ad546 YG	396	ERR_NORM_ADDR = -5,
33ca0643 BP	397	};
	398
	399	struct err_info {
	400	int err_code;
	401	struct mem_ctl_info *src_mci;
	402	int csrow;
	403	int channel;
	404	u16 syndrome;
	405	u32 page;
	406	u32 offset;
	407	};
	408
196b79fc YG	409	static inline u32 get_umc_base(u8 channel)
196b79fc YG	410	{
bdcee774 YG	411	/* chY: 0xY50000 */
bdcee774 YG	412	return 0x50000 + (channel << 20);
196b79fc YG	413	}
196b79fc YG	414
c7e5301a	415	static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	416	{
	417	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
	418
	419	if (boot_cpu_data.x86 == 0xf)
	420	return addr;
	421
	422	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) \| addr;
	423	}
	424
c7e5301a	425	static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
7f19bf75 BP	426	{
	427	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) \| 0x00ffffff;
	428
	429	if (boot_cpu_data.x86 == 0xf)
	430	return lim;
	431
	432	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) \| lim;
	433	}
	434
f192c7b1 BP	435	static inline u16 extract_syndrome(u64 status)
	436	{
	437	return ((status >> 47) & 0xff) \| ((status >> 16) & 0xff00);
	438	}
	439
18b94f66 AG	440	static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
	441	{
	442	if (pvt->fam == 0x15 && pvt->model >= 0x30)
	443	return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) \|
	444	((pvt->dct_sel_lo >> 6) & 0x3);
	445
	446	return ((pvt)->dct_sel_lo >> 6) & 0x3;
	447	}
ae7bb7c6 BP	448	/*
	449	* per-node ECC settings descriptor
	450	*/
	451	struct ecc_settings {
	452	u32 old_nbctl;
	453	bool nbctl_valid;
	454
cfe40fdb	455	struct flags {
d95cf4de BP	456	unsigned long nb_mce_enable:1;
d95cf4de BP	457	unsigned long nb_ecc_prev:1;
cfe40fdb DT	458	} flags;
	459	};
	460
cfe40fdb DT	461	/*
	462	* Each of the PCI Device IDs types have their own set of hardware accessor
	463	* functions and per device encoding/decoding logic.
	464	*/
	465	struct low_ops {
ed623d55 M	466	void (map_sysaddr_to_csrow)(struct mem_ctl_info mci, u64 sys_addr,
	467	struct err_info *err);
	468	int (dbam_to_cs)(struct amd64_pvt pvt, u8 dct,
	469	unsigned int cs_mode, int cs_mask_nr);
9a97a7f4	470	int (hw_info_get)(struct amd64_pvt pvt);
eb2bcdfc	471	bool (ecc_enabled)(struct amd64_pvt pvt);
0a42a37f	472	void (setup_mci_misc_attrs)(struct mem_ctl_info mci);
f6f36382	473	void (dump_misc_regs)(struct amd64_pvt pvt);
b3ece3a6	474	void (get_err_info)(struct mce m, struct err_info *err);
cfe40fdb DT	475	};
cfe40fdb DT	476
66fed2d4 BP	477	int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
66fed2d4 BP	478	u32 val, const char func);
b2b0c605 BP	479	int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
b2b0c605 BP	480	u32 val, const char *func);
6ba5dcdc	481
b2b0c605 BP	482	#define amd64_read_pci_cfg(pdev, offset, val) \
b2b0c605 BP	483	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	484
b2b0c605 BP	485	#define amd64_write_pci_cfg(pdev, offset, val) \
b2b0c605 BP	486	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	487
c5608759	488	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
66fed2d4 BP	489
	490	/* Injection helpers */
	491	static inline void disable_caches(void *dummy)
	492	{
	493	write_cr0(read_cr0() \| X86_CR0_CD);
	494	wbinvd();
	495	}
	496
	497	static inline void enable_caches(void *dummy)
	498	{
	499	write_cr0(read_cr0() & ~X86_CR0_CD);
	500	}
18b94f66 AG	501
	502	static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
	503	{
	504	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	505	u32 tmp;
	506	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
	507	return (u8) tmp & 0xF;
	508	}
	509	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
	510	}
	511
	512	static inline u8 dhar_valid(struct amd64_pvt *pvt)
	513	{
	514	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	515	u32 tmp;
	516	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	517	return (tmp >> 1) & BIT(0);
	518	}
	519	return (pvt)->dhar & BIT(0);
	520	}
	521
	522	static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
	523	{
	524	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
	525	u32 tmp;
	526	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
	527	return (tmp >> 11) & 0x1FFF;
	528	}
	529	return (pvt)->dct_sel_lo & 0xFFFFF800;
	530	}