Commit | Line | Data |
---|---|---|
09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2bc65418 | 2 | #include "amd64_edac.h" |
23ac4ae8 | 3 | #include <asm/amd_nb.h> |
2bc65418 | 4 | |
d1ea71cd | 5 | static struct edac_pci_ctl_info *pci_ctl; |
2bc65418 | 6 | |
2bc65418 DT |
7 | /* |
8 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
9 | * cleared to prevent re-enabling the hardware by this driver. | |
10 | */ | |
11 | static int ecc_enable_override; | |
12 | module_param(ecc_enable_override, int, 0644); | |
13 | ||
a29d8b8e | 14 | static struct msr __percpu *msrs; |
50542251 | 15 | |
ed623d55 | 16 | static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg) |
2151c84e | 17 | { |
ed623d55 | 18 | if (!pvt->flags.zn_regs_v2) |
2151c84e YG |
19 | return reg; |
20 | ||
21 | switch (reg) { | |
22 | case UMCCH_ADDR_CFG: return UMCCH_ADDR_CFG_DDR5; | |
23 | case UMCCH_ADDR_MASK_SEC: return UMCCH_ADDR_MASK_SEC_DDR5; | |
24 | case UMCCH_DIMM_CFG: return UMCCH_DIMM_CFG_DDR5; | |
25 | } | |
26 | ||
27 | WARN_ONCE(1, "%s: unknown register 0x%x", __func__, reg); | |
28 | return 0; | |
29 | } | |
30 | ||
2ec591ac | 31 | /* Per-node stuff */ |
ae7bb7c6 | 32 | static struct ecc_settings **ecc_stngs; |
2bc65418 | 33 | |
706657b1 BP |
34 | /* Device for the PCI component */ |
35 | static struct device *pci_ctl_dev; | |
36 | ||
b70ef010 BP |
37 | /* |
38 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
39 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
40 | * or higher value'. | |
41 | * | |
42 | *FIXME: Produce a better mapping/linearisation. | |
43 | */ | |
c7e5301a | 44 | static const struct scrubrate { |
39094443 BP |
45 | u32 scrubval; /* bit pattern for scrub rate */ |
46 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
47 | } scrubrates[] = { | |
b70ef010 BP |
48 | { 0x01, 1600000000UL}, |
49 | { 0x02, 800000000UL}, | |
50 | { 0x03, 400000000UL}, | |
51 | { 0x04, 200000000UL}, | |
52 | { 0x05, 100000000UL}, | |
53 | { 0x06, 50000000UL}, | |
54 | { 0x07, 25000000UL}, | |
55 | { 0x08, 12284069UL}, | |
56 | { 0x09, 6274509UL}, | |
57 | { 0x0A, 3121951UL}, | |
58 | { 0x0B, 1560975UL}, | |
59 | { 0x0C, 781440UL}, | |
60 | { 0x0D, 390720UL}, | |
61 | { 0x0E, 195300UL}, | |
62 | { 0x0F, 97650UL}, | |
63 | { 0x10, 48854UL}, | |
64 | { 0x11, 24427UL}, | |
65 | { 0x12, 12213UL}, | |
66 | { 0x13, 6101UL}, | |
67 | { 0x14, 3051UL}, | |
68 | { 0x15, 1523UL}, | |
69 | { 0x16, 761UL}, | |
70 | { 0x00, 0UL}, /* scrubbing off */ | |
71 | }; | |
72 | ||
66fed2d4 BP |
73 | int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
74 | u32 *val, const char *func) | |
b2b0c605 BP |
75 | { |
76 | int err = 0; | |
77 | ||
78 | err = pci_read_config_dword(pdev, offset, val); | |
79 | if (err) | |
80 | amd64_warn("%s: error reading F%dx%03x.\n", | |
81 | func, PCI_FUNC(pdev->devfn), offset); | |
82 | ||
83 | return err; | |
84 | } | |
85 | ||
86 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
87 | u32 val, const char *func) | |
88 | { | |
89 | int err = 0; | |
90 | ||
91 | err = pci_write_config_dword(pdev, offset, val); | |
92 | if (err) | |
93 | amd64_warn("%s: error writing to F%dx%03x.\n", | |
94 | func, PCI_FUNC(pdev->devfn), offset); | |
95 | ||
96 | return err; | |
97 | } | |
98 | ||
7981a28f AG |
99 | /* |
100 | * Select DCT to which PCI cfg accesses are routed | |
101 | */ | |
102 | static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) | |
103 | { | |
104 | u32 reg = 0; | |
105 | ||
106 | amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); | |
107 | reg &= (pvt->model == 0x30) ? ~3 : ~1; | |
108 | reg |= dct; | |
109 | amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); | |
110 | } | |
111 | ||
b2b0c605 BP |
112 | /* |
113 | * | |
114 | * Depending on the family, F2 DCT reads need special handling: | |
115 | * | |
7981a28f | 116 | * K8: has a single DCT only and no address offsets >= 0x100 |
b2b0c605 BP |
117 | * |
118 | * F10h: each DCT has its own set of regs | |
119 | * DCT0 -> F2x040.. | |
120 | * DCT1 -> F2x140.. | |
121 | * | |
94c1acf2 | 122 | * F16h: has only 1 DCT |
7981a28f AG |
123 | * |
124 | * F15h: we select which DCT we access using F1x10C[DctCfgSel] | |
b2b0c605 | 125 | */ |
7981a28f AG |
126 | static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, |
127 | int offset, u32 *val) | |
b2b0c605 | 128 | { |
7981a28f AG |
129 | switch (pvt->fam) { |
130 | case 0xf: | |
131 | if (dct || offset >= 0x100) | |
132 | return -EINVAL; | |
133 | break; | |
b2b0c605 | 134 | |
7981a28f AG |
135 | case 0x10: |
136 | if (dct) { | |
137 | /* | |
138 | * Note: If ganging is enabled, barring the regs | |
139 | * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx | |
140 | * return 0. (cf. Section 2.8.1 F10h BKDG) | |
141 | */ | |
142 | if (dct_ganging_enabled(pvt)) | |
143 | return 0; | |
b2b0c605 | 144 | |
7981a28f AG |
145 | offset += 0x100; |
146 | } | |
147 | break; | |
73ba8593 | 148 | |
7981a28f AG |
149 | case 0x15: |
150 | /* | |
151 | * F15h: F2x1xx addresses do not map explicitly to DCT1. | |
152 | * We should select which DCT we access using F1x10C[DctCfgSel] | |
153 | */ | |
154 | dct = (dct && pvt->model == 0x30) ? 3 : dct; | |
155 | f15h_select_dct(pvt, dct); | |
156 | break; | |
73ba8593 | 157 | |
7981a28f AG |
158 | case 0x16: |
159 | if (dct) | |
160 | return -EINVAL; | |
161 | break; | |
b2b0c605 | 162 | |
7981a28f AG |
163 | default: |
164 | break; | |
b2b0c605 | 165 | } |
7981a28f | 166 | return amd64_read_pci_cfg(pvt->F2, offset, val); |
b2b0c605 BP |
167 | } |
168 | ||
2bc65418 DT |
169 | /* |
170 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
171 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
172 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
173 | * functionality. | |
174 | * | |
175 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
176 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
177 | * bytes/sec for the setting. | |
178 | * | |
179 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
180 | * other archs, we might not have access to the caches directly. | |
181 | */ | |
182 | ||
183 | /* | |
8051c0af | 184 | * Scan the scrub rate mapping table for a close or matching bandwidth value to |
2bc65418 DT |
185 | * issue. If requested is too big, then use last maximum value found. |
186 | */ | |
da92110d | 187 | static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) |
2bc65418 DT |
188 | { |
189 | u32 scrubval; | |
190 | int i; | |
191 | ||
192 | /* | |
193 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
194 | * memory controller and apply to register. Search for the first | |
195 | * bandwidth entry that is greater or equal than the setting requested | |
196 | * and program that. If at last entry, turn off DRAM scrubbing. | |
168bfeef AM |
197 | * |
198 | * If no suitable bandwidth is found, turn off DRAM scrubbing entirely | |
199 | * by falling back to the last element in scrubrates[]. | |
2bc65418 | 200 | */ |
168bfeef | 201 | for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { |
2bc65418 DT |
202 | /* |
203 | * skip scrub rates which aren't recommended | |
204 | * (see F10 BKDG, F3x58) | |
205 | */ | |
395ae783 | 206 | if (scrubrates[i].scrubval < min_rate) |
2bc65418 DT |
207 | continue; |
208 | ||
209 | if (scrubrates[i].bandwidth <= new_bw) | |
210 | break; | |
2bc65418 DT |
211 | } |
212 | ||
213 | scrubval = scrubrates[i].scrubval; | |
2bc65418 | 214 | |
6e241bc9 | 215 | if (pvt->fam == 0x15 && pvt->model == 0x60) { |
da92110d AG |
216 | f15h_select_dct(pvt, 0); |
217 | pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); | |
218 | f15h_select_dct(pvt, 1); | |
219 | pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); | |
220 | } else { | |
221 | pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); | |
222 | } | |
2bc65418 | 223 | |
39094443 BP |
224 | if (scrubval) |
225 | return scrubrates[i].bandwidth; | |
226 | ||
2bc65418 DT |
227 | return 0; |
228 | } | |
229 | ||
d1ea71cd | 230 | static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw) |
2bc65418 DT |
231 | { |
232 | struct amd64_pvt *pvt = mci->pvt_info; | |
87b3e0e6 | 233 | u32 min_scrubrate = 0x5; |
2bc65418 | 234 | |
a4b4bedc | 235 | if (pvt->fam == 0xf) |
87b3e0e6 BP |
236 | min_scrubrate = 0x0; |
237 | ||
da92110d AG |
238 | if (pvt->fam == 0x15) { |
239 | /* Erratum #505 */ | |
240 | if (pvt->model < 0x10) | |
241 | f15h_select_dct(pvt, 0); | |
73ba8593 | 242 | |
da92110d AG |
243 | if (pvt->model == 0x60) |
244 | min_scrubrate = 0x6; | |
245 | } | |
246 | return __set_scrub_rate(pvt, bw, min_scrubrate); | |
2bc65418 DT |
247 | } |
248 | ||
d1ea71cd | 249 | static int get_scrub_rate(struct mem_ctl_info *mci) |
2bc65418 DT |
250 | { |
251 | struct amd64_pvt *pvt = mci->pvt_info; | |
39094443 | 252 | int i, retval = -EINVAL; |
8051c0af | 253 | u32 scrubval = 0; |
2bc65418 | 254 | |
6e241bc9 | 255 | if (pvt->fam == 0x15) { |
dcd01394 YG |
256 | /* Erratum #505 */ |
257 | if (pvt->model < 0x10) | |
258 | f15h_select_dct(pvt, 0); | |
8051c0af | 259 | |
dcd01394 YG |
260 | if (pvt->model == 0x60) |
261 | amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); | |
ee470bb2 BP |
262 | else |
263 | amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); | |
dcd01394 | 264 | } else { |
da92110d | 265 | amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); |
8051c0af | 266 | } |
2bc65418 DT |
267 | |
268 | scrubval = scrubval & 0x001F; | |
269 | ||
926311fd | 270 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { |
2bc65418 | 271 | if (scrubrates[i].scrubval == scrubval) { |
39094443 | 272 | retval = scrubrates[i].bandwidth; |
2bc65418 DT |
273 | break; |
274 | } | |
275 | } | |
39094443 | 276 | return retval; |
2bc65418 DT |
277 | } |
278 | ||
6775763a | 279 | /* |
7f19bf75 BP |
280 | * returns true if the SysAddr given by sys_addr matches the |
281 | * DRAM base/limit associated with node_id | |
6775763a | 282 | */ |
d1ea71cd | 283 | static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) |
6775763a | 284 | { |
7f19bf75 | 285 | u64 addr; |
6775763a DT |
286 | |
287 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
288 | * all ones if the most significant implemented address bit is 1. | |
289 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
290 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
291 | * Application Programming. | |
292 | */ | |
293 | addr = sys_addr & 0x000000ffffffffffull; | |
294 | ||
7f19bf75 BP |
295 | return ((addr >= get_dram_base(pvt, nid)) && |
296 | (addr <= get_dram_limit(pvt, nid))); | |
6775763a DT |
297 | } |
298 | ||
299 | /* | |
300 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
301 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
302 | * | |
303 | * On failure, return NULL. | |
304 | */ | |
305 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
306 | u64 sys_addr) | |
307 | { | |
308 | struct amd64_pvt *pvt; | |
c7e5301a | 309 | u8 node_id; |
6775763a DT |
310 | u32 intlv_en, bits; |
311 | ||
312 | /* | |
313 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
314 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
315 | */ | |
316 | pvt = mci->pvt_info; | |
317 | ||
318 | /* | |
319 | * The value of this field should be the same for all DRAM Base | |
320 | * registers. Therefore we arbitrarily choose to read it from the | |
321 | * register for node 0. | |
322 | */ | |
7f19bf75 | 323 | intlv_en = dram_intlv_en(pvt, 0); |
6775763a DT |
324 | |
325 | if (intlv_en == 0) { | |
7f19bf75 | 326 | for (node_id = 0; node_id < DRAM_RANGES; node_id++) { |
d1ea71cd | 327 | if (base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 328 | goto found; |
6775763a | 329 | } |
8edc5445 | 330 | goto err_no_match; |
6775763a DT |
331 | } |
332 | ||
72f158fe BP |
333 | if (unlikely((intlv_en != 0x01) && |
334 | (intlv_en != 0x03) && | |
335 | (intlv_en != 0x07))) { | |
24f9a7fe | 336 | amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en); |
6775763a DT |
337 | return NULL; |
338 | } | |
339 | ||
340 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
341 | ||
342 | for (node_id = 0; ; ) { | |
7f19bf75 | 343 | if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) |
6775763a DT |
344 | break; /* intlv_sel field matches */ |
345 | ||
7f19bf75 | 346 | if (++node_id >= DRAM_RANGES) |
6775763a DT |
347 | goto err_no_match; |
348 | } | |
349 | ||
350 | /* sanity test for sys_addr */ | |
d1ea71cd | 351 | if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { |
24f9a7fe BP |
352 | amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address" |
353 | "range for node %d with node interleaving enabled.\n", | |
354 | __func__, sys_addr, node_id); | |
6775763a DT |
355 | return NULL; |
356 | } | |
357 | ||
358 | found: | |
b487c33e | 359 | return edac_mc_find((int)node_id); |
6775763a DT |
360 | |
361 | err_no_match: | |
956b9ba1 JP |
362 | edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n", |
363 | (unsigned long)sys_addr); | |
6775763a DT |
364 | |
365 | return NULL; | |
366 | } | |
e2ce7255 DT |
367 | |
368 | /* | |
11c75ead BP |
369 | * compute the CS base address of the @csrow on the DRAM controller @dct. |
370 | * For details see F2x[5C:40] in the processor's BKDG | |
e2ce7255 | 371 | */ |
11c75ead BP |
372 | static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, |
373 | u64 *base, u64 *mask) | |
e2ce7255 | 374 | { |
11c75ead BP |
375 | u64 csbase, csmask, base_bits, mask_bits; |
376 | u8 addr_shift; | |
e2ce7255 | 377 | |
18b94f66 | 378 | if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
379 | csbase = pvt->csels[dct].csbases[csrow]; |
380 | csmask = pvt->csels[dct].csmasks[csrow]; | |
10ef6b0d CG |
381 | base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9); |
382 | mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9); | |
11c75ead | 383 | addr_shift = 4; |
94c1acf2 AG |
384 | |
385 | /* | |
18b94f66 AG |
386 | * F16h and F15h, models 30h and later need two addr_shift values: |
387 | * 8 for high and 6 for low (cf. F16h BKDG). | |
388 | */ | |
389 | } else if (pvt->fam == 0x16 || | |
390 | (pvt->fam == 0x15 && pvt->model >= 0x30)) { | |
94c1acf2 AG |
391 | csbase = pvt->csels[dct].csbases[csrow]; |
392 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
393 | ||
10ef6b0d CG |
394 | *base = (csbase & GENMASK_ULL(15, 5)) << 6; |
395 | *base |= (csbase & GENMASK_ULL(30, 19)) << 8; | |
94c1acf2 AG |
396 | |
397 | *mask = ~0ULL; | |
398 | /* poke holes for the csmask */ | |
10ef6b0d CG |
399 | *mask &= ~((GENMASK_ULL(15, 5) << 6) | |
400 | (GENMASK_ULL(30, 19) << 8)); | |
94c1acf2 | 401 | |
10ef6b0d CG |
402 | *mask |= (csmask & GENMASK_ULL(15, 5)) << 6; |
403 | *mask |= (csmask & GENMASK_ULL(30, 19)) << 8; | |
94c1acf2 AG |
404 | |
405 | return; | |
11c75ead BP |
406 | } else { |
407 | csbase = pvt->csels[dct].csbases[csrow]; | |
408 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
409 | addr_shift = 8; | |
e2ce7255 | 410 | |
a4b4bedc | 411 | if (pvt->fam == 0x15) |
10ef6b0d CG |
412 | base_bits = mask_bits = |
413 | GENMASK_ULL(30,19) | GENMASK_ULL(13,5); | |
11c75ead | 414 | else |
10ef6b0d CG |
415 | base_bits = mask_bits = |
416 | GENMASK_ULL(28,19) | GENMASK_ULL(13,5); | |
11c75ead | 417 | } |
e2ce7255 | 418 | |
11c75ead | 419 | *base = (csbase & base_bits) << addr_shift; |
e2ce7255 | 420 | |
11c75ead BP |
421 | *mask = ~0ULL; |
422 | /* poke holes for the csmask */ | |
423 | *mask &= ~(mask_bits << addr_shift); | |
424 | /* OR them in */ | |
425 | *mask |= (csmask & mask_bits) << addr_shift; | |
e2ce7255 DT |
426 | } |
427 | ||
11c75ead BP |
428 | #define for_each_chip_select(i, dct, pvt) \ |
429 | for (i = 0; i < pvt->csels[dct].b_cnt; i++) | |
430 | ||
614ec9d8 BP |
431 | #define chip_select_base(i, dct, pvt) \ |
432 | pvt->csels[dct].csbases[i] | |
433 | ||
11c75ead BP |
434 | #define for_each_chip_select_mask(i, dct, pvt) \ |
435 | for (i = 0; i < pvt->csels[dct].m_cnt; i++) | |
436 | ||
4d30d2bc | 437 | #define for_each_umc(i) \ |
ed623d55 | 438 | for (i = 0; i < pvt->max_mcs; i++) |
4d30d2bc | 439 | |
e2ce7255 DT |
440 | /* |
441 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
442 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
443 | */ | |
444 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
445 | { | |
446 | struct amd64_pvt *pvt; | |
447 | int csrow; | |
448 | u64 base, mask; | |
449 | ||
450 | pvt = mci->pvt_info; | |
451 | ||
11c75ead BP |
452 | for_each_chip_select(csrow, 0, pvt) { |
453 | if (!csrow_enabled(csrow, 0, pvt)) | |
e2ce7255 DT |
454 | continue; |
455 | ||
11c75ead BP |
456 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
457 | ||
458 | mask = ~mask; | |
e2ce7255 DT |
459 | |
460 | if ((input_addr & mask) == (base & mask)) { | |
956b9ba1 JP |
461 | edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n", |
462 | (unsigned long)input_addr, csrow, | |
463 | pvt->mc_node_id); | |
e2ce7255 DT |
464 | |
465 | return csrow; | |
466 | } | |
467 | } | |
956b9ba1 JP |
468 | edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n", |
469 | (unsigned long)input_addr, pvt->mc_node_id); | |
e2ce7255 DT |
470 | |
471 | return -1; | |
472 | } | |
473 | ||
e2ce7255 DT |
474 | /* |
475 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
476 | * for the node represented by mci. Info is passed back in *hole_base, | |
477 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
478 | * info is invalid. Info may be invalid for either of the following reasons: | |
479 | * | |
480 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
481 | * Address Register does not exist. | |
482 | * | |
483 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
484 | * indicating that its contents are not valid. | |
485 | * | |
486 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
487 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
488 | * only represent bits 31-24 of the base and offset values. | |
489 | */ | |
2a28ceef BP |
490 | static int get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, |
491 | u64 *hole_offset, u64 *hole_size) | |
e2ce7255 DT |
492 | { |
493 | struct amd64_pvt *pvt = mci->pvt_info; | |
e2ce7255 DT |
494 | |
495 | /* only revE and later have the DRAM Hole Address Register */ | |
a4b4bedc | 496 | if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { |
956b9ba1 JP |
497 | edac_dbg(1, " revision %d for node %d does not support DHAR\n", |
498 | pvt->ext_model, pvt->mc_node_id); | |
e2ce7255 DT |
499 | return 1; |
500 | } | |
501 | ||
bc21fa57 | 502 | /* valid for Fam10h and above */ |
a4b4bedc | 503 | if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { |
956b9ba1 | 504 | edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n"); |
e2ce7255 DT |
505 | return 1; |
506 | } | |
507 | ||
c8e518d5 | 508 | if (!dhar_valid(pvt)) { |
956b9ba1 JP |
509 | edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n", |
510 | pvt->mc_node_id); | |
e2ce7255 DT |
511 | return 1; |
512 | } | |
513 | ||
514 | /* This node has Memory Hoisting */ | |
515 | ||
516 | /* +------------------+--------------------+--------------------+----- | |
517 | * | memory | DRAM hole | relocated | | |
518 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
519 | * | | | DRAM hole | | |
520 | * | | | [0x100000000, | | |
521 | * | | | (0x100000000+ | | |
522 | * | | | (0xffffffff-x))] | | |
523 | * +------------------+--------------------+--------------------+----- | |
524 | * | |
525 | * Above is a diagram of physical memory showing the DRAM hole and the | |
526 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
527 | * starts at address x (the base address) and extends through address | |
528 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
529 | * addresses in the hole so that they start at 0x100000000. | |
530 | */ | |
531 | ||
1f31677e BP |
532 | *hole_base = dhar_base(pvt); |
533 | *hole_size = (1ULL << 32) - *hole_base; | |
e2ce7255 | 534 | |
a4b4bedc BP |
535 | *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) |
536 | : k8_dhar_offset(pvt); | |
e2ce7255 | 537 | |
956b9ba1 JP |
538 | edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", |
539 | pvt->mc_node_id, (unsigned long)*hole_base, | |
540 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
e2ce7255 DT |
541 | |
542 | return 0; | |
543 | } | |
2a28ceef BP |
544 | |
545 | #ifdef CONFIG_EDAC_DEBUG | |
546 | #define EDAC_DCT_ATTR_SHOW(reg) \ | |
547 | static ssize_t reg##_show(struct device *dev, \ | |
548 | struct device_attribute *mattr, char *data) \ | |
549 | { \ | |
550 | struct mem_ctl_info *mci = to_mci(dev); \ | |
551 | struct amd64_pvt *pvt = mci->pvt_info; \ | |
552 | \ | |
553 | return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \ | |
554 | } | |
555 | ||
556 | EDAC_DCT_ATTR_SHOW(dhar); | |
557 | EDAC_DCT_ATTR_SHOW(dbam0); | |
558 | EDAC_DCT_ATTR_SHOW(top_mem); | |
559 | EDAC_DCT_ATTR_SHOW(top_mem2); | |
560 | ||
d19faf0e DR |
561 | static ssize_t dram_hole_show(struct device *dev, struct device_attribute *mattr, |
562 | char *data) | |
2a28ceef BP |
563 | { |
564 | struct mem_ctl_info *mci = to_mci(dev); | |
565 | ||
566 | u64 hole_base = 0; | |
567 | u64 hole_offset = 0; | |
568 | u64 hole_size = 0; | |
569 | ||
570 | get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size); | |
571 | ||
572 | return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset, | |
573 | hole_size); | |
574 | } | |
575 | ||
576 | /* | |
577 | * update NUM_DBG_ATTRS in case you add new members | |
578 | */ | |
579 | static DEVICE_ATTR(dhar, S_IRUGO, dhar_show, NULL); | |
580 | static DEVICE_ATTR(dbam, S_IRUGO, dbam0_show, NULL); | |
581 | static DEVICE_ATTR(topmem, S_IRUGO, top_mem_show, NULL); | |
582 | static DEVICE_ATTR(topmem2, S_IRUGO, top_mem2_show, NULL); | |
d19faf0e | 583 | static DEVICE_ATTR_RO(dram_hole); |
2a28ceef BP |
584 | |
585 | static struct attribute *dbg_attrs[] = { | |
586 | &dev_attr_dhar.attr, | |
587 | &dev_attr_dbam.attr, | |
588 | &dev_attr_topmem.attr, | |
589 | &dev_attr_topmem2.attr, | |
590 | &dev_attr_dram_hole.attr, | |
591 | NULL | |
592 | }; | |
593 | ||
594 | static const struct attribute_group dbg_group = { | |
595 | .attrs = dbg_attrs, | |
596 | }; | |
2a28ceef | 597 | |
61810096 BP |
598 | static ssize_t inject_section_show(struct device *dev, |
599 | struct device_attribute *mattr, char *buf) | |
600 | { | |
601 | struct mem_ctl_info *mci = to_mci(dev); | |
602 | struct amd64_pvt *pvt = mci->pvt_info; | |
603 | return sprintf(buf, "0x%x\n", pvt->injection.section); | |
604 | } | |
605 | ||
606 | /* | |
607 | * store error injection section value which refers to one of 4 16-byte sections | |
608 | * within a 64-byte cacheline | |
609 | * | |
610 | * range: 0..3 | |
611 | */ | |
612 | static ssize_t inject_section_store(struct device *dev, | |
613 | struct device_attribute *mattr, | |
614 | const char *data, size_t count) | |
615 | { | |
616 | struct mem_ctl_info *mci = to_mci(dev); | |
617 | struct amd64_pvt *pvt = mci->pvt_info; | |
618 | unsigned long value; | |
619 | int ret; | |
620 | ||
621 | ret = kstrtoul(data, 10, &value); | |
622 | if (ret < 0) | |
623 | return ret; | |
624 | ||
625 | if (value > 3) { | |
626 | amd64_warn("%s: invalid section 0x%lx\n", __func__, value); | |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | pvt->injection.section = (u32) value; | |
631 | return count; | |
632 | } | |
633 | ||
634 | static ssize_t inject_word_show(struct device *dev, | |
635 | struct device_attribute *mattr, char *buf) | |
636 | { | |
637 | struct mem_ctl_info *mci = to_mci(dev); | |
638 | struct amd64_pvt *pvt = mci->pvt_info; | |
639 | return sprintf(buf, "0x%x\n", pvt->injection.word); | |
640 | } | |
641 | ||
642 | /* | |
643 | * store error injection word value which refers to one of 9 16-bit word of the | |
644 | * 16-byte (128-bit + ECC bits) section | |
645 | * | |
646 | * range: 0..8 | |
647 | */ | |
648 | static ssize_t inject_word_store(struct device *dev, | |
649 | struct device_attribute *mattr, | |
650 | const char *data, size_t count) | |
651 | { | |
652 | struct mem_ctl_info *mci = to_mci(dev); | |
653 | struct amd64_pvt *pvt = mci->pvt_info; | |
654 | unsigned long value; | |
655 | int ret; | |
656 | ||
657 | ret = kstrtoul(data, 10, &value); | |
658 | if (ret < 0) | |
659 | return ret; | |
660 | ||
661 | if (value > 8) { | |
662 | amd64_warn("%s: invalid word 0x%lx\n", __func__, value); | |
663 | return -EINVAL; | |
664 | } | |
665 | ||
666 | pvt->injection.word = (u32) value; | |
667 | return count; | |
668 | } | |
669 | ||
670 | static ssize_t inject_ecc_vector_show(struct device *dev, | |
671 | struct device_attribute *mattr, | |
672 | char *buf) | |
673 | { | |
674 | struct mem_ctl_info *mci = to_mci(dev); | |
675 | struct amd64_pvt *pvt = mci->pvt_info; | |
676 | return sprintf(buf, "0x%x\n", pvt->injection.bit_map); | |
677 | } | |
678 | ||
679 | /* | |
680 | * store 16 bit error injection vector which enables injecting errors to the | |
681 | * corresponding bit within the error injection word above. When used during a | |
682 | * DRAM ECC read, it holds the contents of the of the DRAM ECC bits. | |
683 | */ | |
684 | static ssize_t inject_ecc_vector_store(struct device *dev, | |
685 | struct device_attribute *mattr, | |
686 | const char *data, size_t count) | |
687 | { | |
688 | struct mem_ctl_info *mci = to_mci(dev); | |
689 | struct amd64_pvt *pvt = mci->pvt_info; | |
690 | unsigned long value; | |
691 | int ret; | |
692 | ||
693 | ret = kstrtoul(data, 16, &value); | |
694 | if (ret < 0) | |
695 | return ret; | |
696 | ||
697 | if (value & 0xFFFF0000) { | |
698 | amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value); | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | pvt->injection.bit_map = (u32) value; | |
703 | return count; | |
704 | } | |
705 | ||
706 | /* | |
707 | * Do a DRAM ECC read. Assemble staged values in the pvt area, format into | |
708 | * fields needed by the injection registers and read the NB Array Data Port. | |
709 | */ | |
710 | static ssize_t inject_read_store(struct device *dev, | |
711 | struct device_attribute *mattr, | |
712 | const char *data, size_t count) | |
713 | { | |
714 | struct mem_ctl_info *mci = to_mci(dev); | |
715 | struct amd64_pvt *pvt = mci->pvt_info; | |
716 | unsigned long value; | |
717 | u32 section, word_bits; | |
718 | int ret; | |
719 | ||
720 | ret = kstrtoul(data, 10, &value); | |
721 | if (ret < 0) | |
722 | return ret; | |
723 | ||
724 | /* Form value to choose 16-byte section of cacheline */ | |
725 | section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); | |
726 | ||
727 | amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); | |
728 | ||
729 | word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); | |
730 | ||
731 | /* Issue 'word' and 'bit' along with the READ request */ | |
732 | amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); | |
733 | ||
734 | edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits); | |
735 | ||
736 | return count; | |
737 | } | |
738 | ||
739 | /* | |
740 | * Do a DRAM ECC write. Assemble staged values in the pvt area and format into | |
741 | * fields needed by the injection registers. | |
742 | */ | |
743 | static ssize_t inject_write_store(struct device *dev, | |
744 | struct device_attribute *mattr, | |
745 | const char *data, size_t count) | |
746 | { | |
747 | struct mem_ctl_info *mci = to_mci(dev); | |
748 | struct amd64_pvt *pvt = mci->pvt_info; | |
749 | u32 section, word_bits, tmp; | |
750 | unsigned long value; | |
751 | int ret; | |
752 | ||
753 | ret = kstrtoul(data, 10, &value); | |
754 | if (ret < 0) | |
755 | return ret; | |
756 | ||
757 | /* Form value to choose 16-byte section of cacheline */ | |
758 | section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); | |
759 | ||
760 | amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); | |
761 | ||
762 | word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); | |
763 | ||
764 | pr_notice_once("Don't forget to decrease MCE polling interval in\n" | |
765 | "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n" | |
766 | "so that you can get the error report faster.\n"); | |
767 | ||
768 | on_each_cpu(disable_caches, NULL, 1); | |
769 | ||
770 | /* Issue 'word' and 'bit' along with the READ request */ | |
771 | amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); | |
772 | ||
773 | retry: | |
774 | /* wait until injection happens */ | |
775 | amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); | |
776 | if (tmp & F10_NB_ARR_ECC_WR_REQ) { | |
777 | cpu_relax(); | |
778 | goto retry; | |
779 | } | |
780 | ||
781 | on_each_cpu(enable_caches, NULL, 1); | |
782 | ||
783 | edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits); | |
784 | ||
785 | return count; | |
786 | } | |
787 | ||
788 | /* | |
789 | * update NUM_INJ_ATTRS in case you add new members | |
790 | */ | |
791 | ||
d19faf0e DR |
792 | static DEVICE_ATTR_RW(inject_section); |
793 | static DEVICE_ATTR_RW(inject_word); | |
794 | static DEVICE_ATTR_RW(inject_ecc_vector); | |
795 | static DEVICE_ATTR_WO(inject_write); | |
796 | static DEVICE_ATTR_WO(inject_read); | |
61810096 BP |
797 | |
798 | static struct attribute *inj_attrs[] = { | |
799 | &dev_attr_inject_section.attr, | |
800 | &dev_attr_inject_word.attr, | |
801 | &dev_attr_inject_ecc_vector.attr, | |
802 | &dev_attr_inject_write.attr, | |
803 | &dev_attr_inject_read.attr, | |
804 | NULL | |
805 | }; | |
806 | ||
807 | static umode_t inj_is_visible(struct kobject *kobj, struct attribute *attr, int idx) | |
808 | { | |
809 | struct device *dev = kobj_to_dev(kobj); | |
810 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); | |
811 | struct amd64_pvt *pvt = mci->pvt_info; | |
812 | ||
1865bc71 BP |
813 | /* Families which have that injection hw */ |
814 | if (pvt->fam >= 0x10 && pvt->fam <= 0x16) | |
815 | return attr->mode; | |
816 | ||
817 | return 0; | |
61810096 BP |
818 | } |
819 | ||
820 | static const struct attribute_group inj_group = { | |
821 | .attrs = inj_attrs, | |
822 | .is_visible = inj_is_visible, | |
823 | }; | |
824 | #endif /* CONFIG_EDAC_DEBUG */ | |
e2ce7255 | 825 | |
93c2df58 DT |
826 | /* |
827 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
828 | * assumed that sys_addr maps to the node given by mci. | |
829 | * | |
830 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
831 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
832 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
833 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
834 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
835 | * These parts of the documentation are unclear. I interpret them as follows: | |
836 | * | |
837 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
838 | * | |
839 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
840 | * Limit registers for node n. If the SysAddr is not within the range | |
841 | * specified by the base and limit values, then node n ignores the Sysaddr | |
842 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
843 | * | |
844 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
845 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
846 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
847 | * hole. If not, skip to step 3 below. Else get the value of the | |
848 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
849 | * offset defined by this value from the SysAddr. | |
850 | * | |
851 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
852 | * Base register for node n. To obtain the DramAddr, subtract the base | |
853 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
854 | */ | |
855 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
856 | { | |
7f19bf75 | 857 | struct amd64_pvt *pvt = mci->pvt_info; |
93c2df58 | 858 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; |
1f31677e | 859 | int ret; |
93c2df58 | 860 | |
7f19bf75 | 861 | dram_base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 | 862 | |
2a28ceef | 863 | ret = get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size); |
93c2df58 | 864 | if (!ret) { |
1f31677e BP |
865 | if ((sys_addr >= (1ULL << 32)) && |
866 | (sys_addr < ((1ULL << 32) + hole_size))) { | |
93c2df58 DT |
867 | /* use DHAR to translate SysAddr to DramAddr */ |
868 | dram_addr = sys_addr - hole_offset; | |
869 | ||
956b9ba1 JP |
870 | edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n", |
871 | (unsigned long)sys_addr, | |
872 | (unsigned long)dram_addr); | |
93c2df58 DT |
873 | |
874 | return dram_addr; | |
875 | } | |
876 | } | |
877 | ||
878 | /* | |
879 | * Translate the SysAddr to a DramAddr as shown near the start of | |
880 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
881 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
882 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
883 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
884 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
885 | * Programmer's Manual Volume 1 Application Programming. | |
886 | */ | |
10ef6b0d | 887 | dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; |
93c2df58 | 888 | |
956b9ba1 JP |
889 | edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n", |
890 | (unsigned long)sys_addr, (unsigned long)dram_addr); | |
93c2df58 DT |
891 | return dram_addr; |
892 | } | |
893 | ||
894 | /* | |
895 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
896 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
897 | * for node interleaving. | |
898 | */ | |
899 | static int num_node_interleave_bits(unsigned intlv_en) | |
900 | { | |
901 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
902 | int n; | |
903 | ||
904 | BUG_ON(intlv_en > 7); | |
905 | n = intlv_shift_table[intlv_en]; | |
906 | return n; | |
907 | } | |
908 | ||
909 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
910 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
911 | { | |
912 | struct amd64_pvt *pvt; | |
913 | int intlv_shift; | |
914 | u64 input_addr; | |
915 | ||
916 | pvt = mci->pvt_info; | |
917 | ||
918 | /* | |
919 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
920 | * concerning translating a DramAddr to an InputAddr. | |
921 | */ | |
7f19bf75 | 922 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
10ef6b0d | 923 | input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) + |
f678b8cc | 924 | (dram_addr & 0xfff); |
93c2df58 | 925 | |
956b9ba1 JP |
926 | edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", |
927 | intlv_shift, (unsigned long)dram_addr, | |
928 | (unsigned long)input_addr); | |
93c2df58 DT |
929 | |
930 | return input_addr; | |
931 | } | |
932 | ||
933 | /* | |
934 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
935 | * assumed that @sys_addr maps to the node given by mci. | |
936 | */ | |
937 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
938 | { | |
939 | u64 input_addr; | |
940 | ||
941 | input_addr = | |
942 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
943 | ||
c19ca6cb | 944 | edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n", |
956b9ba1 | 945 | (unsigned long)sys_addr, (unsigned long)input_addr); |
93c2df58 DT |
946 | |
947 | return input_addr; | |
948 | } | |
949 | ||
93c2df58 DT |
950 | /* Map the Error address to a PAGE and PAGE OFFSET. */ |
951 | static inline void error_address_to_page_and_offset(u64 error_address, | |
33ca0643 | 952 | struct err_info *err) |
93c2df58 | 953 | { |
33ca0643 BP |
954 | err->page = (u32) (error_address >> PAGE_SHIFT); |
955 | err->offset = ((u32) error_address) & ~PAGE_MASK; | |
93c2df58 DT |
956 | } |
957 | ||
958 | /* | |
959 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
960 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
961 | * of a node that detected an ECC memory error. mci represents the node that | |
962 | * the error address maps to (possibly different from the node that detected | |
963 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
964 | * error. | |
965 | */ | |
966 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
967 | { | |
968 | int csrow; | |
969 | ||
970 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
971 | ||
972 | if (csrow == -1) | |
24f9a7fe BP |
973 | amd64_mc_err(mci, "Failed to translate InputAddr to csrow for " |
974 | "address 0x%lx\n", (unsigned long)sys_addr); | |
93c2df58 DT |
975 | return csrow; |
976 | } | |
e2ce7255 | 977 | |
4251566e YG |
978 | /* |
979 | * See AMD PPR DF::LclNodeTypeMap | |
980 | * | |
981 | * This register gives information for nodes of the same type within a system. | |
982 | * | |
983 | * Reading this register from a GPU node will tell how many GPU nodes are in the | |
984 | * system and what the lowest AMD Node ID value is for the GPU nodes. Use this | |
985 | * info to fixup the Linux logical "Node ID" value set in the AMD NB code and EDAC. | |
986 | */ | |
987 | static struct local_node_map { | |
988 | u16 node_count; | |
989 | u16 base_node_id; | |
990 | } gpu_node_map; | |
991 | ||
992 | #define PCI_DEVICE_ID_AMD_MI200_DF_F1 0x14d1 | |
993 | #define REG_LOCAL_NODE_TYPE_MAP 0x144 | |
994 | ||
995 | /* Local Node Type Map (LNTM) fields */ | |
996 | #define LNTM_NODE_COUNT GENMASK(27, 16) | |
997 | #define LNTM_BASE_NODE_ID GENMASK(11, 0) | |
998 | ||
12f230c0 | 999 | static int gpu_get_node_map(struct amd64_pvt *pvt) |
4251566e YG |
1000 | { |
1001 | struct pci_dev *pdev; | |
1002 | int ret; | |
1003 | u32 tmp; | |
1004 | ||
1005 | /* | |
12f230c0 M |
1006 | * Mapping of nodes from hardware-provided AMD Node ID to a |
1007 | * Linux logical one is applicable for MI200 models. Therefore, | |
1008 | * return early for other heterogeneous systems. | |
1009 | */ | |
1010 | if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3) | |
1011 | return 0; | |
1012 | ||
1013 | /* | |
1014 | * Node ID 0 is reserved for CPUs. Therefore, a non-zero Node ID | |
1015 | * means the values have been already cached. | |
4251566e YG |
1016 | */ |
1017 | if (gpu_node_map.base_node_id) | |
1018 | return 0; | |
1019 | ||
1020 | pdev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F1, NULL); | |
1021 | if (!pdev) { | |
1022 | ret = -ENODEV; | |
1023 | goto out; | |
1024 | } | |
1025 | ||
1026 | ret = pci_read_config_dword(pdev, REG_LOCAL_NODE_TYPE_MAP, &tmp); | |
1027 | if (ret) | |
1028 | goto out; | |
1029 | ||
1030 | gpu_node_map.node_count = FIELD_GET(LNTM_NODE_COUNT, tmp); | |
1031 | gpu_node_map.base_node_id = FIELD_GET(LNTM_BASE_NODE_ID, tmp); | |
1032 | ||
1033 | out: | |
1034 | pci_dev_put(pdev); | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | static int fixup_node_id(int node_id, struct mce *m) | |
1039 | { | |
1040 | /* MCA_IPID[InstanceIdHi] give the AMD Node ID for the bank. */ | |
1041 | u8 nid = (m->ipid >> 44) & 0xF; | |
1042 | ||
1043 | if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2) | |
1044 | return node_id; | |
1045 | ||
1046 | /* Nodes below the GPU base node are CPU nodes and don't need a fixup. */ | |
1047 | if (nid < gpu_node_map.base_node_id) | |
1048 | return node_id; | |
1049 | ||
1050 | /* Convert the hardware-provided AMD Node ID to a Linux logical one. */ | |
1051 | return nid - gpu_node_map.base_node_id + 1; | |
1052 | } | |
1053 | ||
b3218ae4 YG |
1054 | /* Protect the PCI config register pairs used for DF indirect access. */ |
1055 | static DEFINE_MUTEX(df_indirect_mutex); | |
1056 | ||
1057 | /* | |
1058 | * Data Fabric Indirect Access uses FICAA/FICAD. | |
1059 | * | |
1060 | * Fabric Indirect Configuration Access Address (FICAA): Constructed based | |
1061 | * on the device's Instance Id and the PCI function and register offset of | |
1062 | * the desired register. | |
1063 | * | |
1064 | * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO | |
1065 | * and FICAD HI registers but so far we only need the LO register. | |
448c3d60 YG |
1066 | * |
1067 | * Use Instance Id 0xFF to indicate a broadcast read. | |
b3218ae4 | 1068 | */ |
448c3d60 YG |
1069 | #define DF_BROADCAST 0xFF |
1070 | static int __df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) | |
b3218ae4 YG |
1071 | { |
1072 | struct pci_dev *F4; | |
1073 | u32 ficaa; | |
1074 | int err = -ENODEV; | |
1075 | ||
1076 | if (node >= amd_nb_num()) | |
1077 | goto out; | |
1078 | ||
1079 | F4 = node_to_amd_nb(node)->link; | |
1080 | if (!F4) | |
1081 | goto out; | |
1082 | ||
448c3d60 | 1083 | ficaa = (instance_id == DF_BROADCAST) ? 0 : 1; |
b3218ae4 YG |
1084 | ficaa |= reg & 0x3FC; |
1085 | ficaa |= (func & 0x7) << 11; | |
1086 | ficaa |= instance_id << 16; | |
1087 | ||
1088 | mutex_lock(&df_indirect_mutex); | |
1089 | ||
1090 | err = pci_write_config_dword(F4, 0x5C, ficaa); | |
1091 | if (err) { | |
1092 | pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); | |
1093 | goto out_unlock; | |
1094 | } | |
1095 | ||
1096 | err = pci_read_config_dword(F4, 0x98, lo); | |
1097 | if (err) | |
1098 | pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); | |
1099 | ||
1100 | out_unlock: | |
1101 | mutex_unlock(&df_indirect_mutex); | |
1102 | ||
1103 | out: | |
1104 | return err; | |
1105 | } | |
1106 | ||
448c3d60 YG |
1107 | static int df_indirect_read_instance(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) |
1108 | { | |
1109 | return __df_indirect_read(node, func, reg, instance_id, lo); | |
1110 | } | |
1111 | ||
1112 | static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) | |
1113 | { | |
1114 | return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); | |
1115 | } | |
1116 | ||
70aeb807 YG |
1117 | struct addr_ctx { |
1118 | u64 ret_addr; | |
1119 | u32 tmp; | |
1120 | u16 nid; | |
1121 | u8 inst_id; | |
1122 | }; | |
1123 | ||
0b746e8c YG |
1124 | static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) |
1125 | { | |
1126 | u64 dram_base_addr, dram_limit_addr, dram_hole_base; | |
0b746e8c YG |
1127 | |
1128 | u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; | |
1129 | u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; | |
1130 | u8 intlv_addr_sel, intlv_addr_bit; | |
1131 | u8 num_intlv_bits, hashed_bit; | |
1132 | u8 lgcy_mmio_hole_en, base = 0; | |
1133 | u8 cs_mask, cs_id = 0; | |
1134 | bool hash_enabled = false; | |
1135 | ||
70aeb807 YG |
1136 | struct addr_ctx ctx; |
1137 | ||
1138 | memset(&ctx, 0, sizeof(ctx)); | |
1139 | ||
1140 | /* Start from the normalized address */ | |
1141 | ctx.ret_addr = norm_addr; | |
1142 | ||
1143 | ctx.nid = nid; | |
1144 | ctx.inst_id = umc; | |
1145 | ||
0b746e8c | 1146 | /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ |
70aeb807 | 1147 | if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp)) |
0b746e8c YG |
1148 | goto out_err; |
1149 | ||
1150 | /* Remove HiAddrOffset from normalized address, if enabled: */ | |
70aeb807 YG |
1151 | if (ctx.tmp & BIT(0)) { |
1152 | u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8; | |
0b746e8c YG |
1153 | |
1154 | if (norm_addr >= hi_addr_offset) { | |
70aeb807 | 1155 | ctx.ret_addr -= hi_addr_offset; |
0b746e8c YG |
1156 | base = 1; |
1157 | } | |
1158 | } | |
1159 | ||
1160 | /* Read D18F0x110 (DramBaseAddress). */ | |
70aeb807 | 1161 | if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp)) |
0b746e8c YG |
1162 | goto out_err; |
1163 | ||
1164 | /* Check if address range is valid. */ | |
70aeb807 | 1165 | if (!(ctx.tmp & BIT(0))) { |
0b746e8c | 1166 | pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", |
70aeb807 | 1167 | __func__, ctx.tmp); |
0b746e8c YG |
1168 | goto out_err; |
1169 | } | |
1170 | ||
70aeb807 YG |
1171 | lgcy_mmio_hole_en = ctx.tmp & BIT(1); |
1172 | intlv_num_chan = (ctx.tmp >> 4) & 0xF; | |
1173 | intlv_addr_sel = (ctx.tmp >> 8) & 0x7; | |
1174 | dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16; | |
0b746e8c YG |
1175 | |
1176 | /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ | |
1177 | if (intlv_addr_sel > 3) { | |
1178 | pr_err("%s: Invalid interleave address select %d.\n", | |
1179 | __func__, intlv_addr_sel); | |
1180 | goto out_err; | |
1181 | } | |
1182 | ||
1183 | /* Read D18F0x114 (DramLimitAddress). */ | |
70aeb807 | 1184 | if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp)) |
0b746e8c YG |
1185 | goto out_err; |
1186 | ||
70aeb807 YG |
1187 | intlv_num_sockets = (ctx.tmp >> 8) & 0x1; |
1188 | intlv_num_dies = (ctx.tmp >> 10) & 0x3; | |
1189 | dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); | |
0b746e8c YG |
1190 | |
1191 | intlv_addr_bit = intlv_addr_sel + 8; | |
1192 | ||
1193 | /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ | |
1194 | switch (intlv_num_chan) { | |
1195 | case 0: intlv_num_chan = 0; break; | |
1196 | case 1: intlv_num_chan = 1; break; | |
1197 | case 3: intlv_num_chan = 2; break; | |
1198 | case 5: intlv_num_chan = 3; break; | |
1199 | case 7: intlv_num_chan = 4; break; | |
1200 | ||
1201 | case 8: intlv_num_chan = 1; | |
1202 | hash_enabled = true; | |
1203 | break; | |
1204 | default: | |
1205 | pr_err("%s: Invalid number of interleaved channels %d.\n", | |
1206 | __func__, intlv_num_chan); | |
1207 | goto out_err; | |
1208 | } | |
1209 | ||
1210 | num_intlv_bits = intlv_num_chan; | |
1211 | ||
1212 | if (intlv_num_dies > 2) { | |
1213 | pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", | |
1214 | __func__, intlv_num_dies); | |
1215 | goto out_err; | |
1216 | } | |
1217 | ||
1218 | num_intlv_bits += intlv_num_dies; | |
1219 | ||
1220 | /* Add a bit if sockets are interleaved. */ | |
1221 | num_intlv_bits += intlv_num_sockets; | |
1222 | ||
1223 | /* Assert num_intlv_bits <= 4 */ | |
1224 | if (num_intlv_bits > 4) { | |
1225 | pr_err("%s: Invalid interleave bits %d.\n", | |
1226 | __func__, num_intlv_bits); | |
1227 | goto out_err; | |
1228 | } | |
1229 | ||
1230 | if (num_intlv_bits > 0) { | |
1231 | u64 temp_addr_x, temp_addr_i, temp_addr_y; | |
1232 | u8 die_id_bit, sock_id_bit, cs_fabric_id; | |
1233 | ||
1234 | /* | |
1235 | * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. | |
1236 | * This is the fabric id for this coherent slave. Use | |
1237 | * umc/channel# as instance id of the coherent slave | |
1238 | * for FICAA. | |
1239 | */ | |
70aeb807 | 1240 | if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp)) |
0b746e8c YG |
1241 | goto out_err; |
1242 | ||
70aeb807 | 1243 | cs_fabric_id = (ctx.tmp >> 8) & 0xFF; |
0b746e8c YG |
1244 | die_id_bit = 0; |
1245 | ||
1246 | /* If interleaved over more than 1 channel: */ | |
1247 | if (intlv_num_chan) { | |
1248 | die_id_bit = intlv_num_chan; | |
1249 | cs_mask = (1 << die_id_bit) - 1; | |
1250 | cs_id = cs_fabric_id & cs_mask; | |
1251 | } | |
1252 | ||
1253 | sock_id_bit = die_id_bit; | |
1254 | ||
1255 | /* Read D18F1x208 (SystemFabricIdMask). */ | |
1256 | if (intlv_num_dies || intlv_num_sockets) | |
70aeb807 | 1257 | if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp)) |
0b746e8c YG |
1258 | goto out_err; |
1259 | ||
1260 | /* If interleaved over more than 1 die. */ | |
1261 | if (intlv_num_dies) { | |
1262 | sock_id_bit = die_id_bit + intlv_num_dies; | |
70aeb807 YG |
1263 | die_id_shift = (ctx.tmp >> 24) & 0xF; |
1264 | die_id_mask = (ctx.tmp >> 8) & 0xFF; | |
0b746e8c YG |
1265 | |
1266 | cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; | |
1267 | } | |
1268 | ||
1269 | /* If interleaved over more than 1 socket. */ | |
1270 | if (intlv_num_sockets) { | |
70aeb807 YG |
1271 | socket_id_shift = (ctx.tmp >> 28) & 0xF; |
1272 | socket_id_mask = (ctx.tmp >> 16) & 0xFF; | |
0b746e8c YG |
1273 | |
1274 | cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; | |
1275 | } | |
1276 | ||
1277 | /* | |
1278 | * The pre-interleaved address consists of XXXXXXIIIYYYYY | |
1279 | * where III is the ID for this CS, and XXXXXXYYYYY are the | |
1280 | * address bits from the post-interleaved address. | |
1281 | * "num_intlv_bits" has been calculated to tell us how many "I" | |
1282 | * bits there are. "intlv_addr_bit" tells us how many "Y" bits | |
1283 | * there are (where "I" starts). | |
1284 | */ | |
70aeb807 | 1285 | temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); |
0b746e8c | 1286 | temp_addr_i = (cs_id << intlv_addr_bit); |
70aeb807 YG |
1287 | temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; |
1288 | ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; | |
0b746e8c YG |
1289 | } |
1290 | ||
1291 | /* Add dram base address */ | |
70aeb807 | 1292 | ctx.ret_addr += dram_base_addr; |
0b746e8c YG |
1293 | |
1294 | /* If legacy MMIO hole enabled */ | |
1295 | if (lgcy_mmio_hole_en) { | |
70aeb807 | 1296 | if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp)) |
0b746e8c YG |
1297 | goto out_err; |
1298 | ||
70aeb807 YG |
1299 | dram_hole_base = ctx.tmp & GENMASK(31, 24); |
1300 | if (ctx.ret_addr >= dram_hole_base) | |
1301 | ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); | |
0b746e8c YG |
1302 | } |
1303 | ||
1304 | if (hash_enabled) { | |
1305 | /* Save some parentheses and grab ls-bit at the end. */ | |
70aeb807 YG |
1306 | hashed_bit = (ctx.ret_addr >> 12) ^ |
1307 | (ctx.ret_addr >> 18) ^ | |
1308 | (ctx.ret_addr >> 21) ^ | |
1309 | (ctx.ret_addr >> 30) ^ | |
0b746e8c YG |
1310 | cs_id; |
1311 | ||
1312 | hashed_bit &= BIT(0); | |
1313 | ||
70aeb807 YG |
1314 | if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) |
1315 | ctx.ret_addr ^= BIT(intlv_addr_bit); | |
0b746e8c YG |
1316 | } |
1317 | ||
1318 | /* Is calculated system address is above DRAM limit address? */ | |
70aeb807 | 1319 | if (ctx.ret_addr > dram_limit_addr) |
0b746e8c YG |
1320 | goto out_err; |
1321 | ||
70aeb807 | 1322 | *sys_addr = ctx.ret_addr; |
0b746e8c YG |
1323 | return 0; |
1324 | ||
1325 | out_err: | |
1326 | return -EINVAL; | |
1327 | } | |
1328 | ||
bfc04aec | 1329 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); |
2da11654 | 1330 | |
2da11654 DT |
1331 | /* |
1332 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
1333 | * are ECC capable. | |
1334 | */ | |
f6a4b4a1 | 1335 | static unsigned long dct_determine_edac_cap(struct amd64_pvt *pvt) |
2da11654 | 1336 | { |
1f6189ed | 1337 | unsigned long edac_cap = EDAC_FLAG_NONE; |
d27f3a34 YG |
1338 | u8 bit; |
1339 | ||
f6a4b4a1 M |
1340 | bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) |
1341 | ? 19 | |
1342 | : 17; | |
2da11654 | 1343 | |
f6a4b4a1 M |
1344 | if (pvt->dclr0 & BIT(bit)) |
1345 | edac_cap = EDAC_FLAG_SECDED; | |
2da11654 | 1346 | |
f6a4b4a1 M |
1347 | return edac_cap; |
1348 | } | |
d27f3a34 | 1349 | |
f6a4b4a1 M |
1350 | static unsigned long umc_determine_edac_cap(struct amd64_pvt *pvt) |
1351 | { | |
1352 | u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0; | |
1353 | unsigned long edac_cap = EDAC_FLAG_NONE; | |
d27f3a34 | 1354 | |
49aba1c5 YL |
1355 | for_each_umc(i) { |
1356 | if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) | |
1357 | continue; | |
d27f3a34 | 1358 | |
49aba1c5 | 1359 | umc_en_mask |= BIT(i); |
d27f3a34 | 1360 | |
49aba1c5 YL |
1361 | /* UMC Configuration bit 12 (DimmEccEn) */ |
1362 | if (pvt->umc[i].umc_cfg & BIT(12)) | |
1363 | dimm_ecc_en_mask |= BIT(i); | |
d27f3a34 | 1364 | } |
2da11654 | 1365 | |
49aba1c5 YL |
1366 | if (umc_en_mask == dimm_ecc_en_mask) |
1367 | edac_cap = EDAC_FLAG_SECDED; | |
2da11654 DT |
1368 | |
1369 | return edac_cap; | |
1370 | } | |
1371 | ||
00e4feb8 YG |
1372 | /* |
1373 | * debug routine to display the memory sizes of all logical DIMMs and its | |
1374 | * CSROWs | |
1375 | */ | |
1376 | static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) | |
1377 | { | |
1378 | u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; | |
1379 | u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
1380 | int dimm, size0, size1; | |
1381 | ||
1382 | if (pvt->fam == 0xf) { | |
1383 | /* K8 families < revF not supported yet */ | |
1384 | if (pvt->ext_model < K8_REV_F) | |
1385 | return; | |
1386 | ||
1387 | WARN_ON(ctrl != 0); | |
1388 | } | |
1389 | ||
1390 | if (pvt->fam == 0x10) { | |
1391 | dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 | |
1392 | : pvt->dbam0; | |
1393 | dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? | |
1394 | pvt->csels[1].csbases : | |
1395 | pvt->csels[0].csbases; | |
1396 | } else if (ctrl) { | |
1397 | dbam = pvt->dbam0; | |
1398 | dcsb = pvt->csels[1].csbases; | |
1399 | } | |
1400 | edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", | |
1401 | ctrl, dbam); | |
1402 | ||
1403 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); | |
1404 | ||
1405 | /* Dump memory sizes for DIMM and its CSROWs */ | |
1406 | for (dimm = 0; dimm < 4; dimm++) { | |
1407 | size0 = 0; | |
1408 | if (dcsb[dimm * 2] & DCSB_CS_ENABLE) | |
1409 | /* | |
1410 | * For F15m60h, we need multiplier for LRDIMM cs_size | |
1411 | * calculation. We pass dimm value to the dbam_to_cs | |
1412 | * mapper so we can find the multiplier from the | |
1413 | * corresponding DCSM. | |
1414 | */ | |
1415 | size0 = pvt->ops->dbam_to_cs(pvt, ctrl, | |
1416 | DBAM_DIMM(dimm, dbam), | |
1417 | dimm); | |
1418 | ||
1419 | size1 = 0; | |
1420 | if (dcsb[dimm * 2 + 1] & DCSB_CS_ENABLE) | |
1421 | size1 = pvt->ops->dbam_to_cs(pvt, ctrl, | |
1422 | DBAM_DIMM(dimm, dbam), | |
1423 | dimm); | |
1424 | ||
1425 | amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n", | |
1426 | dimm * 2, size0, | |
1427 | dimm * 2 + 1, size1); | |
1428 | } | |
1429 | } | |
1430 | ||
2da11654 | 1431 | |
d1ea71cd | 1432 | static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) |
68798e17 | 1433 | { |
956b9ba1 | 1434 | edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); |
68798e17 | 1435 | |
a597d2a5 AG |
1436 | if (pvt->dram_type == MEM_LRDDR3) { |
1437 | u32 dcsm = pvt->csels[chan].csmasks[0]; | |
1438 | /* | |
1439 | * It's assumed all LRDIMMs in a DCT are going to be of | |
1440 | * same 'type' until proven otherwise. So, use a cs | |
1441 | * value of '0' here to get dcsm value. | |
1442 | */ | |
1443 | edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3)); | |
1444 | } | |
1445 | ||
1446 | edac_dbg(1, "All DIMMs support ECC:%s\n", | |
1447 | (dclr & BIT(19)) ? "yes" : "no"); | |
1448 | ||
68798e17 | 1449 | |
956b9ba1 JP |
1450 | edac_dbg(1, " PAR/ERR parity: %s\n", |
1451 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
68798e17 | 1452 | |
a4b4bedc | 1453 | if (pvt->fam == 0x10) |
956b9ba1 JP |
1454 | edac_dbg(1, " DCT 128bit mode width: %s\n", |
1455 | (dclr & BIT(11)) ? "128b" : "64b"); | |
68798e17 | 1456 | |
956b9ba1 JP |
1457 | edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", |
1458 | (dclr & BIT(12)) ? "yes" : "no", | |
1459 | (dclr & BIT(13)) ? "yes" : "no", | |
1460 | (dclr & BIT(14)) ? "yes" : "no", | |
1461 | (dclr & BIT(15)) ? "yes" : "no"); | |
68798e17 BP |
1462 | } |
1463 | ||
e53a3b26 YG |
1464 | #define CS_EVEN_PRIMARY BIT(0) |
1465 | #define CS_ODD_PRIMARY BIT(1) | |
81f5090d YG |
1466 | #define CS_EVEN_SECONDARY BIT(2) |
1467 | #define CS_ODD_SECONDARY BIT(3) | |
9f4873fb | 1468 | #define CS_3R_INTERLEAVE BIT(4) |
e53a3b26 | 1469 | |
81f5090d YG |
1470 | #define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY) |
1471 | #define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY) | |
e53a3b26 | 1472 | |
c0984666 | 1473 | static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) |
fc00c6a4 | 1474 | { |
9f4873fb | 1475 | u8 base, count = 0; |
e53a3b26 | 1476 | int cs_mode = 0; |
fc00c6a4 | 1477 | |
e53a3b26 YG |
1478 | if (csrow_enabled(2 * dimm, ctrl, pvt)) |
1479 | cs_mode |= CS_EVEN_PRIMARY; | |
fc00c6a4 | 1480 | |
e53a3b26 YG |
1481 | if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) |
1482 | cs_mode |= CS_ODD_PRIMARY; | |
1483 | ||
81f5090d YG |
1484 | /* Asymmetric dual-rank DIMM support. */ |
1485 | if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) | |
1486 | cs_mode |= CS_ODD_SECONDARY; | |
1487 | ||
9f4873fb YG |
1488 | /* |
1489 | * 3 Rank inteleaving support. | |
1490 | * There should be only three bases enabled and their two masks should | |
1491 | * be equal. | |
1492 | */ | |
1493 | for_each_chip_select(base, ctrl, pvt) | |
1494 | count += csrow_enabled(base, ctrl, pvt); | |
1495 | ||
1496 | if (count == 3 && | |
1497 | pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { | |
1498 | edac_dbg(1, "3R interleaving in use.\n"); | |
1499 | cs_mode |= CS_3R_INTERLEAVE; | |
1500 | } | |
1501 | ||
e53a3b26 | 1502 | return cs_mode; |
fc00c6a4 YG |
1503 | } |
1504 | ||
9c42edd5 M |
1505 | static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode, |
1506 | int csrow_nr, int dimm) | |
1507 | { | |
1508 | u32 msb, weight, num_zero_bits; | |
1509 | u32 addr_mask_deinterleaved; | |
1510 | int size = 0; | |
1511 | ||
1512 | /* | |
1513 | * The number of zero bits in the mask is equal to the number of bits | |
1514 | * in a full mask minus the number of bits in the current mask. | |
1515 | * | |
1516 | * The MSB is the number of bits in the full mask because BIT[0] is | |
1517 | * always 0. | |
1518 | * | |
1519 | * In the special 3 Rank interleaving case, a single bit is flipped | |
1520 | * without swapping with the most significant bit. This can be handled | |
1521 | * by keeping the MSB where it is and ignoring the single zero bit. | |
1522 | */ | |
1523 | msb = fls(addr_mask_orig) - 1; | |
1524 | weight = hweight_long(addr_mask_orig); | |
1525 | num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); | |
1526 | ||
1527 | /* Take the number of zero bits off from the top of the mask. */ | |
1528 | addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); | |
1529 | ||
1530 | edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm); | |
1531 | edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig); | |
1532 | edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved); | |
1533 | ||
1534 | /* Register [31:1] = Address [39:9]. Size is in kBs here. */ | |
1535 | size = (addr_mask_deinterleaved >> 2) + 1; | |
1536 | ||
1537 | /* Return size in MBs. */ | |
1538 | return size >> 10; | |
1539 | } | |
1540 | ||
a2e59ab8 YG |
1541 | static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, |
1542 | unsigned int cs_mode, int csrow_nr) | |
1543 | { | |
a2e59ab8 | 1544 | int cs_mask_nr = csrow_nr; |
9c42edd5 | 1545 | u32 addr_mask_orig; |
a2e59ab8 YG |
1546 | int dimm, size = 0; |
1547 | ||
1548 | /* No Chip Selects are enabled. */ | |
1549 | if (!cs_mode) | |
1550 | return size; | |
1551 | ||
1552 | /* Requested size of an even CS but none are enabled. */ | |
1553 | if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1)) | |
1554 | return size; | |
1555 | ||
1556 | /* Requested size of an odd CS but none are enabled. */ | |
1557 | if (!(cs_mode & CS_ODD) && (csrow_nr & 1)) | |
1558 | return size; | |
1559 | ||
1560 | /* | |
1561 | * Family 17h introduced systems with one mask per DIMM, | |
1562 | * and two Chip Selects per DIMM. | |
1563 | * | |
1564 | * CS0 and CS1 -> MASK0 / DIMM0 | |
1565 | * CS2 and CS3 -> MASK1 / DIMM1 | |
1566 | * | |
1567 | * Family 19h Model 10h introduced systems with one mask per Chip Select, | |
1568 | * and two Chip Selects per DIMM. | |
1569 | * | |
1570 | * CS0 -> MASK0 -> DIMM0 | |
1571 | * CS1 -> MASK1 -> DIMM0 | |
1572 | * CS2 -> MASK2 -> DIMM1 | |
1573 | * CS3 -> MASK3 -> DIMM1 | |
1574 | * | |
1575 | * Keep the mask number equal to the Chip Select number for newer systems, | |
1576 | * and shift the mask number for older systems. | |
1577 | */ | |
1578 | dimm = csrow_nr >> 1; | |
1579 | ||
ed623d55 | 1580 | if (!pvt->flags.zn_regs_v2) |
a2e59ab8 YG |
1581 | cs_mask_nr >>= 1; |
1582 | ||
1583 | /* Asymmetric dual-rank DIMM support. */ | |
1584 | if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY)) | |
1585 | addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; | |
1586 | else | |
1587 | addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; | |
1588 | ||
9c42edd5 | 1589 | return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm); |
a2e59ab8 YG |
1590 | } |
1591 | ||
00e4feb8 | 1592 | static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) |
07ed82ef | 1593 | { |
e53a3b26 | 1594 | int dimm, size0, size1, cs0, cs1, cs_mode; |
07ed82ef YG |
1595 | |
1596 | edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl); | |
1597 | ||
d971e28e | 1598 | for (dimm = 0; dimm < 2; dimm++) { |
eb77e6b8 | 1599 | cs0 = dimm * 2; |
eb77e6b8 YG |
1600 | cs1 = dimm * 2 + 1; |
1601 | ||
c0984666 | 1602 | cs_mode = umc_get_cs_mode(dimm, ctrl, pvt); |
e53a3b26 | 1603 | |
a2e59ab8 YG |
1604 | size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0); |
1605 | size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1); | |
07ed82ef YG |
1606 | |
1607 | amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n", | |
eb77e6b8 YG |
1608 | cs0, size0, |
1609 | cs1, size1); | |
07ed82ef YG |
1610 | } |
1611 | } | |
1612 | ||
f6f36382 | 1613 | static void umc_dump_misc_regs(struct amd64_pvt *pvt) |
07ed82ef YG |
1614 | { |
1615 | struct amd64_umc *umc; | |
1616 | u32 i, tmp, umc_base; | |
1617 | ||
4d30d2bc | 1618 | for_each_umc(i) { |
07ed82ef YG |
1619 | umc_base = get_umc_base(i); |
1620 | umc = &pvt->umc[i]; | |
1621 | ||
1622 | edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); | |
1623 | edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); | |
1624 | edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); | |
1625 | edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); | |
1626 | ||
1627 | amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); | |
1628 | edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp); | |
1629 | ||
1630 | amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); | |
1631 | edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp); | |
1632 | edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); | |
1633 | ||
1634 | edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n", | |
1635 | i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", | |
1636 | (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); | |
1637 | edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n", | |
1638 | i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); | |
1639 | edac_dbg(1, "UMC%d x4 DIMMs present: %s\n", | |
1640 | i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); | |
1641 | edac_dbg(1, "UMC%d x16 DIMMs present: %s\n", | |
1642 | i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); | |
1643 | ||
2151c84e YG |
1644 | if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) { |
1645 | amd_smn_read(pvt->mc_node_id, | |
ed623d55 | 1646 | umc_base + get_umc_reg(pvt, UMCCH_ADDR_CFG), |
2151c84e | 1647 | &tmp); |
07ed82ef YG |
1648 | edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n", |
1649 | i, 1 << ((tmp >> 4) & 0x3)); | |
1650 | } | |
1651 | ||
00e4feb8 | 1652 | umc_debug_display_dimm_sizes(pvt, i); |
07ed82ef | 1653 | } |
07ed82ef YG |
1654 | } |
1655 | ||
f6f36382 | 1656 | static void dct_dump_misc_regs(struct amd64_pvt *pvt) |
2da11654 | 1657 | { |
956b9ba1 | 1658 | edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
68798e17 | 1659 | |
956b9ba1 JP |
1660 | edac_dbg(1, " NB two channel DRAM capable: %s\n", |
1661 | (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); | |
2da11654 | 1662 | |
956b9ba1 JP |
1663 | edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n", |
1664 | (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", | |
1665 | (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); | |
68798e17 | 1666 | |
d1ea71cd | 1667 | debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); |
2da11654 | 1668 | |
956b9ba1 | 1669 | edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 1670 | |
956b9ba1 JP |
1671 | edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n", |
1672 | pvt->dhar, dhar_base(pvt), | |
a4b4bedc BP |
1673 | (pvt->fam == 0xf) ? k8_dhar_offset(pvt) |
1674 | : f10_dhar_offset(pvt)); | |
2da11654 | 1675 | |
00e4feb8 | 1676 | dct_debug_display_dimm_sizes(pvt, 0); |
4d796364 | 1677 | |
8de1d91e | 1678 | /* everything below this point is Fam10h and above */ |
a4b4bedc | 1679 | if (pvt->fam == 0xf) |
2da11654 | 1680 | return; |
4d796364 | 1681 | |
00e4feb8 | 1682 | dct_debug_display_dimm_sizes(pvt, 1); |
2da11654 | 1683 | |
8de1d91e | 1684 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 | 1685 | if (!dct_ganging_enabled(pvt)) |
d1ea71cd | 1686 | debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); |
cf981562 YG |
1687 | |
1688 | edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); | |
07ed82ef | 1689 | |
7835961d | 1690 | amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); |
07ed82ef YG |
1691 | } |
1692 | ||
94be4bff | 1693 | /* |
18b94f66 | 1694 | * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] |
94be4bff | 1695 | */ |
637f60ef | 1696 | static void dct_prep_chip_selects(struct amd64_pvt *pvt) |
94be4bff | 1697 | { |
18b94f66 | 1698 | if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
1699 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
1700 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; | |
a597d2a5 | 1701 | } else if (pvt->fam == 0x15 && pvt->model == 0x30) { |
18b94f66 AG |
1702 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; |
1703 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; | |
9d858bb1 | 1704 | } else { |
11c75ead BP |
1705 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
1706 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; | |
94be4bff DT |
1707 | } |
1708 | } | |
1709 | ||
637f60ef M |
1710 | static void umc_prep_chip_selects(struct amd64_pvt *pvt) |
1711 | { | |
1712 | int umc; | |
1713 | ||
1714 | for_each_umc(umc) { | |
1715 | pvt->csels[umc].b_cnt = 4; | |
1716 | pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2; | |
1717 | } | |
1718 | } | |
1719 | ||
b29dad9b | 1720 | static void umc_read_base_mask(struct amd64_pvt *pvt) |
d971e28e | 1721 | { |
7574729e YG |
1722 | u32 umc_base_reg, umc_base_reg_sec; |
1723 | u32 umc_mask_reg, umc_mask_reg_sec; | |
1724 | u32 base_reg, base_reg_sec; | |
1725 | u32 mask_reg, mask_reg_sec; | |
1726 | u32 *base, *base_sec; | |
1727 | u32 *mask, *mask_sec; | |
d971e28e YG |
1728 | int cs, umc; |
1729 | ||
1730 | for_each_umc(umc) { | |
1731 | umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR; | |
7574729e | 1732 | umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC; |
d971e28e YG |
1733 | |
1734 | for_each_chip_select(cs, umc, pvt) { | |
1735 | base = &pvt->csels[umc].csbases[cs]; | |
7574729e | 1736 | base_sec = &pvt->csels[umc].csbases_sec[cs]; |
d971e28e YG |
1737 | |
1738 | base_reg = umc_base_reg + (cs * 4); | |
7574729e | 1739 | base_reg_sec = umc_base_reg_sec + (cs * 4); |
d971e28e YG |
1740 | |
1741 | if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) | |
1742 | edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n", | |
1743 | umc, cs, *base, base_reg); | |
7574729e YG |
1744 | |
1745 | if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) | |
1746 | edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n", | |
1747 | umc, cs, *base_sec, base_reg_sec); | |
d971e28e YG |
1748 | } |
1749 | ||
1750 | umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK; | |
ed623d55 | 1751 | umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(pvt, UMCCH_ADDR_MASK_SEC); |
d971e28e YG |
1752 | |
1753 | for_each_chip_select_mask(cs, umc, pvt) { | |
1754 | mask = &pvt->csels[umc].csmasks[cs]; | |
7574729e | 1755 | mask_sec = &pvt->csels[umc].csmasks_sec[cs]; |
d971e28e YG |
1756 | |
1757 | mask_reg = umc_mask_reg + (cs * 4); | |
7574729e | 1758 | mask_reg_sec = umc_mask_reg_sec + (cs * 4); |
d971e28e YG |
1759 | |
1760 | if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) | |
1761 | edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n", | |
1762 | umc, cs, *mask, mask_reg); | |
7574729e YG |
1763 | |
1764 | if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) | |
1765 | edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n", | |
1766 | umc, cs, *mask_sec, mask_reg_sec); | |
d971e28e YG |
1767 | } |
1768 | } | |
1769 | } | |
1770 | ||
94be4bff | 1771 | /* |
11c75ead | 1772 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers |
94be4bff | 1773 | */ |
b29dad9b | 1774 | static void dct_read_base_mask(struct amd64_pvt *pvt) |
94be4bff | 1775 | { |
d971e28e | 1776 | int cs; |
94be4bff | 1777 | |
11c75ead | 1778 | for_each_chip_select(cs, 0, pvt) { |
d971e28e YG |
1779 | int reg0 = DCSB0 + (cs * 4); |
1780 | int reg1 = DCSB1 + (cs * 4); | |
11c75ead BP |
1781 | u32 *base0 = &pvt->csels[0].csbases[cs]; |
1782 | u32 *base1 = &pvt->csels[1].csbases[cs]; | |
b2b0c605 | 1783 | |
d971e28e YG |
1784 | if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) |
1785 | edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n", | |
1786 | cs, *base0, reg0); | |
8de9930a | 1787 | |
d971e28e YG |
1788 | if (pvt->fam == 0xf) |
1789 | continue; | |
b64ce7cd | 1790 | |
d971e28e YG |
1791 | if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) |
1792 | edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n", | |
1793 | cs, *base1, (pvt->fam == 0x10) ? reg1 | |
1794 | : reg0); | |
94be4bff DT |
1795 | } |
1796 | ||
11c75ead | 1797 | for_each_chip_select_mask(cs, 0, pvt) { |
d971e28e YG |
1798 | int reg0 = DCSM0 + (cs * 4); |
1799 | int reg1 = DCSM1 + (cs * 4); | |
11c75ead BP |
1800 | u32 *mask0 = &pvt->csels[0].csmasks[cs]; |
1801 | u32 *mask1 = &pvt->csels[1].csmasks[cs]; | |
b2b0c605 | 1802 | |
d971e28e YG |
1803 | if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) |
1804 | edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n", | |
1805 | cs, *mask0, reg0); | |
b64ce7cd | 1806 | |
d971e28e YG |
1807 | if (pvt->fam == 0xf) |
1808 | continue; | |
8de9930a | 1809 | |
d971e28e YG |
1810 | if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) |
1811 | edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n", | |
1812 | cs, *mask1, (pvt->fam == 0x10) ? reg1 | |
1813 | : reg0); | |
94be4bff DT |
1814 | } |
1815 | } | |
1816 | ||
78ec161a | 1817 | static void umc_determine_memory_type(struct amd64_pvt *pvt) |
94be4bff | 1818 | { |
75aeaaf2 YG |
1819 | struct amd64_umc *umc; |
1820 | u32 i; | |
94be4bff | 1821 | |
75aeaaf2 YG |
1822 | for_each_umc(i) { |
1823 | umc = &pvt->umc[i]; | |
1824 | ||
1825 | if (!(umc->sdp_ctrl & UMC_SDP_INIT)) { | |
1826 | umc->dram_type = MEM_EMPTY; | |
1827 | continue; | |
1828 | } | |
1829 | ||
2151c84e YG |
1830 | /* |
1831 | * Check if the system supports the "DDR Type" field in UMC Config | |
1832 | * and has DDR5 DIMMs in use. | |
1833 | */ | |
ed623d55 | 1834 | if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { |
2151c84e YG |
1835 | if (umc->dimm_cfg & BIT(5)) |
1836 | umc->dram_type = MEM_LRDDR5; | |
1837 | else if (umc->dimm_cfg & BIT(4)) | |
1838 | umc->dram_type = MEM_RDDR5; | |
1839 | else | |
1840 | umc->dram_type = MEM_DDR5; | |
1841 | } else { | |
1842 | if (umc->dimm_cfg & BIT(5)) | |
1843 | umc->dram_type = MEM_LRDDR4; | |
1844 | else if (umc->dimm_cfg & BIT(4)) | |
1845 | umc->dram_type = MEM_RDDR4; | |
1846 | else | |
1847 | umc->dram_type = MEM_DDR4; | |
1848 | } | |
75aeaaf2 YG |
1849 | |
1850 | edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); | |
dcd01394 | 1851 | } |
75aeaaf2 YG |
1852 | } |
1853 | ||
78ec161a | 1854 | static void dct_determine_memory_type(struct amd64_pvt *pvt) |
75aeaaf2 YG |
1855 | { |
1856 | u32 dram_ctrl, dcsm; | |
1857 | ||
a597d2a5 AG |
1858 | switch (pvt->fam) { |
1859 | case 0xf: | |
1860 | if (pvt->ext_model >= K8_REV_F) | |
1861 | goto ddr3; | |
1862 | ||
1863 | pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; | |
1864 | return; | |
1865 | ||
1866 | case 0x10: | |
6b4c0bde | 1867 | if (pvt->dchr0 & DDR3_MODE) |
a597d2a5 AG |
1868 | goto ddr3; |
1869 | ||
1870 | pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
1871 | return; | |
1872 | ||
1873 | case 0x15: | |
1874 | if (pvt->model < 0x60) | |
1875 | goto ddr3; | |
1876 | ||
1877 | /* | |
1878 | * Model 0x60h needs special handling: | |
1879 | * | |
1880 | * We use a Chip Select value of '0' to obtain dcsm. | |
1881 | * Theoretically, it is possible to populate LRDIMMs of different | |
1882 | * 'Rank' value on a DCT. But this is not the common case. So, | |
1883 | * it's reasonable to assume all DIMMs are going to be of same | |
1884 | * 'type' until proven otherwise. | |
1885 | */ | |
1886 | amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); | |
1887 | dcsm = pvt->csels[0].csmasks[0]; | |
1888 | ||
1889 | if (((dram_ctrl >> 8) & 0x7) == 0x2) | |
1890 | pvt->dram_type = MEM_DDR4; | |
1891 | else if (pvt->dclr0 & BIT(16)) | |
1892 | pvt->dram_type = MEM_DDR3; | |
1893 | else if (dcsm & 0x3) | |
1894 | pvt->dram_type = MEM_LRDDR3; | |
6b4c0bde | 1895 | else |
a597d2a5 | 1896 | pvt->dram_type = MEM_RDDR3; |
94be4bff | 1897 | |
a597d2a5 AG |
1898 | return; |
1899 | ||
1900 | case 0x16: | |
1901 | goto ddr3; | |
1902 | ||
1903 | default: | |
1904 | WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); | |
1905 | pvt->dram_type = MEM_EMPTY; | |
1906 | } | |
78ec161a M |
1907 | |
1908 | edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); | |
a597d2a5 | 1909 | return; |
94be4bff | 1910 | |
a597d2a5 AG |
1911 | ddr3: |
1912 | pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
94be4bff DT |
1913 | } |
1914 | ||
70046624 | 1915 | /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ |
a4b4bedc | 1916 | static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) |
ddff876d | 1917 | { |
db970bd2 | 1918 | u16 mce_nid = topology_die_id(m->extcpu); |
2ec591ac | 1919 | struct mem_ctl_info *mci; |
70046624 BP |
1920 | u8 start_bit = 1; |
1921 | u8 end_bit = 47; | |
2ec591ac BP |
1922 | u64 addr; |
1923 | ||
1924 | mci = edac_mc_find(mce_nid); | |
1925 | if (!mci) | |
1926 | return 0; | |
1927 | ||
1928 | pvt = mci->pvt_info; | |
70046624 | 1929 | |
a4b4bedc | 1930 | if (pvt->fam == 0xf) { |
70046624 BP |
1931 | start_bit = 3; |
1932 | end_bit = 39; | |
1933 | } | |
1934 | ||
10ef6b0d | 1935 | addr = m->addr & GENMASK_ULL(end_bit, start_bit); |
c1ae6830 BP |
1936 | |
1937 | /* | |
1938 | * Erratum 637 workaround | |
1939 | */ | |
a4b4bedc | 1940 | if (pvt->fam == 0x15) { |
c1ae6830 BP |
1941 | u64 cc6_base, tmp_addr; |
1942 | u32 tmp; | |
8b84c8df | 1943 | u8 intlv_en; |
c1ae6830 | 1944 | |
10ef6b0d | 1945 | if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7) |
c1ae6830 BP |
1946 | return addr; |
1947 | ||
c1ae6830 BP |
1948 | |
1949 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); | |
1950 | intlv_en = tmp >> 21 & 0x7; | |
1951 | ||
1952 | /* add [47:27] + 3 trailing bits */ | |
10ef6b0d | 1953 | cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3; |
c1ae6830 BP |
1954 | |
1955 | /* reverse and add DramIntlvEn */ | |
1956 | cc6_base |= intlv_en ^ 0x7; | |
1957 | ||
1958 | /* pin at [47:24] */ | |
1959 | cc6_base <<= 24; | |
1960 | ||
1961 | if (!intlv_en) | |
10ef6b0d | 1962 | return cc6_base | (addr & GENMASK_ULL(23, 0)); |
c1ae6830 BP |
1963 | |
1964 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); | |
1965 | ||
1966 | /* faster log2 */ | |
10ef6b0d | 1967 | tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1); |
c1ae6830 BP |
1968 | |
1969 | /* OR DramIntlvSel into bits [14:12] */ | |
10ef6b0d | 1970 | tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9; |
c1ae6830 BP |
1971 | |
1972 | /* add remaining [11:0] bits from original MC4_ADDR */ | |
10ef6b0d | 1973 | tmp_addr |= addr & GENMASK_ULL(11, 0); |
c1ae6830 BP |
1974 | |
1975 | return cc6_base | tmp_addr; | |
1976 | } | |
1977 | ||
1978 | return addr; | |
ddff876d DT |
1979 | } |
1980 | ||
e2c0bffe DB |
1981 | static struct pci_dev *pci_get_related_function(unsigned int vendor, |
1982 | unsigned int device, | |
1983 | struct pci_dev *related) | |
1984 | { | |
1985 | struct pci_dev *dev = NULL; | |
1986 | ||
1987 | while ((dev = pci_get_device(vendor, device, dev))) { | |
1988 | if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) && | |
1989 | (dev->bus->number == related->bus->number) && | |
1990 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1991 | break; | |
1992 | } | |
1993 | ||
1994 | return dev; | |
1995 | } | |
1996 | ||
7f19bf75 | 1997 | static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) |
ddff876d | 1998 | { |
e2c0bffe | 1999 | struct amd_northbridge *nb; |
18b94f66 AG |
2000 | struct pci_dev *f1 = NULL; |
2001 | unsigned int pci_func; | |
71d2a32e | 2002 | int off = range << 3; |
e2c0bffe | 2003 | u32 llim; |
ddff876d | 2004 | |
7f19bf75 BP |
2005 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); |
2006 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); | |
ddff876d | 2007 | |
18b94f66 | 2008 | if (pvt->fam == 0xf) |
7f19bf75 | 2009 | return; |
ddff876d | 2010 | |
7f19bf75 BP |
2011 | if (!dram_rw(pvt, range)) |
2012 | return; | |
ddff876d | 2013 | |
7f19bf75 BP |
2014 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); |
2015 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); | |
f08e457c | 2016 | |
e2c0bffe | 2017 | /* F15h: factor in CC6 save area by reading dst node's limit reg */ |
18b94f66 | 2018 | if (pvt->fam != 0x15) |
e2c0bffe | 2019 | return; |
f08e457c | 2020 | |
e2c0bffe DB |
2021 | nb = node_to_amd_nb(dram_dst_node(pvt, range)); |
2022 | if (WARN_ON(!nb)) | |
2023 | return; | |
f08e457c | 2024 | |
a597d2a5 AG |
2025 | if (pvt->model == 0x60) |
2026 | pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; | |
2027 | else if (pvt->model == 0x30) | |
2028 | pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; | |
2029 | else | |
2030 | pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1; | |
18b94f66 AG |
2031 | |
2032 | f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc); | |
e2c0bffe DB |
2033 | if (WARN_ON(!f1)) |
2034 | return; | |
f08e457c | 2035 | |
e2c0bffe | 2036 | amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim); |
f08e457c | 2037 | |
10ef6b0d | 2038 | pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); |
f08e457c | 2039 | |
e2c0bffe DB |
2040 | /* {[39:27],111b} */ |
2041 | pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; | |
f08e457c | 2042 | |
10ef6b0d | 2043 | pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); |
f08e457c | 2044 | |
e2c0bffe DB |
2045 | /* [47:40] */ |
2046 | pvt->ranges[range].lim.hi |= llim >> 13; | |
2047 | ||
2048 | pci_dev_put(f1); | |
ddff876d DT |
2049 | } |
2050 | ||
f192c7b1 | 2051 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 2052 | struct err_info *err) |
ddff876d | 2053 | { |
f192c7b1 | 2054 | struct amd64_pvt *pvt = mci->pvt_info; |
ddff876d | 2055 | |
33ca0643 | 2056 | error_address_to_page_and_offset(sys_addr, err); |
ab5a503c MCC |
2057 | |
2058 | /* | |
2059 | * Find out which node the error address belongs to. This may be | |
2060 | * different from the node that detected the error. | |
2061 | */ | |
33ca0643 BP |
2062 | err->src_mci = find_mc_by_sys_addr(mci, sys_addr); |
2063 | if (!err->src_mci) { | |
ab5a503c MCC |
2064 | amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n", |
2065 | (unsigned long)sys_addr); | |
33ca0643 | 2066 | err->err_code = ERR_NODE; |
ab5a503c MCC |
2067 | return; |
2068 | } | |
2069 | ||
2070 | /* Now map the sys_addr to a CSROW */ | |
33ca0643 BP |
2071 | err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); |
2072 | if (err->csrow < 0) { | |
2073 | err->err_code = ERR_CSROW; | |
ab5a503c MCC |
2074 | return; |
2075 | } | |
2076 | ||
ddff876d | 2077 | /* CHIPKILL enabled */ |
f192c7b1 | 2078 | if (pvt->nbcfg & NBCFG_CHIPKILL) { |
33ca0643 BP |
2079 | err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); |
2080 | if (err->channel < 0) { | |
ddff876d DT |
2081 | /* |
2082 | * Syndrome didn't map, so we don't know which of the | |
2083 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
2084 | * as suspect. | |
2085 | */ | |
33ca0643 | 2086 | amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " |
ab5a503c | 2087 | "possible error reporting race\n", |
33ca0643 BP |
2088 | err->syndrome); |
2089 | err->err_code = ERR_CHANNEL; | |
ddff876d DT |
2090 | return; |
2091 | } | |
2092 | } else { | |
2093 | /* | |
2094 | * non-chipkill ecc mode | |
2095 | * | |
2096 | * The k8 documentation is unclear about how to determine the | |
2097 | * channel number when using non-chipkill memory. This method | |
2098 | * was obtained from email communication with someone at AMD. | |
2099 | * (Wish the email was placed in this comment - norsk) | |
2100 | */ | |
33ca0643 | 2101 | err->channel = ((sys_addr & BIT(3)) != 0); |
ddff876d | 2102 | } |
ddff876d DT |
2103 | } |
2104 | ||
41d8bfab | 2105 | static int ddr2_cs_size(unsigned i, bool dct_width) |
ddff876d | 2106 | { |
41d8bfab | 2107 | unsigned shift = 0; |
ddff876d | 2108 | |
41d8bfab BP |
2109 | if (i <= 2) |
2110 | shift = i; | |
2111 | else if (!(i & 0x1)) | |
2112 | shift = i >> 1; | |
1433eb99 | 2113 | else |
41d8bfab | 2114 | shift = (i + 1) >> 1; |
ddff876d | 2115 | |
41d8bfab BP |
2116 | return 128 << (shift + !!dct_width); |
2117 | } | |
2118 | ||
2119 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
a597d2a5 | 2120 | unsigned cs_mode, int cs_mask_nr) |
41d8bfab BP |
2121 | { |
2122 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
2123 | ||
2124 | if (pvt->ext_model >= K8_REV_F) { | |
2125 | WARN_ON(cs_mode > 11); | |
2126 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); | |
2127 | } | |
2128 | else if (pvt->ext_model >= K8_REV_D) { | |
11b0a314 | 2129 | unsigned diff; |
41d8bfab BP |
2130 | WARN_ON(cs_mode > 10); |
2131 | ||
11b0a314 BP |
2132 | /* |
2133 | * the below calculation, besides trying to win an obfuscated C | |
2134 | * contest, maps cs_mode values to DIMM chip select sizes. The | |
2135 | * mappings are: | |
2136 | * | |
2137 | * cs_mode CS size (mb) | |
2138 | * ======= ============ | |
2139 | * 0 32 | |
2140 | * 1 64 | |
2141 | * 2 128 | |
2142 | * 3 128 | |
2143 | * 4 256 | |
2144 | * 5 512 | |
2145 | * 6 256 | |
2146 | * 7 512 | |
2147 | * 8 1024 | |
2148 | * 9 1024 | |
2149 | * 10 2048 | |
2150 | * | |
2151 | * Basically, it calculates a value with which to shift the | |
2152 | * smallest CS size of 32MB. | |
2153 | * | |
2154 | * ddr[23]_cs_size have a similar purpose. | |
2155 | */ | |
2156 | diff = cs_mode/3 + (unsigned)(cs_mode > 5); | |
2157 | ||
2158 | return 32 << (cs_mode - diff); | |
41d8bfab BP |
2159 | } |
2160 | else { | |
2161 | WARN_ON(cs_mode > 6); | |
2162 | return 32 << cs_mode; | |
2163 | } | |
ddff876d DT |
2164 | } |
2165 | ||
41d8bfab | 2166 | static int ddr3_cs_size(unsigned i, bool dct_width) |
1afd3c98 | 2167 | { |
41d8bfab BP |
2168 | unsigned shift = 0; |
2169 | int cs_size = 0; | |
2170 | ||
2171 | if (i == 0 || i == 3 || i == 4) | |
2172 | cs_size = -1; | |
2173 | else if (i <= 2) | |
2174 | shift = i; | |
2175 | else if (i == 12) | |
2176 | shift = 7; | |
2177 | else if (!(i & 0x1)) | |
2178 | shift = i >> 1; | |
2179 | else | |
2180 | shift = (i + 1) >> 1; | |
2181 | ||
2182 | if (cs_size != -1) | |
2183 | cs_size = (128 * (1 << !!dct_width)) << shift; | |
2184 | ||
2185 | return cs_size; | |
2186 | } | |
2187 | ||
a597d2a5 AG |
2188 | static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply) |
2189 | { | |
2190 | unsigned shift = 0; | |
2191 | int cs_size = 0; | |
2192 | ||
2193 | if (i < 4 || i == 6) | |
2194 | cs_size = -1; | |
2195 | else if (i == 12) | |
2196 | shift = 7; | |
2197 | else if (!(i & 0x1)) | |
2198 | shift = i >> 1; | |
2199 | else | |
2200 | shift = (i + 1) >> 1; | |
2201 | ||
2202 | if (cs_size != -1) | |
2203 | cs_size = rank_multiply * (128 << shift); | |
2204 | ||
2205 | return cs_size; | |
2206 | } | |
2207 | ||
2208 | static int ddr4_cs_size(unsigned i) | |
2209 | { | |
2210 | int cs_size = 0; | |
2211 | ||
2212 | if (i == 0) | |
2213 | cs_size = -1; | |
2214 | else if (i == 1) | |
2215 | cs_size = 1024; | |
2216 | else | |
2217 | /* Min cs_size = 1G */ | |
2218 | cs_size = 1024 * (1 << (i >> 1)); | |
2219 | ||
2220 | return cs_size; | |
2221 | } | |
2222 | ||
41d8bfab | 2223 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, |
a597d2a5 | 2224 | unsigned cs_mode, int cs_mask_nr) |
41d8bfab BP |
2225 | { |
2226 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
2227 | ||
2228 | WARN_ON(cs_mode > 11); | |
1433eb99 BP |
2229 | |
2230 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
41d8bfab | 2231 | return ddr3_cs_size(cs_mode, dclr & WIDTH_128); |
1433eb99 | 2232 | else |
41d8bfab BP |
2233 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); |
2234 | } | |
2235 | ||
2236 | /* | |
2237 | * F15h supports only 64bit DCT interfaces | |
2238 | */ | |
2239 | static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
a597d2a5 | 2240 | unsigned cs_mode, int cs_mask_nr) |
41d8bfab BP |
2241 | { |
2242 | WARN_ON(cs_mode > 12); | |
1433eb99 | 2243 | |
41d8bfab | 2244 | return ddr3_cs_size(cs_mode, false); |
1afd3c98 DT |
2245 | } |
2246 | ||
a597d2a5 AG |
2247 | /* F15h M60h supports DDR4 mapping as well.. */ |
2248 | static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
2249 | unsigned cs_mode, int cs_mask_nr) | |
2250 | { | |
2251 | int cs_size; | |
2252 | u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; | |
2253 | ||
2254 | WARN_ON(cs_mode > 12); | |
2255 | ||
2256 | if (pvt->dram_type == MEM_DDR4) { | |
2257 | if (cs_mode > 9) | |
2258 | return -1; | |
2259 | ||
2260 | cs_size = ddr4_cs_size(cs_mode); | |
2261 | } else if (pvt->dram_type == MEM_LRDDR3) { | |
2262 | unsigned rank_multiply = dcsm & 0xf; | |
2263 | ||
2264 | if (rank_multiply == 3) | |
2265 | rank_multiply = 4; | |
2266 | cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply); | |
2267 | } else { | |
2268 | /* Minimum cs size is 512mb for F15hM60h*/ | |
2269 | if (cs_mode == 0x1) | |
2270 | return -1; | |
2271 | ||
2272 | cs_size = ddr3_cs_size(cs_mode, false); | |
2273 | } | |
2274 | ||
2275 | return cs_size; | |
2276 | } | |
2277 | ||
94c1acf2 | 2278 | /* |
18b94f66 | 2279 | * F16h and F15h model 30h have only limited cs_modes. |
94c1acf2 AG |
2280 | */ |
2281 | static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
a597d2a5 | 2282 | unsigned cs_mode, int cs_mask_nr) |
94c1acf2 AG |
2283 | { |
2284 | WARN_ON(cs_mode > 12); | |
2285 | ||
2286 | if (cs_mode == 6 || cs_mode == 8 || | |
2287 | cs_mode == 9 || cs_mode == 12) | |
2288 | return -1; | |
2289 | else | |
2290 | return ddr3_cs_size(cs_mode, false); | |
2291 | } | |
2292 | ||
5a5d2371 | 2293 | static void read_dram_ctl_register(struct amd64_pvt *pvt) |
6163b5d4 | 2294 | { |
6163b5d4 | 2295 | |
a4b4bedc | 2296 | if (pvt->fam == 0xf) |
5a5d2371 BP |
2297 | return; |
2298 | ||
7981a28f | 2299 | if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { |
956b9ba1 JP |
2300 | edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n", |
2301 | pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); | |
72381bd5 | 2302 | |
956b9ba1 JP |
2303 | edac_dbg(0, " DCTs operate in %s mode\n", |
2304 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); | |
72381bd5 BP |
2305 | |
2306 | if (!dct_ganging_enabled(pvt)) | |
956b9ba1 JP |
2307 | edac_dbg(0, " Address range split per DCT: %s\n", |
2308 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
72381bd5 | 2309 | |
956b9ba1 JP |
2310 | edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n", |
2311 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
2312 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
72381bd5 | 2313 | |
956b9ba1 JP |
2314 | edac_dbg(0, " channel interleave: %s, " |
2315 | "interleave bits selector: 0x%x\n", | |
2316 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), | |
2317 | dct_sel_interleave_addr(pvt)); | |
6163b5d4 DT |
2318 | } |
2319 | ||
7981a28f | 2320 | amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); |
6163b5d4 DT |
2321 | } |
2322 | ||
18b94f66 AG |
2323 | /* |
2324 | * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG, | |
2325 | * 2.10.12 Memory Interleaving Modes). | |
2326 | */ | |
2327 | static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, | |
2328 | u8 intlv_en, int num_dcts_intlv, | |
2329 | u32 dct_sel) | |
2330 | { | |
2331 | u8 channel = 0; | |
2332 | u8 select; | |
2333 | ||
2334 | if (!(intlv_en)) | |
2335 | return (u8)(dct_sel); | |
2336 | ||
2337 | if (num_dcts_intlv == 2) { | |
2338 | select = (sys_addr >> 8) & 0x3; | |
2339 | channel = select ? 0x3 : 0; | |
9d0e8d83 AG |
2340 | } else if (num_dcts_intlv == 4) { |
2341 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
2342 | switch (intlv_addr) { | |
2343 | case 0x4: | |
2344 | channel = (sys_addr >> 8) & 0x3; | |
2345 | break; | |
2346 | case 0x5: | |
2347 | channel = (sys_addr >> 9) & 0x3; | |
2348 | break; | |
2349 | } | |
2350 | } | |
18b94f66 AG |
2351 | return channel; |
2352 | } | |
2353 | ||
f71d0a05 | 2354 | /* |
229a7a11 | 2355 | * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory |
f71d0a05 DT |
2356 | * Interleaving Modes. |
2357 | */ | |
b15f0fca | 2358 | static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
229a7a11 | 2359 | bool hi_range_sel, u8 intlv_en) |
6163b5d4 | 2360 | { |
151fa71c | 2361 | u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; |
6163b5d4 DT |
2362 | |
2363 | if (dct_ganging_enabled(pvt)) | |
229a7a11 | 2364 | return 0; |
6163b5d4 | 2365 | |
229a7a11 BP |
2366 | if (hi_range_sel) |
2367 | return dct_sel_high; | |
6163b5d4 | 2368 | |
229a7a11 BP |
2369 | /* |
2370 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
2371 | */ | |
2372 | if (dct_interleave_enabled(pvt)) { | |
2373 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
2374 | ||
2375 | /* return DCT select function: 0=DCT0, 1=DCT1 */ | |
2376 | if (!intlv_addr) | |
2377 | return sys_addr >> 6 & 1; | |
2378 | ||
2379 | if (intlv_addr & 0x2) { | |
2380 | u8 shift = intlv_addr & 0x1 ? 9 : 6; | |
dc0a50a8 | 2381 | u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1; |
229a7a11 BP |
2382 | |
2383 | return ((sys_addr >> shift) & 1) ^ temp; | |
2384 | } | |
2385 | ||
dc0a50a8 YG |
2386 | if (intlv_addr & 0x4) { |
2387 | u8 shift = intlv_addr & 0x1 ? 9 : 8; | |
2388 | ||
2389 | return (sys_addr >> shift) & 1; | |
2390 | } | |
2391 | ||
229a7a11 BP |
2392 | return (sys_addr >> (12 + hweight8(intlv_en))) & 1; |
2393 | } | |
2394 | ||
2395 | if (dct_high_range_enabled(pvt)) | |
2396 | return ~dct_sel_high & 1; | |
6163b5d4 DT |
2397 | |
2398 | return 0; | |
2399 | } | |
2400 | ||
c8e518d5 | 2401 | /* Convert the sys_addr to the normalized DCT address */ |
c7e5301a | 2402 | static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, |
c8e518d5 BP |
2403 | u64 sys_addr, bool hi_rng, |
2404 | u32 dct_sel_base_addr) | |
6163b5d4 DT |
2405 | { |
2406 | u64 chan_off; | |
c8e518d5 BP |
2407 | u64 dram_base = get_dram_base(pvt, range); |
2408 | u64 hole_off = f10_dhar_offset(pvt); | |
6f3508f6 | 2409 | u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; |
6163b5d4 | 2410 | |
c8e518d5 BP |
2411 | if (hi_rng) { |
2412 | /* | |
2413 | * if | |
2414 | * base address of high range is below 4Gb | |
2415 | * (bits [47:27] at [31:11]) | |
2416 | * DRAM address space on this DCT is hoisted above 4Gb && | |
2417 | * sys_addr > 4Gb | |
2418 | * | |
2419 | * remove hole offset from sys_addr | |
2420 | * else | |
2421 | * remove high range offset from sys_addr | |
2422 | */ | |
2423 | if ((!(dct_sel_base_addr >> 16) || | |
2424 | dct_sel_base_addr < dhar_base(pvt)) && | |
972ea17a | 2425 | dhar_valid(pvt) && |
c8e518d5 | 2426 | (sys_addr >= BIT_64(32))) |
bc21fa57 | 2427 | chan_off = hole_off; |
6163b5d4 DT |
2428 | else |
2429 | chan_off = dct_sel_base_off; | |
2430 | } else { | |
c8e518d5 BP |
2431 | /* |
2432 | * if | |
2433 | * we have a valid hole && | |
2434 | * sys_addr > 4Gb | |
2435 | * | |
2436 | * remove hole | |
2437 | * else | |
2438 | * remove dram base to normalize to DCT address | |
2439 | */ | |
972ea17a | 2440 | if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) |
bc21fa57 | 2441 | chan_off = hole_off; |
6163b5d4 | 2442 | else |
c8e518d5 | 2443 | chan_off = dram_base; |
6163b5d4 DT |
2444 | } |
2445 | ||
10ef6b0d | 2446 | return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); |
6163b5d4 DT |
2447 | } |
2448 | ||
6163b5d4 DT |
2449 | /* |
2450 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
2451 | * spare row | |
2452 | */ | |
11c75ead | 2453 | static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) |
6163b5d4 | 2454 | { |
614ec9d8 BP |
2455 | int tmp_cs; |
2456 | ||
2457 | if (online_spare_swap_done(pvt, dct) && | |
2458 | csrow == online_spare_bad_dramcs(pvt, dct)) { | |
2459 | ||
2460 | for_each_chip_select(tmp_cs, dct, pvt) { | |
2461 | if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { | |
2462 | csrow = tmp_cs; | |
2463 | break; | |
2464 | } | |
2465 | } | |
6163b5d4 DT |
2466 | } |
2467 | return csrow; | |
2468 | } | |
2469 | ||
2470 | /* | |
2471 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
2472 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
2473 | * | |
2474 | * Return: | |
2475 | * -EINVAL: NOT FOUND | |
2476 | * 0..csrow = Chip-Select Row | |
2477 | */ | |
c7e5301a | 2478 | static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct) |
6163b5d4 DT |
2479 | { |
2480 | struct mem_ctl_info *mci; | |
2481 | struct amd64_pvt *pvt; | |
11c75ead | 2482 | u64 cs_base, cs_mask; |
6163b5d4 DT |
2483 | int cs_found = -EINVAL; |
2484 | int csrow; | |
2485 | ||
2ec591ac | 2486 | mci = edac_mc_find(nid); |
6163b5d4 DT |
2487 | if (!mci) |
2488 | return cs_found; | |
2489 | ||
2490 | pvt = mci->pvt_info; | |
2491 | ||
956b9ba1 | 2492 | edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct); |
6163b5d4 | 2493 | |
11c75ead BP |
2494 | for_each_chip_select(csrow, dct, pvt) { |
2495 | if (!csrow_enabled(csrow, dct, pvt)) | |
6163b5d4 DT |
2496 | continue; |
2497 | ||
11c75ead | 2498 | get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); |
6163b5d4 | 2499 | |
956b9ba1 JP |
2500 | edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n", |
2501 | csrow, cs_base, cs_mask); | |
6163b5d4 | 2502 | |
11c75ead | 2503 | cs_mask = ~cs_mask; |
6163b5d4 | 2504 | |
956b9ba1 JP |
2505 | edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n", |
2506 | (in_addr & cs_mask), (cs_base & cs_mask)); | |
6163b5d4 | 2507 | |
11c75ead | 2508 | if ((in_addr & cs_mask) == (cs_base & cs_mask)) { |
18b94f66 AG |
2509 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { |
2510 | cs_found = csrow; | |
2511 | break; | |
2512 | } | |
11c75ead | 2513 | cs_found = f10_process_possible_spare(pvt, dct, csrow); |
6163b5d4 | 2514 | |
956b9ba1 | 2515 | edac_dbg(1, " MATCH csrow=%d\n", cs_found); |
6163b5d4 DT |
2516 | break; |
2517 | } | |
2518 | } | |
2519 | return cs_found; | |
2520 | } | |
2521 | ||
95b0ef55 BP |
2522 | /* |
2523 | * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is | |
2524 | * swapped with a region located at the bottom of memory so that the GPU can use | |
2525 | * the interleaved region and thus two channels. | |
2526 | */ | |
b15f0fca | 2527 | static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) |
95b0ef55 BP |
2528 | { |
2529 | u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr; | |
2530 | ||
a4b4bedc | 2531 | if (pvt->fam == 0x10) { |
95b0ef55 | 2532 | /* only revC3 and revE have that feature */ |
a4b4bedc | 2533 | if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) |
95b0ef55 BP |
2534 | return sys_addr; |
2535 | } | |
2536 | ||
7981a28f | 2537 | amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); |
95b0ef55 BP |
2538 | |
2539 | if (!(swap_reg & 0x1)) | |
2540 | return sys_addr; | |
2541 | ||
2542 | swap_base = (swap_reg >> 3) & 0x7f; | |
2543 | swap_limit = (swap_reg >> 11) & 0x7f; | |
2544 | rgn_size = (swap_reg >> 20) & 0x7f; | |
2545 | tmp_addr = sys_addr >> 27; | |
2546 | ||
2547 | if (!(sys_addr >> 34) && | |
2548 | (((tmp_addr >= swap_base) && | |
2549 | (tmp_addr <= swap_limit)) || | |
2550 | (tmp_addr < rgn_size))) | |
2551 | return sys_addr ^ (u64)swap_base << 27; | |
2552 | ||
2553 | return sys_addr; | |
2554 | } | |
2555 | ||
f71d0a05 | 2556 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
e761359a | 2557 | static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, |
33ca0643 | 2558 | u64 sys_addr, int *chan_sel) |
f71d0a05 | 2559 | { |
229a7a11 | 2560 | int cs_found = -EINVAL; |
c8e518d5 | 2561 | u64 chan_addr; |
5d4b58e8 | 2562 | u32 dct_sel_base; |
11c75ead | 2563 | u8 channel; |
229a7a11 | 2564 | bool high_range = false; |
f71d0a05 | 2565 | |
7f19bf75 | 2566 | u8 node_id = dram_dst_node(pvt, range); |
229a7a11 | 2567 | u8 intlv_en = dram_intlv_en(pvt, range); |
7f19bf75 | 2568 | u32 intlv_sel = dram_intlv_sel(pvt, range); |
f71d0a05 | 2569 | |
956b9ba1 JP |
2570 | edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", |
2571 | range, sys_addr, get_dram_limit(pvt, range)); | |
f71d0a05 | 2572 | |
355fba60 BP |
2573 | if (dhar_valid(pvt) && |
2574 | dhar_base(pvt) <= sys_addr && | |
2575 | sys_addr < BIT_64(32)) { | |
2576 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
2577 | sys_addr); | |
2578 | return -EINVAL; | |
2579 | } | |
2580 | ||
f030ddfb | 2581 | if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en))) |
f71d0a05 DT |
2582 | return -EINVAL; |
2583 | ||
b15f0fca | 2584 | sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); |
95b0ef55 | 2585 | |
f71d0a05 DT |
2586 | dct_sel_base = dct_sel_baseaddr(pvt); |
2587 | ||
2588 | /* | |
2589 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
2590 | * select between DCT0 and DCT1. | |
2591 | */ | |
2592 | if (dct_high_range_enabled(pvt) && | |
2593 | !dct_ganging_enabled(pvt) && | |
2594 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
229a7a11 | 2595 | high_range = true; |
f71d0a05 | 2596 | |
b15f0fca | 2597 | channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); |
f71d0a05 | 2598 | |
b15f0fca | 2599 | chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, |
c8e518d5 | 2600 | high_range, dct_sel_base); |
f71d0a05 | 2601 | |
e2f79dbd BP |
2602 | /* Remove node interleaving, see F1x120 */ |
2603 | if (intlv_en) | |
2604 | chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) | | |
2605 | (chan_addr & 0xfff); | |
f71d0a05 | 2606 | |
5d4b58e8 | 2607 | /* remove channel interleave */ |
f71d0a05 DT |
2608 | if (dct_interleave_enabled(pvt) && |
2609 | !dct_high_range_enabled(pvt) && | |
2610 | !dct_ganging_enabled(pvt)) { | |
5d4b58e8 BP |
2611 | |
2612 | if (dct_sel_interleave_addr(pvt) != 1) { | |
2613 | if (dct_sel_interleave_addr(pvt) == 0x3) | |
2614 | /* hash 9 */ | |
2615 | chan_addr = ((chan_addr >> 10) << 9) | | |
2616 | (chan_addr & 0x1ff); | |
2617 | else | |
2618 | /* A[6] or hash 6 */ | |
2619 | chan_addr = ((chan_addr >> 7) << 6) | | |
2620 | (chan_addr & 0x3f); | |
2621 | } else | |
2622 | /* A[12] */ | |
2623 | chan_addr = ((chan_addr >> 13) << 12) | | |
2624 | (chan_addr & 0xfff); | |
f71d0a05 DT |
2625 | } |
2626 | ||
956b9ba1 | 2627 | edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); |
f71d0a05 | 2628 | |
b15f0fca | 2629 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel); |
f71d0a05 | 2630 | |
33ca0643 | 2631 | if (cs_found >= 0) |
f71d0a05 | 2632 | *chan_sel = channel; |
33ca0643 | 2633 | |
f71d0a05 DT |
2634 | return cs_found; |
2635 | } | |
2636 | ||
18b94f66 AG |
2637 | static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, |
2638 | u64 sys_addr, int *chan_sel) | |
2639 | { | |
2640 | int cs_found = -EINVAL; | |
2641 | int num_dcts_intlv = 0; | |
2642 | u64 chan_addr, chan_offset; | |
2643 | u64 dct_base, dct_limit; | |
2644 | u32 dct_cont_base_reg, dct_cont_limit_reg, tmp; | |
2645 | u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en; | |
2646 | ||
2647 | u64 dhar_offset = f10_dhar_offset(pvt); | |
2648 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
2649 | u8 node_id = dram_dst_node(pvt, range); | |
2650 | u8 intlv_en = dram_intlv_en(pvt, range); | |
2651 | ||
2652 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); | |
2653 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); | |
2654 | ||
2655 | dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0)); | |
2656 | dct_sel = (u8) ((dct_cont_base_reg >> 4) & 0x7); | |
2657 | ||
2658 | edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", | |
2659 | range, sys_addr, get_dram_limit(pvt, range)); | |
2660 | ||
2661 | if (!(get_dram_base(pvt, range) <= sys_addr) && | |
2662 | !(get_dram_limit(pvt, range) >= sys_addr)) | |
2663 | return -EINVAL; | |
2664 | ||
2665 | if (dhar_valid(pvt) && | |
2666 | dhar_base(pvt) <= sys_addr && | |
2667 | sys_addr < BIT_64(32)) { | |
2668 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
2669 | sys_addr); | |
2670 | return -EINVAL; | |
2671 | } | |
2672 | ||
2673 | /* Verify sys_addr is within DCT Range. */ | |
4fc06b31 AG |
2674 | dct_base = (u64) dct_sel_baseaddr(pvt); |
2675 | dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF; | |
18b94f66 AG |
2676 | |
2677 | if (!(dct_cont_base_reg & BIT(0)) && | |
4fc06b31 AG |
2678 | !(dct_base <= (sys_addr >> 27) && |
2679 | dct_limit >= (sys_addr >> 27))) | |
18b94f66 AG |
2680 | return -EINVAL; |
2681 | ||
2682 | /* Verify number of dct's that participate in channel interleaving. */ | |
2683 | num_dcts_intlv = (int) hweight8(intlv_en); | |
2684 | ||
2685 | if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4)) | |
2686 | return -EINVAL; | |
2687 | ||
dc0a50a8 YG |
2688 | if (pvt->model >= 0x60) |
2689 | channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en); | |
2690 | else | |
2691 | channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, | |
2692 | num_dcts_intlv, dct_sel); | |
18b94f66 AG |
2693 | |
2694 | /* Verify we stay within the MAX number of channels allowed */ | |
7f3f5240 | 2695 | if (channel > 3) |
18b94f66 AG |
2696 | return -EINVAL; |
2697 | ||
2698 | leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0)); | |
2699 | ||
2700 | /* Get normalized DCT addr */ | |
2701 | if (leg_mmio_hole && (sys_addr >= BIT_64(32))) | |
2702 | chan_offset = dhar_offset; | |
2703 | else | |
4fc06b31 | 2704 | chan_offset = dct_base << 27; |
18b94f66 AG |
2705 | |
2706 | chan_addr = sys_addr - chan_offset; | |
2707 | ||
2708 | /* remove channel interleave */ | |
2709 | if (num_dcts_intlv == 2) { | |
2710 | if (intlv_addr == 0x4) | |
2711 | chan_addr = ((chan_addr >> 9) << 8) | | |
2712 | (chan_addr & 0xff); | |
2713 | else if (intlv_addr == 0x5) | |
2714 | chan_addr = ((chan_addr >> 10) << 9) | | |
2715 | (chan_addr & 0x1ff); | |
2716 | else | |
2717 | return -EINVAL; | |
2718 | ||
2719 | } else if (num_dcts_intlv == 4) { | |
2720 | if (intlv_addr == 0x4) | |
2721 | chan_addr = ((chan_addr >> 10) << 8) | | |
2722 | (chan_addr & 0xff); | |
2723 | else if (intlv_addr == 0x5) | |
2724 | chan_addr = ((chan_addr >> 11) << 9) | | |
2725 | (chan_addr & 0x1ff); | |
2726 | else | |
2727 | return -EINVAL; | |
2728 | } | |
2729 | ||
2730 | if (dct_offset_en) { | |
2731 | amd64_read_pci_cfg(pvt->F1, | |
2732 | DRAM_CONT_HIGH_OFF + (int) channel * 4, | |
2733 | &tmp); | |
4fc06b31 | 2734 | chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27; |
18b94f66 AG |
2735 | } |
2736 | ||
2737 | f15h_select_dct(pvt, channel); | |
2738 | ||
2739 | edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); | |
2740 | ||
2741 | /* | |
2742 | * Find Chip select: | |
2743 | * if channel = 3, then alias it to 1. This is because, in F15 M30h, | |
2744 | * there is support for 4 DCT's, but only 2 are currently functional. | |
2745 | * They are DCT0 and DCT3. But we have read all registers of DCT3 into | |
2746 | * pvt->csels[1]. So we need to use '1' here to get correct info. | |
2747 | * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications. | |
2748 | */ | |
2749 | alias_channel = (channel == 3) ? 1 : channel; | |
2750 | ||
2751 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel); | |
2752 | ||
2753 | if (cs_found >= 0) | |
2754 | *chan_sel = alias_channel; | |
2755 | ||
2756 | return cs_found; | |
2757 | } | |
2758 | ||
2759 | static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, | |
2760 | u64 sys_addr, | |
2761 | int *chan_sel) | |
f71d0a05 | 2762 | { |
e761359a BP |
2763 | int cs_found = -EINVAL; |
2764 | unsigned range; | |
f71d0a05 | 2765 | |
7f19bf75 | 2766 | for (range = 0; range < DRAM_RANGES; range++) { |
7f19bf75 | 2767 | if (!dram_rw(pvt, range)) |
f71d0a05 DT |
2768 | continue; |
2769 | ||
18b94f66 AG |
2770 | if (pvt->fam == 0x15 && pvt->model >= 0x30) |
2771 | cs_found = f15_m30h_match_to_this_node(pvt, range, | |
2772 | sys_addr, | |
2773 | chan_sel); | |
f71d0a05 | 2774 | |
18b94f66 AG |
2775 | else if ((get_dram_base(pvt, range) <= sys_addr) && |
2776 | (get_dram_limit(pvt, range) >= sys_addr)) { | |
b15f0fca | 2777 | cs_found = f1x_match_to_this_node(pvt, range, |
33ca0643 | 2778 | sys_addr, chan_sel); |
f71d0a05 DT |
2779 | if (cs_found >= 0) |
2780 | break; | |
2781 | } | |
2782 | } | |
2783 | return cs_found; | |
2784 | } | |
2785 | ||
2786 | /* | |
bdc30a0c BP |
2787 | * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps |
2788 | * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW). | |
f71d0a05 | 2789 | * |
bdc30a0c BP |
2790 | * The @sys_addr is usually an error address received from the hardware |
2791 | * (MCX_ADDR). | |
f71d0a05 | 2792 | */ |
b15f0fca | 2793 | static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 2794 | struct err_info *err) |
f71d0a05 DT |
2795 | { |
2796 | struct amd64_pvt *pvt = mci->pvt_info; | |
f71d0a05 | 2797 | |
33ca0643 | 2798 | error_address_to_page_and_offset(sys_addr, err); |
ab5a503c | 2799 | |
33ca0643 BP |
2800 | err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); |
2801 | if (err->csrow < 0) { | |
2802 | err->err_code = ERR_CSROW; | |
bdc30a0c BP |
2803 | return; |
2804 | } | |
2805 | ||
bdc30a0c BP |
2806 | /* |
2807 | * We need the syndromes for channel detection only when we're | |
2808 | * ganged. Otherwise @chan should already contain the channel at | |
2809 | * this point. | |
2810 | */ | |
a97fa68e | 2811 | if (dct_ganging_enabled(pvt)) |
33ca0643 | 2812 | err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); |
f71d0a05 DT |
2813 | } |
2814 | ||
b1289d6f | 2815 | /* |
bfc04aec BP |
2816 | * These are tables of eigenvectors (one per line) which can be used for the |
2817 | * construction of the syndrome tables. The modified syndrome search algorithm | |
2818 | * uses those to find the symbol in error and thus the DIMM. | |
b1289d6f | 2819 | * |
bfc04aec | 2820 | * Algorithm courtesy of Ross LaFetra from AMD. |
b1289d6f | 2821 | */ |
c7e5301a | 2822 | static const u16 x4_vectors[] = { |
bfc04aec BP |
2823 | 0x2f57, 0x1afe, 0x66cc, 0xdd88, |
2824 | 0x11eb, 0x3396, 0x7f4c, 0xeac8, | |
2825 | 0x0001, 0x0002, 0x0004, 0x0008, | |
2826 | 0x1013, 0x3032, 0x4044, 0x8088, | |
2827 | 0x106b, 0x30d6, 0x70fc, 0xe0a8, | |
2828 | 0x4857, 0xc4fe, 0x13cc, 0x3288, | |
2829 | 0x1ac5, 0x2f4a, 0x5394, 0xa1e8, | |
2830 | 0x1f39, 0x251e, 0xbd6c, 0x6bd8, | |
2831 | 0x15c1, 0x2a42, 0x89ac, 0x4758, | |
2832 | 0x2b03, 0x1602, 0x4f0c, 0xca08, | |
2833 | 0x1f07, 0x3a0e, 0x6b04, 0xbd08, | |
2834 | 0x8ba7, 0x465e, 0x244c, 0x1cc8, | |
2835 | 0x2b87, 0x164e, 0x642c, 0xdc18, | |
2836 | 0x40b9, 0x80de, 0x1094, 0x20e8, | |
2837 | 0x27db, 0x1eb6, 0x9dac, 0x7b58, | |
2838 | 0x11c1, 0x2242, 0x84ac, 0x4c58, | |
2839 | 0x1be5, 0x2d7a, 0x5e34, 0xa718, | |
2840 | 0x4b39, 0x8d1e, 0x14b4, 0x28d8, | |
2841 | 0x4c97, 0xc87e, 0x11fc, 0x33a8, | |
2842 | 0x8e97, 0x497e, 0x2ffc, 0x1aa8, | |
2843 | 0x16b3, 0x3d62, 0x4f34, 0x8518, | |
2844 | 0x1e2f, 0x391a, 0x5cac, 0xf858, | |
2845 | 0x1d9f, 0x3b7a, 0x572c, 0xfe18, | |
2846 | 0x15f5, 0x2a5a, 0x5264, 0xa3b8, | |
2847 | 0x1dbb, 0x3b66, 0x715c, 0xe3f8, | |
2848 | 0x4397, 0xc27e, 0x17fc, 0x3ea8, | |
2849 | 0x1617, 0x3d3e, 0x6464, 0xb8b8, | |
2850 | 0x23ff, 0x12aa, 0xab6c, 0x56d8, | |
2851 | 0x2dfb, 0x1ba6, 0x913c, 0x7328, | |
2852 | 0x185d, 0x2ca6, 0x7914, 0x9e28, | |
2853 | 0x171b, 0x3e36, 0x7d7c, 0xebe8, | |
2854 | 0x4199, 0x82ee, 0x19f4, 0x2e58, | |
2855 | 0x4807, 0xc40e, 0x130c, 0x3208, | |
2856 | 0x1905, 0x2e0a, 0x5804, 0xac08, | |
2857 | 0x213f, 0x132a, 0xadfc, 0x5ba8, | |
2858 | 0x19a9, 0x2efe, 0xb5cc, 0x6f88, | |
b1289d6f DT |
2859 | }; |
2860 | ||
c7e5301a | 2861 | static const u16 x8_vectors[] = { |
bfc04aec BP |
2862 | 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480, |
2863 | 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80, | |
2864 | 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80, | |
2865 | 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80, | |
2866 | 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780, | |
2867 | 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080, | |
2868 | 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080, | |
2869 | 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080, | |
2870 | 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80, | |
2871 | 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580, | |
2872 | 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880, | |
2873 | 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280, | |
2874 | 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180, | |
2875 | 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580, | |
2876 | 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280, | |
2877 | 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180, | |
2878 | 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, | |
2879 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
2880 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, | |
2881 | }; | |
2882 | ||
c7e5301a | 2883 | static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs, |
d34a6ecd | 2884 | unsigned v_dim) |
b1289d6f | 2885 | { |
bfc04aec BP |
2886 | unsigned int i, err_sym; |
2887 | ||
2888 | for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) { | |
2889 | u16 s = syndrome; | |
d34a6ecd BP |
2890 | unsigned v_idx = err_sym * v_dim; |
2891 | unsigned v_end = (err_sym + 1) * v_dim; | |
bfc04aec BP |
2892 | |
2893 | /* walk over all 16 bits of the syndrome */ | |
2894 | for (i = 1; i < (1U << 16); i <<= 1) { | |
2895 | ||
2896 | /* if bit is set in that eigenvector... */ | |
2897 | if (v_idx < v_end && vectors[v_idx] & i) { | |
2898 | u16 ev_comp = vectors[v_idx++]; | |
2899 | ||
2900 | /* ... and bit set in the modified syndrome, */ | |
2901 | if (s & i) { | |
2902 | /* remove it. */ | |
2903 | s ^= ev_comp; | |
4d37607a | 2904 | |
bfc04aec BP |
2905 | if (!s) |
2906 | return err_sym; | |
2907 | } | |
b1289d6f | 2908 | |
bfc04aec BP |
2909 | } else if (s & i) |
2910 | /* can't get to zero, move to next symbol */ | |
2911 | break; | |
2912 | } | |
b1289d6f DT |
2913 | } |
2914 | ||
956b9ba1 | 2915 | edac_dbg(0, "syndrome(%x) not found\n", syndrome); |
b1289d6f DT |
2916 | return -1; |
2917 | } | |
d27bf6fa | 2918 | |
bfc04aec BP |
2919 | static int map_err_sym_to_channel(int err_sym, int sym_size) |
2920 | { | |
2921 | if (sym_size == 4) | |
2922 | switch (err_sym) { | |
2923 | case 0x20: | |
2924 | case 0x21: | |
2925 | return 0; | |
bfc04aec BP |
2926 | case 0x22: |
2927 | case 0x23: | |
2928 | return 1; | |
bfc04aec BP |
2929 | default: |
2930 | return err_sym >> 4; | |
bfc04aec BP |
2931 | } |
2932 | /* x8 symbols */ | |
2933 | else | |
2934 | switch (err_sym) { | |
2935 | /* imaginary bits not in a DIMM */ | |
2936 | case 0x10: | |
2937 | WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n", | |
2938 | err_sym); | |
2939 | return -1; | |
bfc04aec BP |
2940 | case 0x11: |
2941 | return 0; | |
bfc04aec BP |
2942 | case 0x12: |
2943 | return 1; | |
bfc04aec BP |
2944 | default: |
2945 | return err_sym >> 3; | |
bfc04aec BP |
2946 | } |
2947 | return -1; | |
2948 | } | |
2949 | ||
2950 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome) | |
2951 | { | |
2952 | struct amd64_pvt *pvt = mci->pvt_info; | |
ad6a32e9 BP |
2953 | int err_sym = -1; |
2954 | ||
a3b7db09 | 2955 | if (pvt->ecc_sym_sz == 8) |
ad6a32e9 BP |
2956 | err_sym = decode_syndrome(syndrome, x8_vectors, |
2957 | ARRAY_SIZE(x8_vectors), | |
a3b7db09 BP |
2958 | pvt->ecc_sym_sz); |
2959 | else if (pvt->ecc_sym_sz == 4) | |
ad6a32e9 BP |
2960 | err_sym = decode_syndrome(syndrome, x4_vectors, |
2961 | ARRAY_SIZE(x4_vectors), | |
a3b7db09 | 2962 | pvt->ecc_sym_sz); |
ad6a32e9 | 2963 | else { |
a3b7db09 | 2964 | amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); |
ad6a32e9 | 2965 | return err_sym; |
bfc04aec | 2966 | } |
ad6a32e9 | 2967 | |
a3b7db09 | 2968 | return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); |
bfc04aec BP |
2969 | } |
2970 | ||
e70984d9 | 2971 | static void __log_ecc_error(struct mem_ctl_info *mci, struct err_info *err, |
33ca0643 | 2972 | u8 ecc_type) |
d27bf6fa | 2973 | { |
33ca0643 BP |
2974 | enum hw_event_mc_err_type err_type; |
2975 | const char *string; | |
d27bf6fa | 2976 | |
33ca0643 BP |
2977 | if (ecc_type == 2) |
2978 | err_type = HW_EVENT_ERR_CORRECTED; | |
2979 | else if (ecc_type == 1) | |
2980 | err_type = HW_EVENT_ERR_UNCORRECTED; | |
d12a969e YG |
2981 | else if (ecc_type == 3) |
2982 | err_type = HW_EVENT_ERR_DEFERRED; | |
33ca0643 BP |
2983 | else { |
2984 | WARN(1, "Something is rotten in the state of Denmark.\n"); | |
d27bf6fa DT |
2985 | return; |
2986 | } | |
2987 | ||
33ca0643 BP |
2988 | switch (err->err_code) { |
2989 | case DECODE_OK: | |
2990 | string = ""; | |
2991 | break; | |
2992 | case ERR_NODE: | |
2993 | string = "Failed to map error addr to a node"; | |
2994 | break; | |
2995 | case ERR_CSROW: | |
2996 | string = "Failed to map error addr to a csrow"; | |
2997 | break; | |
2998 | case ERR_CHANNEL: | |
713ad546 YG |
2999 | string = "Unknown syndrome - possible error reporting race"; |
3000 | break; | |
3001 | case ERR_SYND: | |
3002 | string = "MCA_SYND not valid - unknown syndrome and csrow"; | |
3003 | break; | |
3004 | case ERR_NORM_ADDR: | |
3005 | string = "Cannot decode normalized address"; | |
33ca0643 BP |
3006 | break; |
3007 | default: | |
3008 | string = "WTF error"; | |
3009 | break; | |
d27bf6fa | 3010 | } |
33ca0643 BP |
3011 | |
3012 | edac_mc_handle_error(err_type, mci, 1, | |
3013 | err->page, err->offset, err->syndrome, | |
3014 | err->csrow, err->channel, -1, | |
3015 | string, ""); | |
d27bf6fa DT |
3016 | } |
3017 | ||
df781d03 | 3018 | static inline void decode_bus_error(int node_id, struct mce *m) |
d27bf6fa | 3019 | { |
0c510cc8 DB |
3020 | struct mem_ctl_info *mci; |
3021 | struct amd64_pvt *pvt; | |
f192c7b1 | 3022 | u8 ecc_type = (m->status >> 45) & 0x3; |
66fed2d4 BP |
3023 | u8 xec = XEC(m->status, 0x1f); |
3024 | u16 ec = EC(m->status); | |
33ca0643 BP |
3025 | u64 sys_addr; |
3026 | struct err_info err; | |
d27bf6fa | 3027 | |
0c510cc8 DB |
3028 | mci = edac_mc_find(node_id); |
3029 | if (!mci) | |
3030 | return; | |
3031 | ||
3032 | pvt = mci->pvt_info; | |
3033 | ||
66fed2d4 | 3034 | /* Bail out early if this was an 'observed' error */ |
5980bb9c | 3035 | if (PP(ec) == NBSL_PP_OBS) |
b70ef010 | 3036 | return; |
d27bf6fa | 3037 | |
ecaf5606 BP |
3038 | /* Do only ECC errors */ |
3039 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 3040 | return; |
d27bf6fa | 3041 | |
33ca0643 BP |
3042 | memset(&err, 0, sizeof(err)); |
3043 | ||
a4b4bedc | 3044 | sys_addr = get_error_address(pvt, m); |
33ca0643 | 3045 | |
ecaf5606 | 3046 | if (ecc_type == 2) |
33ca0643 BP |
3047 | err.syndrome = extract_syndrome(m->status); |
3048 | ||
3049 | pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); | |
3050 | ||
e70984d9 | 3051 | __log_ecc_error(mci, &err, ecc_type); |
d27bf6fa DT |
3052 | } |
3053 | ||
713ad546 YG |
3054 | /* |
3055 | * To find the UMC channel represented by this bank we need to match on its | |
3056 | * instance_id. The instance_id of a bank is held in the lower 32 bits of its | |
3057 | * IPID. | |
bdcee774 YG |
3058 | * |
3059 | * Currently, we can derive the channel number by looking at the 6th nibble in | |
3060 | * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel | |
3061 | * number. | |
b3ece3a6 M |
3062 | * |
3063 | * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of | |
3064 | * the MCA_SYND[ErrorInformation] field. | |
713ad546 | 3065 | */ |
b3ece3a6 | 3066 | static void umc_get_err_info(struct mce *m, struct err_info *err) |
713ad546 | 3067 | { |
b3ece3a6 M |
3068 | err->channel = (m->ipid & GENMASK(31, 0)) >> 20; |
3069 | err->csrow = m->synd & 0x7; | |
713ad546 YG |
3070 | } |
3071 | ||
3072 | static void decode_umc_error(int node_id, struct mce *m) | |
3073 | { | |
3074 | u8 ecc_type = (m->status >> 45) & 0x3; | |
3075 | struct mem_ctl_info *mci; | |
3076 | struct amd64_pvt *pvt; | |
3077 | struct err_info err; | |
3078 | u64 sys_addr; | |
3079 | ||
4251566e YG |
3080 | node_id = fixup_node_id(node_id, m); |
3081 | ||
713ad546 YG |
3082 | mci = edac_mc_find(node_id); |
3083 | if (!mci) | |
3084 | return; | |
3085 | ||
3086 | pvt = mci->pvt_info; | |
3087 | ||
3088 | memset(&err, 0, sizeof(err)); | |
3089 | ||
3090 | if (m->status & MCI_STATUS_DEFERRED) | |
3091 | ecc_type = 3; | |
3092 | ||
713ad546 YG |
3093 | if (!(m->status & MCI_STATUS_SYNDV)) { |
3094 | err.err_code = ERR_SYND; | |
3095 | goto log_error; | |
3096 | } | |
3097 | ||
3098 | if (ecc_type == 2) { | |
3099 | u8 length = (m->synd >> 18) & 0x3f; | |
3100 | ||
3101 | if (length) | |
3102 | err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0); | |
3103 | else | |
3104 | err.err_code = ERR_CHANNEL; | |
3105 | } | |
3106 | ||
b3ece3a6 | 3107 | pvt->ops->get_err_info(m, &err); |
713ad546 | 3108 | |
8a2eaab7 YG |
3109 | if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { |
3110 | err.err_code = ERR_NORM_ADDR; | |
3111 | goto log_error; | |
3112 | } | |
3113 | ||
3114 | error_address_to_page_and_offset(sys_addr, &err); | |
3115 | ||
713ad546 YG |
3116 | log_error: |
3117 | __log_ecc_error(mci, &err, ecc_type); | |
3118 | } | |
3119 | ||
0ec449ee | 3120 | /* |
3f37a36b BP |
3121 | * Use pvt->F3 which contains the F3 CPU PCI device to get the related |
3122 | * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error. | |
0ec449ee | 3123 | */ |
936fc3af YG |
3124 | static int |
3125 | reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) | |
3126 | { | |
0ec449ee | 3127 | /* Reserve the ADDRESS MAP Device */ |
936fc3af | 3128 | pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); |
8d5b5d9c | 3129 | if (!pvt->F1) { |
6a4afe38 | 3130 | edac_dbg(1, "F1 not found: device 0x%x\n", pci_id1); |
bbd0c1f6 | 3131 | return -ENODEV; |
0ec449ee DT |
3132 | } |
3133 | ||
3f37a36b | 3134 | /* Reserve the DCT Device */ |
936fc3af | 3135 | pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); |
3f37a36b | 3136 | if (!pvt->F2) { |
8d5b5d9c BP |
3137 | pci_dev_put(pvt->F1); |
3138 | pvt->F1 = NULL; | |
0ec449ee | 3139 | |
6a4afe38 | 3140 | edac_dbg(1, "F2 not found: device 0x%x\n", pci_id2); |
5246c540 | 3141 | return -ENODEV; |
0ec449ee | 3142 | } |
936fc3af | 3143 | |
706657b1 BP |
3144 | if (!pci_ctl_dev) |
3145 | pci_ctl_dev = &pvt->F2->dev; | |
3146 | ||
956b9ba1 JP |
3147 | edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); |
3148 | edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); | |
3149 | edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); | |
0ec449ee DT |
3150 | |
3151 | return 0; | |
3152 | } | |
3153 | ||
b64ce7cd YG |
3154 | static void determine_ecc_sym_sz(struct amd64_pvt *pvt) |
3155 | { | |
3156 | pvt->ecc_sym_sz = 4; | |
3157 | ||
5a1adb37 | 3158 | if (pvt->fam >= 0x10) { |
b64ce7cd YG |
3159 | u32 tmp; |
3160 | ||
3161 | amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); | |
3162 | /* F16h has only DCT0, so no need to read dbam1. */ | |
3163 | if (pvt->fam != 0x16) | |
3164 | amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); | |
3165 | ||
3166 | /* F10h, revD and later can do x8 ECC too. */ | |
3167 | if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) | |
3168 | pvt->ecc_sym_sz = 8; | |
3169 | } | |
3170 | } | |
3171 | ||
3172 | /* | |
3173 | * Retrieve the hardware registers of the memory controller. | |
3174 | */ | |
32ecdf86 | 3175 | static void umc_read_mc_regs(struct amd64_pvt *pvt) |
b64ce7cd YG |
3176 | { |
3177 | u8 nid = pvt->mc_node_id; | |
3178 | struct amd64_umc *umc; | |
3179 | u32 i, umc_base; | |
3180 | ||
3181 | /* Read registers from each UMC */ | |
4d30d2bc | 3182 | for_each_umc(i) { |
b64ce7cd YG |
3183 | |
3184 | umc_base = get_umc_base(i); | |
3185 | umc = &pvt->umc[i]; | |
3186 | ||
ed623d55 | 3187 | amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &umc->dimm_cfg); |
07ed82ef | 3188 | amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); |
b64ce7cd YG |
3189 | amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); |
3190 | amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); | |
07ed82ef | 3191 | amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); |
b64ce7cd YG |
3192 | } |
3193 | } | |
3194 | ||
0ec449ee DT |
3195 | /* |
3196 | * Retrieve the hardware registers of the memory controller (this includes the | |
3197 | * 'Address Map' and 'Misc' device regs) | |
3198 | */ | |
32ecdf86 | 3199 | static void dct_read_mc_regs(struct amd64_pvt *pvt) |
0ec449ee | 3200 | { |
b64ce7cd | 3201 | unsigned int range; |
0ec449ee | 3202 | u64 msr_val; |
0ec449ee DT |
3203 | |
3204 | /* | |
3205 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
b64ce7cd | 3206 | * those are Read-As-Zero. |
0ec449ee | 3207 | */ |
e97f8bb8 | 3208 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
956b9ba1 | 3209 | edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); |
0ec449ee | 3210 | |
b64ce7cd | 3211 | /* Check first whether TOP_MEM2 is enabled: */ |
059e5c32 | 3212 | rdmsrl(MSR_AMD64_SYSCFG, msr_val); |
b64ce7cd | 3213 | if (msr_val & BIT(21)) { |
e97f8bb8 | 3214 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
956b9ba1 | 3215 | edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); |
b64ce7cd | 3216 | } else { |
956b9ba1 | 3217 | edac_dbg(0, " TOP_MEM2 disabled\n"); |
b64ce7cd YG |
3218 | } |
3219 | ||
5980bb9c | 3220 | amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); |
0ec449ee | 3221 | |
5a5d2371 | 3222 | read_dram_ctl_register(pvt); |
0ec449ee | 3223 | |
7f19bf75 BP |
3224 | for (range = 0; range < DRAM_RANGES; range++) { |
3225 | u8 rw; | |
0ec449ee | 3226 | |
7f19bf75 BP |
3227 | /* read settings for this DRAM range */ |
3228 | read_dram_base_limit_regs(pvt, range); | |
3229 | ||
3230 | rw = dram_rw(pvt, range); | |
3231 | if (!rw) | |
3232 | continue; | |
3233 | ||
956b9ba1 JP |
3234 | edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n", |
3235 | range, | |
3236 | get_dram_base(pvt, range), | |
3237 | get_dram_limit(pvt, range)); | |
7f19bf75 | 3238 | |
956b9ba1 JP |
3239 | edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n", |
3240 | dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", | |
3241 | (rw & 0x1) ? "R" : "-", | |
3242 | (rw & 0x2) ? "W" : "-", | |
3243 | dram_intlv_sel(pvt, range), | |
3244 | dram_dst_node(pvt, range)); | |
0ec449ee DT |
3245 | } |
3246 | ||
bc21fa57 | 3247 | amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); |
7981a28f | 3248 | amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); |
0ec449ee | 3249 | |
8d5b5d9c | 3250 | amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); |
0ec449ee | 3251 | |
7981a28f AG |
3252 | amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); |
3253 | amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); | |
0ec449ee | 3254 | |
78da121e | 3255 | if (!dct_ganging_enabled(pvt)) { |
7981a28f AG |
3256 | amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); |
3257 | amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); | |
0ec449ee | 3258 | } |
ad6a32e9 | 3259 | |
b64ce7cd | 3260 | determine_ecc_sym_sz(pvt); |
0ec449ee DT |
3261 | } |
3262 | ||
3263 | /* | |
3264 | * NOTE: CPU Revision Dependent code | |
3265 | * | |
3266 | * Input: | |
11c75ead | 3267 | * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1) |
0ec449ee DT |
3268 | * k8 private pointer to --> |
3269 | * DRAM Bank Address mapping register | |
3270 | * node_id | |
3271 | * DCL register where dual_channel_active is | |
3272 | * | |
3273 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
3274 | * | |
3275 | * Bits: CSROWs | |
3276 | * 0-3 CSROWs 0 and 1 | |
3277 | * 4-7 CSROWs 2 and 3 | |
3278 | * 8-11 CSROWs 4 and 5 | |
3279 | * 12-15 CSROWs 6 and 7 | |
3280 | * | |
3281 | * Values range from: 0 to 15 | |
3282 | * The meaning of the values depends on CPU revision and dual-channel state, | |
3283 | * see relevant BKDG more info. | |
3284 | * | |
3285 | * The memory controller provides for total of only 8 CSROWs in its current | |
3286 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
3287 | * single channel or two (2) DIMMs in dual channel mode. | |
3288 | * | |
3289 | * The following code logic collapses the various tables for CSROW based on CPU | |
3290 | * revision. | |
3291 | * | |
3292 | * Returns: | |
3293 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
3294 | * encompasses | |
3295 | * | |
3296 | */ | |
c0984666 | 3297 | static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) |
0ec449ee | 3298 | { |
f92cae45 | 3299 | u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; |
eb77e6b8 | 3300 | u32 cs_mode, nr_pages; |
0ec449ee | 3301 | |
c0984666 YG |
3302 | csrow_nr >>= 1; |
3303 | cs_mode = DBAM_DIMM(csrow_nr, dbam); | |
0ec449ee | 3304 | |
eb77e6b8 YG |
3305 | nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); |
3306 | nr_pages <<= 20 - PAGE_SHIFT; | |
0ec449ee | 3307 | |
10de6497 | 3308 | edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n", |
c0984666 | 3309 | csrow_nr, dct, cs_mode); |
10de6497 | 3310 | edac_dbg(0, "nr_pages/channel: %u\n", nr_pages); |
0ec449ee DT |
3311 | |
3312 | return nr_pages; | |
3313 | } | |
3314 | ||
c0984666 YG |
3315 | static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) |
3316 | { | |
3317 | int csrow_nr = csrow_nr_orig; | |
3318 | u32 cs_mode, nr_pages; | |
3319 | ||
3320 | cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt); | |
3321 | ||
a2e59ab8 | 3322 | nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); |
c0984666 YG |
3323 | nr_pages <<= 20 - PAGE_SHIFT; |
3324 | ||
3325 | edac_dbg(0, "csrow: %d, channel: %d, cs_mode %d\n", | |
3326 | csrow_nr_orig, dct, cs_mode); | |
10de6497 | 3327 | edac_dbg(0, "nr_pages/channel: %u\n", nr_pages); |
0ec449ee DT |
3328 | |
3329 | return nr_pages; | |
3330 | } | |
3331 | ||
6fb8b5fb | 3332 | static void umc_init_csrows(struct mem_ctl_info *mci) |
353a1fcb YG |
3333 | { |
3334 | struct amd64_pvt *pvt = mci->pvt_info; | |
3335 | enum edac_type edac_mode = EDAC_NONE; | |
3336 | enum dev_type dev_type = DEV_UNKNOWN; | |
3337 | struct dimm_info *dimm; | |
353a1fcb YG |
3338 | u8 umc, cs; |
3339 | ||
3340 | if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) { | |
3341 | edac_mode = EDAC_S16ECD16ED; | |
3342 | dev_type = DEV_X16; | |
3343 | } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) { | |
3344 | edac_mode = EDAC_S8ECD8ED; | |
3345 | dev_type = DEV_X8; | |
3346 | } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) { | |
3347 | edac_mode = EDAC_S4ECD4ED; | |
3348 | dev_type = DEV_X4; | |
3349 | } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) { | |
3350 | edac_mode = EDAC_SECDED; | |
3351 | } | |
3352 | ||
3353 | for_each_umc(umc) { | |
3354 | for_each_chip_select(cs, umc, pvt) { | |
3355 | if (!csrow_enabled(cs, umc, pvt)) | |
3356 | continue; | |
3357 | ||
353a1fcb YG |
3358 | dimm = mci->csrows[cs]->channels[umc]->dimm; |
3359 | ||
3360 | edac_dbg(1, "MC node: %d, csrow: %d\n", | |
3361 | pvt->mc_node_id, cs); | |
3362 | ||
c0984666 | 3363 | dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs); |
75aeaaf2 | 3364 | dimm->mtype = pvt->umc[umc].dram_type; |
353a1fcb YG |
3365 | dimm->edac_mode = edac_mode; |
3366 | dimm->dtype = dev_type; | |
466503d6 | 3367 | dimm->grain = 64; |
353a1fcb YG |
3368 | } |
3369 | } | |
353a1fcb YG |
3370 | } |
3371 | ||
0ec449ee DT |
3372 | /* |
3373 | * Initialize the array of csrow attribute instances, based on the values | |
3374 | * from pci config hardware registers. | |
3375 | */ | |
6fb8b5fb | 3376 | static void dct_init_csrows(struct mem_ctl_info *mci) |
0ec449ee | 3377 | { |
10de6497 | 3378 | struct amd64_pvt *pvt = mci->pvt_info; |
2d09d8f3 | 3379 | enum edac_type edac_mode = EDAC_NONE; |
0ec449ee | 3380 | struct csrow_info *csrow; |
de3910eb | 3381 | struct dimm_info *dimm; |
a895bf8b | 3382 | int nr_pages = 0; |
6fb8b5fb | 3383 | int i, j; |
10de6497 | 3384 | u32 val; |
0ec449ee | 3385 | |
353a1fcb | 3386 | amd64_read_pci_cfg(pvt->F3, NBCFG, &val); |
0ec449ee | 3387 | |
353a1fcb YG |
3388 | pvt->nbcfg = val; |
3389 | ||
3390 | edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", | |
3391 | pvt->mc_node_id, val, | |
3392 | !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); | |
0ec449ee | 3393 | |
10de6497 BP |
3394 | /* |
3395 | * We iterate over DCT0 here but we look at DCT1 in parallel, if needed. | |
3396 | */ | |
11c75ead | 3397 | for_each_chip_select(i, 0, pvt) { |
10de6497 BP |
3398 | bool row_dct0 = !!csrow_enabled(i, 0, pvt); |
3399 | bool row_dct1 = false; | |
0ec449ee | 3400 | |
a4b4bedc | 3401 | if (pvt->fam != 0xf) |
10de6497 BP |
3402 | row_dct1 = !!csrow_enabled(i, 1, pvt); |
3403 | ||
3404 | if (!row_dct0 && !row_dct1) | |
0ec449ee | 3405 | continue; |
0ec449ee | 3406 | |
10de6497 | 3407 | csrow = mci->csrows[i]; |
10de6497 BP |
3408 | |
3409 | edac_dbg(1, "MC node: %d, csrow: %d\n", | |
3410 | pvt->mc_node_id, i); | |
3411 | ||
1eef1282 | 3412 | if (row_dct0) { |
c0984666 | 3413 | nr_pages = dct_get_csrow_nr_pages(pvt, 0, i); |
1eef1282 MCC |
3414 | csrow->channels[0]->dimm->nr_pages = nr_pages; |
3415 | } | |
11c75ead | 3416 | |
10de6497 | 3417 | /* K8 has only one DCT */ |
a4b4bedc | 3418 | if (pvt->fam != 0xf && row_dct1) { |
c0984666 | 3419 | int row_dct1_pages = dct_get_csrow_nr_pages(pvt, 1, i); |
1eef1282 MCC |
3420 | |
3421 | csrow->channels[1]->dimm->nr_pages = row_dct1_pages; | |
3422 | nr_pages += row_dct1_pages; | |
3423 | } | |
0ec449ee | 3424 | |
10de6497 | 3425 | edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages); |
0ec449ee | 3426 | |
2d09d8f3 | 3427 | /* Determine DIMM ECC mode: */ |
353a1fcb | 3428 | if (pvt->nbcfg & NBCFG_ECC_ENABLE) { |
2d09d8f3 YG |
3429 | edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) |
3430 | ? EDAC_S4ECD4ED | |
3431 | : EDAC_SECDED; | |
3432 | } | |
084a4fcc | 3433 | |
ed623d55 | 3434 | for (j = 0; j < pvt->max_mcs; j++) { |
de3910eb | 3435 | dimm = csrow->channels[j]->dimm; |
a597d2a5 | 3436 | dimm->mtype = pvt->dram_type; |
de3910eb | 3437 | dimm->edac_mode = edac_mode; |
466503d6 | 3438 | dimm->grain = 64; |
084a4fcc | 3439 | } |
0ec449ee | 3440 | } |
0ec449ee | 3441 | } |
d27bf6fa | 3442 | |
f6d6ae96 | 3443 | /* get all cores on this DCT */ |
8b84c8df | 3444 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid) |
f6d6ae96 BP |
3445 | { |
3446 | int cpu; | |
3447 | ||
3448 | for_each_online_cpu(cpu) | |
db970bd2 | 3449 | if (topology_die_id(cpu) == nid) |
f6d6ae96 BP |
3450 | cpumask_set_cpu(cpu, mask); |
3451 | } | |
3452 | ||
3453 | /* check MCG_CTL on all the cpus on this node */ | |
d1ea71cd | 3454 | static bool nb_mce_bank_enabled_on_node(u16 nid) |
f6d6ae96 BP |
3455 | { |
3456 | cpumask_var_t mask; | |
50542251 | 3457 | int cpu, nbe; |
f6d6ae96 BP |
3458 | bool ret = false; |
3459 | ||
3460 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
24f9a7fe | 3461 | amd64_warn("%s: Error allocating mask\n", __func__); |
f6d6ae96 BP |
3462 | return false; |
3463 | } | |
3464 | ||
3465 | get_cpus_on_this_dct_cpumask(mask, nid); | |
3466 | ||
f6d6ae96 BP |
3467 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); |
3468 | ||
3469 | for_each_cpu(cpu, mask) { | |
50542251 | 3470 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
5980bb9c | 3471 | nbe = reg->l & MSR_MCGCTL_NBE; |
f6d6ae96 | 3472 | |
956b9ba1 JP |
3473 | edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", |
3474 | cpu, reg->q, | |
3475 | (nbe ? "enabled" : "disabled")); | |
f6d6ae96 BP |
3476 | |
3477 | if (!nbe) | |
3478 | goto out; | |
f6d6ae96 BP |
3479 | } |
3480 | ret = true; | |
3481 | ||
3482 | out: | |
f6d6ae96 BP |
3483 | free_cpumask_var(mask); |
3484 | return ret; | |
3485 | } | |
3486 | ||
c7e5301a | 3487 | static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on) |
f6d6ae96 BP |
3488 | { |
3489 | cpumask_var_t cmask; | |
50542251 | 3490 | int cpu; |
f6d6ae96 BP |
3491 | |
3492 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
24f9a7fe | 3493 | amd64_warn("%s: error allocating mask\n", __func__); |
0de27884 | 3494 | return -ENOMEM; |
f6d6ae96 BP |
3495 | } |
3496 | ||
ae7bb7c6 | 3497 | get_cpus_on_this_dct_cpumask(cmask, nid); |
f6d6ae96 | 3498 | |
f6d6ae96 BP |
3499 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); |
3500 | ||
3501 | for_each_cpu(cpu, cmask) { | |
3502 | ||
50542251 BP |
3503 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
3504 | ||
f6d6ae96 | 3505 | if (on) { |
5980bb9c | 3506 | if (reg->l & MSR_MCGCTL_NBE) |
ae7bb7c6 | 3507 | s->flags.nb_mce_enable = 1; |
f6d6ae96 | 3508 | |
5980bb9c | 3509 | reg->l |= MSR_MCGCTL_NBE; |
f6d6ae96 BP |
3510 | } else { |
3511 | /* | |
d95cf4de | 3512 | * Turn off NB MCE reporting only when it was off before |
f6d6ae96 | 3513 | */ |
ae7bb7c6 | 3514 | if (!s->flags.nb_mce_enable) |
5980bb9c | 3515 | reg->l &= ~MSR_MCGCTL_NBE; |
f6d6ae96 | 3516 | } |
f6d6ae96 BP |
3517 | } |
3518 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
3519 | ||
f6d6ae96 BP |
3520 | free_cpumask_var(cmask); |
3521 | ||
3522 | return 0; | |
3523 | } | |
3524 | ||
c7e5301a | 3525 | static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid, |
2299ef71 | 3526 | struct pci_dev *F3) |
f9431992 | 3527 | { |
2299ef71 | 3528 | bool ret = true; |
c9f4f26e | 3529 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
f9431992 | 3530 | |
2299ef71 BP |
3531 | if (toggle_ecc_err_reporting(s, nid, ON)) { |
3532 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); | |
3533 | return false; | |
3534 | } | |
3535 | ||
c9f4f26e | 3536 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 3537 | |
ae7bb7c6 BP |
3538 | s->old_nbctl = value & mask; |
3539 | s->nbctl_valid = true; | |
f9431992 DT |
3540 | |
3541 | value |= mask; | |
c9f4f26e | 3542 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 3543 | |
a97fa68e | 3544 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 3545 | |
956b9ba1 JP |
3546 | edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
3547 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 3548 | |
a97fa68e | 3549 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe | 3550 | amd64_warn("DRAM ECC disabled on this node, enabling...\n"); |
f9431992 | 3551 | |
ae7bb7c6 | 3552 | s->flags.nb_ecc_prev = 0; |
d95cf4de | 3553 | |
f9431992 | 3554 | /* Attempt to turn on DRAM ECC Enable */ |
a97fa68e BP |
3555 | value |= NBCFG_ECC_ENABLE; |
3556 | amd64_write_pci_cfg(F3, NBCFG, value); | |
f9431992 | 3557 | |
a97fa68e | 3558 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 3559 | |
a97fa68e | 3560 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe BP |
3561 | amd64_warn("Hardware rejected DRAM ECC enable," |
3562 | "check memory DIMM configuration.\n"); | |
2299ef71 | 3563 | ret = false; |
f9431992 | 3564 | } else { |
24f9a7fe | 3565 | amd64_info("Hardware accepted DRAM ECC Enable\n"); |
f9431992 | 3566 | } |
d95cf4de | 3567 | } else { |
ae7bb7c6 | 3568 | s->flags.nb_ecc_prev = 1; |
f9431992 | 3569 | } |
d95cf4de | 3570 | |
956b9ba1 JP |
3571 | edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
3572 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 3573 | |
2299ef71 | 3574 | return ret; |
f9431992 DT |
3575 | } |
3576 | ||
c7e5301a | 3577 | static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid, |
360b7f3c | 3578 | struct pci_dev *F3) |
f9431992 | 3579 | { |
c9f4f26e BP |
3580 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
3581 | ||
ae7bb7c6 | 3582 | if (!s->nbctl_valid) |
f9431992 DT |
3583 | return; |
3584 | ||
c9f4f26e | 3585 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 3586 | value &= ~mask; |
ae7bb7c6 | 3587 | value |= s->old_nbctl; |
f9431992 | 3588 | |
c9f4f26e | 3589 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 3590 | |
ae7bb7c6 BP |
3591 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ |
3592 | if (!s->flags.nb_ecc_prev) { | |
a97fa68e BP |
3593 | amd64_read_pci_cfg(F3, NBCFG, &value); |
3594 | value &= ~NBCFG_ECC_ENABLE; | |
3595 | amd64_write_pci_cfg(F3, NBCFG, value); | |
d95cf4de BP |
3596 | } |
3597 | ||
3598 | /* restore the NB Enable MCGCTL bit */ | |
2299ef71 | 3599 | if (toggle_ecc_err_reporting(s, nid, OFF)) |
24f9a7fe | 3600 | amd64_warn("Error restoring NB MCGCTL settings!\n"); |
f9431992 DT |
3601 | } |
3602 | ||
eb2bcdfc | 3603 | static bool dct_ecc_enabled(struct amd64_pvt *pvt) |
f9431992 | 3604 | { |
1c9b08ba | 3605 | u16 nid = pvt->mc_node_id; |
06724535 | 3606 | bool nb_mce_en = false; |
eb2bcdfc | 3607 | u8 ecc_en = 0; |
196b79fc | 3608 | u32 value; |
f9431992 | 3609 | |
eb2bcdfc | 3610 | amd64_read_pci_cfg(pvt->F3, NBCFG, &value); |
f9431992 | 3611 | |
eb2bcdfc | 3612 | ecc_en = !!(value & NBCFG_ECC_ENABLE); |
196b79fc | 3613 | |
eb2bcdfc M |
3614 | nb_mce_en = nb_mce_bank_enabled_on_node(nid); |
3615 | if (!nb_mce_en) | |
3616 | edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n", | |
3617 | MSR_IA32_MCG_CTL, nid); | |
196b79fc | 3618 | |
eb2bcdfc | 3619 | edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled")); |
196b79fc | 3620 | |
eb2bcdfc M |
3621 | if (!ecc_en || !nb_mce_en) |
3622 | return false; | |
3623 | else | |
3624 | return true; | |
3625 | } | |
196b79fc | 3626 | |
eb2bcdfc M |
3627 | static bool umc_ecc_enabled(struct amd64_pvt *pvt) |
3628 | { | |
3629 | u8 umc_en_mask = 0, ecc_en_mask = 0; | |
3630 | u16 nid = pvt->mc_node_id; | |
3631 | struct amd64_umc *umc; | |
3632 | u8 ecc_en = 0, i; | |
196b79fc | 3633 | |
eb2bcdfc M |
3634 | for_each_umc(i) { |
3635 | umc = &pvt->umc[i]; | |
f9431992 | 3636 | |
eb2bcdfc M |
3637 | /* Only check enabled UMCs. */ |
3638 | if (!(umc->sdp_ctrl & UMC_SDP_INIT)) | |
3639 | continue; | |
f9431992 | 3640 | |
eb2bcdfc | 3641 | umc_en_mask |= BIT(i); |
196b79fc | 3642 | |
eb2bcdfc M |
3643 | if (umc->umc_cap_hi & UMC_ECC_ENABLED) |
3644 | ecc_en_mask |= BIT(i); | |
196b79fc YG |
3645 | } |
3646 | ||
eb2bcdfc M |
3647 | /* Check whether at least one UMC is enabled: */ |
3648 | if (umc_en_mask) | |
3649 | ecc_en = umc_en_mask == ecc_en_mask; | |
3650 | else | |
3651 | edac_dbg(0, "Node %d: No enabled UMCs.\n", nid); | |
3652 | ||
4cbcb73b | 3653 | edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled")); |
f9431992 | 3654 | |
eb2bcdfc | 3655 | if (!ecc_en) |
2299ef71 | 3656 | return false; |
7fdfee92 BP |
3657 | else |
3658 | return true; | |
f9431992 DT |
3659 | } |
3660 | ||
2d09d8f3 | 3661 | static inline void |
9369239e | 3662 | umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) |
2d09d8f3 | 3663 | { |
f8be8e56 | 3664 | u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1; |
2d09d8f3 | 3665 | |
4d30d2bc | 3666 | for_each_umc(i) { |
2d09d8f3 YG |
3667 | if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { |
3668 | ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); | |
3669 | cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); | |
f8be8e56 YG |
3670 | |
3671 | dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); | |
3672 | dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); | |
2d09d8f3 YG |
3673 | } |
3674 | } | |
3675 | ||
3676 | /* Set chipkill only if ECC is enabled: */ | |
3677 | if (ecc_en) { | |
3678 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; | |
3679 | ||
f8be8e56 YG |
3680 | if (!cpk_en) |
3681 | return; | |
3682 | ||
3683 | if (dev_x4) | |
2d09d8f3 | 3684 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; |
f8be8e56 YG |
3685 | else if (dev_x16) |
3686 | mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED; | |
3687 | else | |
3688 | mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED; | |
2d09d8f3 YG |
3689 | } |
3690 | } | |
3691 | ||
0a42a37f | 3692 | static void dct_setup_mci_misc_attrs(struct mem_ctl_info *mci) |
7d6034d3 DT |
3693 | { |
3694 | struct amd64_pvt *pvt = mci->pvt_info; | |
3695 | ||
3696 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
3697 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 | 3698 | |
0a42a37f M |
3699 | if (pvt->nbcap & NBCAP_SECDED) |
3700 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; | |
7d6034d3 | 3701 | |
0a42a37f M |
3702 | if (pvt->nbcap & NBCAP_CHIPKILL) |
3703 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; | |
7d6034d3 | 3704 | |
f6a4b4a1 | 3705 | mci->edac_cap = dct_determine_edac_cap(pvt); |
7d6034d3 | 3706 | mci->mod_name = EDAC_MOD_STR; |
ed623d55 | 3707 | mci->ctl_name = pvt->ctl_name; |
e7934b70 | 3708 | mci->dev_name = pci_name(pvt->F3); |
7d6034d3 DT |
3709 | mci->ctl_page_to_phys = NULL; |
3710 | ||
7d6034d3 | 3711 | /* memory scrubber interface */ |
d1ea71cd BP |
3712 | mci->set_sdram_scrub_rate = set_scrub_rate; |
3713 | mci->get_sdram_scrub_rate = get_scrub_rate; | |
6fb8b5fb M |
3714 | |
3715 | dct_init_csrows(mci); | |
7d6034d3 DT |
3716 | } |
3717 | ||
0a42a37f M |
3718 | static void umc_setup_mci_misc_attrs(struct mem_ctl_info *mci) |
3719 | { | |
3720 | struct amd64_pvt *pvt = mci->pvt_info; | |
3721 | ||
3722 | mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4; | |
3723 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
3724 | ||
9369239e | 3725 | umc_determine_edac_ctl_cap(mci, pvt); |
0a42a37f | 3726 | |
f6a4b4a1 | 3727 | mci->edac_cap = umc_determine_edac_cap(pvt); |
0a42a37f M |
3728 | mci->mod_name = EDAC_MOD_STR; |
3729 | mci->ctl_name = pvt->ctl_name; | |
3730 | mci->dev_name = pci_name(pvt->F3); | |
3731 | mci->ctl_page_to_phys = NULL; | |
6fb8b5fb M |
3732 | |
3733 | umc_init_csrows(mci); | |
0a42a37f M |
3734 | } |
3735 | ||
9a97a7f4 YG |
3736 | static int dct_hw_info_get(struct amd64_pvt *pvt) |
3737 | { | |
3738 | int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id); | |
3739 | ||
3740 | if (ret) | |
3741 | return ret; | |
3742 | ||
637f60ef | 3743 | dct_prep_chip_selects(pvt); |
b29dad9b | 3744 | dct_read_base_mask(pvt); |
32ecdf86 | 3745 | dct_read_mc_regs(pvt); |
78ec161a | 3746 | dct_determine_memory_type(pvt); |
9a97a7f4 YG |
3747 | |
3748 | return 0; | |
3749 | } | |
3750 | ||
3751 | static int umc_hw_info_get(struct amd64_pvt *pvt) | |
3752 | { | |
3753 | pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); | |
3754 | if (!pvt->umc) | |
3755 | return -ENOMEM; | |
3756 | ||
637f60ef | 3757 | umc_prep_chip_selects(pvt); |
b29dad9b | 3758 | umc_read_base_mask(pvt); |
32ecdf86 | 3759 | umc_read_mc_regs(pvt); |
78ec161a | 3760 | umc_determine_memory_type(pvt); |
9a97a7f4 YG |
3761 | |
3762 | return 0; | |
3763 | } | |
3764 | ||
9c42edd5 M |
3765 | /* |
3766 | * The CPUs have one channel per UMC, so UMC number is equivalent to a | |
3767 | * channel number. The GPUs have 8 channels per UMC, so the UMC number no | |
3768 | * longer works as a channel number. | |
3769 | * | |
3770 | * The channel number within a GPU UMC is given in MCA_IPID[15:12]. | |
3771 | * However, the IDs are split such that two UMC values go to one UMC, and | |
3772 | * the channel numbers are split in two groups of four. | |
3773 | * | |
3774 | * Refer to comment on gpu_get_umc_base(). | |
3775 | * | |
3776 | * For example, | |
3777 | * UMC0 CH[3:0] = 0x0005[3:0]000 | |
3778 | * UMC0 CH[7:4] = 0x0015[3:0]000 | |
3779 | * UMC1 CH[3:0] = 0x0025[3:0]000 | |
3780 | * UMC1 CH[7:4] = 0x0035[3:0]000 | |
3781 | */ | |
3782 | static void gpu_get_err_info(struct mce *m, struct err_info *err) | |
3783 | { | |
3784 | u8 ch = (m->ipid & GENMASK(31, 0)) >> 20; | |
3785 | u8 phy = ((m->ipid >> 12) & 0xf); | |
3786 | ||
3787 | err->channel = ch % 2 ? phy + 4 : phy; | |
3788 | err->csrow = phy; | |
3789 | } | |
3790 | ||
3791 | static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, | |
3792 | unsigned int cs_mode, int csrow_nr) | |
3793 | { | |
3794 | u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; | |
3795 | ||
3796 | return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1); | |
3797 | } | |
3798 | ||
3799 | static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) | |
3800 | { | |
3801 | int size, cs_mode, cs = 0; | |
3802 | ||
3803 | edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl); | |
3804 | ||
3805 | cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY; | |
3806 | ||
3807 | for_each_chip_select(cs, ctrl, pvt) { | |
3808 | size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs); | |
3809 | amd64_info(EDAC_MC ": %d: %5dMB\n", cs, size); | |
3810 | } | |
3811 | } | |
3812 | ||
3813 | static void gpu_dump_misc_regs(struct amd64_pvt *pvt) | |
3814 | { | |
3815 | struct amd64_umc *umc; | |
3816 | u32 i; | |
3817 | ||
3818 | for_each_umc(i) { | |
3819 | umc = &pvt->umc[i]; | |
3820 | ||
3821 | edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); | |
3822 | edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); | |
3823 | edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); | |
3824 | edac_dbg(1, "UMC%d All HBMs support ECC: yes\n", i); | |
3825 | ||
3826 | gpu_debug_display_dimm_sizes(pvt, i); | |
3827 | } | |
3828 | } | |
3829 | ||
3830 | static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) | |
3831 | { | |
3832 | u32 nr_pages; | |
3833 | int cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY; | |
3834 | ||
3835 | nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); | |
3836 | nr_pages <<= 20 - PAGE_SHIFT; | |
3837 | ||
3838 | edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct); | |
3839 | edac_dbg(0, "nr_pages/channel: %u\n", nr_pages); | |
3840 | ||
3841 | return nr_pages; | |
3842 | } | |
3843 | ||
3844 | static void gpu_init_csrows(struct mem_ctl_info *mci) | |
3845 | { | |
3846 | struct amd64_pvt *pvt = mci->pvt_info; | |
3847 | struct dimm_info *dimm; | |
3848 | u8 umc, cs; | |
3849 | ||
3850 | for_each_umc(umc) { | |
3851 | for_each_chip_select(cs, umc, pvt) { | |
3852 | if (!csrow_enabled(cs, umc, pvt)) | |
3853 | continue; | |
3854 | ||
3855 | dimm = mci->csrows[umc]->channels[cs]->dimm; | |
3856 | ||
3857 | edac_dbg(1, "MC node: %d, csrow: %d\n", | |
3858 | pvt->mc_node_id, cs); | |
3859 | ||
3860 | dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs); | |
3861 | dimm->edac_mode = EDAC_SECDED; | |
12f230c0 | 3862 | dimm->mtype = pvt->dram_type; |
9c42edd5 M |
3863 | dimm->dtype = DEV_X16; |
3864 | dimm->grain = 64; | |
3865 | } | |
3866 | } | |
3867 | } | |
3868 | ||
3869 | static void gpu_setup_mci_misc_attrs(struct mem_ctl_info *mci) | |
3870 | { | |
3871 | struct amd64_pvt *pvt = mci->pvt_info; | |
3872 | ||
3873 | mci->mtype_cap = MEM_FLAG_HBM2; | |
3874 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; | |
3875 | ||
3876 | mci->edac_cap = EDAC_FLAG_EC; | |
3877 | mci->mod_name = EDAC_MOD_STR; | |
3878 | mci->ctl_name = pvt->ctl_name; | |
3879 | mci->dev_name = pci_name(pvt->F3); | |
3880 | mci->ctl_page_to_phys = NULL; | |
3881 | ||
3882 | gpu_init_csrows(mci); | |
3883 | } | |
3884 | ||
3885 | /* ECC is enabled by default on GPU nodes */ | |
3886 | static bool gpu_ecc_enabled(struct amd64_pvt *pvt) | |
3887 | { | |
3888 | return true; | |
3889 | } | |
3890 | ||
12f230c0 | 3891 | static inline u32 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel) |
9c42edd5 M |
3892 | { |
3893 | /* | |
3894 | * On CPUs, there is one channel per UMC, so UMC numbering equals | |
3895 | * channel numbering. On GPUs, there are eight channels per UMC, | |
3896 | * so the channel numbering is different from UMC numbering. | |
3897 | * | |
3898 | * On CPU nodes channels are selected in 6th nibble | |
3899 | * UMC chY[3:0]= [(chY*2 + 1) : (chY*2)]50000; | |
3900 | * | |
3901 | * On GPU nodes channels are selected in 3rd nibble | |
3902 | * HBM chX[3:0]= [Y ]5X[3:0]000; | |
3903 | * HBM chX[7:4]= [Y+1]5X[3:0]000 | |
12f230c0 M |
3904 | * |
3905 | * On MI300 APU nodes, same as GPU nodes but channels are selected | |
3906 | * in the base address of 0x90000 | |
9c42edd5 M |
3907 | */ |
3908 | umc *= 2; | |
3909 | ||
3910 | if (channel >= 4) | |
3911 | umc++; | |
3912 | ||
12f230c0 | 3913 | return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12); |
9c42edd5 M |
3914 | } |
3915 | ||
3916 | static void gpu_read_mc_regs(struct amd64_pvt *pvt) | |
3917 | { | |
3918 | u8 nid = pvt->mc_node_id; | |
3919 | struct amd64_umc *umc; | |
3920 | u32 i, umc_base; | |
3921 | ||
3922 | /* Read registers from each UMC */ | |
3923 | for_each_umc(i) { | |
12f230c0 | 3924 | umc_base = gpu_get_umc_base(pvt, i, 0); |
9c42edd5 M |
3925 | umc = &pvt->umc[i]; |
3926 | ||
3927 | amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); | |
3928 | amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); | |
3929 | amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); | |
3930 | } | |
3931 | } | |
3932 | ||
3933 | static void gpu_read_base_mask(struct amd64_pvt *pvt) | |
3934 | { | |
3935 | u32 base_reg, mask_reg; | |
3936 | u32 *base, *mask; | |
3937 | int umc, cs; | |
3938 | ||
3939 | for_each_umc(umc) { | |
3940 | for_each_chip_select(cs, umc, pvt) { | |
12f230c0 | 3941 | base_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_BASE_ADDR; |
9c42edd5 M |
3942 | base = &pvt->csels[umc].csbases[cs]; |
3943 | ||
3944 | if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) { | |
3945 | edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n", | |
3946 | umc, cs, *base, base_reg); | |
3947 | } | |
3948 | ||
12f230c0 | 3949 | mask_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_ADDR_MASK; |
9c42edd5 M |
3950 | mask = &pvt->csels[umc].csmasks[cs]; |
3951 | ||
3952 | if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) { | |
3953 | edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n", | |
3954 | umc, cs, *mask, mask_reg); | |
3955 | } | |
3956 | } | |
3957 | } | |
3958 | } | |
3959 | ||
3960 | static void gpu_prep_chip_selects(struct amd64_pvt *pvt) | |
3961 | { | |
3962 | int umc; | |
3963 | ||
3964 | for_each_umc(umc) { | |
3965 | pvt->csels[umc].b_cnt = 8; | |
3966 | pvt->csels[umc].m_cnt = 8; | |
3967 | } | |
3968 | } | |
3969 | ||
3970 | static int gpu_hw_info_get(struct amd64_pvt *pvt) | |
3971 | { | |
4251566e YG |
3972 | int ret; |
3973 | ||
12f230c0 | 3974 | ret = gpu_get_node_map(pvt); |
4251566e YG |
3975 | if (ret) |
3976 | return ret; | |
3977 | ||
9c42edd5 M |
3978 | pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); |
3979 | if (!pvt->umc) | |
3980 | return -ENOMEM; | |
3981 | ||
3982 | gpu_prep_chip_selects(pvt); | |
3983 | gpu_read_base_mask(pvt); | |
3984 | gpu_read_mc_regs(pvt); | |
3985 | ||
3986 | return 0; | |
3987 | } | |
3988 | ||
9a97a7f4 YG |
3989 | static void hw_info_put(struct amd64_pvt *pvt) |
3990 | { | |
3991 | pci_dev_put(pvt->F1); | |
3992 | pci_dev_put(pvt->F2); | |
3993 | kfree(pvt->umc); | |
3994 | } | |
3995 | ||
ed623d55 | 3996 | static struct low_ops umc_ops = { |
9a97a7f4 | 3997 | .hw_info_get = umc_hw_info_get, |
eb2bcdfc | 3998 | .ecc_enabled = umc_ecc_enabled, |
0a42a37f | 3999 | .setup_mci_misc_attrs = umc_setup_mci_misc_attrs, |
f6f36382 | 4000 | .dump_misc_regs = umc_dump_misc_regs, |
b3ece3a6 | 4001 | .get_err_info = umc_get_err_info, |
ed623d55 M |
4002 | }; |
4003 | ||
9c42edd5 M |
4004 | static struct low_ops gpu_ops = { |
4005 | .hw_info_get = gpu_hw_info_get, | |
4006 | .ecc_enabled = gpu_ecc_enabled, | |
4007 | .setup_mci_misc_attrs = gpu_setup_mci_misc_attrs, | |
4008 | .dump_misc_regs = gpu_dump_misc_regs, | |
4009 | .get_err_info = gpu_get_err_info, | |
4010 | }; | |
4011 | ||
ed623d55 M |
4012 | /* Use Family 16h versions for defaults and adjust as needed below. */ |
4013 | static struct low_ops dct_ops = { | |
4014 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, | |
4015 | .dbam_to_cs = f16_dbam_to_chip_select, | |
9a97a7f4 | 4016 | .hw_info_get = dct_hw_info_get, |
eb2bcdfc | 4017 | .ecc_enabled = dct_ecc_enabled, |
0a42a37f | 4018 | .setup_mci_misc_attrs = dct_setup_mci_misc_attrs, |
f6f36382 | 4019 | .dump_misc_regs = dct_dump_misc_regs, |
ed623d55 M |
4020 | }; |
4021 | ||
4022 | static int per_family_init(struct amd64_pvt *pvt) | |
395ae783 | 4023 | { |
18b94f66 | 4024 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
b399151c | 4025 | pvt->stepping = boot_cpu_data.x86_stepping; |
18b94f66 AG |
4026 | pvt->model = boot_cpu_data.x86_model; |
4027 | pvt->fam = boot_cpu_data.x86; | |
ed623d55 M |
4028 | pvt->max_mcs = 2; |
4029 | ||
4030 | /* | |
4031 | * Decide on which ops group to use here and do any family/model | |
4032 | * overrides below. | |
4033 | */ | |
4034 | if (pvt->fam >= 0x17) | |
4035 | pvt->ops = &umc_ops; | |
4036 | else | |
4037 | pvt->ops = &dct_ops; | |
18b94f66 AG |
4038 | |
4039 | switch (pvt->fam) { | |
395ae783 | 4040 | case 0xf: |
ed623d55 M |
4041 | pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ? |
4042 | "K8 revF or later" : "K8 revE or earlier"; | |
4043 | pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; | |
4044 | pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; | |
4045 | pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; | |
4046 | pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; | |
395ae783 | 4047 | break; |
df71a053 | 4048 | |
395ae783 | 4049 | case 0x10: |
ed623d55 M |
4050 | pvt->ctl_name = "F10h"; |
4051 | pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; | |
4052 | pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; | |
4053 | pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; | |
df71a053 BP |
4054 | break; |
4055 | ||
4056 | case 0x15: | |
ed623d55 M |
4057 | switch (pvt->model) { |
4058 | case 0x30: | |
4059 | pvt->ctl_name = "F15h_M30h"; | |
4060 | pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; | |
4061 | pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; | |
18b94f66 | 4062 | break; |
ed623d55 M |
4063 | case 0x60: |
4064 | pvt->ctl_name = "F15h_M60h"; | |
4065 | pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; | |
4066 | pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; | |
4067 | pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; | |
4068 | break; | |
4069 | case 0x13: | |
4070 | /* Richland is only client */ | |
4071 | return -ENODEV; | |
4072 | default: | |
4073 | pvt->ctl_name = "F15h"; | |
4074 | pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; | |
4075 | pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; | |
4076 | pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; | |
a597d2a5 | 4077 | break; |
18b94f66 | 4078 | } |
395ae783 BP |
4079 | break; |
4080 | ||
94c1acf2 | 4081 | case 0x16: |
ed623d55 M |
4082 | switch (pvt->model) { |
4083 | case 0x30: | |
4084 | pvt->ctl_name = "F16h_M30h"; | |
4085 | pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; | |
4086 | pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; | |
4087 | break; | |
4088 | default: | |
4089 | pvt->ctl_name = "F16h"; | |
4090 | pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; | |
4091 | pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; | |
85a8885b AG |
4092 | break; |
4093 | } | |
94c1acf2 AG |
4094 | break; |
4095 | ||
f1cbbec9 | 4096 | case 0x17: |
ed623d55 M |
4097 | switch (pvt->model) { |
4098 | case 0x10 ... 0x2f: | |
4099 | pvt->ctl_name = "F17h_M10h"; | |
8960de4a | 4100 | break; |
ed623d55 M |
4101 | case 0x30 ... 0x3f: |
4102 | pvt->ctl_name = "F17h_M30h"; | |
4103 | pvt->max_mcs = 8; | |
6e846239 | 4104 | break; |
ed623d55 M |
4105 | case 0x60 ... 0x6f: |
4106 | pvt->ctl_name = "F17h_M60h"; | |
b6bea24d | 4107 | break; |
ed623d55 M |
4108 | case 0x70 ... 0x7f: |
4109 | pvt->ctl_name = "F17h_M70h"; | |
4110 | break; | |
4111 | default: | |
4112 | pvt->ctl_name = "F17h"; | |
3e443eb3 | 4113 | break; |
8960de4a | 4114 | } |
ed623d55 | 4115 | break; |
c4a3e946 | 4116 | |
ed623d55 M |
4117 | case 0x18: |
4118 | pvt->ctl_name = "F18h"; | |
f1cbbec9 YG |
4119 | break; |
4120 | ||
2eb61c91 | 4121 | case 0x19: |
ed623d55 M |
4122 | switch (pvt->model) { |
4123 | case 0x00 ... 0x0f: | |
4124 | pvt->ctl_name = "F19h"; | |
4125 | pvt->max_mcs = 8; | |
e2be5955 | 4126 | break; |
ed623d55 M |
4127 | case 0x10 ... 0x1f: |
4128 | pvt->ctl_name = "F19h_M10h"; | |
4129 | pvt->max_mcs = 12; | |
4130 | pvt->flags.zn_regs_v2 = 1; | |
b4210eab | 4131 | break; |
ed623d55 M |
4132 | case 0x20 ... 0x2f: |
4133 | pvt->ctl_name = "F19h_M20h"; | |
0b8bf9cb | 4134 | break; |
9c42edd5 M |
4135 | case 0x30 ... 0x3f: |
4136 | if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) { | |
4137 | pvt->ctl_name = "MI200"; | |
4138 | pvt->max_mcs = 4; | |
12f230c0 M |
4139 | pvt->dram_type = MEM_HBM2; |
4140 | pvt->gpu_umc_base = 0x50000; | |
9c42edd5 M |
4141 | pvt->ops = &gpu_ops; |
4142 | } else { | |
4143 | pvt->ctl_name = "F19h_M30h"; | |
4144 | pvt->max_mcs = 8; | |
4145 | } | |
4146 | break; | |
ed623d55 M |
4147 | case 0x50 ... 0x5f: |
4148 | pvt->ctl_name = "F19h_M50h"; | |
4149 | break; | |
6c79e421 HV |
4150 | case 0x60 ... 0x6f: |
4151 | pvt->ctl_name = "F19h_M60h"; | |
4152 | pvt->flags.zn_regs_v2 = 1; | |
4153 | break; | |
4154 | case 0x70 ... 0x7f: | |
4155 | pvt->ctl_name = "F19h_M70h"; | |
4156 | pvt->flags.zn_regs_v2 = 1; | |
4157 | break; | |
12f230c0 M |
4158 | case 0x90 ... 0x9f: |
4159 | pvt->ctl_name = "F19h_M90h"; | |
4160 | pvt->max_mcs = 4; | |
4161 | pvt->dram_type = MEM_HBM3; | |
4162 | pvt->gpu_umc_base = 0x90000; | |
4163 | pvt->ops = &gpu_ops; | |
4164 | break; | |
ed623d55 M |
4165 | case 0xa0 ... 0xaf: |
4166 | pvt->ctl_name = "F19h_MA0h"; | |
4167 | pvt->max_mcs = 12; | |
4168 | pvt->flags.zn_regs_v2 = 1; | |
e2be5955 | 4169 | break; |
b4210eab | 4170 | } |
2eb61c91 YG |
4171 | break; |
4172 | ||
c4d07c37 AN |
4173 | case 0x1A: |
4174 | switch (pvt->model) { | |
4175 | case 0x00 ... 0x1f: | |
4176 | pvt->ctl_name = "F1Ah"; | |
4177 | pvt->max_mcs = 12; | |
4178 | pvt->flags.zn_regs_v2 = 1; | |
4179 | break; | |
4180 | case 0x40 ... 0x4f: | |
4181 | pvt->ctl_name = "F1Ah_M40h"; | |
4182 | pvt->flags.zn_regs_v2 = 1; | |
4183 | break; | |
4184 | } | |
4185 | break; | |
4186 | ||
395ae783 | 4187 | default: |
24f9a7fe | 4188 | amd64_err("Unsupported family!\n"); |
ed623d55 | 4189 | return -ENODEV; |
395ae783 | 4190 | } |
0092b20d | 4191 | |
ed623d55 | 4192 | return 0; |
395ae783 BP |
4193 | } |
4194 | ||
e339f1ec TI |
4195 | static const struct attribute_group *amd64_edac_attr_groups[] = { |
4196 | #ifdef CONFIG_EDAC_DEBUG | |
2a28ceef | 4197 | &dbg_group, |
61810096 | 4198 | &inj_group, |
e339f1ec TI |
4199 | #endif |
4200 | NULL | |
4201 | }; | |
4202 | ||
12f230c0 M |
4203 | /* |
4204 | * For heterogeneous and APU models EDAC CHIP_SELECT and CHANNEL layers | |
4205 | * should be swapped to fit into the layers. | |
4206 | */ | |
4207 | static unsigned int get_layer_size(struct amd64_pvt *pvt, u8 layer) | |
4208 | { | |
4209 | bool is_gpu = (pvt->ops == &gpu_ops); | |
4210 | ||
4211 | if (!layer) | |
4212 | return is_gpu ? pvt->max_mcs | |
4213 | : pvt->csels[0].b_cnt; | |
4214 | else | |
4215 | return is_gpu ? pvt->csels[0].b_cnt | |
4216 | : pvt->max_mcs; | |
4217 | } | |
4218 | ||
80355a3b YG |
4219 | static int init_one_instance(struct amd64_pvt *pvt) |
4220 | { | |
4221 | struct mem_ctl_info *mci = NULL; | |
4222 | struct edac_mc_layer layers[2]; | |
c4605bde | 4223 | int ret = -ENOMEM; |
7d6034d3 | 4224 | |
ab5a503c | 4225 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
12f230c0 | 4226 | layers[0].size = get_layer_size(pvt, 0); |
ab5a503c MCC |
4227 | layers[0].is_virt_csrow = true; |
4228 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
12f230c0 | 4229 | layers[1].size = get_layer_size(pvt, 1); |
ab5a503c | 4230 | layers[1].is_virt_csrow = false; |
f0a56c48 | 4231 | |
80355a3b | 4232 | mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); |
7d6034d3 | 4233 | if (!mci) |
80355a3b | 4234 | return ret; |
7d6034d3 DT |
4235 | |
4236 | mci->pvt_info = pvt; | |
3f37a36b | 4237 | mci->pdev = &pvt->F3->dev; |
7d6034d3 | 4238 | |
0a42a37f | 4239 | pvt->ops->setup_mci_misc_attrs(mci); |
7d6034d3 | 4240 | |
7d6034d3 | 4241 | ret = -ENODEV; |
e339f1ec | 4242 | if (edac_mc_add_mc_with_groups(mci, amd64_edac_attr_groups)) { |
956b9ba1 | 4243 | edac_dbg(1, "failed edac_mc_add_mc()\n"); |
80355a3b YG |
4244 | edac_mc_free(mci); |
4245 | return ret; | |
7d6034d3 DT |
4246 | } |
4247 | ||
7d6034d3 | 4248 | return 0; |
7d6034d3 DT |
4249 | } |
4250 | ||
582f94b5 YG |
4251 | static bool instance_has_memory(struct amd64_pvt *pvt) |
4252 | { | |
4253 | bool cs_enabled = false; | |
4254 | int cs = 0, dct = 0; | |
4255 | ||
ed623d55 | 4256 | for (dct = 0; dct < pvt->max_mcs; dct++) { |
582f94b5 YG |
4257 | for_each_chip_select(cs, dct, pvt) |
4258 | cs_enabled |= csrow_enabled(cs, dct, pvt); | |
4259 | } | |
4260 | ||
4261 | return cs_enabled; | |
4262 | } | |
4263 | ||
3f37a36b | 4264 | static int probe_one_instance(unsigned int nid) |
7d6034d3 | 4265 | { |
2299ef71 | 4266 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
80355a3b | 4267 | struct amd64_pvt *pvt = NULL; |
ae7bb7c6 | 4268 | struct ecc_settings *s; |
3f37a36b | 4269 | int ret; |
7d6034d3 | 4270 | |
ae7bb7c6 BP |
4271 | ret = -ENOMEM; |
4272 | s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL); | |
4273 | if (!s) | |
2299ef71 | 4274 | goto err_out; |
ae7bb7c6 BP |
4275 | |
4276 | ecc_stngs[nid] = s; | |
4277 | ||
80355a3b YG |
4278 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); |
4279 | if (!pvt) | |
4280 | goto err_settings; | |
4281 | ||
4282 | pvt->mc_node_id = nid; | |
4283 | pvt->F3 = F3; | |
4284 | ||
ed623d55 M |
4285 | ret = per_family_init(pvt); |
4286 | if (ret < 0) | |
80355a3b YG |
4287 | goto err_enable; |
4288 | ||
9a97a7f4 | 4289 | ret = pvt->ops->hw_info_get(pvt); |
80355a3b YG |
4290 | if (ret < 0) |
4291 | goto err_enable; | |
4292 | ||
582f94b5 YG |
4293 | ret = 0; |
4294 | if (!instance_has_memory(pvt)) { | |
4295 | amd64_info("Node %d: No DIMMs detected.\n", nid); | |
4296 | goto err_enable; | |
4297 | } | |
4298 | ||
eb2bcdfc | 4299 | if (!pvt->ops->ecc_enabled(pvt)) { |
582f94b5 | 4300 | ret = -ENODEV; |
2299ef71 BP |
4301 | |
4302 | if (!ecc_enable_override) | |
4303 | goto err_enable; | |
4304 | ||
044e7a41 YG |
4305 | if (boot_cpu_data.x86 >= 0x17) { |
4306 | amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS."); | |
4307 | goto err_enable; | |
4308 | } else | |
4309 | amd64_warn("Forcing ECC on!\n"); | |
2299ef71 BP |
4310 | |
4311 | if (!enable_ecc_error_reporting(s, nid, F3)) | |
4312 | goto err_enable; | |
4313 | } | |
4314 | ||
80355a3b | 4315 | ret = init_one_instance(pvt); |
360b7f3c | 4316 | if (ret < 0) { |
ae7bb7c6 | 4317 | amd64_err("Error probing instance: %d\n", nid); |
044e7a41 YG |
4318 | |
4319 | if (boot_cpu_data.x86 < 0x17) | |
4320 | restore_ecc_error_reporting(s, nid, F3); | |
2b9b2c46 YG |
4321 | |
4322 | goto err_enable; | |
360b7f3c | 4323 | } |
7d6034d3 | 4324 | |
ed623d55 | 4325 | amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); |
4cbcb73b | 4326 | |
f6f36382 M |
4327 | /* Display and decode various registers for debug purposes. */ |
4328 | pvt->ops->dump_misc_regs(pvt); | |
582f94b5 | 4329 | |
7d6034d3 | 4330 | return ret; |
2299ef71 BP |
4331 | |
4332 | err_enable: | |
80355a3b YG |
4333 | hw_info_put(pvt); |
4334 | kfree(pvt); | |
4335 | ||
4336 | err_settings: | |
2299ef71 BP |
4337 | kfree(s); |
4338 | ecc_stngs[nid] = NULL; | |
4339 | ||
4340 | err_out: | |
4341 | return ret; | |
7d6034d3 DT |
4342 | } |
4343 | ||
3f37a36b | 4344 | static void remove_one_instance(unsigned int nid) |
7d6034d3 | 4345 | { |
360b7f3c BP |
4346 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
4347 | struct ecc_settings *s = ecc_stngs[nid]; | |
3f37a36b BP |
4348 | struct mem_ctl_info *mci; |
4349 | struct amd64_pvt *pvt; | |
7d6034d3 DT |
4350 | |
4351 | /* Remove from EDAC CORE tracking list */ | |
3f37a36b | 4352 | mci = edac_mc_del_mc(&F3->dev); |
7d6034d3 DT |
4353 | if (!mci) |
4354 | return; | |
4355 | ||
4356 | pvt = mci->pvt_info; | |
4357 | ||
360b7f3c | 4358 | restore_ecc_error_reporting(s, nid, F3); |
7d6034d3 | 4359 | |
360b7f3c BP |
4360 | kfree(ecc_stngs[nid]); |
4361 | ecc_stngs[nid] = NULL; | |
ae7bb7c6 | 4362 | |
7d6034d3 | 4363 | /* Free the EDAC CORE resources */ |
8f68ed97 | 4364 | mci->pvt_info = NULL; |
8f68ed97 | 4365 | |
80355a3b | 4366 | hw_info_put(pvt); |
8f68ed97 | 4367 | kfree(pvt); |
7d6034d3 DT |
4368 | edac_mc_free(mci); |
4369 | } | |
4370 | ||
360b7f3c | 4371 | static void setup_pci_device(void) |
7d6034d3 | 4372 | { |
d1ea71cd | 4373 | if (pci_ctl) |
7d6034d3 DT |
4374 | return; |
4375 | ||
706657b1 | 4376 | pci_ctl = edac_pci_create_generic_ctl(pci_ctl_dev, EDAC_MOD_STR); |
d1ea71cd BP |
4377 | if (!pci_ctl) { |
4378 | pr_warn("%s(): Unable to create PCI control\n", __func__); | |
4379 | pr_warn("%s(): PCI error report via EDAC not set\n", __func__); | |
7d6034d3 DT |
4380 | } |
4381 | } | |
4382 | ||
d6efab74 | 4383 | static const struct x86_cpu_id amd64_cpuids[] = { |
29842621 TG |
4384 | X86_MATCH_VENDOR_FAM(AMD, 0x0F, NULL), |
4385 | X86_MATCH_VENDOR_FAM(AMD, 0x10, NULL), | |
4386 | X86_MATCH_VENDOR_FAM(AMD, 0x15, NULL), | |
4387 | X86_MATCH_VENDOR_FAM(AMD, 0x16, NULL), | |
4388 | X86_MATCH_VENDOR_FAM(AMD, 0x17, NULL), | |
4389 | X86_MATCH_VENDOR_FAM(HYGON, 0x18, NULL), | |
4390 | X86_MATCH_VENDOR_FAM(AMD, 0x19, NULL), | |
c4d07c37 | 4391 | X86_MATCH_VENDOR_FAM(AMD, 0x1A, NULL), |
d6efab74 YG |
4392 | { } |
4393 | }; | |
4394 | MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids); | |
4395 | ||
7d6034d3 DT |
4396 | static int __init amd64_edac_init(void) |
4397 | { | |
301375e7 | 4398 | const char *owner; |
360b7f3c | 4399 | int err = -ENODEV; |
3f37a36b | 4400 | int i; |
7d6034d3 | 4401 | |
315bada6 JH |
4402 | if (ghes_get_devices()) |
4403 | return -EBUSY; | |
4404 | ||
301375e7 TK |
4405 | owner = edac_get_owner(); |
4406 | if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) | |
4407 | return -EBUSY; | |
4408 | ||
1bd9900b YG |
4409 | if (!x86_match_cpu(amd64_cpuids)) |
4410 | return -ENODEV; | |
4411 | ||
e1907d37 | 4412 | if (!amd_nb_num()) |
1bd9900b | 4413 | return -ENODEV; |
7d6034d3 | 4414 | |
6ba92fea BP |
4415 | opstate_init(); |
4416 | ||
cc4d8860 | 4417 | err = -ENOMEM; |
6396bb22 | 4418 | ecc_stngs = kcalloc(amd_nb_num(), sizeof(ecc_stngs[0]), GFP_KERNEL); |
2ec591ac | 4419 | if (!ecc_stngs) |
a9f0fbe2 | 4420 | goto err_free; |
cc4d8860 | 4421 | |
50542251 | 4422 | msrs = msrs_alloc(); |
56b34b91 | 4423 | if (!msrs) |
360b7f3c | 4424 | goto err_free; |
50542251 | 4425 | |
2287c636 YG |
4426 | for (i = 0; i < amd_nb_num(); i++) { |
4427 | err = probe_one_instance(i); | |
4428 | if (err) { | |
3f37a36b BP |
4429 | /* unwind properly */ |
4430 | while (--i >= 0) | |
4431 | remove_one_instance(i); | |
7d6034d3 | 4432 | |
3f37a36b BP |
4433 | goto err_pci; |
4434 | } | |
2287c636 | 4435 | } |
7d6034d3 | 4436 | |
4688c9b4 YG |
4437 | if (!edac_has_mcs()) { |
4438 | err = -ENODEV; | |
4439 | goto err_pci; | |
4440 | } | |
4441 | ||
234365f5 | 4442 | /* register stuff with EDAC MCE */ |
fdce765a | 4443 | if (boot_cpu_data.x86 >= 0x17) { |
234365f5 | 4444 | amd_register_ecc_decoder(decode_umc_error); |
fdce765a | 4445 | } else { |
234365f5 | 4446 | amd_register_ecc_decoder(decode_bus_error); |
fdce765a YG |
4447 | setup_pci_device(); |
4448 | } | |
f5b10c45 TP |
4449 | |
4450 | #ifdef CONFIG_X86_32 | |
4451 | amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR); | |
4452 | #endif | |
4453 | ||
360b7f3c | 4454 | return 0; |
7d6034d3 | 4455 | |
56b34b91 | 4456 | err_pci: |
706657b1 BP |
4457 | pci_ctl_dev = NULL; |
4458 | ||
56b34b91 BP |
4459 | msrs_free(msrs); |
4460 | msrs = NULL; | |
cc4d8860 | 4461 | |
360b7f3c | 4462 | err_free: |
360b7f3c BP |
4463 | kfree(ecc_stngs); |
4464 | ecc_stngs = NULL; | |
4465 | ||
7d6034d3 DT |
4466 | return err; |
4467 | } | |
4468 | ||
4469 | static void __exit amd64_edac_exit(void) | |
4470 | { | |
3f37a36b BP |
4471 | int i; |
4472 | ||
d1ea71cd BP |
4473 | if (pci_ctl) |
4474 | edac_pci_release_generic_ctl(pci_ctl); | |
7d6034d3 | 4475 | |
234365f5 | 4476 | /* unregister from EDAC MCE */ |
234365f5 YG |
4477 | if (boot_cpu_data.x86 >= 0x17) |
4478 | amd_unregister_ecc_decoder(decode_umc_error); | |
4479 | else | |
4480 | amd_unregister_ecc_decoder(decode_bus_error); | |
4481 | ||
3f37a36b BP |
4482 | for (i = 0; i < amd_nb_num(); i++) |
4483 | remove_one_instance(i); | |
50542251 | 4484 | |
ae7bb7c6 BP |
4485 | kfree(ecc_stngs); |
4486 | ecc_stngs = NULL; | |
4487 | ||
706657b1 BP |
4488 | pci_ctl_dev = NULL; |
4489 | ||
50542251 BP |
4490 | msrs_free(msrs); |
4491 | msrs = NULL; | |
7d6034d3 DT |
4492 | } |
4493 | ||
4494 | module_init(amd64_edac_init); | |
4495 | module_exit(amd64_edac_exit); | |
4496 | ||
4497 | MODULE_LICENSE("GPL"); | |
371b27f2 | 4498 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, Dave Peterson, Thayne Harbaugh; AMD"); |
b34348a0 | 4499 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers"); |
7d6034d3 DT |
4500 | |
4501 | module_param(edac_op_state, int, 0444); | |
4502 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |