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EDAC/altera: Initialize peripheral FIFOs in probe()
[linux-block.git] / drivers / edac / altera_edac.c
CommitLineData
3dab6bd5 1// SPDX-License-Identifier: GPL-2.0
71bcada8 2/*
3dab6bd5 3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
c3eea194 4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
71bcada8 5 * Copyright 2011-2012 Calxeda, Inc.
71bcada8
TT		 6 */
7
c3eea194 8#include <asm/cacheflush.h>
71bcada8 9#include <linux/ctype.h>
1166fde9 10#include <linux/delay.h>
71bcada8 11#include <linux/edac.h>
c3eea194 12#include <linux/genalloc.h>
71bcada8 13#include <linux/interrupt.h>
13ab8448 14#include <linux/irqchip/chained_irq.h>
71bcada8
TT		 15#include <linux/kernel.h>
16#include <linux/mfd/syscon.h>
e9918d7f 17#include <linux/notifier.h>
588cb03e 18#include <linux/of_address.h>
13ab8448 19#include <linux/of_irq.h>
71bcada8
TT		 20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/types.h>
24#include <linux/uaccess.h>
25
143f4a5a 26#include "altera_edac.h"
71bcada8
TT		 27#include "edac_module.h"
28
29#define EDAC_MOD_STR "altera_edac"
c3eea194 30#define EDAC_DEVICE "Altera"
71bcada8 31
580b5cf5 32#ifdef CONFIG_EDAC_ALTERA_SDRAM
143f4a5a
TT		 33static const struct altr_sdram_prv_data c5_data = {
34 .ecc_ctrl_offset = CV_CTLCFG_OFST,
35 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
36 .ecc_stat_offset = CV_DRAMSTS_OFST,
37 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
38 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
39 .ecc_saddr_offset = CV_ERRADDR_OFST,
73bcc942 40 .ecc_daddr_offset = CV_ERRADDR_OFST,
143f4a5a
TT		 41 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
42 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
43 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
44 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
45 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
46 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
47 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
48 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
143f4a5a
TT		 49 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
50 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
51 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
71bcada8
TT		 52};
53
73bcc942
TT		 54static const struct altr_sdram_prv_data a10_data = {
55 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
56 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
57 .ecc_stat_offset = A10_INTSTAT_OFST,
58 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
59 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
60 .ecc_saddr_offset = A10_SERRADDR_OFST,
61 .ecc_daddr_offset = A10_DERRADDR_OFST,
62 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
63 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
64 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
65 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
66 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
67 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
73bcc942
TT		 68 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
69 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
70 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
73bcc942
TT		 71};
72
c3eea194
TT		 73/*********************** EDAC Memory Controller Functions ****************/
74
75/* The SDRAM controller uses the EDAC Memory Controller framework. */
76
71bcada8
TT		 77static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
78{
79 struct mem_ctl_info *mci = dev_id;
80 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
143f4a5a 81 const struct altr_sdram_prv_data *priv = drvdata->data;
73bcc942 82 u32 status, err_count = 1, err_addr;
71bcada8 83
143f4a5a 84 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
71bcada8 85
143f4a5a 86 if (status & priv->ecc_stat_ue_mask) {
73bcc942
TT		 87 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
88 &err_addr);
89 if (priv->ecc_uecnt_offset)
90 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
91 &err_count);
71bcada8
TT		 92 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
93 err_count, err_addr);
94 }
143f4a5a 95 if (status & priv->ecc_stat_ce_mask) {
73bcc942
TT		 96 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
97 &err_addr);
98 if (priv->ecc_uecnt_offset)
99 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
100 &err_count);
71bcada8
TT		 101 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
102 err_addr >> PAGE_SHIFT,
103 err_addr & ~PAGE_MASK, 0,
104 0, 0, -1, mci->ctl_name, "");
73bcc942
TT		 105 /* Clear IRQ to resume */
106 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
107 priv->ecc_irq_clr_mask);
71bcada8 108
73bcc942
TT		 109 return IRQ_HANDLED;
110 }
111 return IRQ_NONE;
71bcada8
TT		 112}
113
71bcada8
TT		 114static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
115 const char __user *data,
116 size_t count, loff_t *ppos)
117{
118 struct mem_ctl_info *mci = file->private_data;
119 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
143f4a5a 120 const struct altr_sdram_prv_data *priv = drvdata->data;
71bcada8
TT		 121 u32 *ptemp;
122 dma_addr_t dma_handle;
123 u32 reg, read_reg;
124
125 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
126 if (!ptemp) {
127 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
128 edac_printk(KERN_ERR, EDAC_MC,
129 "Inject: Buffer Allocation error\n");
130 return -ENOMEM;
131 }
132
143f4a5a
TT		 133 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
134 &read_reg);
135 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
71bcada8
TT		 136
137 /* Error are injected by writing a word while the SBE or DBE
138 * bit in the CTLCFG register is set. Reading the word will
139 * trigger the SBE or DBE error and the corresponding IRQ.
140 */
141 if (count == 3) {
142 edac_printk(KERN_ALERT, EDAC_MC,
143 "Inject Double bit error\n");
90e493d7 144 local_irq_disable();
143f4a5a
TT		 145 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
146 (read_reg | priv->ue_set_mask));
90e493d7 147 local_irq_enable();
71bcada8
TT		 148 } else {
149 edac_printk(KERN_ALERT, EDAC_MC,
150 "Inject Single bit error\n");
90e493d7 151 local_irq_disable();
143f4a5a
TT		 152 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
153 (read_reg | priv->ce_set_mask));
90e493d7 154 local_irq_enable();
71bcada8
TT		 155 }
156
157 ptemp[0] = 0x5A5A5A5A;
158 ptemp[1] = 0xA5A5A5A5;
159
160 /* Clear the error injection bits */
143f4a5a 161 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
71bcada8
TT		 162 /* Ensure it has been written out */
163 wmb();
164
165 /*
166 * To trigger the error, we need to read the data back
167 * (the data was written with errors above).
332efa63 168 * The READ_ONCE macros and printk are used to prevent the
71bcada8
TT		 169 * the compiler optimizing these reads out.
170 */
332efa63
MR		 171 reg = READ_ONCE(ptemp[0]);
172 read_reg = READ_ONCE(ptemp[1]);
71bcada8
TT		 173 /* Force Read */
174 rmb();
175
176 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
177 reg, read_reg);
178
179 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
180
181 return count;
182}
183
184static const struct file_operations altr_sdr_mc_debug_inject_fops = {
185 .open = simple_open,
186 .write = altr_sdr_mc_err_inject_write,
187 .llseek = generic_file_llseek,
188};
189
190static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
191{
bba3b31e
BP		 192 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
193 return;
194
195 if (!mci->debugfs)
196 return;
197
b8978bad 198 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
bba3b31e 199 &altr_sdr_mc_debug_inject_fops);
71bcada8 200}
71bcada8 201
f9ae487e
TT		 202/* Get total memory size from Open Firmware DTB */
203static unsigned long get_total_mem(void)
71bcada8 204{
f9ae487e 205 struct device_node *np = NULL;
ff0abed4
CP		 206 struct resource res;
207 int ret;
208 unsigned long total_mem = 0;
f9ae487e
TT		 209
210 for_each_node_by_type(np, "memory") {
ff0abed4
CP		 211 ret = of_address_to_resource(np, 0, &res);
212 if (ret)
213 continue;
214
215 total_mem += resource_size(&res);
f9ae487e
TT		 216 }
217 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
218 return total_mem;
71bcada8
TT		 219}
220
143f4a5a 221static const struct of_device_id altr_sdram_ctrl_of_match[] = {
2c911f6c
AB		 222 { .compatible = "altr,sdram-edac", .data = &c5_data},
223 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
08f08bfb 224 { .compatible = "altr,sdram-edac-s10", .data = &a10_data},
143f4a5a
TT		 225 {},
226};
227MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
228
73bcc942
TT		 229static int a10_init(struct regmap *mc_vbase)
230{
231 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
232 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
233 edac_printk(KERN_ERR, EDAC_MC,
234 "Error setting SB IRQ mode\n");
235 return -ENODEV;
236 }
237
238 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
239 edac_printk(KERN_ERR, EDAC_MC,
240 "Error setting trigger count\n");
241 return -ENODEV;
242 }
243
244 return 0;
245}
246
247static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
248{
249 void __iomem *sm_base;
250 int ret = 0;
251
252 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
253 dev_name(&pdev->dev))) {
254 edac_printk(KERN_ERR, EDAC_MC,
255 "Unable to request mem region\n");
256 return -EBUSY;
257 }
258
259 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
260 if (!sm_base) {
261 edac_printk(KERN_ERR, EDAC_MC,
262 "Unable to ioremap device\n");
263
264 ret = -ENOMEM;
265 goto release;
266 }
267
268 iowrite32(mask, sm_base);
269
270 iounmap(sm_base);
271
272release:
273 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
274
275 return ret;
276}
277
08f08bfb 278static int socfpga_is_a10(void);
71bcada8
TT		 279static int altr_sdram_probe(struct platform_device *pdev)
280{
143f4a5a 281 const struct of_device_id *id;
71bcada8
TT		 282 struct edac_mc_layer layers[2];
283 struct mem_ctl_info *mci;
284 struct altr_sdram_mc_data *drvdata;
143f4a5a 285 const struct altr_sdram_prv_data *priv;
71bcada8
TT		 286 struct regmap *mc_vbase;
287 struct dimm_info *dimm;
143f4a5a 288 u32 read_reg;
73bcc942
TT		 289 int irq, irq2, res = 0;
290 unsigned long mem_size, irqflags = 0;
143f4a5a
TT		 291
292 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
293 if (!id)
294 return -ENODEV;
71bcada8 295
71bcada8
TT		 296 /* Grab the register range from the sdr controller in device tree */
297 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
298 "altr,sdr-syscon");
299 if (IS_ERR(mc_vbase)) {
300 edac_printk(KERN_ERR, EDAC_MC,
301 "regmap for altr,sdr-syscon lookup failed.\n");
302 return -ENODEV;
303 }
304
143f4a5a
TT		 305 /* Check specific dependencies for the module */
306 priv = of_match_node(altr_sdram_ctrl_of_match,
307 pdev->dev.of_node)->data;
308
309 /* Validate the SDRAM controller has ECC enabled */
310 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
311 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
71bcada8
TT		 312 edac_printk(KERN_ERR, EDAC_MC,
313 "No ECC/ECC disabled [0x%08X]\n", read_reg);
314 return -ENODEV;
315 }
316
317 /* Grab memory size from device tree. */
f9ae487e 318 mem_size = get_total_mem();
71bcada8 319 if (!mem_size) {
f9ae487e 320 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
71bcada8
TT		 321 return -ENODEV;
322 }
323
143f4a5a
TT		 324 /* Ensure the SDRAM Interrupt is disabled */
325 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
326 priv->ecc_irq_en_mask, 0)) {
327 edac_printk(KERN_ERR, EDAC_MC,
328 "Error disabling SDRAM ECC IRQ\n");
329 return -ENODEV;
330 }
331
332 /* Toggle to clear the SDRAM Error count */
333 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
334 priv->ecc_cnt_rst_mask,
335 priv->ecc_cnt_rst_mask)) {
336 edac_printk(KERN_ERR, EDAC_MC,
337 "Error clearing SDRAM ECC count\n");
338 return -ENODEV;
339 }
340
341 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
342 priv->ecc_cnt_rst_mask, 0)) {
71bcada8 343 edac_printk(KERN_ERR, EDAC_MC,
143f4a5a 344 "Error clearing SDRAM ECC count\n");
71bcada8
TT		 345 return -ENODEV;
346 }
347
348 irq = platform_get_irq(pdev, 0);
349 if (irq < 0) {
350 edac_printk(KERN_ERR, EDAC_MC,
351 "No irq %d in DT\n", irq);
352 return -ENODEV;
353 }
354
73bcc942
TT		 355 /* Arria10 has a 2nd IRQ */
356 irq2 = platform_get_irq(pdev, 1);
357
71bcada8
TT		 358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
359 layers[0].size = 1;
360 layers[0].is_virt_csrow = true;
361 layers[1].type = EDAC_MC_LAYER_CHANNEL;
362 layers[1].size = 1;
363 layers[1].is_virt_csrow = false;
364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
365 sizeof(struct altr_sdram_mc_data));
366 if (!mci)
367 return -ENOMEM;
368
369 mci->pdev = &pdev->dev;
370 drvdata = mci->pvt_info;
371 drvdata->mc_vbase = mc_vbase;
143f4a5a 372 drvdata->data = priv;
71bcada8
TT		 373 platform_set_drvdata(pdev, mci);
374
375 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
143f4a5a
TT		 376 edac_printk(KERN_ERR, EDAC_MC,
377 "Unable to get managed device resource\n");
71bcada8
TT		 378 res = -ENOMEM;
379 goto free;
380 }
381
382 mci->mtype_cap = MEM_FLAG_DDR3;
383 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
384 mci->edac_cap = EDAC_FLAG_SECDED;
385 mci->mod_name = EDAC_MOD_STR;
71bcada8
TT		 386 mci->ctl_name = dev_name(&pdev->dev);
387 mci->scrub_mode = SCRUB_SW_SRC;
388 mci->dev_name = dev_name(&pdev->dev);
389
390 dimm = *mci->dimms;
391 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
392 dimm->grain = 8;
393 dimm->dtype = DEV_X8;
394 dimm->mtype = MEM_DDR3;
395 dimm->edac_mode = EDAC_SECDED;
396
397 res = edac_mc_add_mc(mci);
398 if (res < 0)
399 goto err;
400
73bcc942 401 /* Only the Arria10 has separate IRQs */
08f08bfb 402 if (socfpga_is_a10()) {
73bcc942
TT		 403 /* Arria10 specific initialization */
404 res = a10_init(mc_vbase);
405 if (res < 0)
406 goto err2;
407
408 res = devm_request_irq(&pdev->dev, irq2,
409 altr_sdram_mc_err_handler,
410 IRQF_SHARED, dev_name(&pdev->dev), mci);
411 if (res < 0) {
412 edac_mc_printk(mci, KERN_ERR,
413 "Unable to request irq %d\n", irq2);
414 res = -ENODEV;
415 goto err2;
416 }
417
418 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
419 if (res < 0)
420 goto err2;
421
422 irqflags = IRQF_SHARED;
423 }
424
71bcada8 425 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
73bcc942 426 irqflags, dev_name(&pdev->dev), mci);
71bcada8
TT		 427 if (res < 0) {
428 edac_mc_printk(mci, KERN_ERR,
429 "Unable to request irq %d\n", irq);
430 res = -ENODEV;
431 goto err2;
432 }
433
143f4a5a
TT		 434 /* Infrastructure ready - enable the IRQ */
435 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
436 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
71bcada8
TT		 437 edac_mc_printk(mci, KERN_ERR,
438 "Error enabling SDRAM ECC IRQ\n");
439 res = -ENODEV;
440 goto err2;
441 }
442
443 altr_sdr_mc_create_debugfs_nodes(mci);
444
445 devres_close_group(&pdev->dev, NULL);
446
447 return 0;
448
449err2:
450 edac_mc_del_mc(&pdev->dev);
451err:
452 devres_release_group(&pdev->dev, NULL);
453free:
454 edac_mc_free(mci);
455 edac_printk(KERN_ERR, EDAC_MC,
456 "EDAC Probe Failed; Error %d\n", res);
457
458 return res;
459}
460
461static int altr_sdram_remove(struct platform_device *pdev)
462{
463 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
464
465 edac_mc_del_mc(&pdev->dev);
466 edac_mc_free(mci);
467 platform_set_drvdata(pdev, NULL);
468
469 return 0;
470}
471
580b5cf5
TT		 472/*
473 * If you want to suspend, need to disable EDAC by removing it
474 * from the device tree or defconfig.
475 */
476#ifdef CONFIG_PM
477static int altr_sdram_prepare(struct device *dev)
478{
479 pr_err("Suspend not allowed when EDAC is enabled.\n");
480
481 return -EPERM;
482}
483
484static const struct dev_pm_ops altr_sdram_pm_ops = {
485 .prepare = altr_sdram_prepare,
486};
487#endif
488
489static struct platform_driver altr_sdram_edac_driver = {
490 .probe = altr_sdram_probe,
491 .remove = altr_sdram_remove,
492 .driver = {
493 .name = "altr_sdram_edac",
494#ifdef CONFIG_PM
495 .pm = &altr_sdram_pm_ops,
496#endif
497 .of_match_table = altr_sdram_ctrl_of_match,
498 },
499};
500
501module_platform_driver(altr_sdram_edac_driver);
502
503#endif /* CONFIG_EDAC_ALTERA_SDRAM */
504
3dab6bd5
TT		 505/**************** Stratix 10 EDAC Memory Controller Functions ************/
506
507/**
508 * s10_protected_reg_write
509 * Write to a protected SMC register.
510 * @context: Not used.
511 * @reg: Address of register
512 * @value: Value to write
513 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
514 * INTEL_SIP_SMC_REG_ERROR on error
515 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
516 */
517static int s10_protected_reg_write(void *context, unsigned int reg,
518 unsigned int val)
519{
520 struct arm_smccc_res result;
08f08bfb 521 unsigned long offset = (unsigned long)context;
3dab6bd5 522
08f08bfb 523 arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
3dab6bd5
TT		 524 0, 0, 0, &result);
525
526 return (int)result.a0;
527}
528
529/**
530 * s10_protected_reg_read
531 * Read the status of a protected SMC register
532 * @context: Not used.
533 * @reg: Address of register
534 * @value: Value read.
535 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
536 * INTEL_SIP_SMC_REG_ERROR on error
537 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
538 */
539static int s10_protected_reg_read(void *context, unsigned int reg,
540 unsigned int *val)
541{
542 struct arm_smccc_res result;
08f08bfb 543 unsigned long offset = (unsigned long)context;
3dab6bd5 544
08f08bfb 545 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
3dab6bd5
TT		 546 0, 0, 0, &result);
547
548 *val = (unsigned int)result.a1;
549
550 return (int)result.a0;
551}
552
3dab6bd5
TT		 553static const struct regmap_config s10_sdram_regmap_cfg = {
554 .name = "s10_ddr",
555 .reg_bits = 32,
556 .reg_stride = 4,
557 .val_bits = 32,
08f08bfb 558 .max_register = 0xffd12228,
3dab6bd5
TT		 559 .reg_read = s10_protected_reg_read,
560 .reg_write = s10_protected_reg_write,
1c96a2f6
DF		 561 .use_single_read = true,
562 .use_single_write = true,
3dab6bd5
TT		 563};
564
3dab6bd5
TT		 565/************** </Stratix10 EDAC Memory Controller Functions> ***********/
566
c3eea194
TT		 567/************************* EDAC Parent Probe *************************/
568
569static const struct of_device_id altr_edac_device_of_match[];
570
571static const struct of_device_id altr_edac_of_match[] = {
572 { .compatible = "altr,socfpga-ecc-manager" },
573 {},
574};
575MODULE_DEVICE_TABLE(of, altr_edac_of_match);
576
577static int altr_edac_probe(struct platform_device *pdev)
578{
579 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
580 NULL, &pdev->dev);
581 return 0;
582}
583
584static struct platform_driver altr_edac_driver = {
585 .probe = altr_edac_probe,
586 .driver = {
587 .name = "socfpga_ecc_manager",
588 .of_match_table = altr_edac_of_match,
589 },
590};
591module_platform_driver(altr_edac_driver);
592
593/************************* EDAC Device Functions *************************/
594
595/*
596 * EDAC Device Functions (shared between various IPs).
597 * The discrete memories use the EDAC Device framework. The probe
598 * and error handling functions are very similar between memories
599 * so they are shared. The memory allocation and freeing for EDAC
600 * trigger testing are different for each memory.
601 */
602
1cf70377
TT		 603static const struct edac_device_prv_data ocramecc_data;
604static const struct edac_device_prv_data l2ecc_data;
605static const struct edac_device_prv_data a10_ocramecc_data;
606static const struct edac_device_prv_data a10_l2ecc_data;
c3eea194 607
c3eea194
TT		 608static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
609{
610 irqreturn_t ret_value = IRQ_NONE;
611 struct edac_device_ctl_info *dci = dev_id;
612 struct altr_edac_device_dev *drvdata = dci->pvt_info;
613 const struct edac_device_prv_data *priv = drvdata->data;
614
615 if (irq == drvdata->sb_irq) {
616 if (priv->ce_clear_mask)
617 writel(priv->ce_clear_mask, drvdata->base);
618 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
619 ret_value = IRQ_HANDLED;
620 } else if (irq == drvdata->db_irq) {
621 if (priv->ue_clear_mask)
622 writel(priv->ue_clear_mask, drvdata->base);
623 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
624 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
625 ret_value = IRQ_HANDLED;
626 } else {
627 WARN_ON(1);
628 }
629
630 return ret_value;
631}
632
633static ssize_t altr_edac_device_trig(struct file *file,
634 const char __user *user_buf,
635 size_t count, loff_t *ppos)
636
637{
638 u32 *ptemp, i, error_mask;
639 int result = 0;
640 u8 trig_type;
641 unsigned long flags;
642 struct edac_device_ctl_info *edac_dci = file->private_data;
643 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
644 const struct edac_device_prv_data *priv = drvdata->data;
645 void *generic_ptr = edac_dci->dev;
646
647 if (!user_buf || get_user(trig_type, user_buf))
648 return -EFAULT;
649
650 if (!priv->alloc_mem)
651 return -ENOMEM;
652
653 /*
654 * Note that generic_ptr is initialized to the device * but in
655 * some alloc_functions, this is overridden and returns data.
656 */
657 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
658 if (!ptemp) {
659 edac_printk(KERN_ERR, EDAC_DEVICE,
660 "Inject: Buffer Allocation error\n");
661 return -ENOMEM;
662 }
663
664 if (trig_type == ALTR_UE_TRIGGER_CHAR)
665 error_mask = priv->ue_set_mask;
666 else
667 error_mask = priv->ce_set_mask;
668
669 edac_printk(KERN_ALERT, EDAC_DEVICE,
670 "Trigger Error Mask (0x%X)\n", error_mask);
671
672 local_irq_save(flags);
673 /* write ECC corrupted data out. */
674 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
675 /* Read data so we're in the correct state */
676 rmb();
332efa63 677 if (READ_ONCE(ptemp[i]))
c3eea194
TT		 678 result = -1;
679 /* Toggle Error bit (it is latched), leave ECC enabled */
811fce4f
TT		 680 writel(error_mask, (drvdata->base + priv->set_err_ofst));
681 writel(priv->ecc_enable_mask, (drvdata->base +
682 priv->set_err_ofst));
c3eea194
TT		 683 ptemp[i] = i;
684 }
685 /* Ensure it has been written out */
686 wmb();
687 local_irq_restore(flags);
688
689 if (result)
690 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
691
692 /* Read out written data. ECC error caused here */
693 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
332efa63 694 if (READ_ONCE(ptemp[i]) != i)
c3eea194
TT		 695 edac_printk(KERN_ERR, EDAC_DEVICE,
696 "Read doesn't match written data\n");
697
698 if (priv->free_mem)
699 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
700
701 return count;
702}
703
704static const struct file_operations altr_edac_device_inject_fops = {
705 .open = simple_open,
706 .write = altr_edac_device_trig,
707 .llseek = generic_file_llseek,
708};
709
c7b4be8d
TT		 710static ssize_t altr_edac_a10_device_trig(struct file *file,
711 const char __user *user_buf,
712 size_t count, loff_t *ppos);
713
714static const struct file_operations altr_edac_a10_device_inject_fops = {
715 .open = simple_open,
716 .write = altr_edac_a10_device_trig,
717 .llseek = generic_file_llseek,
718};
719
064acbd4
TT		 720static ssize_t altr_edac_a10_device_trig2(struct file *file,
721 const char __user *user_buf,
722 size_t count, loff_t *ppos);
723
724static const struct file_operations altr_edac_a10_device_inject2_fops = {
725 .open = simple_open,
726 .write = altr_edac_a10_device_trig2,
727 .llseek = generic_file_llseek,
728};
729
c3eea194
TT		 730static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
731 const struct edac_device_prv_data *priv)
732{
733 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
734
735 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
736 return;
737
738 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
739 if (!drvdata->debugfs_dir)
740 return;
741
f399f34b 742 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
c3eea194 743 drvdata->debugfs_dir, edac_dci,
e17ced2c 744 priv->inject_fops))
c3eea194
TT		 745 debugfs_remove_recursive(drvdata->debugfs_dir);
746}
747
748static const struct of_device_id altr_edac_device_of_match[] = {
749#ifdef CONFIG_EDAC_ALTERA_L2C
2c911f6c 750 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
c3eea194
TT		 751#endif
752#ifdef CONFIG_EDAC_ALTERA_OCRAM
2c911f6c 753 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
c3eea194
TT		 754#endif
755 {},
756};
757MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
758
759/*
760 * altr_edac_device_probe()
761 * This is a generic EDAC device driver that will support
762 * various Altera memory devices such as the L2 cache ECC and
763 * OCRAM ECC as well as the memories for other peripherals.
764 * Module specific initialization is done by passing the
765 * function index in the device tree.
766 */
767static int altr_edac_device_probe(struct platform_device *pdev)
768{
769 struct edac_device_ctl_info *dci;
770 struct altr_edac_device_dev *drvdata;
771 struct resource *r;
772 int res = 0;
773 struct device_node *np = pdev->dev.of_node;
774 char *ecc_name = (char *)np->name;
775 static int dev_instance;
776
777 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
778 edac_printk(KERN_ERR, EDAC_DEVICE,
779 "Unable to open devm\n");
780 return -ENOMEM;
781 }
782
783 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
784 if (!r) {
785 edac_printk(KERN_ERR, EDAC_DEVICE,
786 "Unable to get mem resource\n");
787 res = -ENODEV;
788 goto fail;
789 }
790
791 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
792 dev_name(&pdev->dev))) {
793 edac_printk(KERN_ERR, EDAC_DEVICE,
794 "%s:Error requesting mem region\n", ecc_name);
795 res = -EBUSY;
796 goto fail;
797 }
798
799 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
800 1, ecc_name, 1, 0, NULL, 0,
801 dev_instance++);
802
803 if (!dci) {
804 edac_printk(KERN_ERR, EDAC_DEVICE,
805 "%s: Unable to allocate EDAC device\n", ecc_name);
806 res = -ENOMEM;
807 goto fail;
808 }
809
810 drvdata = dci->pvt_info;
811 dci->dev = &pdev->dev;
812 platform_set_drvdata(pdev, dci);
813 drvdata->edac_dev_name = ecc_name;
814
815 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
8b073d94
CJ		 816 if (!drvdata->base) {
817 res = -ENOMEM;
c3eea194 818 goto fail1;
8b073d94 819 }
c3eea194
TT		 820
821 /* Get driver specific data for this EDAC device */
822 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
823
824 /* Check specific dependencies for the module */
825 if (drvdata->data->setup) {
328ca7ae 826 res = drvdata->data->setup(drvdata);
c3eea194
TT		 827 if (res)
828 goto fail1;
829 }
830
831 drvdata->sb_irq = platform_get_irq(pdev, 0);
832 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
833 altr_edac_device_handler,
834 0, dev_name(&pdev->dev), dci);
835 if (res)
836 goto fail1;
837
838 drvdata->db_irq = platform_get_irq(pdev, 1);
839 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
840 altr_edac_device_handler,
841 0, dev_name(&pdev->dev), dci);
842 if (res)
843 goto fail1;
844
845 dci->mod_name = "Altera ECC Manager";
846 dci->dev_name = drvdata->edac_dev_name;
847
848 res = edac_device_add_device(dci);
849 if (res)
850 goto fail1;
851
852 altr_create_edacdev_dbgfs(dci, drvdata->data);
853
854 devres_close_group(&pdev->dev, NULL);
855
856 return 0;
857
858fail1:
859 edac_device_free_ctl_info(dci);
860fail:
861 devres_release_group(&pdev->dev, NULL);
862 edac_printk(KERN_ERR, EDAC_DEVICE,
863 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
864
865 return res;
866}
867
868static int altr_edac_device_remove(struct platform_device *pdev)
869{
870 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
871 struct altr_edac_device_dev *drvdata = dci->pvt_info;
872
873 debugfs_remove_recursive(drvdata->debugfs_dir);
874 edac_device_del_device(&pdev->dev);
875 edac_device_free_ctl_info(dci);
876
877 return 0;
878}
879
880static struct platform_driver altr_edac_device_driver = {
881 .probe = altr_edac_device_probe,
882 .remove = altr_edac_device_remove,
883 .driver = {
884 .name = "altr_edac_device",
885 .of_match_table = altr_edac_device_of_match,
886 },
887};
888module_platform_driver(altr_edac_device_driver);
889
6b300fb9 890/******************* Arria10 Device ECC Shared Functions *****************/
c3eea194 891
1aa6eb5c
AB		 892/*
893 * Test for memory's ECC dependencies upon entry because platform specific
894 * startup should have initialized the memory and enabled the ECC.
895 * Can't turn on ECC here because accessing un-initialized memory will
896 * cause CE/UE errors possibly causing an ABORT.
897 */
6b300fb9
TT		 898static int __maybe_unused
899altr_check_ecc_deps(struct altr_edac_device_dev *device)
1aa6eb5c
AB		 900{
901 void __iomem *base = device->base;
902 const struct edac_device_prv_data *prv = device->data;
903
904 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
905 return 0;
906
907 edac_printk(KERN_ERR, EDAC_DEVICE,
908 "%s: No ECC present or ECC disabled.\n",
909 device->edac_dev_name);
910 return -ENODEV;
911}
c3eea194 912
6b300fb9
TT		 913static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
914{
915 struct altr_edac_device_dev *dci = dev_id;
916 void __iomem *base = dci->base;
917
918 if (irq == dci->sb_irq) {
919 writel(ALTR_A10_ECC_SERRPENA,
920 base + ALTR_A10_ECC_INTSTAT_OFST);
921 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
922
923 return IRQ_HANDLED;
924 } else if (irq == dci->db_irq) {
925 writel(ALTR_A10_ECC_DERRPENA,
926 base + ALTR_A10_ECC_INTSTAT_OFST);
927 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
928 if (dci->data->panic)
929 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
930
931 return IRQ_HANDLED;
932 }
933
934 WARN_ON(1);
935
936 return IRQ_NONE;
937}
938
1166fde9
TT		 939/******************* Arria10 Memory Buffer Functions *********************/
940
941static inline int a10_get_irq_mask(struct device_node *np)
942{
943 int irq;
944 const u32 *handle = of_get_property(np, "interrupts", NULL);
945
946 if (!handle)
947 return -ENODEV;
948 irq = be32_to_cpup(handle);
949 return irq;
950}
951
952static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
953{
954 u32 value = readl(ioaddr);
955
956 value |= bit_mask;
957 writel(value, ioaddr);
958}
959
960static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
961{
962 u32 value = readl(ioaddr);
963
964 value &= ~bit_mask;
965 writel(value, ioaddr);
966}
967
968static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
969{
970 u32 value = readl(ioaddr);
971
972 return (value & bit_mask) ? 1 : 0;
973}
974
975/*
976 * This function uses the memory initialization block in the Arria10 ECC
977 * controller to initialize/clear the entire memory data and ECC data.
978 */
979static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
980{
981 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
982 u32 init_mask, stat_mask, clear_mask;
983 int ret = 0;
984
985 if (port) {
986 init_mask = ALTR_A10_ECC_INITB;
987 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
988 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
989 } else {
990 init_mask = ALTR_A10_ECC_INITA;
991 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
992 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
993 }
994
995 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
996 while (limit--) {
997 if (ecc_test_bits(stat_mask,
998 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
999 break;
1000 udelay(1);
1001 }
1002 if (limit < 0)
1003 ret = -EBUSY;
1004
1005 /* Clear any pending ECC interrupts */
1006 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1007
1008 return ret;
1009}
1010
064acbd4
TT		 1011static int socfpga_is_a10(void)
1012{
1013 return of_machine_is_compatible("altr,socfpga-arria10");
1014}
1015
1016static int socfpga_is_s10(void)
1017{
1018 return of_machine_is_compatible("altr,socfpga-stratix10");
1019}
1020
1166fde9
TT		 1021static __init int __maybe_unused
1022altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1023 u32 ecc_ctrl_en_mask, bool dual_port)
1024{
1025 int ret = 0;
1026 void __iomem *ecc_block_base;
1027 struct regmap *ecc_mgr_map;
1028 char *ecc_name;
1029 struct device_node *np_eccmgr;
1030
1031 ecc_name = (char *)np->name;
1032
1033 /* Get the ECC Manager - parent of the device EDACs */
1034 np_eccmgr = of_get_parent(np);
064acbd4
TT		 1035
1036 if (socfpga_is_a10()) {
1037 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1038 "altr,sysmgr-syscon");
1039 } else {
1040 struct device_node *sysmgr_np;
1041 struct resource res;
8537bf10 1042 uintptr_t base;
064acbd4
TT		 1043
1044 sysmgr_np = of_parse_phandle(np_eccmgr,
1045 "altr,sysmgr-syscon", 0);
1046 if (!sysmgr_np) {
1047 edac_printk(KERN_ERR, EDAC_DEVICE,
1048 "Unable to find altr,sysmgr-syscon\n");
1049 return -ENODEV;
1050 }
1051
7f736599
HZ		 1052 if (of_address_to_resource(sysmgr_np, 0, &res)) {
1053 of_node_put(sysmgr_np);
064acbd4 1054 return -ENOMEM;
7f736599 1055 }
064acbd4
TT		 1056
1057 /* Need physical address for SMCC call */
8537bf10 1058 base = res.start;
064acbd4 1059
8537bf10 1060 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
064acbd4 1061 &s10_sdram_regmap_cfg);
7f736599 1062 of_node_put(sysmgr_np);
064acbd4 1063 }
1166fde9
TT		 1064 of_node_put(np_eccmgr);
1065 if (IS_ERR(ecc_mgr_map)) {
1066 edac_printk(KERN_ERR, EDAC_DEVICE,
1067 "Unable to get syscon altr,sysmgr-syscon\n");
1068 return -ENODEV;
1069 }
1070
1071 /* Map the ECC Block */
1072 ecc_block_base = of_iomap(np, 0);
1073 if (!ecc_block_base) {
1074 edac_printk(KERN_ERR, EDAC_DEVICE,
1075 "Unable to map %s ECC block\n", ecc_name);
1076 return -ENODEV;
1077 }
1078
1079 /* Disable ECC */
1080 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1081 writel(ALTR_A10_ECC_SERRINTEN,
1082 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1083 ecc_clear_bits(ecc_ctrl_en_mask,
1084 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1085 /* Ensure all writes complete */
1086 wmb();
1087 /* Use HW initialization block to initialize memory for ECC */
1088 ret = altr_init_memory_port(ecc_block_base, 0);
1089 if (ret) {
1090 edac_printk(KERN_ERR, EDAC_DEVICE,
1091 "ECC: cannot init %s PORTA memory\n", ecc_name);
1092 goto out;
1093 }
1094
1095 if (dual_port) {
1096 ret = altr_init_memory_port(ecc_block_base, 1);
1097 if (ret) {
1098 edac_printk(KERN_ERR, EDAC_DEVICE,
1099 "ECC: cannot init %s PORTB memory\n",
1100 ecc_name);
1101 goto out;
1102 }
1103 }
1104
1105 /* Interrupt mode set to every SBERR */
1106 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1107 ALTR_A10_ECC_INTMODE);
1108 /* Enable ECC */
1109 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1110 ALTR_A10_ECC_CTRL_OFST));
1111 writel(ALTR_A10_ECC_SERRINTEN,
1112 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1113 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1114 /* Ensure all writes complete */
1115 wmb();
1116out:
1117 iounmap(ecc_block_base);
1118 return ret;
1119}
1120
1121static int validate_parent_available(struct device_node *np);
1122static const struct of_device_id altr_edac_a10_device_of_match[];
1123static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1124{
1125 int irq;
25b223dd
TT		 1126 struct device_node *child, *np;
1127
064acbd4 1128 if (!socfpga_is_a10() && !socfpga_is_s10())
25b223dd
TT		 1129 return -ENODEV;
1130
1131 np = of_find_compatible_node(NULL, NULL,
1132 "altr,socfpga-a10-ecc-manager");
1166fde9
TT		 1133 if (!np) {
1134 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1135 return -ENODEV;
1136 }
1137
1138 for_each_child_of_node(np, child) {
1139 const struct of_device_id *pdev_id;
1140 const struct edac_device_prv_data *prv;
1141
1142 if (!of_device_is_available(child))
1143 continue;
1144 if (!of_device_is_compatible(child, compat))
1145 continue;
1146
1147 if (validate_parent_available(child))
1148 continue;
1149
1150 irq = a10_get_irq_mask(child);
1151 if (irq < 0)
1152 continue;
1153
1154 /* Get matching node and check for valid result */
1155 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1156 if (IS_ERR_OR_NULL(pdev_id))
1157 continue;
1158
1159 /* Validate private data pointer before dereferencing */
1160 prv = pdev_id->data;
1161 if (!prv)
1162 continue;
1163
1164 altr_init_a10_ecc_block(child, BIT(irq),
1165 prv->ecc_enable_mask, 0);
1166 }
1167
1168 of_node_put(np);
1169 return 0;
1170}
1171
6b300fb9
TT		 1172/*********************** OCRAM EDAC Device Functions *********************/
1173
1174#ifdef CONFIG_EDAC_ALTERA_OCRAM
1175
c3eea194
TT		 1176static void *ocram_alloc_mem(size_t size, void **other)
1177{
1178 struct device_node *np;
1179 struct gen_pool *gp;
1180 void *sram_addr;
1181
1182 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1183 if (!np)
1184 return NULL;
1185
1186 gp = of_gen_pool_get(np, "iram", 0);
1187 of_node_put(np);
1188 if (!gp)
1189 return NULL;
1190
1191 sram_addr = (void *)gen_pool_alloc(gp, size);
1192 if (!sram_addr)
1193 return NULL;
1194
1195 memset(sram_addr, 0, size);
1196 /* Ensure data is written out */
1197 wmb();
1198
1199 /* Remember this handle for freeing later */
1200 *other = gp;
1201
1202 return sram_addr;
1203}
1204
1205static void ocram_free_mem(void *p, size_t size, void *other)
1206{
9ef20753 1207 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
c3eea194
TT		 1208}
1209
1cf70377 1210static const struct edac_device_prv_data ocramecc_data = {
aa1f06dc 1211 .setup = altr_check_ecc_deps,
c3eea194
TT		 1212 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1213 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
c3eea194
TT		 1214 .alloc_mem = ocram_alloc_mem,
1215 .free_mem = ocram_free_mem,
1216 .ecc_enable_mask = ALTR_OCR_ECC_EN,
943ad917 1217 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
c3eea194
TT		 1218 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1219 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
811fce4f 1220 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
c3eea194 1221 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
e17ced2c 1222 .inject_fops = &altr_edac_device_inject_fops,
c3eea194
TT		 1223};
1224
1cf70377 1225static const struct edac_device_prv_data a10_ocramecc_data = {
c7b4be8d
TT		 1226 .setup = altr_check_ecc_deps,
1227 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1228 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1229 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
c7b4be8d
TT		 1230 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1231 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1232 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1233 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1234 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1235 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1236 .inject_fops = &altr_edac_a10_device_inject_fops,
2b083d65
TT		 1237 /*
1238 * OCRAM panic on uncorrectable error because sleep/resume
1239 * functions and FPGA contents are stored in OCRAM. Prefer
1240 * a kernel panic over executing/loading corrupted data.
1241 */
1242 .panic = true,
c7b4be8d
TT		 1243};
1244
c3eea194
TT		 1245#endif /* CONFIG_EDAC_ALTERA_OCRAM */
1246
1247/********************* L2 Cache EDAC Device Functions ********************/
1248
1249#ifdef CONFIG_EDAC_ALTERA_L2C
1250
1251static void *l2_alloc_mem(size_t size, void **other)
1252{
1253 struct device *dev = *other;
1254 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1255
1256 if (!ptemp)
1257 return NULL;
1258
1259 /* Make sure everything is written out */
1260 wmb();
1261
1262 /*
1263 * Clean all cache levels up to LoC (includes L2)
1264 * This ensures the corrupted data is written into
1265 * L2 cache for readback test (which causes ECC error).
1266 */
1267 flush_cache_all();
1268
1269 return ptemp;
1270}
1271
1272static void l2_free_mem(void *p, size_t size, void *other)
1273{
1274 struct device *dev = other;
1275
1276 if (dev && p)
1277 devm_kfree(dev, p);
1278}
1279
1280/*
1281 * altr_l2_check_deps()
1282 * Test for L2 cache ECC dependencies upon entry because
1283 * platform specific startup should have initialized the L2
1284 * memory and enabled the ECC.
1285 * Bail if ECC is not enabled.
1286 * Note that L2 Cache Enable is forced at build time.
1287 */
328ca7ae 1288static int altr_l2_check_deps(struct altr_edac_device_dev *device)
c3eea194 1289{
328ca7ae 1290 void __iomem *base = device->base;
27439a1a
TT		 1291 const struct edac_device_prv_data *prv = device->data;
1292
1293 if ((readl(base) & prv->ecc_enable_mask) ==
1294 prv->ecc_enable_mask)
c3eea194
TT		 1295 return 0;
1296
1297 edac_printk(KERN_ERR, EDAC_DEVICE,
1298 "L2: No ECC present, or ECC disabled\n");
1299 return -ENODEV;
1300}
1301
13ab8448 1302static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
588cb03e 1303{
13ab8448
TT		 1304 struct altr_edac_device_dev *dci = dev_id;
1305
1306 if (irq == dci->sb_irq) {
588cb03e
TT		 1307 regmap_write(dci->edac->ecc_mgr_map,
1308 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1309 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1310 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
13ab8448
TT		 1311
1312 return IRQ_HANDLED;
1313 } else if (irq == dci->db_irq) {
588cb03e
TT		 1314 regmap_write(dci->edac->ecc_mgr_map,
1315 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1316 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1317 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1318 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
13ab8448
TT		 1319
1320 return IRQ_HANDLED;
588cb03e 1321 }
13ab8448
TT		 1322
1323 WARN_ON(1);
1324
1325 return IRQ_NONE;
588cb03e
TT		 1326}
1327
1cf70377 1328static const struct edac_device_prv_data l2ecc_data = {
c3eea194
TT		 1329 .setup = altr_l2_check_deps,
1330 .ce_clear_mask = 0,
1331 .ue_clear_mask = 0,
c3eea194
TT		 1332 .alloc_mem = l2_alloc_mem,
1333 .free_mem = l2_free_mem,
1334 .ecc_enable_mask = ALTR_L2_ECC_EN,
1335 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1336 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
811fce4f 1337 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
c3eea194 1338 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
e17ced2c 1339 .inject_fops = &altr_edac_device_inject_fops,
c3eea194
TT		 1340};
1341
1cf70377 1342static const struct edac_device_prv_data a10_l2ecc_data = {
588cb03e
TT		 1343 .setup = altr_l2_check_deps,
1344 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1345 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1346 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
588cb03e
TT		 1347 .alloc_mem = l2_alloc_mem,
1348 .free_mem = l2_free_mem,
1349 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1350 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1351 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1352 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1353 .ecc_irq_handler = altr_edac_a10_l2_irq,
1354 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
e17ced2c 1355 .inject_fops = &altr_edac_device_inject_fops,
588cb03e
TT		 1356};
1357
c3eea194
TT		 1358#endif /* CONFIG_EDAC_ALTERA_L2C */
1359
ab8c1e0f
TT		 1360/********************* Ethernet Device Functions ********************/
1361
1362#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1363
788586ef
TT		 1364static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1365{
1366 int ret;
1367
1368 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1369 if (ret)
1370 return ret;
1371
1372 return altr_check_ecc_deps(dev);
1373}
1374
ab8c1e0f 1375static const struct edac_device_prv_data a10_enetecc_data = {
788586ef 1376 .setup = socfpga_init_ethernet_ecc,
ab8c1e0f
TT		 1377 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1378 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
ab8c1e0f
TT		 1379 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1380 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1381 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1382 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1383 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1384 .ecc_irq_handler = altr_edac_a10_ecc_irq,
064acbd4 1385 .inject_fops = &altr_edac_a10_device_inject2_fops,
ab8c1e0f
TT		 1386};
1387
ab8c1e0f
TT		 1388#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1389
c6882fb2
TT		 1390/********************** NAND Device Functions **********************/
1391
1392#ifdef CONFIG_EDAC_ALTERA_NAND
1393
788586ef
TT		 1394static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1395{
1396 int ret;
1397
1398 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1399 if (ret)
1400 return ret;
1401
1402 return altr_check_ecc_deps(device);
1403}
1404
c6882fb2 1405static const struct edac_device_prv_data a10_nandecc_data = {
788586ef 1406 .setup = socfpga_init_nand_ecc,
c6882fb2
TT		 1407 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1408 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
c6882fb2
TT		 1409 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1410 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1411 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1412 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1413 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1414 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1415 .inject_fops = &altr_edac_a10_device_inject_fops,
1416};
1417
c6882fb2
TT		 1418#endif /* CONFIG_EDAC_ALTERA_NAND */
1419
e8263793
TT		 1420/********************** DMA Device Functions **********************/
1421
1422#ifdef CONFIG_EDAC_ALTERA_DMA
1423
788586ef
TT		 1424static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1425{
1426 int ret;
1427
1428 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1429 if (ret)
1430 return ret;
1431
1432 return altr_check_ecc_deps(device);
1433}
1434
e8263793 1435static const struct edac_device_prv_data a10_dmaecc_data = {
788586ef 1436 .setup = socfpga_init_dma_ecc,
e8263793
TT		 1437 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1438 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
e8263793
TT		 1439 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1440 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1441 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1442 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1443 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1444 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1445 .inject_fops = &altr_edac_a10_device_inject_fops,
1446};
1447
e8263793
TT		 1448#endif /* CONFIG_EDAC_ALTERA_DMA */
1449
c609581d
TT		 1450/********************** USB Device Functions **********************/
1451
1452#ifdef CONFIG_EDAC_ALTERA_USB
1453
788586ef
TT		 1454static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1455{
1456 int ret;
1457
1458 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1459 if (ret)
1460 return ret;
1461
1462 return altr_check_ecc_deps(device);
1463}
1464
c609581d 1465static const struct edac_device_prv_data a10_usbecc_data = {
788586ef 1466 .setup = socfpga_init_usb_ecc,
c609581d
TT		 1467 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1468 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
c609581d
TT		 1469 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1470 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1471 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1472 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1473 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1474 .ecc_irq_handler = altr_edac_a10_ecc_irq,
064acbd4 1475 .inject_fops = &altr_edac_a10_device_inject2_fops,
c609581d
TT		 1476};
1477
c609581d
TT		 1478#endif /* CONFIG_EDAC_ALTERA_USB */
1479
485fe9e2
TT		 1480/********************** QSPI Device Functions **********************/
1481
1482#ifdef CONFIG_EDAC_ALTERA_QSPI
1483
788586ef
TT		 1484static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1485{
1486 int ret;
1487
1488 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1489 if (ret)
1490 return ret;
1491
1492 return altr_check_ecc_deps(device);
1493}
1494
485fe9e2 1495static const struct edac_device_prv_data a10_qspiecc_data = {
788586ef 1496 .setup = socfpga_init_qspi_ecc,
485fe9e2
TT		 1497 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1498 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
485fe9e2
TT		 1499 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1500 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1501 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1502 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1503 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1504 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1505 .inject_fops = &altr_edac_a10_device_inject_fops,
1506};
1507
485fe9e2
TT		 1508#endif /* CONFIG_EDAC_ALTERA_QSPI */
1509
91104984
TT		 1510/********************* SDMMC Device Functions **********************/
1511
1512#ifdef CONFIG_EDAC_ALTERA_SDMMC
1513
1514static const struct edac_device_prv_data a10_sdmmceccb_data;
1515static int altr_portb_setup(struct altr_edac_device_dev *device)
1516{
1517 struct edac_device_ctl_info *dci;
1518 struct altr_edac_device_dev *altdev;
1519 char *ecc_name = "sdmmcb-ecc";
1520 int edac_idx, rc;
1521 struct device_node *np;
1522 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1523
1524 rc = altr_check_ecc_deps(device);
1525 if (rc)
1526 return rc;
1527
1528 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1529 if (!np) {
1530 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1531 return -ENODEV;
1532 }
1533
1534 /* Create the PortB EDAC device */
1535 edac_idx = edac_device_alloc_index();
1536 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1537 ecc_name, 1, 0, NULL, 0, edac_idx);
1538 if (!dci) {
1539 edac_printk(KERN_ERR, EDAC_DEVICE,
1540 "%s: Unable to allocate PortB EDAC device\n",
1541 ecc_name);
1542 return -ENOMEM;
1543 }
1544
1545 /* Initialize the PortB EDAC device structure from PortA structure */
1546 altdev = dci->pvt_info;
1547 *altdev = *device;
1548
1549 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1550 return -ENOMEM;
1551
1552 /* Update PortB specific values */
1553 altdev->edac_dev_name = ecc_name;
1554 altdev->edac_idx = edac_idx;
1555 altdev->edac_dev = dci;
1556 altdev->data = prv;
1557 dci->dev = &altdev->ddev;
1558 dci->ctl_name = "Altera ECC Manager";
1559 dci->mod_name = ecc_name;
1560 dci->dev_name = ecc_name;
1561
1562 /* Update the IRQs for PortB */
1563 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1564 if (!altdev->sb_irq) {
1565 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1566 rc = -ENODEV;
1567 goto err_release_group_1;
1568 }
1569 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1570 prv->ecc_irq_handler,
a29d64a4
TT		 1571 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1572 ecc_name, altdev);
91104984
TT		 1573 if (rc) {
1574 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1575 goto err_release_group_1;
1576 }
1577
1578 altdev->db_irq = irq_of_parse_and_map(np, 3);
1579 if (!altdev->db_irq) {
1580 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1581 rc = -ENODEV;
1582 goto err_release_group_1;
1583 }
1584 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1585 prv->ecc_irq_handler,
a29d64a4
TT		 1586 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1587 ecc_name, altdev);
91104984
TT		 1588 if (rc) {
1589 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1590 goto err_release_group_1;
1591 }
1592
1593 rc = edac_device_add_device(dci);
1594 if (rc) {
1595 edac_printk(KERN_ERR, EDAC_DEVICE,
1596 "edac_device_add_device portB failed\n");
1597 rc = -ENOMEM;
1598 goto err_release_group_1;
1599 }
1600 altr_create_edacdev_dbgfs(dci, prv);
1601
1602 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1603
1604 devres_remove_group(&altdev->ddev, altr_portb_setup);
1605
1606 return 0;
1607
1608err_release_group_1:
1609 edac_device_free_ctl_info(dci);
1610 devres_release_group(&altdev->ddev, altr_portb_setup);
1611 edac_printk(KERN_ERR, EDAC_DEVICE,
1612 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1613 return rc;
1614}
1615
788586ef
TT		 1616static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1617{
1618 int rc = -ENODEV;
1619 struct device_node *child;
1620
1621 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1622 if (!child)
1623 return -ENODEV;
1624
1625 if (!of_device_is_available(child))
1626 goto exit;
1627
1628 if (validate_parent_available(child))
1629 goto exit;
1630
1631 /* Init portB */
1632 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1633 a10_sdmmceccb_data.ecc_enable_mask, 1);
1634 if (rc)
1635 goto exit;
1636
1637 /* Setup portB */
1638 return altr_portb_setup(device);
1639
1640exit:
1641 of_node_put(child);
1642 return rc;
1643}
1644
91104984
TT		 1645static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1646{
1647 struct altr_edac_device_dev *ad = dev_id;
1648 void __iomem *base = ad->base;
1649 const struct edac_device_prv_data *priv = ad->data;
1650
1651 if (irq == ad->sb_irq) {
1652 writel(priv->ce_clear_mask,
1653 base + ALTR_A10_ECC_INTSTAT_OFST);
1654 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1655 return IRQ_HANDLED;
1656 } else if (irq == ad->db_irq) {
1657 writel(priv->ue_clear_mask,
1658 base + ALTR_A10_ECC_INTSTAT_OFST);
1659 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1660 return IRQ_HANDLED;
1661 }
1662
1663 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1664
1665 return IRQ_NONE;
1666}
1667
1668static const struct edac_device_prv_data a10_sdmmcecca_data = {
788586ef 1669 .setup = socfpga_init_sdmmc_ecc,
91104984
TT		 1670 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1671 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
91104984
TT		 1672 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1673 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1674 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1675 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1676 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1677 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1678 .inject_fops = &altr_edac_a10_device_inject_fops,
1679};
1680
1681static const struct edac_device_prv_data a10_sdmmceccb_data = {
788586ef 1682 .setup = socfpga_init_sdmmc_ecc,
91104984
TT		 1683 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1684 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
91104984
TT		 1685 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1686 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1687 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1688 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1689 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1690 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1691 .inject_fops = &altr_edac_a10_device_inject_fops,
1692};
1693
91104984
TT		 1694#endif /* CONFIG_EDAC_ALTERA_SDMMC */
1695
588cb03e 1696/********************* Arria10 EDAC Device Functions *************************/
ab564cb5
TT		 1697static const struct of_device_id altr_edac_a10_device_of_match[] = {
1698#ifdef CONFIG_EDAC_ALTERA_L2C
1699 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1700#endif
1701#ifdef CONFIG_EDAC_ALTERA_OCRAM
1702 { .compatible = "altr,socfpga-a10-ocram-ecc",
1703 .data = &a10_ocramecc_data },
ab8c1e0f
TT		 1704#endif
1705#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1706 { .compatible = "altr,socfpga-eth-mac-ecc",
1707 .data = &a10_enetecc_data },
c6882fb2
TT		 1708#endif
1709#ifdef CONFIG_EDAC_ALTERA_NAND
1710 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
e8263793
TT		 1711#endif
1712#ifdef CONFIG_EDAC_ALTERA_DMA
1713 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
c609581d
TT		 1714#endif
1715#ifdef CONFIG_EDAC_ALTERA_USB
1716 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
485fe9e2
TT		 1717#endif
1718#ifdef CONFIG_EDAC_ALTERA_QSPI
1719 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
91104984
TT		 1720#endif
1721#ifdef CONFIG_EDAC_ALTERA_SDMMC
1722 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
ab564cb5
TT		 1723#endif
1724 {},
1725};
1726MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
588cb03e
TT		 1727
1728/*
1729 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1730 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1731 * manager manages the IRQs and the children.
1732 * Based on xgene_edac.c peripheral code.
1733 */
1734
c7b4be8d
TT		 1735static ssize_t altr_edac_a10_device_trig(struct file *file,
1736 const char __user *user_buf,
1737 size_t count, loff_t *ppos)
1738{
1739 struct edac_device_ctl_info *edac_dci = file->private_data;
1740 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1741 const struct edac_device_prv_data *priv = drvdata->data;
1742 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1743 unsigned long flags;
1744 u8 trig_type;
1745
1746 if (!user_buf || get_user(trig_type, user_buf))
1747 return -EFAULT;
1748
1749 local_irq_save(flags);
1750 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1751 writel(priv->ue_set_mask, set_addr);
1752 else
1753 writel(priv->ce_set_mask, set_addr);
064acbd4
TT		 1754
1755 /* Ensure the interrupt test bits are set */
1756 wmb();
1757 local_irq_restore(flags);
1758
1759 return count;
1760}
1761
1762/*
1763 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1764 * slightly. A few Arria10 peripherals can use this injection function.
1765 * Inject the error into the memory and then readback to trigger the IRQ.
1766 */
1767static ssize_t altr_edac_a10_device_trig2(struct file *file,
1768 const char __user *user_buf,
1769 size_t count, loff_t *ppos)
1770{
1771 struct edac_device_ctl_info *edac_dci = file->private_data;
1772 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1773 const struct edac_device_prv_data *priv = drvdata->data;
1774 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1775 unsigned long flags;
1776 u8 trig_type;
1777
1778 if (!user_buf || get_user(trig_type, user_buf))
1779 return -EFAULT;
1780
1781 local_irq_save(flags);
1782 if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1783 writel(priv->ue_set_mask, set_addr);
1784 } else {
436b0a58 1785 /* Setup read/write of 4 bytes */
064acbd4
TT		 1786 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1787 /* Setup Address to 0 */
436b0a58
TT		 1788 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1789 /* Setup accctrl to read & ecc & data override */
1790 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
064acbd4
TT		 1791 /* Kick it. */
1792 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1793 /* Setup write for single bit change */
436b0a58
TT		 1794 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1795 drvdata->base + ECC_BLK_WDATA0_OFST);
1796 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1797 drvdata->base + ECC_BLK_WDATA1_OFST);
1798 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1799 drvdata->base + ECC_BLK_WDATA2_OFST);
1800 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1801 drvdata->base + ECC_BLK_WDATA3_OFST);
1802
064acbd4
TT		 1803 /* Copy Read ECC to Write ECC */
1804 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1805 drvdata->base + ECC_BLK_WECC0_OFST);
1806 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1807 drvdata->base + ECC_BLK_WECC1_OFST);
1808 /* Setup accctrl to write & ecc override & data override */
1809 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1810 /* Kick it. */
1811 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1812 /* Setup accctrl to read & ecc overwrite & data overwrite */
1813 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1814 /* Kick it. */
1815 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1816 }
1817
c7b4be8d
TT		 1818 /* Ensure the interrupt test bits are set */
1819 wmb();
1820 local_irq_restore(flags);
1821
1822 return count;
1823}
1824
13ab8448 1825static void altr_edac_a10_irq_handler(struct irq_desc *desc)
588cb03e 1826{
13ab8448
TT		 1827 int dberr, bit, sm_offset, irq_status;
1828 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1829 struct irq_chip *chip = irq_desc_get_chip(desc);
1830 int irq = irq_desc_get_irq(desc);
1831
1832 dberr = (irq == edac->db_irq) ? 1 : 0;
1833 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1834 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1835
1836 chained_irq_enter(chip, desc);
588cb03e
TT		 1837
1838 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1839
13ab8448
TT		 1840 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1841 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1842 if (irq)
1843 generic_handle_irq(irq);
588cb03e
TT		 1844 }
1845
13ab8448 1846 chained_irq_exit(chip, desc);
588cb03e
TT		 1847}
1848
44ec9b30
TT		 1849static int validate_parent_available(struct device_node *np)
1850{
1851 struct device_node *parent;
1852 int ret = 0;
1853
1854 /* Ensure parent device is enabled if parent node exists */
1855 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1856 if (parent && !of_device_is_available(parent))
1857 ret = -ENODEV;
1858
1859 of_node_put(parent);
1860 return ret;
1861}
1862
588cb03e
TT		 1863static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1864 struct device_node *np)
1865{
1866 struct edac_device_ctl_info *dci;
1867 struct altr_edac_device_dev *altdev;
1868 char *ecc_name = (char *)np->name;
1869 struct resource res;
1870 int edac_idx;
1871 int rc = 0;
1872 const struct edac_device_prv_data *prv;
1873 /* Get matching node and check for valid result */
1874 const struct of_device_id *pdev_id =
ab564cb5 1875 of_match_node(altr_edac_a10_device_of_match, np);
588cb03e
TT		 1876 if (IS_ERR_OR_NULL(pdev_id))
1877 return -ENODEV;
1878
1879 /* Get driver specific data for this EDAC device */
1880 prv = pdev_id->data;
1881 if (IS_ERR_OR_NULL(prv))
1882 return -ENODEV;
1883
44ec9b30
TT		 1884 if (validate_parent_available(np))
1885 return -ENODEV;
1886
588cb03e
TT		 1887 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1888 return -ENOMEM;
1889
1890 rc = of_address_to_resource(np, 0, &res);
1891 if (rc < 0) {
1892 edac_printk(KERN_ERR, EDAC_DEVICE,
1893 "%s: no resource address\n", ecc_name);
1894 goto err_release_group;
1895 }
1896
1897 edac_idx = edac_device_alloc_index();
1898 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1899 1, ecc_name, 1, 0, NULL, 0,
1900 edac_idx);
1901
1902 if (!dci) {
1903 edac_printk(KERN_ERR, EDAC_DEVICE,
1904 "%s: Unable to allocate EDAC device\n", ecc_name);
1905 rc = -ENOMEM;
1906 goto err_release_group;
1907 }
1908
1909 altdev = dci->pvt_info;
1910 dci->dev = edac->dev;
1911 altdev->edac_dev_name = ecc_name;
1912 altdev->edac_idx = edac_idx;
1913 altdev->edac = edac;
1914 altdev->edac_dev = dci;
1915 altdev->data = prv;
1916 altdev->ddev = *edac->dev;
1917 dci->dev = &altdev->ddev;
1918 dci->ctl_name = "Altera ECC Manager";
1919 dci->mod_name = ecc_name;
1920 dci->dev_name = ecc_name;
1921
1922 altdev->base = devm_ioremap_resource(edac->dev, &res);
1923 if (IS_ERR(altdev->base)) {
1924 rc = PTR_ERR(altdev->base);
1925 goto err_release_group1;
1926 }
1927
1928 /* Check specific dependencies for the module */
1929 if (altdev->data->setup) {
1930 rc = altdev->data->setup(altdev);
1931 if (rc)
1932 goto err_release_group1;
1933 }
1934
13ab8448
TT		 1935 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1936 if (!altdev->sb_irq) {
1937 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1938 rc = -ENODEV;
1939 goto err_release_group1;
1940 }
a29d64a4
TT		 1941 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1942 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1943 ecc_name, altdev);
13ab8448 1944 if (rc) {
3763569f 1945 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
13ab8448
TT		 1946 goto err_release_group1;
1947 }
1948
1bd76ff4
TT		 1949#ifdef CONFIG_ARCH_STRATIX10
1950 /* Use IRQ to determine SError origin instead of assigning IRQ */
1951 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1952 if (rc) {
1953 edac_printk(KERN_ERR, EDAC_DEVICE,
1954 "Unable to parse DB IRQ index\n");
1955 goto err_release_group1;
1956 }
1957#else
13ab8448
TT		 1958 altdev->db_irq = irq_of_parse_and_map(np, 1);
1959 if (!altdev->db_irq) {
1960 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1961 rc = -ENODEV;
1962 goto err_release_group1;
1963 }
a29d64a4
TT		 1964 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1965 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1966 ecc_name, altdev);
13ab8448
TT		 1967 if (rc) {
1968 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1969 goto err_release_group1;
1970 }
1bd76ff4 1971#endif
13ab8448 1972
588cb03e
TT		 1973 rc = edac_device_add_device(dci);
1974 if (rc) {
1975 dev_err(edac->dev, "edac_device_add_device failed\n");
1976 rc = -ENOMEM;
1977 goto err_release_group1;
1978 }
1979
1980 altr_create_edacdev_dbgfs(dci, prv);
1981
1982 list_add(&altdev->next, &edac->a10_ecc_devices);
1983
1984 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1985
1986 return 0;
1987
1988err_release_group1:
1989 edac_device_free_ctl_info(dci);
1990err_release_group:
588cb03e
TT		 1991 devres_release_group(edac->dev, NULL);
1992 edac_printk(KERN_ERR, EDAC_DEVICE,
1993 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1994
1995 return rc;
1996}
1997
13ab8448
TT		 1998static void a10_eccmgr_irq_mask(struct irq_data *d)
1999{
2000 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2001
2002 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2003 BIT(d->hwirq));
2004}
2005
2006static void a10_eccmgr_irq_unmask(struct irq_data *d)
2007{
2008 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2009
2010 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2011 BIT(d->hwirq));
2012}
2013
2014static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2015 irq_hw_number_t hwirq)
2016{
2017 struct altr_arria10_edac *edac = d->host_data;
2018
2019 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2020 irq_set_chip_data(irq, edac);
2021 irq_set_noprobe(irq);
2022
2023 return 0;
2024}
2025
18caec20 2026static const struct irq_domain_ops a10_eccmgr_ic_ops = {
13ab8448
TT		 2027 .map = a10_eccmgr_irqdomain_map,
2028 .xlate = irq_domain_xlate_twocell,
2029};
2030
d5fc9125
TT		 2031/************** Stratix 10 EDAC Double Bit Error Handler ************/
2032#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2033
1bd76ff4
TT		 2034#ifdef CONFIG_ARCH_STRATIX10
2035/* panic routine issues reboot on non-zero panic_timeout */
2036extern int panic_timeout;
2037
d5fc9125
TT		 2038/*
2039 * The double bit error is handled through SError which is fatal. This is
2040 * called as a panic notifier to printout ECC error info as part of the panic.
2041 */
2042static int s10_edac_dberr_handler(struct notifier_block *this,
2043 unsigned long event, void *ptr)
2044{
2045 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2046 int err_addr, dberror;
2047
2048 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2049 &dberror);
2050 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
1bd76ff4
TT		 2051 if (dberror & S10_DBE_IRQ_MASK) {
2052 struct list_head *position;
2053 struct altr_edac_device_dev *ed;
2054 struct arm_smccc_res result;
2055
2056 /* Find the matching DBE in the list of devices */
2057 list_for_each(position, &edac->a10_ecc_devices) {
2058 ed = list_entry(position, struct altr_edac_device_dev,
2059 next);
2060 if (!(BIT(ed->db_irq) & dberror))
2061 continue;
2062
2063 writel(ALTR_A10_ECC_DERRPENA,
2064 ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2065 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2066 regmap_write(edac->ecc_mgr_map,
2067 S10_SYSMGR_UE_ADDR_OFST, err_addr);
2068 edac_printk(KERN_ERR, EDAC_DEVICE,
2069 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2070 ed->edac_dev_name, err_addr);
2071 break;
2072 }
2073 /* Notify the System through SMC. Reboot delay = 1 second */
2074 panic_timeout = 1;
2075 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2076 0, 0, &result);
d5fc9125
TT		 2077 }
2078
2079 return NOTIFY_DONE;
2080}
1bd76ff4 2081#endif
d5fc9125
TT		 2082
2083/****************** Arria 10 EDAC Probe Function *********************/
588cb03e
TT		 2084static int altr_edac_a10_probe(struct platform_device *pdev)
2085{
2086 struct altr_arria10_edac *edac;
2087 struct device_node *child;
588cb03e
TT		 2088
2089 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2090 if (!edac)
2091 return -ENOMEM;
2092
2093 edac->dev = &pdev->dev;
2094 platform_set_drvdata(pdev, edac);
2095 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2096
d5fc9125
TT		 2097 if (socfpga_is_a10()) {
2098 edac->ecc_mgr_map =
2099 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
588cb03e 2100 "altr,sysmgr-syscon");
d5fc9125
TT		 2101 } else {
2102 struct device_node *sysmgr_np;
2103 struct resource res;
8537bf10 2104 uintptr_t base;
d5fc9125
TT		 2105
2106 sysmgr_np = of_parse_phandle(pdev->dev.of_node,
2107 "altr,sysmgr-syscon", 0);
2108 if (!sysmgr_np) {
2109 edac_printk(KERN_ERR, EDAC_DEVICE,
2110 "Unable to find altr,sysmgr-syscon\n");
2111 return -ENODEV;
2112 }
2113
2114 if (of_address_to_resource(sysmgr_np, 0, &res))
2115 return -ENOMEM;
2116
2117 /* Need physical address for SMCC call */
8537bf10 2118 base = res.start;
d5fc9125 2119
8537bf10
AB		 2120 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
2121 (void *)base,
d5fc9125
TT		 2122 &s10_sdram_regmap_cfg);
2123 }
2124
588cb03e
TT		 2125 if (IS_ERR(edac->ecc_mgr_map)) {
2126 edac_printk(KERN_ERR, EDAC_DEVICE,
2127 "Unable to get syscon altr,sysmgr-syscon\n");
2128 return PTR_ERR(edac->ecc_mgr_map);
2129 }
2130
13ab8448
TT		 2131 edac->irq_chip.name = pdev->dev.of_node->name;
2132 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2133 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2134 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2135 &a10_eccmgr_ic_ops, edac);
2136 if (!edac->domain) {
2137 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2138 return -ENOMEM;
2139 }
2140
588cb03e 2141 edac->sb_irq = platform_get_irq(pdev, 0);
13ab8448
TT		 2142 if (edac->sb_irq < 0) {
2143 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2144 return edac->sb_irq;
588cb03e
TT		 2145 }
2146
13ab8448
TT		 2147 irq_set_chained_handler_and_data(edac->sb_irq,
2148 altr_edac_a10_irq_handler,
2149 edac);
2150
1bd76ff4
TT		 2151#ifdef CONFIG_ARCH_STRATIX10
2152 {
d5fc9125
TT		 2153 int dberror, err_addr;
2154
2155 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2156 atomic_notifier_chain_register(&panic_notifier_list,
2157 &edac->panic_notifier);
2158
2159 /* Printout a message if uncorrectable error previously. */
2160 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2161 &dberror);
2162 if (dberror) {
2163 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2164 &err_addr);
2165 edac_printk(KERN_ERR, EDAC_DEVICE,
2166 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2167 dberror, err_addr);
2168 /* Reset the sticky registers */
2169 regmap_write(edac->ecc_mgr_map,
2170 S10_SYSMGR_UE_VAL_OFST, 0);
2171 regmap_write(edac->ecc_mgr_map,
2172 S10_SYSMGR_UE_ADDR_OFST, 0);
2173 }
588cb03e 2174 }
1bd76ff4
TT		 2175#else
2176 edac->db_irq = platform_get_irq(pdev, 1);
2177 if (edac->db_irq < 0) {
2178 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2179 return edac->db_irq;
2180 }
2181 irq_set_chained_handler_and_data(edac->db_irq,
2182 altr_edac_a10_irq_handler, edac);
2183#endif
588cb03e
TT		 2184
2185 for_each_child_of_node(pdev->dev.of_node, child) {
2186 if (!of_device_is_available(child))
2187 continue;
c6882fb2
TT		 2188
2189 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2190 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2191 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
e8263793 2192 of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
c609581d 2193 of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
485fe9e2 2194 of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
91104984
TT		 2195 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2196 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
c6882fb2 2197
c7b4be8d 2198 altr_edac_a10_device_add(edac, child);
c6882fb2 2199
580b5cf5 2200#ifdef CONFIG_EDAC_ALTERA_SDRAM
d5fc9125
TT		 2201 else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) ||
2202 (of_device_is_compatible(child, "altr,sdram-edac-s10")))
ab564cb5
TT		 2203 of_platform_populate(pdev->dev.of_node,
2204 altr_sdram_ctrl_of_match,
2205 NULL, &pdev->dev);
580b5cf5 2206#endif
588cb03e
TT		 2207 }
2208
2209 return 0;
2210}
2211
2212static const struct of_device_id altr_edac_a10_of_match[] = {
2213 { .compatible = "altr,socfpga-a10-ecc-manager" },
d5fc9125 2214 { .compatible = "altr,socfpga-s10-ecc-manager" },
588cb03e
TT		 2215 {},
2216};
2217MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2218
2219static struct platform_driver altr_edac_a10_driver = {
2220 .probe = altr_edac_a10_probe,
2221 .driver = {
2222 .name = "socfpga_a10_ecc_manager",
2223 .of_match_table = altr_edac_a10_of_match,
2224 },
2225};
2226module_platform_driver(altr_edac_a10_driver);
2227
71bcada8
TT		 2228MODULE_LICENSE("GPL v2");
2229MODULE_AUTHOR("Thor Thayer");
c3eea194 2230MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
Linux 6.x block layer and io_uring tree(s)