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3dab6bd5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
71bcada8 | 2 | /* |
3dab6bd5 | 3 | * Copyright (C) 2017-2018, Intel Corporation. All rights reserved |
c3eea194 | 4 | * Copyright Altera Corporation (C) 2014-2016. All rights reserved. |
71bcada8 | 5 | * Copyright 2011-2012 Calxeda, Inc. |
71bcada8 TT |
6 | */ |
7 | ||
c3eea194 | 8 | #include <asm/cacheflush.h> |
71bcada8 | 9 | #include <linux/ctype.h> |
1166fde9 | 10 | #include <linux/delay.h> |
71bcada8 | 11 | #include <linux/edac.h> |
c3eea194 | 12 | #include <linux/genalloc.h> |
71bcada8 | 13 | #include <linux/interrupt.h> |
13ab8448 | 14 | #include <linux/irqchip/chained_irq.h> |
71bcada8 TT |
15 | #include <linux/kernel.h> |
16 | #include <linux/mfd/syscon.h> | |
e9918d7f | 17 | #include <linux/notifier.h> |
588cb03e | 18 | #include <linux/of_address.h> |
13ab8448 | 19 | #include <linux/of_irq.h> |
71bcada8 TT |
20 | #include <linux/of_platform.h> |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/uaccess.h> | |
25 | ||
143f4a5a | 26 | #include "altera_edac.h" |
71bcada8 TT |
27 | #include "edac_module.h" |
28 | ||
29 | #define EDAC_MOD_STR "altera_edac" | |
c3eea194 | 30 | #define EDAC_DEVICE "Altera" |
71bcada8 | 31 | |
143f4a5a TT |
32 | static const struct altr_sdram_prv_data c5_data = { |
33 | .ecc_ctrl_offset = CV_CTLCFG_OFST, | |
34 | .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, | |
35 | .ecc_stat_offset = CV_DRAMSTS_OFST, | |
36 | .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, | |
37 | .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, | |
38 | .ecc_saddr_offset = CV_ERRADDR_OFST, | |
73bcc942 | 39 | .ecc_daddr_offset = CV_ERRADDR_OFST, |
143f4a5a TT |
40 | .ecc_cecnt_offset = CV_SBECOUNT_OFST, |
41 | .ecc_uecnt_offset = CV_DBECOUNT_OFST, | |
42 | .ecc_irq_en_offset = CV_DRAMINTR_OFST, | |
43 | .ecc_irq_en_mask = CV_DRAMINTR_INTREN, | |
44 | .ecc_irq_clr_offset = CV_DRAMINTR_OFST, | |
45 | .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), | |
46 | .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, | |
47 | .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, | |
143f4a5a TT |
48 | .ce_ue_trgr_offset = CV_CTLCFG_OFST, |
49 | .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, | |
50 | .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, | |
71bcada8 TT |
51 | }; |
52 | ||
73bcc942 TT |
53 | static const struct altr_sdram_prv_data a10_data = { |
54 | .ecc_ctrl_offset = A10_ECCCTRL1_OFST, | |
55 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
56 | .ecc_stat_offset = A10_INTSTAT_OFST, | |
57 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
58 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
59 | .ecc_saddr_offset = A10_SERRADDR_OFST, | |
60 | .ecc_daddr_offset = A10_DERRADDR_OFST, | |
61 | .ecc_irq_en_offset = A10_ERRINTEN_OFST, | |
62 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
63 | .ecc_irq_clr_offset = A10_INTSTAT_OFST, | |
64 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
65 | .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, | |
66 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
73bcc942 TT |
67 | .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, |
68 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
69 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
73bcc942 TT |
70 | }; |
71 | ||
3dab6bd5 TT |
72 | static const struct altr_sdram_prv_data s10_data = { |
73 | .ecc_ctrl_offset = S10_ECCCTRL1_OFST, | |
74 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
75 | .ecc_stat_offset = S10_INTSTAT_OFST, | |
76 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
77 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
78 | .ecc_saddr_offset = S10_SERRADDR_OFST, | |
79 | .ecc_daddr_offset = S10_DERRADDR_OFST, | |
80 | .ecc_irq_en_offset = S10_ERRINTEN_OFST, | |
81 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
82 | .ecc_irq_clr_offset = S10_INTSTAT_OFST, | |
83 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
84 | .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST, | |
85 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
86 | .ce_ue_trgr_offset = S10_DIAGINTTEST_OFST, | |
87 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
88 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
89 | }; | |
90 | ||
c3eea194 TT |
91 | /*********************** EDAC Memory Controller Functions ****************/ |
92 | ||
93 | /* The SDRAM controller uses the EDAC Memory Controller framework. */ | |
94 | ||
71bcada8 TT |
95 | static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) |
96 | { | |
97 | struct mem_ctl_info *mci = dev_id; | |
98 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 99 | const struct altr_sdram_prv_data *priv = drvdata->data; |
73bcc942 | 100 | u32 status, err_count = 1, err_addr; |
71bcada8 | 101 | |
143f4a5a | 102 | regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); |
71bcada8 | 103 | |
143f4a5a | 104 | if (status & priv->ecc_stat_ue_mask) { |
73bcc942 TT |
105 | regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, |
106 | &err_addr); | |
107 | if (priv->ecc_uecnt_offset) | |
108 | regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, | |
109 | &err_count); | |
71bcada8 TT |
110 | panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", |
111 | err_count, err_addr); | |
112 | } | |
143f4a5a | 113 | if (status & priv->ecc_stat_ce_mask) { |
73bcc942 TT |
114 | regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, |
115 | &err_addr); | |
116 | if (priv->ecc_uecnt_offset) | |
117 | regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, | |
118 | &err_count); | |
71bcada8 TT |
119 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, |
120 | err_addr >> PAGE_SHIFT, | |
121 | err_addr & ~PAGE_MASK, 0, | |
122 | 0, 0, -1, mci->ctl_name, ""); | |
73bcc942 TT |
123 | /* Clear IRQ to resume */ |
124 | regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, | |
125 | priv->ecc_irq_clr_mask); | |
71bcada8 | 126 | |
73bcc942 TT |
127 | return IRQ_HANDLED; |
128 | } | |
129 | return IRQ_NONE; | |
71bcada8 TT |
130 | } |
131 | ||
71bcada8 TT |
132 | static ssize_t altr_sdr_mc_err_inject_write(struct file *file, |
133 | const char __user *data, | |
134 | size_t count, loff_t *ppos) | |
135 | { | |
136 | struct mem_ctl_info *mci = file->private_data; | |
137 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 138 | const struct altr_sdram_prv_data *priv = drvdata->data; |
71bcada8 TT |
139 | u32 *ptemp; |
140 | dma_addr_t dma_handle; | |
141 | u32 reg, read_reg; | |
142 | ||
143 | ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); | |
144 | if (!ptemp) { | |
145 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
146 | edac_printk(KERN_ERR, EDAC_MC, | |
147 | "Inject: Buffer Allocation error\n"); | |
148 | return -ENOMEM; | |
149 | } | |
150 | ||
143f4a5a TT |
151 | regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
152 | &read_reg); | |
153 | read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); | |
71bcada8 TT |
154 | |
155 | /* Error are injected by writing a word while the SBE or DBE | |
156 | * bit in the CTLCFG register is set. Reading the word will | |
157 | * trigger the SBE or DBE error and the corresponding IRQ. | |
158 | */ | |
159 | if (count == 3) { | |
160 | edac_printk(KERN_ALERT, EDAC_MC, | |
161 | "Inject Double bit error\n"); | |
90e493d7 | 162 | local_irq_disable(); |
143f4a5a TT |
163 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
164 | (read_reg | priv->ue_set_mask)); | |
90e493d7 | 165 | local_irq_enable(); |
71bcada8 TT |
166 | } else { |
167 | edac_printk(KERN_ALERT, EDAC_MC, | |
168 | "Inject Single bit error\n"); | |
90e493d7 | 169 | local_irq_disable(); |
143f4a5a TT |
170 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
171 | (read_reg | priv->ce_set_mask)); | |
90e493d7 | 172 | local_irq_enable(); |
71bcada8 TT |
173 | } |
174 | ||
175 | ptemp[0] = 0x5A5A5A5A; | |
176 | ptemp[1] = 0xA5A5A5A5; | |
177 | ||
178 | /* Clear the error injection bits */ | |
143f4a5a | 179 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); |
71bcada8 TT |
180 | /* Ensure it has been written out */ |
181 | wmb(); | |
182 | ||
183 | /* | |
184 | * To trigger the error, we need to read the data back | |
185 | * (the data was written with errors above). | |
332efa63 | 186 | * The READ_ONCE macros and printk are used to prevent the |
71bcada8 TT |
187 | * the compiler optimizing these reads out. |
188 | */ | |
332efa63 MR |
189 | reg = READ_ONCE(ptemp[0]); |
190 | read_reg = READ_ONCE(ptemp[1]); | |
71bcada8 TT |
191 | /* Force Read */ |
192 | rmb(); | |
193 | ||
194 | edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", | |
195 | reg, read_reg); | |
196 | ||
197 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
198 | ||
199 | return count; | |
200 | } | |
201 | ||
202 | static const struct file_operations altr_sdr_mc_debug_inject_fops = { | |
203 | .open = simple_open, | |
204 | .write = altr_sdr_mc_err_inject_write, | |
205 | .llseek = generic_file_llseek, | |
206 | }; | |
207 | ||
208 | static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) | |
209 | { | |
bba3b31e BP |
210 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) |
211 | return; | |
212 | ||
213 | if (!mci->debugfs) | |
214 | return; | |
215 | ||
b8978bad | 216 | edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, |
bba3b31e | 217 | &altr_sdr_mc_debug_inject_fops); |
71bcada8 | 218 | } |
71bcada8 | 219 | |
f9ae487e TT |
220 | /* Get total memory size from Open Firmware DTB */ |
221 | static unsigned long get_total_mem(void) | |
71bcada8 | 222 | { |
f9ae487e | 223 | struct device_node *np = NULL; |
ff0abed4 CP |
224 | struct resource res; |
225 | int ret; | |
226 | unsigned long total_mem = 0; | |
f9ae487e TT |
227 | |
228 | for_each_node_by_type(np, "memory") { | |
ff0abed4 CP |
229 | ret = of_address_to_resource(np, 0, &res); |
230 | if (ret) | |
231 | continue; | |
232 | ||
233 | total_mem += resource_size(&res); | |
f9ae487e TT |
234 | } |
235 | edac_dbg(0, "total_mem 0x%lx\n", total_mem); | |
236 | return total_mem; | |
71bcada8 TT |
237 | } |
238 | ||
143f4a5a | 239 | static const struct of_device_id altr_sdram_ctrl_of_match[] = { |
2c911f6c AB |
240 | { .compatible = "altr,sdram-edac", .data = &c5_data}, |
241 | { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, | |
3dab6bd5 | 242 | { .compatible = "altr,sdram-edac-s10", .data = &s10_data}, |
143f4a5a TT |
243 | {}, |
244 | }; | |
245 | MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); | |
246 | ||
73bcc942 TT |
247 | static int a10_init(struct regmap *mc_vbase) |
248 | { | |
249 | if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, | |
250 | A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { | |
251 | edac_printk(KERN_ERR, EDAC_MC, | |
252 | "Error setting SB IRQ mode\n"); | |
253 | return -ENODEV; | |
254 | } | |
255 | ||
256 | if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { | |
257 | edac_printk(KERN_ERR, EDAC_MC, | |
258 | "Error setting trigger count\n"); | |
259 | return -ENODEV; | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int a10_unmask_irq(struct platform_device *pdev, u32 mask) | |
266 | { | |
267 | void __iomem *sm_base; | |
268 | int ret = 0; | |
269 | ||
270 | if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), | |
271 | dev_name(&pdev->dev))) { | |
272 | edac_printk(KERN_ERR, EDAC_MC, | |
273 | "Unable to request mem region\n"); | |
274 | return -EBUSY; | |
275 | } | |
276 | ||
277 | sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
278 | if (!sm_base) { | |
279 | edac_printk(KERN_ERR, EDAC_MC, | |
280 | "Unable to ioremap device\n"); | |
281 | ||
282 | ret = -ENOMEM; | |
283 | goto release; | |
284 | } | |
285 | ||
286 | iowrite32(mask, sm_base); | |
287 | ||
288 | iounmap(sm_base); | |
289 | ||
290 | release: | |
291 | release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
71bcada8 TT |
296 | static int altr_sdram_probe(struct platform_device *pdev) |
297 | { | |
143f4a5a | 298 | const struct of_device_id *id; |
71bcada8 TT |
299 | struct edac_mc_layer layers[2]; |
300 | struct mem_ctl_info *mci; | |
301 | struct altr_sdram_mc_data *drvdata; | |
143f4a5a | 302 | const struct altr_sdram_prv_data *priv; |
71bcada8 TT |
303 | struct regmap *mc_vbase; |
304 | struct dimm_info *dimm; | |
143f4a5a | 305 | u32 read_reg; |
73bcc942 TT |
306 | int irq, irq2, res = 0; |
307 | unsigned long mem_size, irqflags = 0; | |
143f4a5a TT |
308 | |
309 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
310 | if (!id) | |
311 | return -ENODEV; | |
71bcada8 | 312 | |
71bcada8 TT |
313 | /* Grab the register range from the sdr controller in device tree */ |
314 | mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
315 | "altr,sdr-syscon"); | |
316 | if (IS_ERR(mc_vbase)) { | |
317 | edac_printk(KERN_ERR, EDAC_MC, | |
318 | "regmap for altr,sdr-syscon lookup failed.\n"); | |
319 | return -ENODEV; | |
320 | } | |
321 | ||
143f4a5a TT |
322 | /* Check specific dependencies for the module */ |
323 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
324 | pdev->dev.of_node)->data; | |
325 | ||
326 | /* Validate the SDRAM controller has ECC enabled */ | |
327 | if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || | |
328 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
71bcada8 TT |
329 | edac_printk(KERN_ERR, EDAC_MC, |
330 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
331 | return -ENODEV; | |
332 | } | |
333 | ||
334 | /* Grab memory size from device tree. */ | |
f9ae487e | 335 | mem_size = get_total_mem(); |
71bcada8 | 336 | if (!mem_size) { |
f9ae487e | 337 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); |
71bcada8 TT |
338 | return -ENODEV; |
339 | } | |
340 | ||
143f4a5a TT |
341 | /* Ensure the SDRAM Interrupt is disabled */ |
342 | if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, | |
343 | priv->ecc_irq_en_mask, 0)) { | |
344 | edac_printk(KERN_ERR, EDAC_MC, | |
345 | "Error disabling SDRAM ECC IRQ\n"); | |
346 | return -ENODEV; | |
347 | } | |
348 | ||
349 | /* Toggle to clear the SDRAM Error count */ | |
350 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
351 | priv->ecc_cnt_rst_mask, | |
352 | priv->ecc_cnt_rst_mask)) { | |
353 | edac_printk(KERN_ERR, EDAC_MC, | |
354 | "Error clearing SDRAM ECC count\n"); | |
355 | return -ENODEV; | |
356 | } | |
357 | ||
358 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
359 | priv->ecc_cnt_rst_mask, 0)) { | |
71bcada8 | 360 | edac_printk(KERN_ERR, EDAC_MC, |
143f4a5a | 361 | "Error clearing SDRAM ECC count\n"); |
71bcada8 TT |
362 | return -ENODEV; |
363 | } | |
364 | ||
365 | irq = platform_get_irq(pdev, 0); | |
366 | if (irq < 0) { | |
367 | edac_printk(KERN_ERR, EDAC_MC, | |
368 | "No irq %d in DT\n", irq); | |
369 | return -ENODEV; | |
370 | } | |
371 | ||
73bcc942 TT |
372 | /* Arria10 has a 2nd IRQ */ |
373 | irq2 = platform_get_irq(pdev, 1); | |
374 | ||
71bcada8 TT |
375 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
376 | layers[0].size = 1; | |
377 | layers[0].is_virt_csrow = true; | |
378 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
379 | layers[1].size = 1; | |
380 | layers[1].is_virt_csrow = false; | |
381 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
382 | sizeof(struct altr_sdram_mc_data)); | |
383 | if (!mci) | |
384 | return -ENOMEM; | |
385 | ||
386 | mci->pdev = &pdev->dev; | |
387 | drvdata = mci->pvt_info; | |
388 | drvdata->mc_vbase = mc_vbase; | |
143f4a5a | 389 | drvdata->data = priv; |
71bcada8 TT |
390 | platform_set_drvdata(pdev, mci); |
391 | ||
392 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
143f4a5a TT |
393 | edac_printk(KERN_ERR, EDAC_MC, |
394 | "Unable to get managed device resource\n"); | |
71bcada8 TT |
395 | res = -ENOMEM; |
396 | goto free; | |
397 | } | |
398 | ||
399 | mci->mtype_cap = MEM_FLAG_DDR3; | |
400 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
401 | mci->edac_cap = EDAC_FLAG_SECDED; | |
402 | mci->mod_name = EDAC_MOD_STR; | |
71bcada8 TT |
403 | mci->ctl_name = dev_name(&pdev->dev); |
404 | mci->scrub_mode = SCRUB_SW_SRC; | |
405 | mci->dev_name = dev_name(&pdev->dev); | |
406 | ||
407 | dimm = *mci->dimms; | |
408 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
409 | dimm->grain = 8; | |
410 | dimm->dtype = DEV_X8; | |
411 | dimm->mtype = MEM_DDR3; | |
412 | dimm->edac_mode = EDAC_SECDED; | |
413 | ||
414 | res = edac_mc_add_mc(mci); | |
415 | if (res < 0) | |
416 | goto err; | |
417 | ||
73bcc942 TT |
418 | /* Only the Arria10 has separate IRQs */ |
419 | if (irq2 > 0) { | |
420 | /* Arria10 specific initialization */ | |
421 | res = a10_init(mc_vbase); | |
422 | if (res < 0) | |
423 | goto err2; | |
424 | ||
425 | res = devm_request_irq(&pdev->dev, irq2, | |
426 | altr_sdram_mc_err_handler, | |
427 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
428 | if (res < 0) { | |
429 | edac_mc_printk(mci, KERN_ERR, | |
430 | "Unable to request irq %d\n", irq2); | |
431 | res = -ENODEV; | |
432 | goto err2; | |
433 | } | |
434 | ||
435 | res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); | |
436 | if (res < 0) | |
437 | goto err2; | |
438 | ||
439 | irqflags = IRQF_SHARED; | |
440 | } | |
441 | ||
71bcada8 | 442 | res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, |
73bcc942 | 443 | irqflags, dev_name(&pdev->dev), mci); |
71bcada8 TT |
444 | if (res < 0) { |
445 | edac_mc_printk(mci, KERN_ERR, | |
446 | "Unable to request irq %d\n", irq); | |
447 | res = -ENODEV; | |
448 | goto err2; | |
449 | } | |
450 | ||
143f4a5a TT |
451 | /* Infrastructure ready - enable the IRQ */ |
452 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, | |
453 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
71bcada8 TT |
454 | edac_mc_printk(mci, KERN_ERR, |
455 | "Error enabling SDRAM ECC IRQ\n"); | |
456 | res = -ENODEV; | |
457 | goto err2; | |
458 | } | |
459 | ||
460 | altr_sdr_mc_create_debugfs_nodes(mci); | |
461 | ||
462 | devres_close_group(&pdev->dev, NULL); | |
463 | ||
464 | return 0; | |
465 | ||
466 | err2: | |
467 | edac_mc_del_mc(&pdev->dev); | |
468 | err: | |
469 | devres_release_group(&pdev->dev, NULL); | |
470 | free: | |
471 | edac_mc_free(mci); | |
472 | edac_printk(KERN_ERR, EDAC_MC, | |
473 | "EDAC Probe Failed; Error %d\n", res); | |
474 | ||
475 | return res; | |
476 | } | |
477 | ||
478 | static int altr_sdram_remove(struct platform_device *pdev) | |
479 | { | |
480 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
481 | ||
482 | edac_mc_del_mc(&pdev->dev); | |
483 | edac_mc_free(mci); | |
484 | platform_set_drvdata(pdev, NULL); | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
3dab6bd5 TT |
489 | /**************** Stratix 10 EDAC Memory Controller Functions ************/ |
490 | ||
491 | /** | |
492 | * s10_protected_reg_write | |
493 | * Write to a protected SMC register. | |
494 | * @context: Not used. | |
495 | * @reg: Address of register | |
496 | * @value: Value to write | |
497 | * Return: INTEL_SIP_SMC_STATUS_OK (0) on success | |
498 | * INTEL_SIP_SMC_REG_ERROR on error | |
499 | * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported | |
500 | */ | |
501 | static int s10_protected_reg_write(void *context, unsigned int reg, | |
502 | unsigned int val) | |
503 | { | |
504 | struct arm_smccc_res result; | |
505 | ||
506 | arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0, | |
507 | 0, 0, 0, &result); | |
508 | ||
509 | return (int)result.a0; | |
510 | } | |
511 | ||
512 | /** | |
513 | * s10_protected_reg_read | |
514 | * Read the status of a protected SMC register | |
515 | * @context: Not used. | |
516 | * @reg: Address of register | |
517 | * @value: Value read. | |
518 | * Return: INTEL_SIP_SMC_STATUS_OK (0) on success | |
519 | * INTEL_SIP_SMC_REG_ERROR on error | |
520 | * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported | |
521 | */ | |
522 | static int s10_protected_reg_read(void *context, unsigned int reg, | |
523 | unsigned int *val) | |
524 | { | |
525 | struct arm_smccc_res result; | |
526 | ||
527 | arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0, | |
528 | 0, 0, 0, &result); | |
529 | ||
530 | *val = (unsigned int)result.a1; | |
531 | ||
532 | return (int)result.a0; | |
533 | } | |
534 | ||
535 | static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg) | |
536 | { | |
537 | switch (reg) { | |
538 | case S10_ECCCTRL1_OFST: | |
539 | case S10_ERRINTEN_OFST: | |
540 | case S10_INTMODE_OFST: | |
541 | case S10_INTSTAT_OFST: | |
542 | case S10_DIAGINTTEST_OFST: | |
543 | case S10_SYSMGR_ECC_INTMASK_VAL_OFST: | |
544 | case S10_SYSMGR_ECC_INTMASK_SET_OFST: | |
545 | case S10_SYSMGR_ECC_INTMASK_CLR_OFST: | |
546 | return true; | |
547 | } | |
548 | return false; | |
549 | } | |
550 | ||
551 | static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg) | |
552 | { | |
553 | switch (reg) { | |
554 | case S10_ECCCTRL1_OFST: | |
555 | case S10_ERRINTEN_OFST: | |
556 | case S10_INTMODE_OFST: | |
557 | case S10_INTSTAT_OFST: | |
558 | case S10_DERRADDR_OFST: | |
559 | case S10_SERRADDR_OFST: | |
560 | case S10_DIAGINTTEST_OFST: | |
561 | case S10_SYSMGR_ECC_INTMASK_VAL_OFST: | |
562 | case S10_SYSMGR_ECC_INTMASK_SET_OFST: | |
563 | case S10_SYSMGR_ECC_INTMASK_CLR_OFST: | |
564 | case S10_SYSMGR_ECC_INTSTAT_SERR_OFST: | |
565 | case S10_SYSMGR_ECC_INTSTAT_DERR_OFST: | |
566 | return true; | |
567 | } | |
568 | return false; | |
569 | } | |
570 | ||
571 | static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg) | |
572 | { | |
573 | switch (reg) { | |
574 | case S10_ECCCTRL1_OFST: | |
575 | case S10_ERRINTEN_OFST: | |
576 | case S10_INTMODE_OFST: | |
577 | case S10_INTSTAT_OFST: | |
578 | case S10_DERRADDR_OFST: | |
579 | case S10_SERRADDR_OFST: | |
580 | case S10_DIAGINTTEST_OFST: | |
581 | case S10_SYSMGR_ECC_INTMASK_VAL_OFST: | |
582 | case S10_SYSMGR_ECC_INTMASK_SET_OFST: | |
583 | case S10_SYSMGR_ECC_INTMASK_CLR_OFST: | |
584 | case S10_SYSMGR_ECC_INTSTAT_SERR_OFST: | |
585 | case S10_SYSMGR_ECC_INTSTAT_DERR_OFST: | |
586 | return true; | |
587 | } | |
588 | return false; | |
589 | } | |
590 | ||
591 | static const struct regmap_config s10_sdram_regmap_cfg = { | |
592 | .name = "s10_ddr", | |
593 | .reg_bits = 32, | |
594 | .reg_stride = 4, | |
595 | .val_bits = 32, | |
596 | .max_register = 0xffffffff, | |
597 | .writeable_reg = s10_sdram_writeable_reg, | |
598 | .readable_reg = s10_sdram_readable_reg, | |
599 | .volatile_reg = s10_sdram_volatile_reg, | |
600 | .reg_read = s10_protected_reg_read, | |
601 | .reg_write = s10_protected_reg_write, | |
602 | .use_single_rw = true, | |
603 | }; | |
604 | ||
605 | static int altr_s10_sdram_probe(struct platform_device *pdev) | |
606 | { | |
607 | const struct of_device_id *id; | |
608 | struct edac_mc_layer layers[2]; | |
609 | struct mem_ctl_info *mci; | |
610 | struct altr_sdram_mc_data *drvdata; | |
611 | const struct altr_sdram_prv_data *priv; | |
612 | struct regmap *regmap; | |
613 | struct dimm_info *dimm; | |
614 | u32 read_reg; | |
615 | int irq, ret = 0; | |
616 | unsigned long mem_size; | |
617 | ||
618 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
619 | if (!id) | |
620 | return -ENODEV; | |
621 | ||
622 | /* Grab specific offsets and masks for Stratix10 */ | |
623 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
624 | pdev->dev.of_node)->data; | |
625 | ||
626 | regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv, | |
627 | &s10_sdram_regmap_cfg); | |
628 | if (IS_ERR(regmap)) | |
629 | return PTR_ERR(regmap); | |
630 | ||
631 | /* Validate the SDRAM controller has ECC enabled */ | |
632 | if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) || | |
633 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
634 | edac_printk(KERN_ERR, EDAC_MC, | |
635 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
636 | return -ENODEV; | |
637 | } | |
638 | ||
639 | /* Grab memory size from device tree. */ | |
640 | mem_size = get_total_mem(); | |
641 | if (!mem_size) { | |
642 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); | |
643 | return -ENODEV; | |
644 | } | |
645 | ||
646 | /* Ensure the SDRAM Interrupt is disabled */ | |
647 | if (regmap_update_bits(regmap, priv->ecc_irq_en_offset, | |
648 | priv->ecc_irq_en_mask, 0)) { | |
649 | edac_printk(KERN_ERR, EDAC_MC, | |
650 | "Error disabling SDRAM ECC IRQ\n"); | |
651 | return -ENODEV; | |
652 | } | |
653 | ||
654 | /* Toggle to clear the SDRAM Error count */ | |
655 | if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset, | |
656 | priv->ecc_cnt_rst_mask, | |
657 | priv->ecc_cnt_rst_mask)) { | |
658 | edac_printk(KERN_ERR, EDAC_MC, | |
659 | "Error clearing SDRAM ECC count\n"); | |
660 | return -ENODEV; | |
661 | } | |
662 | ||
663 | if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset, | |
664 | priv->ecc_cnt_rst_mask, 0)) { | |
665 | edac_printk(KERN_ERR, EDAC_MC, | |
666 | "Error clearing SDRAM ECC count\n"); | |
667 | return -ENODEV; | |
668 | } | |
669 | ||
670 | irq = platform_get_irq(pdev, 0); | |
671 | if (irq < 0) { | |
672 | edac_printk(KERN_ERR, EDAC_MC, | |
673 | "No irq %d in DT\n", irq); | |
674 | return -ENODEV; | |
675 | } | |
676 | ||
677 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; | |
678 | layers[0].size = 1; | |
679 | layers[0].is_virt_csrow = true; | |
680 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
681 | layers[1].size = 1; | |
682 | layers[1].is_virt_csrow = false; | |
683 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
684 | sizeof(struct altr_sdram_mc_data)); | |
685 | if (!mci) | |
686 | return -ENOMEM; | |
687 | ||
688 | mci->pdev = &pdev->dev; | |
689 | drvdata = mci->pvt_info; | |
690 | drvdata->mc_vbase = regmap; | |
691 | drvdata->data = priv; | |
692 | platform_set_drvdata(pdev, mci); | |
693 | ||
694 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
695 | edac_printk(KERN_ERR, EDAC_MC, | |
696 | "Unable to get managed device resource\n"); | |
697 | ret = -ENOMEM; | |
698 | goto free; | |
699 | } | |
700 | ||
701 | mci->mtype_cap = MEM_FLAG_DDR3; | |
702 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
703 | mci->edac_cap = EDAC_FLAG_SECDED; | |
704 | mci->mod_name = EDAC_MOD_STR; | |
705 | mci->ctl_name = dev_name(&pdev->dev); | |
706 | mci->scrub_mode = SCRUB_SW_SRC; | |
707 | mci->dev_name = dev_name(&pdev->dev); | |
708 | ||
709 | dimm = *mci->dimms; | |
710 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
711 | dimm->grain = 8; | |
712 | dimm->dtype = DEV_X8; | |
713 | dimm->mtype = MEM_DDR3; | |
714 | dimm->edac_mode = EDAC_SECDED; | |
715 | ||
716 | ret = edac_mc_add_mc(mci); | |
717 | if (ret < 0) | |
718 | goto err; | |
719 | ||
720 | ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, | |
721 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
722 | if (ret < 0) { | |
723 | edac_mc_printk(mci, KERN_ERR, | |
724 | "Unable to request irq %d\n", irq); | |
725 | ret = -ENODEV; | |
726 | goto err2; | |
727 | } | |
728 | ||
e9918d7f TT |
729 | if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST, |
730 | S10_DDR0_IRQ_MASK)) { | |
731 | edac_printk(KERN_ERR, EDAC_MC, | |
732 | "Error clearing SDRAM ECC count\n"); | |
9d72fe1c CJ |
733 | ret = -ENODEV; |
734 | goto err2; | |
e9918d7f TT |
735 | } |
736 | ||
3dab6bd5 TT |
737 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, |
738 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
739 | edac_mc_printk(mci, KERN_ERR, | |
740 | "Error enabling SDRAM ECC IRQ\n"); | |
741 | ret = -ENODEV; | |
742 | goto err2; | |
743 | } | |
744 | ||
745 | altr_sdr_mc_create_debugfs_nodes(mci); | |
746 | ||
747 | devres_close_group(&pdev->dev, NULL); | |
748 | ||
749 | return 0; | |
750 | ||
751 | err2: | |
752 | edac_mc_del_mc(&pdev->dev); | |
753 | err: | |
754 | devres_release_group(&pdev->dev, NULL); | |
755 | free: | |
756 | edac_mc_free(mci); | |
757 | edac_printk(KERN_ERR, EDAC_MC, | |
758 | "EDAC Probe Failed; Error %d\n", ret); | |
759 | ||
760 | return ret; | |
761 | } | |
762 | ||
763 | static int altr_s10_sdram_remove(struct platform_device *pdev) | |
764 | { | |
765 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
766 | ||
767 | edac_mc_del_mc(&pdev->dev); | |
768 | edac_mc_free(mci); | |
769 | platform_set_drvdata(pdev, NULL); | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | /************** </Stratix10 EDAC Memory Controller Functions> ***********/ | |
775 | ||
6f2b6422 AT |
776 | /* |
777 | * If you want to suspend, need to disable EDAC by removing it | |
778 | * from the device tree or defconfig. | |
779 | */ | |
780 | #ifdef CONFIG_PM | |
781 | static int altr_sdram_prepare(struct device *dev) | |
782 | { | |
783 | pr_err("Suspend not allowed when EDAC is enabled.\n"); | |
784 | ||
785 | return -EPERM; | |
786 | } | |
787 | ||
788 | static const struct dev_pm_ops altr_sdram_pm_ops = { | |
789 | .prepare = altr_sdram_prepare, | |
790 | }; | |
791 | #endif | |
792 | ||
71bcada8 TT |
793 | static struct platform_driver altr_sdram_edac_driver = { |
794 | .probe = altr_sdram_probe, | |
795 | .remove = altr_sdram_remove, | |
796 | .driver = { | |
797 | .name = "altr_sdram_edac", | |
6f2b6422 AT |
798 | #ifdef CONFIG_PM |
799 | .pm = &altr_sdram_pm_ops, | |
800 | #endif | |
71bcada8 TT |
801 | .of_match_table = altr_sdram_ctrl_of_match, |
802 | }, | |
803 | }; | |
804 | ||
805 | module_platform_driver(altr_sdram_edac_driver); | |
806 | ||
3dab6bd5 TT |
807 | static struct platform_driver altr_s10_sdram_edac_driver = { |
808 | .probe = altr_s10_sdram_probe, | |
809 | .remove = altr_s10_sdram_remove, | |
810 | .driver = { | |
811 | .name = "altr_s10_sdram_edac", | |
812 | #ifdef CONFIG_PM | |
813 | .pm = &altr_sdram_pm_ops, | |
814 | #endif | |
815 | .of_match_table = altr_sdram_ctrl_of_match, | |
816 | }, | |
817 | }; | |
818 | ||
819 | module_platform_driver(altr_s10_sdram_edac_driver); | |
820 | ||
c3eea194 TT |
821 | /************************* EDAC Parent Probe *************************/ |
822 | ||
823 | static const struct of_device_id altr_edac_device_of_match[]; | |
824 | ||
825 | static const struct of_device_id altr_edac_of_match[] = { | |
826 | { .compatible = "altr,socfpga-ecc-manager" }, | |
827 | {}, | |
828 | }; | |
829 | MODULE_DEVICE_TABLE(of, altr_edac_of_match); | |
830 | ||
831 | static int altr_edac_probe(struct platform_device *pdev) | |
832 | { | |
833 | of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, | |
834 | NULL, &pdev->dev); | |
835 | return 0; | |
836 | } | |
837 | ||
838 | static struct platform_driver altr_edac_driver = { | |
839 | .probe = altr_edac_probe, | |
840 | .driver = { | |
841 | .name = "socfpga_ecc_manager", | |
842 | .of_match_table = altr_edac_of_match, | |
843 | }, | |
844 | }; | |
845 | module_platform_driver(altr_edac_driver); | |
846 | ||
847 | /************************* EDAC Device Functions *************************/ | |
848 | ||
849 | /* | |
850 | * EDAC Device Functions (shared between various IPs). | |
851 | * The discrete memories use the EDAC Device framework. The probe | |
852 | * and error handling functions are very similar between memories | |
853 | * so they are shared. The memory allocation and freeing for EDAC | |
854 | * trigger testing are different for each memory. | |
855 | */ | |
856 | ||
1cf70377 TT |
857 | static const struct edac_device_prv_data ocramecc_data; |
858 | static const struct edac_device_prv_data l2ecc_data; | |
859 | static const struct edac_device_prv_data a10_ocramecc_data; | |
860 | static const struct edac_device_prv_data a10_l2ecc_data; | |
c3eea194 | 861 | |
c3eea194 TT |
862 | static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) |
863 | { | |
864 | irqreturn_t ret_value = IRQ_NONE; | |
865 | struct edac_device_ctl_info *dci = dev_id; | |
866 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
867 | const struct edac_device_prv_data *priv = drvdata->data; | |
868 | ||
869 | if (irq == drvdata->sb_irq) { | |
870 | if (priv->ce_clear_mask) | |
871 | writel(priv->ce_clear_mask, drvdata->base); | |
872 | edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); | |
873 | ret_value = IRQ_HANDLED; | |
874 | } else if (irq == drvdata->db_irq) { | |
875 | if (priv->ue_clear_mask) | |
876 | writel(priv->ue_clear_mask, drvdata->base); | |
877 | edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); | |
878 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
879 | ret_value = IRQ_HANDLED; | |
880 | } else { | |
881 | WARN_ON(1); | |
882 | } | |
883 | ||
884 | return ret_value; | |
885 | } | |
886 | ||
887 | static ssize_t altr_edac_device_trig(struct file *file, | |
888 | const char __user *user_buf, | |
889 | size_t count, loff_t *ppos) | |
890 | ||
891 | { | |
892 | u32 *ptemp, i, error_mask; | |
893 | int result = 0; | |
894 | u8 trig_type; | |
895 | unsigned long flags; | |
896 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
897 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
898 | const struct edac_device_prv_data *priv = drvdata->data; | |
899 | void *generic_ptr = edac_dci->dev; | |
900 | ||
901 | if (!user_buf || get_user(trig_type, user_buf)) | |
902 | return -EFAULT; | |
903 | ||
904 | if (!priv->alloc_mem) | |
905 | return -ENOMEM; | |
906 | ||
907 | /* | |
908 | * Note that generic_ptr is initialized to the device * but in | |
909 | * some alloc_functions, this is overridden and returns data. | |
910 | */ | |
911 | ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); | |
912 | if (!ptemp) { | |
913 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
914 | "Inject: Buffer Allocation error\n"); | |
915 | return -ENOMEM; | |
916 | } | |
917 | ||
918 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
919 | error_mask = priv->ue_set_mask; | |
920 | else | |
921 | error_mask = priv->ce_set_mask; | |
922 | ||
923 | edac_printk(KERN_ALERT, EDAC_DEVICE, | |
924 | "Trigger Error Mask (0x%X)\n", error_mask); | |
925 | ||
926 | local_irq_save(flags); | |
927 | /* write ECC corrupted data out. */ | |
928 | for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { | |
929 | /* Read data so we're in the correct state */ | |
930 | rmb(); | |
332efa63 | 931 | if (READ_ONCE(ptemp[i])) |
c3eea194 TT |
932 | result = -1; |
933 | /* Toggle Error bit (it is latched), leave ECC enabled */ | |
811fce4f TT |
934 | writel(error_mask, (drvdata->base + priv->set_err_ofst)); |
935 | writel(priv->ecc_enable_mask, (drvdata->base + | |
936 | priv->set_err_ofst)); | |
c3eea194 TT |
937 | ptemp[i] = i; |
938 | } | |
939 | /* Ensure it has been written out */ | |
940 | wmb(); | |
941 | local_irq_restore(flags); | |
942 | ||
943 | if (result) | |
944 | edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); | |
945 | ||
946 | /* Read out written data. ECC error caused here */ | |
947 | for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) | |
332efa63 | 948 | if (READ_ONCE(ptemp[i]) != i) |
c3eea194 TT |
949 | edac_printk(KERN_ERR, EDAC_DEVICE, |
950 | "Read doesn't match written data\n"); | |
951 | ||
952 | if (priv->free_mem) | |
953 | priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); | |
954 | ||
955 | return count; | |
956 | } | |
957 | ||
958 | static const struct file_operations altr_edac_device_inject_fops = { | |
959 | .open = simple_open, | |
960 | .write = altr_edac_device_trig, | |
961 | .llseek = generic_file_llseek, | |
962 | }; | |
963 | ||
c7b4be8d TT |
964 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
965 | const char __user *user_buf, | |
966 | size_t count, loff_t *ppos); | |
967 | ||
968 | static const struct file_operations altr_edac_a10_device_inject_fops = { | |
969 | .open = simple_open, | |
970 | .write = altr_edac_a10_device_trig, | |
971 | .llseek = generic_file_llseek, | |
972 | }; | |
973 | ||
c3eea194 TT |
974 | static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, |
975 | const struct edac_device_prv_data *priv) | |
976 | { | |
977 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
978 | ||
979 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
980 | return; | |
981 | ||
982 | drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); | |
983 | if (!drvdata->debugfs_dir) | |
984 | return; | |
985 | ||
f399f34b | 986 | if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, |
c3eea194 | 987 | drvdata->debugfs_dir, edac_dci, |
e17ced2c | 988 | priv->inject_fops)) |
c3eea194 TT |
989 | debugfs_remove_recursive(drvdata->debugfs_dir); |
990 | } | |
991 | ||
992 | static const struct of_device_id altr_edac_device_of_match[] = { | |
993 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
2c911f6c | 994 | { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, |
c3eea194 TT |
995 | #endif |
996 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
2c911f6c | 997 | { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, |
c3eea194 TT |
998 | #endif |
999 | {}, | |
1000 | }; | |
1001 | MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); | |
1002 | ||
1003 | /* | |
1004 | * altr_edac_device_probe() | |
1005 | * This is a generic EDAC device driver that will support | |
1006 | * various Altera memory devices such as the L2 cache ECC and | |
1007 | * OCRAM ECC as well as the memories for other peripherals. | |
1008 | * Module specific initialization is done by passing the | |
1009 | * function index in the device tree. | |
1010 | */ | |
1011 | static int altr_edac_device_probe(struct platform_device *pdev) | |
1012 | { | |
1013 | struct edac_device_ctl_info *dci; | |
1014 | struct altr_edac_device_dev *drvdata; | |
1015 | struct resource *r; | |
1016 | int res = 0; | |
1017 | struct device_node *np = pdev->dev.of_node; | |
1018 | char *ecc_name = (char *)np->name; | |
1019 | static int dev_instance; | |
1020 | ||
1021 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
1022 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1023 | "Unable to open devm\n"); | |
1024 | return -ENOMEM; | |
1025 | } | |
1026 | ||
1027 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1028 | if (!r) { | |
1029 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1030 | "Unable to get mem resource\n"); | |
1031 | res = -ENODEV; | |
1032 | goto fail; | |
1033 | } | |
1034 | ||
1035 | if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), | |
1036 | dev_name(&pdev->dev))) { | |
1037 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1038 | "%s:Error requesting mem region\n", ecc_name); | |
1039 | res = -EBUSY; | |
1040 | goto fail; | |
1041 | } | |
1042 | ||
1043 | dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, | |
1044 | 1, ecc_name, 1, 0, NULL, 0, | |
1045 | dev_instance++); | |
1046 | ||
1047 | if (!dci) { | |
1048 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1049 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
1050 | res = -ENOMEM; | |
1051 | goto fail; | |
1052 | } | |
1053 | ||
1054 | drvdata = dci->pvt_info; | |
1055 | dci->dev = &pdev->dev; | |
1056 | platform_set_drvdata(pdev, dci); | |
1057 | drvdata->edac_dev_name = ecc_name; | |
1058 | ||
1059 | drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); | |
8b073d94 CJ |
1060 | if (!drvdata->base) { |
1061 | res = -ENOMEM; | |
c3eea194 | 1062 | goto fail1; |
8b073d94 | 1063 | } |
c3eea194 TT |
1064 | |
1065 | /* Get driver specific data for this EDAC device */ | |
1066 | drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; | |
1067 | ||
1068 | /* Check specific dependencies for the module */ | |
1069 | if (drvdata->data->setup) { | |
328ca7ae | 1070 | res = drvdata->data->setup(drvdata); |
c3eea194 TT |
1071 | if (res) |
1072 | goto fail1; | |
1073 | } | |
1074 | ||
1075 | drvdata->sb_irq = platform_get_irq(pdev, 0); | |
1076 | res = devm_request_irq(&pdev->dev, drvdata->sb_irq, | |
1077 | altr_edac_device_handler, | |
1078 | 0, dev_name(&pdev->dev), dci); | |
1079 | if (res) | |
1080 | goto fail1; | |
1081 | ||
1082 | drvdata->db_irq = platform_get_irq(pdev, 1); | |
1083 | res = devm_request_irq(&pdev->dev, drvdata->db_irq, | |
1084 | altr_edac_device_handler, | |
1085 | 0, dev_name(&pdev->dev), dci); | |
1086 | if (res) | |
1087 | goto fail1; | |
1088 | ||
1089 | dci->mod_name = "Altera ECC Manager"; | |
1090 | dci->dev_name = drvdata->edac_dev_name; | |
1091 | ||
1092 | res = edac_device_add_device(dci); | |
1093 | if (res) | |
1094 | goto fail1; | |
1095 | ||
1096 | altr_create_edacdev_dbgfs(dci, drvdata->data); | |
1097 | ||
1098 | devres_close_group(&pdev->dev, NULL); | |
1099 | ||
1100 | return 0; | |
1101 | ||
1102 | fail1: | |
1103 | edac_device_free_ctl_info(dci); | |
1104 | fail: | |
1105 | devres_release_group(&pdev->dev, NULL); | |
1106 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1107 | "%s:Error setting up EDAC device: %d\n", ecc_name, res); | |
1108 | ||
1109 | return res; | |
1110 | } | |
1111 | ||
1112 | static int altr_edac_device_remove(struct platform_device *pdev) | |
1113 | { | |
1114 | struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); | |
1115 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
1116 | ||
1117 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
1118 | edac_device_del_device(&pdev->dev); | |
1119 | edac_device_free_ctl_info(dci); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static struct platform_driver altr_edac_device_driver = { | |
1125 | .probe = altr_edac_device_probe, | |
1126 | .remove = altr_edac_device_remove, | |
1127 | .driver = { | |
1128 | .name = "altr_edac_device", | |
1129 | .of_match_table = altr_edac_device_of_match, | |
1130 | }, | |
1131 | }; | |
1132 | module_platform_driver(altr_edac_device_driver); | |
1133 | ||
6b300fb9 | 1134 | /******************* Arria10 Device ECC Shared Functions *****************/ |
c3eea194 | 1135 | |
1aa6eb5c AB |
1136 | /* |
1137 | * Test for memory's ECC dependencies upon entry because platform specific | |
1138 | * startup should have initialized the memory and enabled the ECC. | |
1139 | * Can't turn on ECC here because accessing un-initialized memory will | |
1140 | * cause CE/UE errors possibly causing an ABORT. | |
1141 | */ | |
6b300fb9 TT |
1142 | static int __maybe_unused |
1143 | altr_check_ecc_deps(struct altr_edac_device_dev *device) | |
1aa6eb5c AB |
1144 | { |
1145 | void __iomem *base = device->base; | |
1146 | const struct edac_device_prv_data *prv = device->data; | |
1147 | ||
1148 | if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) | |
1149 | return 0; | |
1150 | ||
1151 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1152 | "%s: No ECC present or ECC disabled.\n", | |
1153 | device->edac_dev_name); | |
1154 | return -ENODEV; | |
1155 | } | |
c3eea194 | 1156 | |
6b300fb9 TT |
1157 | static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) |
1158 | { | |
1159 | struct altr_edac_device_dev *dci = dev_id; | |
1160 | void __iomem *base = dci->base; | |
1161 | ||
1162 | if (irq == dci->sb_irq) { | |
1163 | writel(ALTR_A10_ECC_SERRPENA, | |
1164 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1165 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1166 | ||
1167 | return IRQ_HANDLED; | |
1168 | } else if (irq == dci->db_irq) { | |
1169 | writel(ALTR_A10_ECC_DERRPENA, | |
1170 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1171 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1172 | if (dci->data->panic) | |
1173 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
1174 | ||
1175 | return IRQ_HANDLED; | |
1176 | } | |
1177 | ||
1178 | WARN_ON(1); | |
1179 | ||
1180 | return IRQ_NONE; | |
1181 | } | |
1182 | ||
1166fde9 TT |
1183 | /******************* Arria10 Memory Buffer Functions *********************/ |
1184 | ||
1185 | static inline int a10_get_irq_mask(struct device_node *np) | |
1186 | { | |
1187 | int irq; | |
1188 | const u32 *handle = of_get_property(np, "interrupts", NULL); | |
1189 | ||
1190 | if (!handle) | |
1191 | return -ENODEV; | |
1192 | irq = be32_to_cpup(handle); | |
1193 | return irq; | |
1194 | } | |
1195 | ||
1196 | static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) | |
1197 | { | |
1198 | u32 value = readl(ioaddr); | |
1199 | ||
1200 | value |= bit_mask; | |
1201 | writel(value, ioaddr); | |
1202 | } | |
1203 | ||
1204 | static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) | |
1205 | { | |
1206 | u32 value = readl(ioaddr); | |
1207 | ||
1208 | value &= ~bit_mask; | |
1209 | writel(value, ioaddr); | |
1210 | } | |
1211 | ||
1212 | static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) | |
1213 | { | |
1214 | u32 value = readl(ioaddr); | |
1215 | ||
1216 | return (value & bit_mask) ? 1 : 0; | |
1217 | } | |
1218 | ||
1219 | /* | |
1220 | * This function uses the memory initialization block in the Arria10 ECC | |
1221 | * controller to initialize/clear the entire memory data and ECC data. | |
1222 | */ | |
1223 | static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) | |
1224 | { | |
1225 | int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; | |
1226 | u32 init_mask, stat_mask, clear_mask; | |
1227 | int ret = 0; | |
1228 | ||
1229 | if (port) { | |
1230 | init_mask = ALTR_A10_ECC_INITB; | |
1231 | stat_mask = ALTR_A10_ECC_INITCOMPLETEB; | |
1232 | clear_mask = ALTR_A10_ECC_ERRPENB_MASK; | |
1233 | } else { | |
1234 | init_mask = ALTR_A10_ECC_INITA; | |
1235 | stat_mask = ALTR_A10_ECC_INITCOMPLETEA; | |
1236 | clear_mask = ALTR_A10_ECC_ERRPENA_MASK; | |
1237 | } | |
1238 | ||
1239 | ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); | |
1240 | while (limit--) { | |
1241 | if (ecc_test_bits(stat_mask, | |
1242 | (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) | |
1243 | break; | |
1244 | udelay(1); | |
1245 | } | |
1246 | if (limit < 0) | |
1247 | ret = -EBUSY; | |
1248 | ||
1249 | /* Clear any pending ECC interrupts */ | |
1250 | writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); | |
1251 | ||
1252 | return ret; | |
1253 | } | |
1254 | ||
1255 | static __init int __maybe_unused | |
1256 | altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, | |
1257 | u32 ecc_ctrl_en_mask, bool dual_port) | |
1258 | { | |
1259 | int ret = 0; | |
1260 | void __iomem *ecc_block_base; | |
1261 | struct regmap *ecc_mgr_map; | |
1262 | char *ecc_name; | |
1263 | struct device_node *np_eccmgr; | |
1264 | ||
1265 | ecc_name = (char *)np->name; | |
1266 | ||
1267 | /* Get the ECC Manager - parent of the device EDACs */ | |
1268 | np_eccmgr = of_get_parent(np); | |
1269 | ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr, | |
1270 | "altr,sysmgr-syscon"); | |
1271 | of_node_put(np_eccmgr); | |
1272 | if (IS_ERR(ecc_mgr_map)) { | |
1273 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1274 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
1275 | return -ENODEV; | |
1276 | } | |
1277 | ||
1278 | /* Map the ECC Block */ | |
1279 | ecc_block_base = of_iomap(np, 0); | |
1280 | if (!ecc_block_base) { | |
1281 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1282 | "Unable to map %s ECC block\n", ecc_name); | |
1283 | return -ENODEV; | |
1284 | } | |
1285 | ||
1286 | /* Disable ECC */ | |
1287 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); | |
1288 | writel(ALTR_A10_ECC_SERRINTEN, | |
1289 | (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); | |
1290 | ecc_clear_bits(ecc_ctrl_en_mask, | |
1291 | (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); | |
1292 | /* Ensure all writes complete */ | |
1293 | wmb(); | |
1294 | /* Use HW initialization block to initialize memory for ECC */ | |
1295 | ret = altr_init_memory_port(ecc_block_base, 0); | |
1296 | if (ret) { | |
1297 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1298 | "ECC: cannot init %s PORTA memory\n", ecc_name); | |
1299 | goto out; | |
1300 | } | |
1301 | ||
1302 | if (dual_port) { | |
1303 | ret = altr_init_memory_port(ecc_block_base, 1); | |
1304 | if (ret) { | |
1305 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1306 | "ECC: cannot init %s PORTB memory\n", | |
1307 | ecc_name); | |
1308 | goto out; | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | /* Interrupt mode set to every SBERR */ | |
1313 | regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, | |
1314 | ALTR_A10_ECC_INTMODE); | |
1315 | /* Enable ECC */ | |
1316 | ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + | |
1317 | ALTR_A10_ECC_CTRL_OFST)); | |
1318 | writel(ALTR_A10_ECC_SERRINTEN, | |
1319 | (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); | |
1320 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); | |
1321 | /* Ensure all writes complete */ | |
1322 | wmb(); | |
1323 | out: | |
1324 | iounmap(ecc_block_base); | |
1325 | return ret; | |
1326 | } | |
1327 | ||
25b223dd TT |
1328 | static int socfpga_is_a10(void) |
1329 | { | |
1330 | return of_machine_is_compatible("altr,socfpga-arria10"); | |
1331 | } | |
1332 | ||
1166fde9 TT |
1333 | static int validate_parent_available(struct device_node *np); |
1334 | static const struct of_device_id altr_edac_a10_device_of_match[]; | |
1335 | static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) | |
1336 | { | |
1337 | int irq; | |
25b223dd TT |
1338 | struct device_node *child, *np; |
1339 | ||
1340 | if (!socfpga_is_a10()) | |
1341 | return -ENODEV; | |
1342 | ||
1343 | np = of_find_compatible_node(NULL, NULL, | |
1344 | "altr,socfpga-a10-ecc-manager"); | |
1166fde9 TT |
1345 | if (!np) { |
1346 | edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); | |
1347 | return -ENODEV; | |
1348 | } | |
1349 | ||
1350 | for_each_child_of_node(np, child) { | |
1351 | const struct of_device_id *pdev_id; | |
1352 | const struct edac_device_prv_data *prv; | |
1353 | ||
1354 | if (!of_device_is_available(child)) | |
1355 | continue; | |
1356 | if (!of_device_is_compatible(child, compat)) | |
1357 | continue; | |
1358 | ||
1359 | if (validate_parent_available(child)) | |
1360 | continue; | |
1361 | ||
1362 | irq = a10_get_irq_mask(child); | |
1363 | if (irq < 0) | |
1364 | continue; | |
1365 | ||
1366 | /* Get matching node and check for valid result */ | |
1367 | pdev_id = of_match_node(altr_edac_a10_device_of_match, child); | |
1368 | if (IS_ERR_OR_NULL(pdev_id)) | |
1369 | continue; | |
1370 | ||
1371 | /* Validate private data pointer before dereferencing */ | |
1372 | prv = pdev_id->data; | |
1373 | if (!prv) | |
1374 | continue; | |
1375 | ||
1376 | altr_init_a10_ecc_block(child, BIT(irq), | |
1377 | prv->ecc_enable_mask, 0); | |
1378 | } | |
1379 | ||
1380 | of_node_put(np); | |
1381 | return 0; | |
1382 | } | |
1383 | ||
6b300fb9 TT |
1384 | /*********************** OCRAM EDAC Device Functions *********************/ |
1385 | ||
1386 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1387 | ||
c3eea194 TT |
1388 | static void *ocram_alloc_mem(size_t size, void **other) |
1389 | { | |
1390 | struct device_node *np; | |
1391 | struct gen_pool *gp; | |
1392 | void *sram_addr; | |
1393 | ||
1394 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); | |
1395 | if (!np) | |
1396 | return NULL; | |
1397 | ||
1398 | gp = of_gen_pool_get(np, "iram", 0); | |
1399 | of_node_put(np); | |
1400 | if (!gp) | |
1401 | return NULL; | |
1402 | ||
1403 | sram_addr = (void *)gen_pool_alloc(gp, size); | |
1404 | if (!sram_addr) | |
1405 | return NULL; | |
1406 | ||
1407 | memset(sram_addr, 0, size); | |
1408 | /* Ensure data is written out */ | |
1409 | wmb(); | |
1410 | ||
1411 | /* Remember this handle for freeing later */ | |
1412 | *other = gp; | |
1413 | ||
1414 | return sram_addr; | |
1415 | } | |
1416 | ||
1417 | static void ocram_free_mem(void *p, size_t size, void *other) | |
1418 | { | |
9ef20753 | 1419 | gen_pool_free((struct gen_pool *)other, (unsigned long)p, size); |
c3eea194 TT |
1420 | } |
1421 | ||
1cf70377 | 1422 | static const struct edac_device_prv_data ocramecc_data = { |
aa1f06dc | 1423 | .setup = altr_check_ecc_deps, |
c3eea194 TT |
1424 | .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), |
1425 | .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), | |
c3eea194 TT |
1426 | .alloc_mem = ocram_alloc_mem, |
1427 | .free_mem = ocram_free_mem, | |
1428 | .ecc_enable_mask = ALTR_OCR_ECC_EN, | |
943ad917 | 1429 | .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 TT |
1430 | .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), |
1431 | .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), | |
811fce4f | 1432 | .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 | 1433 | .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, |
e17ced2c | 1434 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1435 | }; |
1436 | ||
1cf70377 | 1437 | static const struct edac_device_prv_data a10_ocramecc_data = { |
c7b4be8d TT |
1438 | .setup = altr_check_ecc_deps, |
1439 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1440 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1441 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, | |
c7b4be8d TT |
1442 | .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, |
1443 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1444 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1445 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1446 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1447 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1448 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
2b083d65 TT |
1449 | /* |
1450 | * OCRAM panic on uncorrectable error because sleep/resume | |
1451 | * functions and FPGA contents are stored in OCRAM. Prefer | |
1452 | * a kernel panic over executing/loading corrupted data. | |
1453 | */ | |
1454 | .panic = true, | |
c7b4be8d TT |
1455 | }; |
1456 | ||
c3eea194 TT |
1457 | #endif /* CONFIG_EDAC_ALTERA_OCRAM */ |
1458 | ||
1459 | /********************* L2 Cache EDAC Device Functions ********************/ | |
1460 | ||
1461 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1462 | ||
1463 | static void *l2_alloc_mem(size_t size, void **other) | |
1464 | { | |
1465 | struct device *dev = *other; | |
1466 | void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); | |
1467 | ||
1468 | if (!ptemp) | |
1469 | return NULL; | |
1470 | ||
1471 | /* Make sure everything is written out */ | |
1472 | wmb(); | |
1473 | ||
1474 | /* | |
1475 | * Clean all cache levels up to LoC (includes L2) | |
1476 | * This ensures the corrupted data is written into | |
1477 | * L2 cache for readback test (which causes ECC error). | |
1478 | */ | |
1479 | flush_cache_all(); | |
1480 | ||
1481 | return ptemp; | |
1482 | } | |
1483 | ||
1484 | static void l2_free_mem(void *p, size_t size, void *other) | |
1485 | { | |
1486 | struct device *dev = other; | |
1487 | ||
1488 | if (dev && p) | |
1489 | devm_kfree(dev, p); | |
1490 | } | |
1491 | ||
1492 | /* | |
1493 | * altr_l2_check_deps() | |
1494 | * Test for L2 cache ECC dependencies upon entry because | |
1495 | * platform specific startup should have initialized the L2 | |
1496 | * memory and enabled the ECC. | |
1497 | * Bail if ECC is not enabled. | |
1498 | * Note that L2 Cache Enable is forced at build time. | |
1499 | */ | |
328ca7ae | 1500 | static int altr_l2_check_deps(struct altr_edac_device_dev *device) |
c3eea194 | 1501 | { |
328ca7ae | 1502 | void __iomem *base = device->base; |
27439a1a TT |
1503 | const struct edac_device_prv_data *prv = device->data; |
1504 | ||
1505 | if ((readl(base) & prv->ecc_enable_mask) == | |
1506 | prv->ecc_enable_mask) | |
c3eea194 TT |
1507 | return 0; |
1508 | ||
1509 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1510 | "L2: No ECC present, or ECC disabled\n"); | |
1511 | return -ENODEV; | |
1512 | } | |
1513 | ||
13ab8448 | 1514 | static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) |
588cb03e | 1515 | { |
13ab8448 TT |
1516 | struct altr_edac_device_dev *dci = dev_id; |
1517 | ||
1518 | if (irq == dci->sb_irq) { | |
588cb03e TT |
1519 | regmap_write(dci->edac->ecc_mgr_map, |
1520 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1521 | A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); | |
1522 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
13ab8448 TT |
1523 | |
1524 | return IRQ_HANDLED; | |
1525 | } else if (irq == dci->db_irq) { | |
588cb03e TT |
1526 | regmap_write(dci->edac->ecc_mgr_map, |
1527 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1528 | A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); | |
1529 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1530 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
13ab8448 TT |
1531 | |
1532 | return IRQ_HANDLED; | |
588cb03e | 1533 | } |
13ab8448 TT |
1534 | |
1535 | WARN_ON(1); | |
1536 | ||
1537 | return IRQ_NONE; | |
588cb03e TT |
1538 | } |
1539 | ||
1cf70377 | 1540 | static const struct edac_device_prv_data l2ecc_data = { |
c3eea194 TT |
1541 | .setup = altr_l2_check_deps, |
1542 | .ce_clear_mask = 0, | |
1543 | .ue_clear_mask = 0, | |
c3eea194 TT |
1544 | .alloc_mem = l2_alloc_mem, |
1545 | .free_mem = l2_free_mem, | |
1546 | .ecc_enable_mask = ALTR_L2_ECC_EN, | |
1547 | .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), | |
1548 | .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), | |
811fce4f | 1549 | .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, |
c3eea194 | 1550 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, |
e17ced2c | 1551 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1552 | }; |
1553 | ||
1cf70377 | 1554 | static const struct edac_device_prv_data a10_l2ecc_data = { |
588cb03e TT |
1555 | .setup = altr_l2_check_deps, |
1556 | .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, | |
1557 | .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, | |
1558 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, | |
588cb03e TT |
1559 | .alloc_mem = l2_alloc_mem, |
1560 | .free_mem = l2_free_mem, | |
1561 | .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, | |
1562 | .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, | |
1563 | .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, | |
1564 | .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, | |
1565 | .ecc_irq_handler = altr_edac_a10_l2_irq, | |
1566 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, | |
e17ced2c | 1567 | .inject_fops = &altr_edac_device_inject_fops, |
588cb03e TT |
1568 | }; |
1569 | ||
c3eea194 TT |
1570 | #endif /* CONFIG_EDAC_ALTERA_L2C */ |
1571 | ||
ab8c1e0f TT |
1572 | /********************* Ethernet Device Functions ********************/ |
1573 | ||
1574 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1575 | ||
1576 | static const struct edac_device_prv_data a10_enetecc_data = { | |
1577 | .setup = altr_check_ecc_deps, | |
1578 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1579 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
ab8c1e0f TT |
1580 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1581 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1582 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1583 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1584 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1585 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1586 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1587 | }; | |
1588 | ||
1589 | static int __init socfpga_init_ethernet_ecc(void) | |
1590 | { | |
1591 | return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); | |
1592 | } | |
1593 | ||
1594 | early_initcall(socfpga_init_ethernet_ecc); | |
1595 | ||
1596 | #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ | |
1597 | ||
c6882fb2 TT |
1598 | /********************** NAND Device Functions **********************/ |
1599 | ||
1600 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1601 | ||
1602 | static const struct edac_device_prv_data a10_nandecc_data = { | |
1603 | .setup = altr_check_ecc_deps, | |
1604 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1605 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
c6882fb2 TT |
1606 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1607 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1608 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1609 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1610 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1611 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1612 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1613 | }; | |
1614 | ||
1615 | static int __init socfpga_init_nand_ecc(void) | |
1616 | { | |
1617 | return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); | |
1618 | } | |
1619 | ||
1620 | early_initcall(socfpga_init_nand_ecc); | |
1621 | ||
1622 | #endif /* CONFIG_EDAC_ALTERA_NAND */ | |
1623 | ||
e8263793 TT |
1624 | /********************** DMA Device Functions **********************/ |
1625 | ||
1626 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1627 | ||
1628 | static const struct edac_device_prv_data a10_dmaecc_data = { | |
1629 | .setup = altr_check_ecc_deps, | |
1630 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1631 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
e8263793 TT |
1632 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1633 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1634 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1635 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1636 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1637 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1638 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1639 | }; | |
1640 | ||
1641 | static int __init socfpga_init_dma_ecc(void) | |
1642 | { | |
1643 | return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); | |
1644 | } | |
1645 | ||
1646 | early_initcall(socfpga_init_dma_ecc); | |
1647 | ||
1648 | #endif /* CONFIG_EDAC_ALTERA_DMA */ | |
1649 | ||
c609581d TT |
1650 | /********************** USB Device Functions **********************/ |
1651 | ||
1652 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1653 | ||
1654 | static const struct edac_device_prv_data a10_usbecc_data = { | |
1655 | .setup = altr_check_ecc_deps, | |
1656 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1657 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
c609581d TT |
1658 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1659 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1660 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1661 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1662 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1663 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1664 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1665 | }; | |
1666 | ||
1667 | static int __init socfpga_init_usb_ecc(void) | |
1668 | { | |
1669 | return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); | |
1670 | } | |
1671 | ||
1672 | early_initcall(socfpga_init_usb_ecc); | |
1673 | ||
1674 | #endif /* CONFIG_EDAC_ALTERA_USB */ | |
1675 | ||
485fe9e2 TT |
1676 | /********************** QSPI Device Functions **********************/ |
1677 | ||
1678 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1679 | ||
1680 | static const struct edac_device_prv_data a10_qspiecc_data = { | |
1681 | .setup = altr_check_ecc_deps, | |
1682 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1683 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
485fe9e2 TT |
1684 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1685 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1686 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1687 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1688 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1689 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1690 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1691 | }; | |
1692 | ||
1693 | static int __init socfpga_init_qspi_ecc(void) | |
1694 | { | |
1695 | return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); | |
1696 | } | |
1697 | ||
1698 | early_initcall(socfpga_init_qspi_ecc); | |
1699 | ||
1700 | #endif /* CONFIG_EDAC_ALTERA_QSPI */ | |
1701 | ||
91104984 TT |
1702 | /********************* SDMMC Device Functions **********************/ |
1703 | ||
1704 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1705 | ||
1706 | static const struct edac_device_prv_data a10_sdmmceccb_data; | |
1707 | static int altr_portb_setup(struct altr_edac_device_dev *device) | |
1708 | { | |
1709 | struct edac_device_ctl_info *dci; | |
1710 | struct altr_edac_device_dev *altdev; | |
1711 | char *ecc_name = "sdmmcb-ecc"; | |
1712 | int edac_idx, rc; | |
1713 | struct device_node *np; | |
1714 | const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; | |
1715 | ||
1716 | rc = altr_check_ecc_deps(device); | |
1717 | if (rc) | |
1718 | return rc; | |
1719 | ||
1720 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
1721 | if (!np) { | |
1722 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1723 | return -ENODEV; | |
1724 | } | |
1725 | ||
1726 | /* Create the PortB EDAC device */ | |
1727 | edac_idx = edac_device_alloc_index(); | |
1728 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, | |
1729 | ecc_name, 1, 0, NULL, 0, edac_idx); | |
1730 | if (!dci) { | |
1731 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1732 | "%s: Unable to allocate PortB EDAC device\n", | |
1733 | ecc_name); | |
1734 | return -ENOMEM; | |
1735 | } | |
1736 | ||
1737 | /* Initialize the PortB EDAC device structure from PortA structure */ | |
1738 | altdev = dci->pvt_info; | |
1739 | *altdev = *device; | |
1740 | ||
1741 | if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) | |
1742 | return -ENOMEM; | |
1743 | ||
1744 | /* Update PortB specific values */ | |
1745 | altdev->edac_dev_name = ecc_name; | |
1746 | altdev->edac_idx = edac_idx; | |
1747 | altdev->edac_dev = dci; | |
1748 | altdev->data = prv; | |
1749 | dci->dev = &altdev->ddev; | |
1750 | dci->ctl_name = "Altera ECC Manager"; | |
1751 | dci->mod_name = ecc_name; | |
1752 | dci->dev_name = ecc_name; | |
1753 | ||
1754 | /* Update the IRQs for PortB */ | |
1755 | altdev->sb_irq = irq_of_parse_and_map(np, 2); | |
1756 | if (!altdev->sb_irq) { | |
1757 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); | |
1758 | rc = -ENODEV; | |
1759 | goto err_release_group_1; | |
1760 | } | |
1761 | rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, | |
1762 | prv->ecc_irq_handler, | |
a29d64a4 TT |
1763 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, |
1764 | ecc_name, altdev); | |
91104984 TT |
1765 | if (rc) { |
1766 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); | |
1767 | goto err_release_group_1; | |
1768 | } | |
1769 | ||
1770 | altdev->db_irq = irq_of_parse_and_map(np, 3); | |
1771 | if (!altdev->db_irq) { | |
1772 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); | |
1773 | rc = -ENODEV; | |
1774 | goto err_release_group_1; | |
1775 | } | |
1776 | rc = devm_request_irq(&altdev->ddev, altdev->db_irq, | |
1777 | prv->ecc_irq_handler, | |
a29d64a4 TT |
1778 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, |
1779 | ecc_name, altdev); | |
91104984 TT |
1780 | if (rc) { |
1781 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); | |
1782 | goto err_release_group_1; | |
1783 | } | |
1784 | ||
1785 | rc = edac_device_add_device(dci); | |
1786 | if (rc) { | |
1787 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1788 | "edac_device_add_device portB failed\n"); | |
1789 | rc = -ENOMEM; | |
1790 | goto err_release_group_1; | |
1791 | } | |
1792 | altr_create_edacdev_dbgfs(dci, prv); | |
1793 | ||
1794 | list_add(&altdev->next, &altdev->edac->a10_ecc_devices); | |
1795 | ||
1796 | devres_remove_group(&altdev->ddev, altr_portb_setup); | |
1797 | ||
1798 | return 0; | |
1799 | ||
1800 | err_release_group_1: | |
1801 | edac_device_free_ctl_info(dci); | |
1802 | devres_release_group(&altdev->ddev, altr_portb_setup); | |
1803 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1804 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1805 | return rc; | |
1806 | } | |
1807 | ||
1808 | static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) | |
1809 | { | |
1810 | struct altr_edac_device_dev *ad = dev_id; | |
1811 | void __iomem *base = ad->base; | |
1812 | const struct edac_device_prv_data *priv = ad->data; | |
1813 | ||
1814 | if (irq == ad->sb_irq) { | |
1815 | writel(priv->ce_clear_mask, | |
1816 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1817 | edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1818 | return IRQ_HANDLED; | |
1819 | } else if (irq == ad->db_irq) { | |
1820 | writel(priv->ue_clear_mask, | |
1821 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1822 | edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1823 | return IRQ_HANDLED; | |
1824 | } | |
1825 | ||
1826 | WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); | |
1827 | ||
1828 | return IRQ_NONE; | |
1829 | } | |
1830 | ||
1831 | static const struct edac_device_prv_data a10_sdmmcecca_data = { | |
1832 | .setup = altr_portb_setup, | |
1833 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1834 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
91104984 TT |
1835 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1836 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1837 | .ce_set_mask = ALTR_A10_ECC_SERRPENA, | |
1838 | .ue_set_mask = ALTR_A10_ECC_DERRPENA, | |
1839 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1840 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1841 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1842 | }; | |
1843 | ||
1844 | static const struct edac_device_prv_data a10_sdmmceccb_data = { | |
1845 | .setup = altr_portb_setup, | |
1846 | .ce_clear_mask = ALTR_A10_ECC_SERRPENB, | |
1847 | .ue_clear_mask = ALTR_A10_ECC_DERRPENB, | |
91104984 TT |
1848 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1849 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1850 | .ce_set_mask = ALTR_A10_ECC_TSERRB, | |
1851 | .ue_set_mask = ALTR_A10_ECC_TDERRB, | |
1852 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1853 | .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, | |
1854 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1855 | }; | |
1856 | ||
1857 | static int __init socfpga_init_sdmmc_ecc(void) | |
1858 | { | |
1859 | int rc = -ENODEV; | |
25b223dd TT |
1860 | struct device_node *child; |
1861 | ||
1862 | if (!socfpga_is_a10()) | |
1863 | return -ENODEV; | |
1864 | ||
1865 | child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
91104984 TT |
1866 | if (!child) { |
1867 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1868 | return -ENODEV; | |
1869 | } | |
1870 | ||
1871 | if (!of_device_is_available(child)) | |
1872 | goto exit; | |
1873 | ||
1874 | if (validate_parent_available(child)) | |
1875 | goto exit; | |
1876 | ||
1877 | rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, | |
1878 | a10_sdmmcecca_data.ecc_enable_mask, 1); | |
1879 | exit: | |
1880 | of_node_put(child); | |
1881 | return rc; | |
1882 | } | |
1883 | ||
1884 | early_initcall(socfpga_init_sdmmc_ecc); | |
1885 | ||
1886 | #endif /* CONFIG_EDAC_ALTERA_SDMMC */ | |
1887 | ||
588cb03e | 1888 | /********************* Arria10 EDAC Device Functions *************************/ |
ab564cb5 TT |
1889 | static const struct of_device_id altr_edac_a10_device_of_match[] = { |
1890 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1891 | { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, | |
1892 | #endif | |
1893 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1894 | { .compatible = "altr,socfpga-a10-ocram-ecc", | |
1895 | .data = &a10_ocramecc_data }, | |
ab8c1e0f TT |
1896 | #endif |
1897 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1898 | { .compatible = "altr,socfpga-eth-mac-ecc", | |
1899 | .data = &a10_enetecc_data }, | |
c6882fb2 TT |
1900 | #endif |
1901 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1902 | { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, | |
e8263793 TT |
1903 | #endif |
1904 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1905 | { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, | |
c609581d TT |
1906 | #endif |
1907 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1908 | { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, | |
485fe9e2 TT |
1909 | #endif |
1910 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1911 | { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, | |
91104984 TT |
1912 | #endif |
1913 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1914 | { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, | |
ab564cb5 TT |
1915 | #endif |
1916 | {}, | |
1917 | }; | |
1918 | MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); | |
588cb03e TT |
1919 | |
1920 | /* | |
1921 | * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 | |
1922 | * because 2 IRQs are shared among the all ECC peripherals. The ECC | |
1923 | * manager manages the IRQs and the children. | |
1924 | * Based on xgene_edac.c peripheral code. | |
1925 | */ | |
1926 | ||
c7b4be8d TT |
1927 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
1928 | const char __user *user_buf, | |
1929 | size_t count, loff_t *ppos) | |
1930 | { | |
1931 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
1932 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
1933 | const struct edac_device_prv_data *priv = drvdata->data; | |
1934 | void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); | |
1935 | unsigned long flags; | |
1936 | u8 trig_type; | |
1937 | ||
1938 | if (!user_buf || get_user(trig_type, user_buf)) | |
1939 | return -EFAULT; | |
1940 | ||
1941 | local_irq_save(flags); | |
1942 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
1943 | writel(priv->ue_set_mask, set_addr); | |
1944 | else | |
1945 | writel(priv->ce_set_mask, set_addr); | |
1946 | /* Ensure the interrupt test bits are set */ | |
1947 | wmb(); | |
1948 | local_irq_restore(flags); | |
1949 | ||
1950 | return count; | |
1951 | } | |
1952 | ||
13ab8448 | 1953 | static void altr_edac_a10_irq_handler(struct irq_desc *desc) |
588cb03e | 1954 | { |
13ab8448 TT |
1955 | int dberr, bit, sm_offset, irq_status; |
1956 | struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); | |
1957 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1958 | int irq = irq_desc_get_irq(desc); | |
1959 | ||
1960 | dberr = (irq == edac->db_irq) ? 1 : 0; | |
1961 | sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : | |
1962 | A10_SYSMGR_ECC_INTSTAT_SERR_OFST; | |
1963 | ||
1964 | chained_irq_enter(chip, desc); | |
588cb03e TT |
1965 | |
1966 | regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); | |
1967 | ||
13ab8448 TT |
1968 | for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { |
1969 | irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); | |
1970 | if (irq) | |
1971 | generic_handle_irq(irq); | |
588cb03e TT |
1972 | } |
1973 | ||
13ab8448 | 1974 | chained_irq_exit(chip, desc); |
588cb03e TT |
1975 | } |
1976 | ||
44ec9b30 TT |
1977 | static int validate_parent_available(struct device_node *np) |
1978 | { | |
1979 | struct device_node *parent; | |
1980 | int ret = 0; | |
1981 | ||
1982 | /* Ensure parent device is enabled if parent node exists */ | |
1983 | parent = of_parse_phandle(np, "altr,ecc-parent", 0); | |
1984 | if (parent && !of_device_is_available(parent)) | |
1985 | ret = -ENODEV; | |
1986 | ||
1987 | of_node_put(parent); | |
1988 | return ret; | |
1989 | } | |
1990 | ||
588cb03e TT |
1991 | static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, |
1992 | struct device_node *np) | |
1993 | { | |
1994 | struct edac_device_ctl_info *dci; | |
1995 | struct altr_edac_device_dev *altdev; | |
1996 | char *ecc_name = (char *)np->name; | |
1997 | struct resource res; | |
1998 | int edac_idx; | |
1999 | int rc = 0; | |
2000 | const struct edac_device_prv_data *prv; | |
2001 | /* Get matching node and check for valid result */ | |
2002 | const struct of_device_id *pdev_id = | |
ab564cb5 | 2003 | of_match_node(altr_edac_a10_device_of_match, np); |
588cb03e TT |
2004 | if (IS_ERR_OR_NULL(pdev_id)) |
2005 | return -ENODEV; | |
2006 | ||
2007 | /* Get driver specific data for this EDAC device */ | |
2008 | prv = pdev_id->data; | |
2009 | if (IS_ERR_OR_NULL(prv)) | |
2010 | return -ENODEV; | |
2011 | ||
44ec9b30 TT |
2012 | if (validate_parent_available(np)) |
2013 | return -ENODEV; | |
2014 | ||
588cb03e TT |
2015 | if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) |
2016 | return -ENOMEM; | |
2017 | ||
2018 | rc = of_address_to_resource(np, 0, &res); | |
2019 | if (rc < 0) { | |
2020 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2021 | "%s: no resource address\n", ecc_name); | |
2022 | goto err_release_group; | |
2023 | } | |
2024 | ||
2025 | edac_idx = edac_device_alloc_index(); | |
2026 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, | |
2027 | 1, ecc_name, 1, 0, NULL, 0, | |
2028 | edac_idx); | |
2029 | ||
2030 | if (!dci) { | |
2031 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2032 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
2033 | rc = -ENOMEM; | |
2034 | goto err_release_group; | |
2035 | } | |
2036 | ||
2037 | altdev = dci->pvt_info; | |
2038 | dci->dev = edac->dev; | |
2039 | altdev->edac_dev_name = ecc_name; | |
2040 | altdev->edac_idx = edac_idx; | |
2041 | altdev->edac = edac; | |
2042 | altdev->edac_dev = dci; | |
2043 | altdev->data = prv; | |
2044 | altdev->ddev = *edac->dev; | |
2045 | dci->dev = &altdev->ddev; | |
2046 | dci->ctl_name = "Altera ECC Manager"; | |
2047 | dci->mod_name = ecc_name; | |
2048 | dci->dev_name = ecc_name; | |
2049 | ||
2050 | altdev->base = devm_ioremap_resource(edac->dev, &res); | |
2051 | if (IS_ERR(altdev->base)) { | |
2052 | rc = PTR_ERR(altdev->base); | |
2053 | goto err_release_group1; | |
2054 | } | |
2055 | ||
2056 | /* Check specific dependencies for the module */ | |
2057 | if (altdev->data->setup) { | |
2058 | rc = altdev->data->setup(altdev); | |
2059 | if (rc) | |
2060 | goto err_release_group1; | |
2061 | } | |
2062 | ||
13ab8448 TT |
2063 | altdev->sb_irq = irq_of_parse_and_map(np, 0); |
2064 | if (!altdev->sb_irq) { | |
2065 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); | |
2066 | rc = -ENODEV; | |
2067 | goto err_release_group1; | |
2068 | } | |
a29d64a4 TT |
2069 | rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, |
2070 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
2071 | ecc_name, altdev); | |
13ab8448 | 2072 | if (rc) { |
3763569f | 2073 | edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); |
13ab8448 TT |
2074 | goto err_release_group1; |
2075 | } | |
2076 | ||
2077 | altdev->db_irq = irq_of_parse_and_map(np, 1); | |
2078 | if (!altdev->db_irq) { | |
2079 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); | |
2080 | rc = -ENODEV; | |
2081 | goto err_release_group1; | |
2082 | } | |
a29d64a4 TT |
2083 | rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, |
2084 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
2085 | ecc_name, altdev); | |
13ab8448 TT |
2086 | if (rc) { |
2087 | edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); | |
2088 | goto err_release_group1; | |
2089 | } | |
2090 | ||
588cb03e TT |
2091 | rc = edac_device_add_device(dci); |
2092 | if (rc) { | |
2093 | dev_err(edac->dev, "edac_device_add_device failed\n"); | |
2094 | rc = -ENOMEM; | |
2095 | goto err_release_group1; | |
2096 | } | |
2097 | ||
2098 | altr_create_edacdev_dbgfs(dci, prv); | |
2099 | ||
2100 | list_add(&altdev->next, &edac->a10_ecc_devices); | |
2101 | ||
2102 | devres_remove_group(edac->dev, altr_edac_a10_device_add); | |
2103 | ||
2104 | return 0; | |
2105 | ||
2106 | err_release_group1: | |
2107 | edac_device_free_ctl_info(dci); | |
2108 | err_release_group: | |
588cb03e TT |
2109 | devres_release_group(edac->dev, NULL); |
2110 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2111 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
2112 | ||
2113 | return rc; | |
2114 | } | |
2115 | ||
13ab8448 TT |
2116 | static void a10_eccmgr_irq_mask(struct irq_data *d) |
2117 | { | |
2118 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
2119 | ||
2120 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, | |
2121 | BIT(d->hwirq)); | |
2122 | } | |
2123 | ||
2124 | static void a10_eccmgr_irq_unmask(struct irq_data *d) | |
2125 | { | |
2126 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
2127 | ||
2128 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, | |
2129 | BIT(d->hwirq)); | |
2130 | } | |
2131 | ||
2132 | static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
2133 | irq_hw_number_t hwirq) | |
2134 | { | |
2135 | struct altr_arria10_edac *edac = d->host_data; | |
2136 | ||
2137 | irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); | |
2138 | irq_set_chip_data(irq, edac); | |
2139 | irq_set_noprobe(irq); | |
2140 | ||
2141 | return 0; | |
2142 | } | |
2143 | ||
18caec20 | 2144 | static const struct irq_domain_ops a10_eccmgr_ic_ops = { |
13ab8448 TT |
2145 | .map = a10_eccmgr_irqdomain_map, |
2146 | .xlate = irq_domain_xlate_twocell, | |
2147 | }; | |
2148 | ||
588cb03e TT |
2149 | static int altr_edac_a10_probe(struct platform_device *pdev) |
2150 | { | |
2151 | struct altr_arria10_edac *edac; | |
2152 | struct device_node *child; | |
588cb03e TT |
2153 | |
2154 | edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); | |
2155 | if (!edac) | |
2156 | return -ENOMEM; | |
2157 | ||
2158 | edac->dev = &pdev->dev; | |
2159 | platform_set_drvdata(pdev, edac); | |
2160 | INIT_LIST_HEAD(&edac->a10_ecc_devices); | |
2161 | ||
2162 | edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
2163 | "altr,sysmgr-syscon"); | |
2164 | if (IS_ERR(edac->ecc_mgr_map)) { | |
2165 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2166 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
2167 | return PTR_ERR(edac->ecc_mgr_map); | |
2168 | } | |
2169 | ||
13ab8448 TT |
2170 | edac->irq_chip.name = pdev->dev.of_node->name; |
2171 | edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; | |
2172 | edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; | |
2173 | edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, | |
2174 | &a10_eccmgr_ic_ops, edac); | |
2175 | if (!edac->domain) { | |
2176 | dev_err(&pdev->dev, "Error adding IRQ domain\n"); | |
2177 | return -ENOMEM; | |
2178 | } | |
2179 | ||
588cb03e | 2180 | edac->sb_irq = platform_get_irq(pdev, 0); |
13ab8448 TT |
2181 | if (edac->sb_irq < 0) { |
2182 | dev_err(&pdev->dev, "No SBERR IRQ resource\n"); | |
2183 | return edac->sb_irq; | |
588cb03e TT |
2184 | } |
2185 | ||
13ab8448 TT |
2186 | irq_set_chained_handler_and_data(edac->sb_irq, |
2187 | altr_edac_a10_irq_handler, | |
2188 | edac); | |
2189 | ||
588cb03e | 2190 | edac->db_irq = platform_get_irq(pdev, 1); |
13ab8448 TT |
2191 | if (edac->db_irq < 0) { |
2192 | dev_err(&pdev->dev, "No DBERR IRQ resource\n"); | |
2193 | return edac->db_irq; | |
588cb03e | 2194 | } |
13ab8448 TT |
2195 | irq_set_chained_handler_and_data(edac->db_irq, |
2196 | altr_edac_a10_irq_handler, | |
2197 | edac); | |
588cb03e TT |
2198 | |
2199 | for_each_child_of_node(pdev->dev.of_node, child) { | |
2200 | if (!of_device_is_available(child)) | |
2201 | continue; | |
c6882fb2 TT |
2202 | |
2203 | if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || | |
2204 | of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || | |
2205 | of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || | |
e8263793 | 2206 | of_device_is_compatible(child, "altr,socfpga-nand-ecc") || |
c609581d | 2207 | of_device_is_compatible(child, "altr,socfpga-dma-ecc") || |
485fe9e2 | 2208 | of_device_is_compatible(child, "altr,socfpga-usb-ecc") || |
91104984 TT |
2209 | of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || |
2210 | of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) | |
c6882fb2 | 2211 | |
c7b4be8d | 2212 | altr_edac_a10_device_add(edac, child); |
c6882fb2 TT |
2213 | |
2214 | else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) | |
ab564cb5 TT |
2215 | of_platform_populate(pdev->dev.of_node, |
2216 | altr_sdram_ctrl_of_match, | |
2217 | NULL, &pdev->dev); | |
588cb03e TT |
2218 | } |
2219 | ||
2220 | return 0; | |
2221 | } | |
2222 | ||
2223 | static const struct of_device_id altr_edac_a10_of_match[] = { | |
2224 | { .compatible = "altr,socfpga-a10-ecc-manager" }, | |
2225 | {}, | |
2226 | }; | |
2227 | MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); | |
2228 | ||
2229 | static struct platform_driver altr_edac_a10_driver = { | |
2230 | .probe = altr_edac_a10_probe, | |
2231 | .driver = { | |
2232 | .name = "socfpga_a10_ecc_manager", | |
2233 | .of_match_table = altr_edac_a10_of_match, | |
2234 | }, | |
2235 | }; | |
2236 | module_platform_driver(altr_edac_a10_driver); | |
2237 | ||
3dab6bd5 TT |
2238 | /************** Stratix 10 EDAC Device Controller Functions> ************/ |
2239 | ||
e9918d7f TT |
2240 | #define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m) |
2241 | ||
2242 | /* | |
2243 | * The double bit error is handled through SError which is fatal. This is | |
2244 | * called as a panic notifier to printout ECC error info as part of the panic. | |
2245 | */ | |
2246 | static int s10_edac_dberr_handler(struct notifier_block *this, | |
2247 | unsigned long event, void *ptr) | |
2248 | { | |
2249 | struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier); | |
2250 | int err_addr, dberror; | |
2251 | ||
2252 | s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST, | |
2253 | &dberror); | |
2254 | /* Remember the UE Errors for a reboot */ | |
2255 | s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror); | |
2256 | if (dberror & S10_DDR0_IRQ_MASK) { | |
2257 | s10_protected_reg_read(edac, S10_DERRADDR_OFST, &err_addr); | |
2258 | /* Remember the UE Error address */ | |
2259 | s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, | |
2260 | err_addr); | |
2261 | edac_printk(KERN_ERR, EDAC_MC, | |
2262 | "EDAC: [Uncorrectable errors @ 0x%08X]\n\n", | |
2263 | err_addr); | |
2264 | } | |
2265 | ||
2266 | return NOTIFY_DONE; | |
2267 | } | |
2268 | ||
3dab6bd5 TT |
2269 | static void altr_edac_s10_irq_handler(struct irq_desc *desc) |
2270 | { | |
3dab6bd5 TT |
2271 | struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc); |
2272 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
2273 | int irq = irq_desc_get_irq(desc); | |
e9918d7f | 2274 | int bit, sm_offset, irq_status; |
3dab6bd5 | 2275 | |
e9918d7f | 2276 | sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST; |
3dab6bd5 TT |
2277 | |
2278 | chained_irq_enter(chip, desc); | |
2279 | ||
2280 | s10_protected_reg_read(NULL, sm_offset, &irq_status); | |
2281 | ||
2282 | for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { | |
e9918d7f | 2283 | irq = irq_linear_revmap(edac->domain, bit); |
3dab6bd5 TT |
2284 | if (irq) |
2285 | generic_handle_irq(irq); | |
2286 | } | |
2287 | ||
2288 | chained_irq_exit(chip, desc); | |
2289 | } | |
2290 | ||
2291 | static void s10_eccmgr_irq_mask(struct irq_data *d) | |
2292 | { | |
2293 | struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d); | |
2294 | ||
2295 | s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_SET_OFST, | |
2296 | BIT(d->hwirq)); | |
2297 | } | |
2298 | ||
2299 | static void s10_eccmgr_irq_unmask(struct irq_data *d) | |
2300 | { | |
2301 | struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d); | |
2302 | ||
2303 | s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_CLR_OFST, | |
2304 | BIT(d->hwirq)); | |
2305 | } | |
2306 | ||
2307 | static int s10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
2308 | irq_hw_number_t hwirq) | |
2309 | { | |
2310 | struct altr_stratix10_edac *edac = d->host_data; | |
2311 | ||
2312 | irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); | |
2313 | irq_set_chip_data(irq, edac); | |
2314 | irq_set_noprobe(irq); | |
2315 | ||
2316 | return 0; | |
2317 | } | |
2318 | ||
2319 | static const struct irq_domain_ops s10_eccmgr_ic_ops = { | |
2320 | .map = s10_eccmgr_irqdomain_map, | |
2321 | .xlate = irq_domain_xlate_twocell, | |
2322 | }; | |
2323 | ||
2324 | static int altr_edac_s10_probe(struct platform_device *pdev) | |
2325 | { | |
2326 | struct altr_stratix10_edac *edac; | |
2327 | struct device_node *child; | |
e9918d7f | 2328 | int dberror, err_addr; |
3dab6bd5 TT |
2329 | |
2330 | edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); | |
2331 | if (!edac) | |
2332 | return -ENOMEM; | |
2333 | ||
2334 | edac->dev = &pdev->dev; | |
2335 | platform_set_drvdata(pdev, edac); | |
2336 | INIT_LIST_HEAD(&edac->s10_ecc_devices); | |
2337 | ||
2338 | edac->irq_chip.name = pdev->dev.of_node->name; | |
2339 | edac->irq_chip.irq_mask = s10_eccmgr_irq_mask; | |
2340 | edac->irq_chip.irq_unmask = s10_eccmgr_irq_unmask; | |
2341 | edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, | |
2342 | &s10_eccmgr_ic_ops, edac); | |
2343 | if (!edac->domain) { | |
2344 | dev_err(&pdev->dev, "Error adding IRQ domain\n"); | |
2345 | return -ENOMEM; | |
2346 | } | |
2347 | ||
2348 | edac->sb_irq = platform_get_irq(pdev, 0); | |
2349 | if (edac->sb_irq < 0) { | |
2350 | dev_err(&pdev->dev, "No SBERR IRQ resource\n"); | |
2351 | return edac->sb_irq; | |
2352 | } | |
2353 | ||
2354 | irq_set_chained_handler_and_data(edac->sb_irq, | |
2355 | altr_edac_s10_irq_handler, | |
2356 | edac); | |
2357 | ||
e9918d7f TT |
2358 | edac->panic_notifier.notifier_call = s10_edac_dberr_handler; |
2359 | atomic_notifier_chain_register(&panic_notifier_list, | |
2360 | &edac->panic_notifier); | |
2361 | ||
2362 | /* Printout a message if uncorrectable error previously. */ | |
2363 | s10_protected_reg_read(edac, S10_SYSMGR_UE_VAL_OFST, &dberror); | |
2364 | if (dberror) { | |
2365 | s10_protected_reg_read(edac, S10_SYSMGR_UE_ADDR_OFST, | |
2366 | &err_addr); | |
2367 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2368 | "Previous Boot UE detected[0x%X] @ 0x%X\n", | |
2369 | dberror, err_addr); | |
2370 | /* Reset the sticky registers */ | |
2371 | s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, 0); | |
2372 | s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, 0); | |
2373 | } | |
3dab6bd5 TT |
2374 | |
2375 | for_each_child_of_node(pdev->dev.of_node, child) { | |
2376 | if (!of_device_is_available(child)) | |
2377 | continue; | |
2378 | ||
2379 | if (of_device_is_compatible(child, "altr,sdram-edac-s10")) | |
2380 | of_platform_populate(pdev->dev.of_node, | |
2381 | altr_sdram_ctrl_of_match, | |
2382 | NULL, &pdev->dev); | |
2383 | } | |
2384 | ||
2385 | return 0; | |
2386 | } | |
2387 | ||
2388 | static const struct of_device_id altr_edac_s10_of_match[] = { | |
2389 | { .compatible = "altr,socfpga-s10-ecc-manager" }, | |
2390 | {}, | |
2391 | }; | |
2392 | MODULE_DEVICE_TABLE(of, altr_edac_s10_of_match); | |
2393 | ||
2394 | static struct platform_driver altr_edac_s10_driver = { | |
2395 | .probe = altr_edac_s10_probe, | |
2396 | .driver = { | |
2397 | .name = "socfpga_s10_ecc_manager", | |
2398 | .of_match_table = altr_edac_s10_of_match, | |
2399 | }, | |
2400 | }; | |
2401 | module_platform_driver(altr_edac_s10_driver); | |
2402 | ||
71bcada8 TT |
2403 | MODULE_LICENSE("GPL v2"); |
2404 | MODULE_AUTHOR("Thor Thayer"); | |
c3eea194 | 2405 | MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); |